Silicon solar cell and assembly

Abstract

The present application relates to a silicon solar cell, comprising: a silicon substrate, the silicon substrate containing an antimony element; and a carrier separation layer formed on the silicon substrate. At least part of the region of the carrier separation layer close to one side of the silicon substrate is provided with an antimony-containing layer, and the antimony-containing layer contains the antimony element; the peak concentration of the antimony element in the antimony-containing layer is a1, and a1 is equal to and greater than 1E13 atoms / cm3.

Description

Silicon solar cells and modules

[0001] This application claims priority to Chinese Patent Application No. 202410564554.8, filed on May 8, 2024, entitled “A Solar Cell and Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of solar photovoltaics, specifically to silicon solar cells and modules. Background Technology

[0003] Currently, silicon solar cells typically use silicon wafers with n-type or p-type doped substrates. P-type and n-type doped semiconductors are formed at different locations on the silicon wafer, and electrodes are then formed on the respective regions of the p-type and n-type doped semiconductors. When light enters the silicon cell substrate, electron-hole pairs are generated. These ionized electron-hole pairs undergo carrier separation, causing electrons to accumulate near the n-electrode and holes to accumulate near the p-electrode. Connecting an external circuit to the electrodes allows for current output.

[0004] In related technologies, p-type or n-type substrates are typically used as semiconductor substrates for photovoltaics. P-type substrates are usually doped with boron or gallium. N-type substrates are usually doped with phosphorus. Summary of the Invention

[0005] Due to their longer minority carrier diffusion length, n-type substrates, when used in silicon solar cells, allow for the collection of more charge carriers compared to p-type substrates, resulting in higher efficiency. n-type substrates are typically doped with phosphorus. However, both n-type and p-type substrates suffer from efficiency reduction due to poor passivation. Therefore, this application aims to address the problem of poor passivation in the aforementioned prior art.

[0006] The inventors of this application have discovered that when antimony is doped into a silicon substrate, the antimony will overflow into the semiconductor layer to a certain extent. The antimony that overflows into the semiconductor layer will bond with the Si in the semiconductor layer, suppressing the generation of bubbles in the semiconductor layer and avoiding the formation of voids. This can effectively improve passivation and solve the problem of carrier transport suppression.

[0007] This application involves the following:

[0008] In a first aspect, a silicon solar cell is provided, comprising:

[0009] A silicon substrate, wherein the silicon substrate contains antimony, and

[0010] A carrier separation layer is formed on the silicon substrate, wherein,

[0011] The carrier separation layer has an antimony-containing layer in at least a portion of its region on the side closest to the silicon substrate, the antimony-containing layer containing antimony.

[0012] The peak concentration of antimony in the antimony-containing layer is a1, and a1 is equal to or greater than 1E13 atoms / cm. 3 .

[0013] In a second aspect, a solar cell module is provided, comprising the silicon solar cell described in any of the embodiments. Attached Figure Description

[0014] Figure 1 is a structural diagram of a conventional TOPCon battery;

[0015] Figure 2 is a detailed view of the passivated contact structure containing antimony.

[0016] Figure 3 is a partial TOPCon battery structure diagram containing antimony;

[0017] Figure 4 is a structural diagram of a back contact battery containing antimony.

[0018] Figure 5 is a structural diagram of a back contact battery containing antimony.

[0019] Figure 6 is a structural diagram of a back contact battery containing antimony.

[0020] Figure 7 is a structural diagram of a back contact battery containing antimony.

[0021] Figure 8 is a structural diagram of a back contact battery (HPBC structure) containing antimony.

[0022] Figure reference numerals: 1 Silicon substrate, 2 Interface passivation layer, 3 Doped semiconductor layer, 4 Antimony-containing layer, 5 Bode-containing layer x Layer, 21 First interface passivation layer, 31 First doped semiconductor layer, 41 First antimony-containing layer, 51 B-containing layer xp 22 Second interface passivation layer, 32 Second doped semiconductor layer, 42 Second antimony-containing layer, 52 B-containing layer xn 6. Substrate passivation layer, 7. Intrinsic region interface passivation layer, 8. Intrinsic semiconductor layer containing antimony, 9. Intrinsic semiconductor layer without antimony, 10. Intrinsic region side interface passivation layer, 11. P-region electrode. Detailed Implementation

[0023] The following embodiments of this application are only used to illustrate specific implementation methods of this application, and these embodiments should not be construed as limitations on this application. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of this application shall be considered equivalent substitutions and fall within the protection scope of this application.

[0024] Specific embodiments of this application will now be described in more detail. However, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0025] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that different terms may be used to refer to the same component. This specification and claims do not distinguish components based on differences in terminology, but rather on differences in function. The terms "comprising" or "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." The following descriptions in the specification are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of understanding the general principles of the specification and are not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0026] As used herein, "substantially free of" with respect to a particular component is used to indicate that the particular component was not intentionally formulated into the composition and / or is present only as a contaminant or in trace amounts. Therefore, the total amount of the particular component resulting from any accidental contamination of the composition is less than 0.05%, preferably less than 0.01%. Most preferably, the composition is in which the amount of the particular component is undetectable by standard analytical methods.

[0027] As used in this specification, "a" or "an" may mean one or more. As used in the claims, when used with the word "comprising," the word "a" or "an" may mean one or more.

[0028] The term “or” is used in the claims to mean “and / or” unless it is explicitly stated that it refers only to an alternative or that the alternatives are mutually exclusive, although this disclosure supports the definitions of referring only to an alternative and “and / or”. As used herein, “another” can mean at least a second or more.

[0029] In this application, the front side of the silicon substrate refers to the surface facing sunlight under normal battery operating conditions, while the back side refers to the surface of the silicon substrate on the other side opposite to the front side.

[0030] Those skilled in the art will understand that "silicon wafer" generally refers to the raw material bare silicon wafer, and "silicon substrate" generally refers to the portion of the cell formed from the silicon wafer. A light absorber generally refers to a functional component in the cell used to absorb photons, generate photogenerated carriers, and separate these photogenerated carriers. This includes the silicon substrate and regions that separate the carriers generated by the silicon substrate (e.g., the tunneling layer and doped polycrystalline layer in a TOPCon structure), wherein the silicon substrate is used to absorb light and generate photogenerated carriers. It is understood that simple anti-emission layers, other functional layers, and electrodes are not considered light absorbers. Those skilled in the art will understand that light absorbers or silicon substrates can be recovered from the cell, and that the silicon substrate as defined in this application can be obtained by stripping different stacked structures.

[0031] In this application, the doped region can also be used to separate photogenerated carriers, such as the region in the TOPCon cell described below that has been diffused with a Group 3 element (boron).

[0032] The silicon substrate is obtained from bare silicon wafers. It consists of a silicon matrix and doped regions. The silicon matrix is ​​the undoped bulk region used in battery manufacturing, and its performance is identical to that of the raw bare silicon wafer. The doped regions can be regions whose properties and parameters are essentially the same as the bulk region, except for the doping element. These can be formed by direct doping or inward doping within the bare silicon wafer. Furthermore, in some cases, the doped regions are made of antimony or other doping elements, such as Group 3 and Group 5 elements, specifically areas where B or P accumulates. In other cases, the doped regions may be essentially the same as the bulk region, primarily consisting of antimony-doped areas.

[0033] In solar cells with at least partial TOPCon structures (e.g., TOPCon cells, partial TOPCon cells, back-contact hybrid cells, and TBC cells), the silicon substrate typically includes a doped region formed within at least one surface of the silicon substrate. The performance of this doped region is identical to that of the raw silicon wafer. The doped region may have properties and parameters substantially the same as the bulk region, except for the doping element; that is, properties such as antimony concentration, resistivity change rate, and resistivity shift rate are substantially the same. Such a doped region can be formed by direct doping of the raw silicon wafer as described in detail below, or by doping the doping element into the raw silicon wafer through layers such as doped passivation layers and interface passivation layers. In this application, for solar cells with at least partial TOPCon structures, the doped region generally refers to a region formed by direct doping or inward doping within the raw silicon wafer, wherein inward doping is formed by doping polysilicon, referred to as the doped layer, into the interior of the raw silicon wafer through a tunneling layer, referred to as the passivation layer.

[0034] In this application, there are no further limitations on the silicon wafer itself mentioned above. It can be a silicon wafer obtained after machining and slicing following the pulling of silicon ingots (also referred to as a bare silicon wafer). The silicon substrate in this application can be a portion of the silicon substrate peeled and recovered from the battery module, as long as it has a certain shape and can be sheet-like, that is, the size of one side is larger than the size of the side perpendicular to it, and it is flat or plate-like. There are no limitations on the size of the silicon wafer or silicon substrate in this application. The silicon wafer or silicon substrate can be of any size, and it is a portion of the silicon substrate after the light absorber is recovered from the battery module and other layers are peeled off. In addition, those skilled in the art will understand that if some doped regions are damaged during peeling, as long as some doped regions still exist, it should also be understood as the silicon substrate described in this application, and a battery with such a silicon substrate also meets the definition of a battery in this application. For example, in one specific embodiment, the length of at least one side of the silicon wafer or silicon substrate (including the stripped portion of the silicon substrate after recycling and stripping other layer structures) of this application is greater than 156 mm, such as (158±2) mm, (160±2) mm, (165±2) mm, (170±2) mm, (175±2) mm, (180±2) mm, (185±2) mm, 190±2 mm, (195±2) mm, (200±2) mm. (205±2)mm, (210±2)mm, (215±2)mm, (220±2)mm, (225±2)mm, (230±2)mm, (235±2)mm, (240±2)mm, (245±2)mm, (250±2)mm, (255±2)mm, (260±2)mm, (265±2)mm, (270±2)mm, (275±2)mm, and any range between these values. For example, in one specific embodiment, the thickness of the silicon wafer or photosilicon substrate (including the stripped portion of the silicon substrate after recovering and peeling off other layers) of this application is at least 40 μm to 170 μm, such as 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, or 170 μm. In one specific embodiment, the size of the stripped portion of the silicon substrate after recovering and peeling off other layers can be smaller than the above-mentioned size, as long as it is possible to detect the concentration of antimony, resistivity, and calculate the resistivity change rate, resistivity average offset rate, etc., as defined in this application.

[0035] In this application, the concentration of antimony in the silicon wafer, silicon substrate, or carrier separation layer (e.g., doped semiconductor layer, molybdenum oxide layer, PEDOT:PSS layer) can be detected by any method known to those skilled in the art. Those skilled in the art can choose the appropriate method based on their needs, such as SIMS, ICP-MS, GDMS, etc., with ICP-MS being preferred. Those skilled in the art will understand that the concentration of antimony in the silicon wafer or silicon substrate can refer to the concentration of antimony at any site on the surface of the silicon wafer, silicon substrate, or carrier separation layer, or at any location within the silicon wafer, silicon substrate, or carrier separation layer. It can also be the average concentration of antimony at multiple sites or the average concentration of antimony across the entire silicon wafer, silicon substrate, or carrier separation layer. Those skilled in the art can select any of the above-mentioned sites for detection based on the detection conditions and the instruments used, or they can detect multiple sites and calculate the average of the multiple sites as the concentration of antimony. In one specific implementation, the concentration of antimony refers to the average value detected over the thickness of the silicon wafer, silicon substrate, or carrier separation layer. For example, the concentration of antimony in the silicon wafer is detected in a thickness direction using the SIMS method, and the average concentration in that thickness direction is calculated.

[0036] In this application, the concentration of antimony in the silicon substrate detected as described above is considered as a; the maximum value of the concentration of antimony in the antimony-containing layer formed by the above method in at least a portion of the region near the silicon substrate in the carrier separation layer, i.e., the peak concentration of antimony in the antimony-containing layer, is a1.

[0037] In this application, B in the silicon substrate x B xn B xp The concentration of [acid] can be detected by any method known to those skilled in the art, who can choose based on their needs. For example, it can be detected by methods such as SIMS, ICP-MS, and GDMS, with ICP-MS being the preferred method. Those skilled in the art will understand that B in silicon substrates [is a known chemical]. x B xn B xp The concentration can refer to the B concentration at any site on the surface of the doped region of the silicon substrate or within the doped region of the silicon substrate. x B xn B xp The concentration, of course, can also be B at multiple locations. x B xn B xp The average concentration or the B concentration across the entire doped region of the silicon substrate. x B xn B xpThe average concentration. Those skilled in the art can select any of the above-mentioned sites for detection based on the detection conditions and instruments used, or they can detect multiple sites and calculate the average of the multiple sites as B. x B xn B xp The concentration of B. In one specific implementation, B x B xn B xp The concentration refers to the average value detected across the thickness of the doped region on the silicon substrate. For example, the concentration of boron in the doped region of the silicon substrate can be measured using the SIMS method along a thickness direction. x B xn B xp The concentration of B was detected, and the concentration of B in this thickness direction was calculated. x B xn B xp Average concentration.

[0038] Those skilled in the art will fully understand that the above-mentioned testing of silicon wafers or silicon substrates can be performed on silicon wafers or silicon substrates of any size, on bare silicon wafers obtained after cutting following the pulling of silicon rods, or on silicon substrates stripped from cells or modules after other layers have been removed. As long as the test results obtained after testing according to the methods described in this application fall within the scope of this application, they should be considered to be covered by the silicon wafers, solar cells, cell strings, or solar modules claimed in this application.

[0039] In this application, the detection method for whether a certain element is present in the silicon wafer or silicon substrate can be achieved by methods such as SIMS, ICP-MS, and GDMS, with ICP-MS being the preferred method for detecting metallic elements. In this application, the solar cell is also referred to as a battery.

[0040] In one specific embodiment of this application, the silicon wafer (e.g., bare silicon wafer) or silicon substrate of this application is doped with antimony as a Group 5 dopant element instead of phosphorus. In this case, those skilled in the art will understand that, depending on the different sources of the silicon wafer raw materials, the silicon wafer or silicon substrate itself may contain other elements, such as any one, two, or three of phosphorus, gallium, and germanium, but only antimony is actively doped as a Group 5 dopant element instead of phosphorus.

[0041] Figure 1 shows a conventional TOPCon cell, which consists of a silicon substrate 1, an interface passivation layer 2, and a doped semiconductor layer 3. Existing solar cells suffer from efficiency reduction due to poor passivation.

[0042] To address the problems existing in the prior art, this application provides a silicon solar cell, as shown in Figure 2, comprising: a silicon substrate 1 containing antimony, and a carrier separation layer formed on the silicon substrate 1. The carrier separation layer has an antimony-containing layer 4 formed of antimony in at least a portion of its region near the silicon substrate 1. The peak concentration of antimony in the antimony-containing layer 4 is a1, and a1 is equal to or greater than 1E13 atoms / cm². 3 For example, the peak concentration of antimony in antimony-containing layer 4 can be 1E13 atoms / cm³. 3 5E13atoms / cm 3 1E14 atoms / cm 3 5E14 atoms / cm 3 1E15 atoms / cm 3 5E15atoms / cm 3 1E16 atoms / cm 3 5E16 atoms / cm 3 1E17atoms / cm 3 5E17atoms / cm 3 1E18atoms / cm 3 , and any value between these values.

[0043] The peak concentration of antimony in antimony layer 4 is greater than 1E13 atoms / cm 3 This can reduce the proportion of bubbles in the carrier separation layer of existing technologies, and can also address the passivation problem and electrical transport of the carrier separation layer, while improving the mechanical properties of the cell, thereby increasing the efficiency of the solar cell.

[0044] In some specific embodiments, the concentration of antimony in the silicon substrate 1 is 'a', where 'a' ranges from 1E13 to 1E18 atoms / cm³. 3 For example, it could be 1E13 atoms / cm 3 5E13atoms / cm 3 1E14 atoms / cm 3 5E14 atoms / cm 3 1E15 atoms / cm 3 5E15atoms / cm 3 1E16 atoms / cm 3 5E16 atoms / cm 3 1E17atoms / cm 3 5E17atoms / cm 3 1E18atoms / cm 3, and any value between these values.

[0045] Since this application dops Sb element in silicon substrate 1, due to the low concentration of doping, there are fewer defects, which can improve the charge mobility of silicon substrate and reduce the resistivity of silicon substrate; secondly, Sb element can reduce the differentiation of silicon band edge energy levels caused by doping, and Sb element has a high doping ionization rate.

[0046] In some specific embodiments, the concentration of antimony in the antimony-containing layer 4 is equal to or greater than 1E13 atoms / cm³. 3 The thickness d1 of the region is 2nm or more, for example, it can be 2nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, or any value between these values.

[0047] In some specific implementations, a / a1 is defined as u, where u ranges from 0.8 to 1E10. For example, it can be 0.8, 0.9, 1, 2, 5, 10, 50, 100, 500, 1000, 1E5, 5E5, E6, 5E6, 1E7, 5E7, 1E8, 5E8, 1E9, 5E9, 1E10, and any value between these values.

[0048] In some specific embodiments, u is 2 to 1E9. In some specific embodiments, u is 10 to 1E8. In some specific embodiments, u is 100 to 1E7.

[0049] In some specific embodiments, no interface passivation layer 2 is provided between the silicon substrate and the carrier separation layer. In this case, the range of u is 1 to 2, for example, u can be 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, or 2.0. By setting u within the above range, it is ensured that the concentration of antimony escaping from the silicon substrate into the carrier separation layer reaches a preset value, thereby reducing the bubble ratio and improving the passivation effect.

[0050] In some specific embodiments, an interface passivation layer 2 with impurity adsorption function is disposed between the silicon substrate and the carrier separation layer. In this case, u ranges from 0.8 to 1E10, for example, it can be 0.8, 0.9, 1, 2, 5, 10, 50, 100, 500, 1000, 1E5, 5E5, E6, 5E6, 1E7, 5E7, 1E8, 5E8, 1E9, 5E9, 1E10, and any value between these values. By setting u within the above range, it is ensured that the antimony concentration escaping from the silicon substrate to the carrier separation layer reaches a preset value, thereby reducing the bubble ratio and improving the passivation effect.

[0051] In some specific embodiments, an interface passivation layer 2 that does not adsorb impurities is provided between the silicon substrate and the carrier separation layer. In this case, u ranges from 2 to 1E9, for example, it can be 2, 3, 4, 5, 6, 7, 8, 9, 10, 50, 100, 500, 1000, 1E5, 5E5, E6, 5E6, 1E7, 5E7, 1E8, 5E8, 1E9, or any value between these values. By setting u within the above range, it is ensured that the antimony concentration escaping from the silicon substrate into the carrier separation layer reaches a preset value, thereby reducing the bubble ratio and improving the passivation effect.

[0052] The concentration of antimony in silicon substrate 1 is made to be 1E13~1E18 atoms / cm³. 3 And / or the concentration of antimony in antimony layer 4 is greater than 1E13 atoms / cm 3 The thickness d1 of the region is greater than 2nm. Since the recombination at the interface between the carrier separation layer and the silicon substrate 1 mainly comes from the carrier separation layer of a certain thickness close to the silicon substrate, by controlling the concentration of antimony element within the above range, the proportion of bubbles in the 2nm thickness range can be reduced, further improving the recombination problem caused by bubbles in the bottom layer of the carrier separation layer. This can basically solve the passivation problem of the entire carrier separation layer, thereby improving the efficiency of the solar cell.

[0053] In this application, the carrier separation layer can be selected from a doped semiconductor layer, a molybdenum oxide layer, a PEDOT:PSS layer, etc. When the carrier separation layer is a doped semiconductor layer 3, an interface passivation layer 2 is disposed between the silicon substrate 1 and the carrier separation layer. The interface passivation layer 2 can further improve the interface passivation effect between the silicon substrate and the carrier separation layer.

[0054] The materials and thicknesses of the doped semiconductor layer 3 and the interface passivation layer 2 can both be those known in the prior art. For example, the thickness of the doped semiconductor layer 3 can be 50 nm to 300 nm; the material of the doped semiconductor layer 3 can be selected from one or more of polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The thickness of the interface passivation layer 2 can be 0.1 nm to 5 nm; the material of the interface passivation layer 2 can be selected from one or more of silicon oxide, aluminum oxide, silicon nitride, molybdenum oxide, or intrinsic amorphous silicon. Since recombination at the interface between the carrier separation layer and the interface passivation layer 2 mainly originates from a certain thickness of the carrier separation layer close to the interface passivation layer 2, the above parameter range can reduce the proportion of bubbles within a 2 nm thickness range, further improving the recombination problem caused by bubbles in the bottom layer of the carrier separation layer. This can essentially solve the passivation problem of the entire carrier separation layer, thereby improving the efficiency of the solar cell.

[0055] In some specific embodiments, the concentration of antimony in the antimony-containing layer 4 of the carrier separation layer gradually decreases from the side closer to the silicon substrate 1 towards the side away from the silicon substrate 1. This arrangement is primarily because a higher concentration of antimony closer to the silicon substrate 1 results in fewer bubbles, thus reducing recombination problems caused by bubbles. Without bubbles in the silicon substrate, the escape of antimony from the silicon substrate 1 does not affect the passivation of the silicon substrate 1. Furthermore, surface recombination has a significant impact on overall recombination; therefore, a higher antimony concentration closer to the surface in the carrier separation layer 4 leads to better passivation at the interface.

[0056] Furthermore, as shown in Figure 2, the silicon substrate 1 has a B-type surface roughness in at least a portion of the region on the side near the interface passivation layer 2. x Elements, forming elements containing B x Layer 5. Among them, B x The element can be a Group 5 (e.g., phosphorus) or Group 6 (e.g., sulfur) element, or a Group 3 element, such as boron or aluminum. This is because at least a portion of the region near the interface passivation layer 2 contains B... x Elements that can form emitters or high / low junctions in silicon substrate 1 can passivate and further improve battery performance.

[0057] In some specific implementations, containing B x Layer 5, B x The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d2 of the region is greater than 20nm, for example, it can be 20nm, 50nm, 100nm, 200nm, 500nm, 1μm, 2μm, 5μm, and any value between these values.

[0058] In some specific embodiments, the doped semiconductor layer 3 contains B x The element, B, is present in the doped semiconductor layer 3. x The concentration of the element is b, and the range of b is 1E18~5E22 atoms / cm³. 3 The one containing B x B in layer 5 x The peak concentration of the element is 1 atom / cm³. 3Let b / b1 be defined as v, where v ranges from 0.5 to 1E10. For example, it can be 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 5, 10, 50, 100, 500, 1000, 1E5, 5E5, E6, 5E6, 1E7, 5E7, 1E8, 5E8, 1E9, 5E9, 1E10, or any value between these ranges. In some specific embodiments, v is 2 to 1E9. In some specific embodiments, v is 10 to 1E8. In some specific embodiments, v is 100 to 1E5.

[0059] In some specific implementations, the phosphorus concentration in the interface passivation layer 2 is higher than that in the carrier separation layer (doped semiconductor layer 3).

[0060] When B x When the element is phosphorus, v ranges from 0.5 to 1E10. When B x For other elements, v ranges from 1 to 1E10. B x It can be expanded into the silicon substrate 1 to form a predetermined concentration, such as B x Depending on its properties, the element can form an emitter or a high-low junction, improving the passivation effect. But B... x Excessive doping concentration introduces recombination centers into the silicon substrate 1, which degrades battery performance. In this application, by controlling the range of v, the passivation effect can be improved without affecting battery performance.

[0061] In some specific implementations, b1 / a1 is defined as w, where w > 1. For example, it can be 10, 100, 1000, 1E4, 5E4, 1E5, 5E5, 1E6, 5E6, 1E7, 5E7, 1E8, or any value between these. In some specific implementations, w > 100. In some specific implementations, w is greater than 1000. In some specific implementations, w is between 1E3 and 1E8.

[0062] In this application, a larger b1 results in better passivation of the emitter or high / low junction, leading to higher battery performance. Therefore, b1 cannot be too small, meaning w cannot be too small. If w is too small, the passivation effect of the emitter or high / low junction will deteriorate. Therefore, w should be greater than 1. However, excessively high b1 (i.e., excessively large w) will introduce recombination centers in the silicon substrate 1, thereby reducing battery performance. In this application, by controlling the range of w, the passivation effect can be improved without affecting battery performance.

[0063] In this application, by controlling w within the aforementioned range, the iVoc of the battery can be increased, thereby improving the passivation performance of the battery. Furthermore, regardless of whether the structure formed by the above-described n-type or p-type doping is used, the passivation performance of the resulting battery can be effectively improved.

[0064] In some specific implementations, d2 / d1 is defined as x, where x is greater than or equal to 1. For example, x can be 1, 10, 20, 100, 1000, 1E4, 5E4, 1E5, 5E5, 1E6, 5E6, 1E7, 5E7, 1E8, or any value between these values. In some specific implementations, x ranges from 10 to 1E8. In some specific implementations, x ranges from 20 to 1E7.

[0065] In this application, a larger d2 results in better passivation of the emitter or high-low junction, leading to higher battery performance. Therefore, d2 cannot be too small, meaning x cannot be too small; otherwise, the passivation effect of the emitter or high-low junction will deteriorate. However, excessively high d2 will cause the Auger recombination region to be too wide, thereby reducing battery performance. In this application, by controlling the range of x, the passivation effect can be improved without affecting battery performance.

[0066] In this application, similar to the effect of w described above, by controlling x within the aforementioned range, the iVoc of the battery can be increased, thus improving the passivation performance of the battery. Furthermore, regardless of whether the structure formed by the above-described n-type or p-type doping is used, the passivation performance of the resulting battery can be effectively improved.

[0067] In some specific embodiments, the peak concentration of antimony in the interface passivation layer 2 is a2, and the range of a2 is 1E13 to 1E18 atoms / cm. 3 The interface passivation layer 2 contains B x Element, B in interface passivation layer 2 x The peak concentration of the element is b2, and the range of b2 is 1E19~1E22 atoms / cm². 3 This is because B in interface passivation layer 2 x If the element concentration is too low, the carrier transport efficiency of the interface passivation layer 2 will decrease, and the concentration of b2 cannot reach 1E22 atoms / cm due to the influence of solid solubility. 3 That's all. On the other hand, the interface passivation layer 2 has 1E13~1E18 atoms / cm 3 The presence of antimony ensures that the carrier separation layer has a predetermined concentration of antimony.

[0068] In some specific implementations, b2 / a2 is defined as y, where y > 1. For example, it can be 1, 2, 5, 10, 50, 100, 500, 1000, 1E5, 5E5, E6, 5E6, 1E7, 5E7, 1E8, 5E8, 1E9, or any value between these values. In some specific implementations, the range of y is 10 to 1E9.

[0069] In some specific implementations, B xThe elements are selected from Group 5 or Group 6, and the concentration of antimony in antimony layer 4 is greater than 1E13 atoms / cm³. 3 The thickness d1 of the region is greater than 2 nm, and the range of w is 1E4 to 1E8. When B x When the element is selected from Group 5 or Group 6, the escaped antimony element is also a Group 5 element, which will increase the effective doping concentration of the carrier separation layer, thereby increasing the electron concentration of the carrier separation layer, improving the passivation effect and conductivity of the carrier separation layer, reducing the transmission resistance of the carrier separation layer, and reducing the interface resistance between the silicon substrate and the carrier separation layer.

[0070] Furthermore, B in the doped semiconductor layer 3 x The concentration of the element is 1E19~5E22 atoms / cm³ 3 The B mentioned x When the element is phosphorus, it contains B. x The layer is a phosphorus-containing layer, and the concentration of phosphorus in the phosphorus-containing layer is greater than 1E17 atoms / cm³. 3 The thickness d2 of the region is 20nm or more, preferably 30nm or more, 40nm or more, or 50nm or more, and more preferably 120nm or more, 200nm or more, or 300nm or more.

[0071] In some specific implementations, B x The elements are selected from Group III, and the concentration of antimony in the antimony-containing layer 4 is greater than 1E13 atoms / cm³. 3 The thickness d1 of the region is 3 nm or more, and the preferred range of w is 1E3 to 1E7.

[0072] In one specific embodiment, when the carrier separation layer is a silicon thin film, when B x When it is a Group 3 element, the carrier separation layer is P-type. Therefore, as a Group 5 element, antimony has a faster doping rate in the carrier separation layer, resulting in a thicker antimony-containing layer.

[0073] Furthermore, B in the doped semiconductor layer 3 x The concentration of the element is 1E18~5E21 atoms / cm³ 3 When B x When the element is boron, it contains B. x The layer is a boron-containing layer, and the concentration of boron in the boron-containing layer is greater than 1E17 atoms / cm³. 3The thickness d2 of the region is 30nm or more, preferably 40nm or more, 50nm or more, and even more preferably 100nm or more, 200nm or more, 300nm or more, 400nm or more, 500nm or more, 600nm or more, 700nm or more, 800nm ​​or more, 900nm or more, 1000nm or more, 1100nm or more, or 1200nm or more.

[0074] Those skilled in the art will understand that the above-described silicon solar cells can encompass various types of silicon solar cells having the structure shown in Figure 2, as long as the cell structure, the antimony element in the cell, and the B... x The concentration and distribution of elements within the battery must meet the above requirements. For example, the silicon solar cell mentioned in this application can be a TOPCon cell, a partial TOPCon cell, a back-contact cell, an HPBC cell, etc.

[0075] In one specific embodiment, the silicon solar cell is a TOPCon cell, which has the structure shown in Figure 2. Typically, a TOPCon cell includes: a silicon substrate 1 containing antimony; an interface passivation layer 2 formed on the silicon substrate 1; and a doped semiconductor layer 3 formed on the interface passivation layer 2. The doped semiconductor layer 3 has at least a portion of an antimony-containing layer 4 on the side closest to the silicon substrate 1, with a peak antimony concentration of a1 in the antimony-containing layer 4, and a1 being equal to or greater than 1E13 atoms / cm². 3 The doped semiconductor layer 3 can be a p-type doped semiconductor layer or an n-type doped semiconductor layer.

[0076] When the doped semiconductor layer 3 is a p-type doped semiconductor layer, and an n-type doped semiconductor layer is formed on the side of the silicon substrate 1 away from the p-type doped semiconductor layer, the peak concentration of antimony in the antimony-containing layer is a. 1p , change a / a 1p Defined as u p u p The range is 0.8 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E7.

[0077] In one specific manner, the concentration of antimony in the antimony-containing layer is equal to or greater than 1E13 atoms / cm³. 3 The thickness d of the region 1p It is 3nm or larger.

[0078] When the doped semiconductor layer 3 is an n-type doped semiconductor layer, and a p-type doped semiconductor layer is formed on the side of the silicon substrate 1 away from the n-type doped semiconductor layer, the peak concentration of antimony in the antimony-containing layer is a. 1n , change a / a1n Defined as u n u n The range is 0.8 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E7.

[0079] In one specific manner, the concentration of antimony in the antimony-containing layer is equal to or greater than 1E13 atoms / cm³. 3 The thickness d of the region 1n It is 2nm or larger.

[0080] Will u, u n or u p By controlling the process within the above range, Auger recombination and bubbles can be balanced. The more antimony escapes, the fewer bubbles there are, the better the surface passivation, and the lower the Auger recombination in the semiconductor layer.

[0081] In one specific embodiment, the structure shown in Figure 2 is formed on the front or back side of a silicon substrate. When the structure shown in Figure 2 is formed on the back side of the silicon substrate, an interface passivation layer 2 is disposed on the back side of the silicon substrate, and a p-type doped semiconductor layer or an n-type doped semiconductor layer is disposed on the side of the interface passivation layer 2 facing away from the silicon substrate. That is, the carrier separation layer and the interface passivation layer 2 are formed on the back side of the silicon substrate, forming a PN junction with the silicon substrate. In this case, since the antimony-doped silicon substrate has less interstitial doping, less recombination occurs, and the TOPCon structure shown in Figure 2, with the emitter disposed on the back side, has a more advantageous battery performance.

[0082] In one specific embodiment, the silicon solar cell is a partial TOPCon cell. As shown in Figure 3, the partial TOPCon cell includes: a silicon substrate 1 containing antimony; a first interface passivation layer 21 and a second interface passivation layer 22, respectively formed on opposite sides of the silicon substrate 1; a first doped semiconductor layer 31 and a second doped semiconductor layer 32, both doped semiconductor layers formed on the side of the first interface passivation layer 21 away from the silicon substrate 1 and the side of the second interface passivation layer 22 away from the silicon substrate 1, respectively; the area of ​​the first doped semiconductor layer 31 is smaller or larger than the area of ​​the second doped semiconductor layer 32. Figure 3 shows a case where the first doped semiconductor layer 31 is formed on a portion of the silicon substrate 1, and the second doped semiconductor layer 32 is formed on the entire area of ​​the silicon substrate 1; however, those skilled in the art will fully understand that such a structure is merely exemplary. Those skilled in the art can design its structure based on their understanding of partial TOPCon cells.

[0083] The first doped semiconductor layer 31 is doped with a Group 3 element, and the second doped semiconductor layer 32 is doped with a Group 5 or Group 6 element. The first doped semiconductor layer 31 has a first antimony-containing layer 41 containing antimony in at least a portion of its region near the first interface passivation layer 21. The second doped semiconductor layer 32 has a second antimony-containing layer 42 containing antimony in at least a portion of its region near the second interface passivation layer 22. The peak concentration of antimony in the first antimony-containing layer 41 is a. 1p , and a 1p Equal to or greater than 1E13 atoms / cm 3 The peak concentration of antimony in the second antimony-containing layer 42 is a. 1n , and a 1n Equal to or greater than 1E13 atoms / cm 3 .

[0084] Those skilled in the art will understand that the concentration and distribution of antimony and dopant elements in the first interface passivation layer 21 and the second interface passivation layer 22, as well as the first doped semiconductor layer 31 and the second doped semiconductor layer 32, all satisfy the above description of the interface passivation layer 2 and the doped semiconductor layer 3.

[0085] In one specific embodiment, for the battery shown in Figure 3, the concentration of antimony in the first antimony-containing layer is greater than 1E13 atoms / cm³. 3 The thickness d of the region 1p The concentration of antimony in the second antimony-containing layer is greater than or equal to 1E13 atoms / cm³. 3 The thickness d of the region 1n , that is, d 1p ≥d 1n .

[0086] Specifically, the concentration of antimony in the first antimony-containing layer 41 is equal to or greater than 1E13 atoms / cm³. 3 The thickness d of the region 1p The antimony concentration in the second antimony-containing layer 42 is greater than 3nm, and is equal to or greater than 1E13 atoms / cm. 3 The thickness d of the region 1n It is 2nm or larger.

[0087] The concentration of antimony in the antimony-containing layer of the first doped semiconductor layer 31 gradually decreases in the direction from the side close to the silicon substrate 1 to the side away from the silicon substrate 1, and the concentration of antimony in the antimony-containing layer of the second doped semiconductor layer 32 gradually decreases in the direction from the side close to the silicon substrate 1 to the side away from the silicon substrate 1.

[0088] will a / a 1p Defined as u p up The range is 0.8 to 1E10, preferably 2 to 1E9, more preferably 10 to 1E8, and most preferably 100 to 1E7; a / a 1n Defined as u n u n The range is 0.8 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E7.

[0089] The silicon substrate 1 has a B in at least a partial region on the side near the first interface passivation layer 21. xp Elements, forming elements containing B xp Layer 51; The silicon substrate 1 has a B layer in at least a partial region on the side near the second interface passivation layer 22. xn Elements, forming elements containing B xn Layer 52; containing B xp Layer 51, B xp The concentration of the element is greater than 1E17toms / cm 3 The thickness d of the region 2p 30nm or larger; contains B xn Layer 52, B xn The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d of the region 2n It is above 20nm.

[0090] Among them, B xp The elements are selected from Group 3, and B is present in the first doped semiconductor layer 31. xp The concentration of the element is b p b p The range is 1E18~5E21 atoms / cm 3 Contains B xp B in layer 51 xp The peak concentration of the element is b 1p B xn The elements are selected from Group 5 or Group 6, and B is present in the second doped semiconductor layer 32. xn The concentration of the element is b n b n The range is 1E19~5E22 atoms / cm 3 Contains B xn B in layer 52 xn The peak concentration of the element is b 1n b p / b 1p Defined as v p v p The range is 1 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E5. (The last part, "b")n / b 1n Defined as v n v n The range is 0.5 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E5.

[0091] b 1p / a 1p Defined as w p w p >1, preferably >100, preferably greater than 1000, preferably 1E3 to 1E8, and even more preferably 1E3 to 1E7. (The last part, "b", appears to be a typo and can be left as is.) 1n / a 1n Defined as w n w n >1, preferably >100, preferably greater than 1000, preferably 1E3 to 1E8, and more preferably 1E4 to 1E8. In this application, by using w p Controlling the voltage within the above range can improve the battery's iVoc and passivation performance. In this application, by controlling the voltage within the range... n Controlling the iVoc within the above range can improve the battery's iVoc and enhance its passivation performance.

[0092] d 2p / d 1p Greater than or equal to 1, preferably 10 to 1E8, more preferably 20 to 1E7, d 2n / d 1n Greater than or equal to 1, preferably 10 to 1E8, more preferably 20 to 1E7; preferably d 1p ≥d 1n ; and / or d 2p >d 2n d is preferred 2p -d 2n ≥5nm, preferably ≥10nm.

[0093] Among them, due to control, d 2p >d 2n When light shines on the silicon substrate, a single photon excites an electron-hole pair. Under the separation effect of the PN junction, the electron-hole pair separates at the PN junction, forming electron carriers and hole carriers. 2p >d 2n This ensures effective carrier separation within the PN junction. Since the p-region is the emitter region, better passivation is required; therefore, the d-region... 1p ≥d 1nThis allows more antimony to escape, which is beneficial for the passivation of the carrier selection layer interface in the emitter region. The emitter is even more important for the battery; that is, a better passivation effect of the emitter can lead to better battery efficiency.

[0094] In this application, the w mentioned above p The effect is similar, by using d 2p / d 1p Controlling the voltage within the above range can improve the battery's iVoc and passivation performance. In this application, [the following is related to the above-mentioned w] n The effect is similar, by using d 2n / d 1n Controlling the iVoc within the above range can improve the battery's iVoc and enhance its passivation performance.

[0095] The first interface passivation layer 21 contains antimony, and the peak concentration of antimony in the first interface passivation layer 21 is a. 2p a 2p The range is 1E13~1E18 atoms / cm 3 The first interface passivation layer 21 contains B. xp Element, B in the first interface passivation layer 21 xp The peak concentration of the element is b 2p b 2p The range is 1E19~1E22 atoms / cm 3 Preferred option b 2p / a 2p >1, preferably 10~1E9.

[0096] The second interface passivation layer 22 contains antimony, and the peak concentration of antimony in the second interface passivation layer 22 is a. 2n a 2n The range is 1E13~1E18 atoms / cm 3 The second interface passivation layer 22 contains B xn Element, B in the second interface passivation layer 22 xn The peak concentration of the element is b 2n b 2n The range is 1E19~1E22 atoms / cm 3 Preferred option b 2n / a 2n >1, preferably 10~1E9.

[0097] When B xn When the element is phosphorus, it contains B. xn The concentration of phosphorus in layer 52 is greater than 1E17 atoms / cm 3 The thickness d of the region 2nThe thickness is 20nm or greater, preferably 30nm or greater, 40nm or greater, or 50nm or greater, and more preferably d. 2n For 120nm and above, 200nm and above, or 300nm and above. When B xp When the element is boron, it contains B. xp The concentration of boron in layer 51 is greater than 1E17 atoms / cm 3 The thickness d of the region 2p The thickness is 30nm or greater, preferably 40nm or greater or 50nm or greater, and the thickness d is even more preferred. 2p For 100nm and above, 200nm and above, 300nm and above, 400nm and above, 500nm and above, 600nm and above, 700nm and above, 800nm ​​and above, 900nm and above, 1000nm and above, 1100nm and above, or 1200nm and above.

[0098] In one specific embodiment, the silicon solar cell is a back-contact cell. Figures 4-7 show the structures of several typical back-contact cells. A back-contact cell includes: a silicon substrate 1 containing antimony; a first interface passivation layer 21 and a second interface passivation layer 22 formed on the same side of the silicon substrate 1; a first doped semiconductor layer 31 and a second doped semiconductor layer 32, both doped semiconductor layers formed on the side of the first interface passivation layer 21 away from the silicon substrate 1 and the side of the second interface passivation layer 22 away from the silicon substrate 1, respectively; the first doped semiconductor layer 31 is doped with a Group 3 element, and the second doped semiconductor layer 32 is doped with a Group 5 or Group 6 element. Specifically, the first doped semiconductor layer 31 has a first antimony-containing layer 41 containing antimony in at least a portion of its region near the first interface passivation layer 21; the second doped semiconductor layer 32 has a second antimony-containing layer 42 containing antimony in at least a portion of its region near the second interface passivation layer 22; the peak concentration of antimony in the first antimony-containing layer 41 is a. 1p , and a 1p Equal to or greater than 1E13 atoms / cm 3 The peak concentration of antimony in the second antimony-containing layer 42 is a. 1n , and a 1n Equal to or greater than 1E13 atoms / cm 3 The first interface passivation layer 21 and the first doped semiconductor layer 31 form a p-type region, and the second interface passivation layer 22 and the second doped semiconductor layer 32 form an n-type region.

[0099] The concentrations and distributions of antimony and dopant elements in the silicon substrate 1, the first interface passivation layer 21 and the second interface passivation layer 22, as well as the first doped semiconductor layer 31 and the second doped semiconductor layer 32, can be found in the above description of the local TOPCon cell.

[0100] In one specific embodiment, for the battery shown in Figure 4-7, the concentration of antimony in the first antimony-containing layer is greater than 1E13 atoms / cm³. 3 The thickness d of the region 1p The concentration of antimony in the second antimony-containing layer is greater than or equal to 1E13 atoms / cm³. 3 The thickness d of the region 1n , that is, d 1p ≥d 1n .

[0101] As shown in Figure 4-7, there is a gap between the p-type region and the n-type region. A substrate passivation layer 6 is disposed in the gap between the p-type region and the n-type region. The substrate passivation layer 6 covers the gap between the silicon substrate 1 that is not covered by the p-type region and the n-type region.

[0102] Furthermore, an antimony-containing region is formed in the area of ​​the passivation layer 6 near the silicon substrate 1, and the concentration of antimony in the antimony-containing region is a3, where a3 is greater than 1E13 atoms / cm. 3 The thickness d of the region 1钝化层 d 1钝化层 ≤d 1n ≤d 1p Preferably, the d 1钝化层 ≥1nm.

[0103] Where d 1钝化层 ≤d 1n ≤d 1p Because the passivation layer is not an electrically conductive region, it is not subject to many restrictions. High-quality passivation materials such as alumina / silicon nitride can be used directly for passivation. Therefore, less antimony is needed to reduce bubbles and improve the passivation effect in the passivation region. 1n ≤d 1p The technical effects can be found in the above text, and will not be repeated here.

[0104] In this application, by controlling d 1钝化层 ≤d 1n ≤d 1p It can improve the passivation performance of the PN region and further improve the iVoc of the spacer region, thus improving the passivation performance of the battery.

[0105] The spacer region between the p-type region and the n-type region can be an intrinsic spacer region. The intrinsic spacer region covers the spacer region of the silicon substrate 1 that is not covered by the p-type region and the n-type region. Starting from the silicon substrate 1 and moving away from the silicon substrate, it sequentially includes an intrinsic semiconductor layer 8 containing antimony and an intrinsic semiconductor layer 9 that does not contain antimony. Preferably, starting from the silicon substrate and moving away from the silicon substrate, it sequentially includes an intrinsic region interface passivation layer 7, an intrinsic semiconductor layer 8 containing antimony, and an intrinsic semiconductor layer 9 that does not contain antimony.

[0106] The concentration of antimony in the intrinsic semiconductor layer 8 containing antimony is a3, and a3 is greater than 1E13 atoms / cm. 3 The thickness d of the region 1i d 1i ≤d 1n ≤d 1p ; Preferably the d 1i ≥2nm.

[0107] In this application, control d 1钝化层 ≤d 1n This allows for improved passivation of the passivation zone without requiring a large amount of antimony to reduce bubbles.

[0108] In this application, because the intrinsic semiconductor passivation performance is slightly low, and the intrinsic semiconductor layer generally undergoes few thermal processes, its crystal structure may be poor. Therefore, a slightly higher amount of antimony is needed to improve the passivation effect of the underlying layer. Thus, controlling d... 1i A wavelength of ≥2nm can better maintain the passivation effect.

[0109] In this application, by controlling d 1i ≤d 1n ≤d 1p Based on improving the passivation performance of the PN region, the iVoc in the spacer region can be further increased, which can improve the passivation performance of the battery.

[0110] The intrinsic region passivation layer 7, located near the silicon substrate 1, may contain antimony. The concentration of antimony in the intrinsic region passivation layer 7 is a3, where a3 is greater than 1E13 atoms / cm³. 3 The thickness d of the region 1钝 化层 d 1钝化层 ≤d 1n ≤d 1p Preferably, the d 1钝化层 ≥2nm. In this application, by using d 1钝化层 ≤d 1n ≤d 1pBy controlling the values ​​within the above range, the passivation performance of the PN region can be improved, and the iVoc in the spacer region can be further increased, which can improve the passivation performance of the battery.

[0111] Furthermore, an intrinsic region side interface passivation layer 10 may be provided between the intrinsic interval region and the p-type region or between the intrinsic interval region and the n-type region. The side interface passivation layer 10 may be provided on the side closer to the p-type region or on the side closer to the n-type region.

[0112] In one specific embodiment, the silicon solar cell is a back-contact cell with an HPBC structure. As shown in Figure 8, the HPBC back-contact cell includes: a silicon substrate 1 containing antimony, an interface passivation layer 2 formed on the silicon substrate 1, a doped semiconductor layer 3 formed on the interface passivation layer 2 and being an n-type doped semiconductor layer to form an n-type region, a p-region electrode 11 formed on the side of the silicon substrate with the n-type doped semiconductor layer and spaced apart from the n-type doped semiconductor layer, and a BSF layer formed in the silicon substrate 1 corresponding to the p-region electrode 11, wherein the BSF layer and the p-region electrode have the same metal element. The doped semiconductor layer 3 has at least a portion of an antimony-containing layer 4 formed with antimony on the side closest to the silicon substrate 1, and the peak concentration of antimony in the antimony-containing layer 4 is a. 1n , and a 1n Equal to or greater than 1E13 atoms / cm 3 .

[0113] The p-region electrode can be a metal electrode known in the art that can form a p-region, such as an aluminum electrode.

[0114] The concentrations and distributions of antimony and dopant elements in silicon substrate 1, interface passivation layer 2, doped semiconductor layer 3, and antimony-containing layer 4 can be found in the above description of dopant element B. x This is a description of the element selected from the fifth or sixth main family.

[0115] This application also provides a solar cell module, which includes any of the aforementioned silicon solar cells.

[0116] Example

[0117] This application provides a general and / or specific description of the materials and test methods used in the experiments. In the following examples, unless otherwise specified, % represents wt%, i.e., weight percentage. Reagents or instruments used, unless otherwise specified, are all commercially available conventional reagent products.

[0118] Preparation Example

[0119] Silicon wafers with different antimony and phosphorus concentrations were prepared based on the method described in CN117702269A. The concentrations of phosphorus and antimony in the prepared silicon wafers are shown in Table 1.

[0120] Example 1: Comparison of bubble test results (containing antimony concentration)

[0121] n-type silicon wafers were polished with an alkaline solution, followed by acid cleaning, slow water washing and drying. After drying, they were placed in an LPCVD furnace tube for single-sided deposition of a tunneling oxide layer and an amorphous silicon layer. Then, a crystallization treatment was performed at 900℃. Each experimental tube contained 1600 silicon wafers, and 12 wafers were randomly selected from each tube. The surfaces with full poly areas were checked for the presence of bubbles. Statistical data are shown in Table 1 below.

[0122] Table 1

[0123] As can be seen, the number of poly wafers with bubbles decreased significantly after using antimony-containing silicon wafers. The number of batches with poly bubbles also decreased significantly.

[0124] Example 2: Comparative Test of Passivation Quality of Boron-Doped Poly

[0125] The n-type silicon wafer prepared in Example 1 above (using a phosphorus concentration of 1E15 atoms / cm) was used. 3 The n-type phosphorus-containing silicon wafers and antimony concentration are 1E15 atoms / cm³. 3 The n-type antimony-containing silicon wafers were polished with an alkaline solution, followed by acid cleaning, slow water washing and drying. After drying, they were placed in an LPCVD furnace tube for single-sided deposition of a tunneling oxide layer and an amorphous silicon layer. Then, boron diffusion doping crystallization was performed (maximum doping temperature 950℃, using a BBr3 source). The generated BSG (borosilicate glass) was removed using HF, and then double-sided alumina + silicon nitride films were deposited. iVoc testing was then performed using a Sinton analyzer. The test results are shown in Table 2.

[0126] Table 2

[0127] As can be seen, the iVoc of the antimony-containing silicon wafer is significantly increased, indicating a significant improvement in passivation performance.

[0128] Example 3: Comparative Test of Passivation Quality of Phosphorus-Doped Poly

[0129] The n-type silicon wafer prepared in Example 1 above (using a phosphorus concentration of 1E15 atoms / cm) was used. 3 The n-type phosphorus-containing silicon wafers and antimony concentration are 1E15 atoms / cm³. 3The n-type antimony-containing silicon wafers were polished with an alkaline solution, followed by acid cleaning, slow water washing and drying. After drying, they were placed in an LPCVD furnace tube for single-sided deposition of a tunneling oxide layer and an amorphous silicon layer. Then, phosphorus diffusion doping crystallization was performed (doping temperature up to 850℃, using a POCl3 source). The generated PSG (phosphosilicate glass) was removed using HF, and then double-sided alumina + silicon nitride films were deposited. iVoc testing was then performed using a Sinton analyzer, and the results are shown in Table 3.

[0130] Table 3

[0131] As can be seen, the iVoc of the antimony-containing silicon wafer is significantly increased, indicating a significant improvement in passivation performance.

[0132] Although the embodiments of this application have been described above in conjunction with the specific embodiments described, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art can make many other forms based on the teachings of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

Claims

1. A silicon solar cell, comprising: A silicon substrate, wherein the silicon substrate contains antimony, and A carrier separation layer is formed on the silicon substrate, wherein, The carrier separation layer has an antimony-containing layer in at least a portion of its region on the side closest to the silicon substrate, the antimony-containing layer containing antimony. The peak concentration of antimony in the antimony-containing layer is a1, and a1 is equal to or greater than 1E13 atoms / cm. 3 .

2. The silicon solar cell according to claim 1, wherein, The concentration of antimony in the silicon substrate is denoted as 'a', and the range of 'a' is 1E13 to 1E18 atoms / cm³. 3 ;or The concentration of antimony in the antimony-containing layer is greater than or equal to 1E13 atoms / cm³. 3 The thickness d1 of the region is greater than 2nm.

3. The silicon solar cell according to claim 2, wherein, The carrier separation layer is selected from a doped semiconductor layer, a molybdenum oxide layer, or a PEDOT:PSS layer. When the carrier separation layer is a doped semiconductor layer, an interface passivation layer is provided between the silicon substrate and the carrier separation layer. Preferably, the material of the interface passivation layer is selected from one or more of silicon oxide, aluminum oxide, silicon nitride, molybdenum oxide, or intrinsic amorphous silicon.

4. The silicon solar cell according to any one of claims 1 to 3, wherein, The concentration of antimony in the antimony-containing layer of the carrier separation layer gradually decreases from the side closer to the silicon substrate to the side away from the silicon substrate.

5. The silicon solar cell according to claim 2, wherein, Define a / a1 as u, where u ranges from 0.8 to 1E10, preferably from 2 to 1E9, further preferably from 10 to 1E8, and most preferably from 100 to 1E7.

6. The silicon solar cell according to claim 3, wherein, The silicon substrate has a B in at least a portion of the region on the side near the interface passivation layer. x Elements, forming elements containing B x layer, The B-containing x Layer B x The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d2 of the region is greater than 20 nm.

7. The silicon solar cell according to claim 6, wherein, The doped semiconductor layer contains B x The element, wherein the doped semiconductor layer contains B x The concentration of the element is b, and the range of b is 1E18~5E22 atoms / cm³. 3 , The B-containing x B in the layer x The peak concentration of the element is b1. b / b1 is defined as v, and the range of v is 0.5 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E5.

8. The silicon solar cell according to claim 7, wherein, Let b1 / a1 be defined as w, where w>1, preferably w>100, preferably w>1000, and even more preferably 1E3 to 1E8.

9. The silicon solar cell according to claim 6, wherein, Let d2 / d1 be defined as x, where x is greater than or equal to 1, preferably in the range of 10 to 1E8, and more preferably in the range of 20 to 1E7.

10. The silicon solar cell according to any one of claims 6 to 9, wherein, The interface passivation layer contains antimony, and the peak concentration of antimony in the interface passivation layer is a2, with a2 ranging from 1E13 to 1E18 atoms / cm. 3 , and / or The interface passivation layer contains B x Element, B in the interface passivation layer x The peak concentration of the element is b2, and the range of b2 is 1E19~1E22 atoms / cm². 3 , Define b2 / a2 as y, where y>1, and preferably the range of y is 10 to 1E9.

11. The silicon solar cell according to claim 8, wherein, The B x When the element is selected from Group 5 or Group 6, the concentration of antimony in the antimony-containing layer is equal to or greater than 1E13 atoms / cm³. 3 The thickness d1 of the region is 2 nm or more, and preferably the range of w is 1E4 to 1E8.

12. The silicon solar cell according to claim 11, wherein, B in the doped semiconductor layer x The concentration of the element is 1E19~5E22 atoms / cm³ 3 ; Preferably, B x The element is phosphorus, and at this time it contains B. x The layer is a phosphorus-containing layer, and the concentration of phosphorus in the phosphorus-containing layer is greater than 1E17 atoms / cm³. 3 The thickness d2 of the region is 20nm or more, preferably 30nm or more, 40nm or more, or 50nm or more, and more preferably 120nm or more, 200nm or more, or 300nm or more.

13. The silicon solar cell according to claim 8, wherein, The B x When the element is selected from Group III, the concentration of antimony in the antimony-containing layer is greater than 1E13 atoms / cm³. 3 The thickness d1 of the region is 3 nm or more, and preferably the range of w is 1E3 to 1E7.

14. The silicon solar cell according to claim 13, wherein, B in the doped semiconductor layer x The concentration of the element is 1E18~5E21 atoms / cm³ 3 ; Preferably, B x When the element is boron, it contains B. x The layer is a boron-containing layer, and the concentration of boron in the boron-containing layer is greater than 1E17 atoms / cm³. 3 The thickness d2 of the region is 30nm or more, preferably 40nm or more, 50nm or more, and even more preferably 100nm or more, 200nm or more, 300nm or more, 400nm or more, 500nm or more, 600nm or more, 700nm or more, 800nm ​​or more, 900nm or more, 1000nm or more, 1100nm or more, or 1200nm or more.

15. The silicon solar cell according to any one of claims 3 and 6 to 14, wherein, When the doped semiconductor layer is a p-type doped semiconductor layer, and an n-type doped semiconductor layer is formed on the side of the silicon substrate away from the p-type doped semiconductor layer, the peak concentration of antimony in the antimony-containing layer is a. 1p , change a / a 1p Defined as u p u p The range is 0.8 to 1E10, preferably 2 to 1E9, more preferably 10 to 1E8, and most preferably 100 to 1E7; or When the doped semiconductor layer is an n-type doped semiconductor layer, and a p-type doped semiconductor layer is formed on the side of the silicon substrate away from the n-type doped semiconductor layer, the peak concentration of antimony in the antimony-containing layer is a. 1n , change a / a 1n Defined as u n u n The range is 0.8 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E7.

16. The silicon solar cell according to any one of claims 3 and 6 to 14, wherein, When the doped semiconductor layer is a p-type doped semiconductor layer, and an n-type doped semiconductor layer is formed on the silicon substrate near the p-type doped semiconductor layer, the concentration of antimony in the antimony-containing layer is equal to or greater than 1E13 atoms / cm³. 3 The thickness d of the region 1p 3nm or larger; or When the doped semiconductor layer is an n-type doped semiconductor layer, and a p-type doped semiconductor layer is formed on the silicon substrate near the side of the n-type doped semiconductor layer, the concentration of antimony in the antimony-containing layer is equal to or greater than 1E13 atoms / cm³. 3 The thickness d of the region 1n It is 2nm or larger.

17. The silicon solar cell according to any one of claims 3 and 6 to 14, wherein, The carrier separation layer and the interface passivation layer are formed on the back side of the silicon substrate, forming a PN junction with the silicon substrate.

18. The silicon solar cell according to any one of claims 3 and 6 to 14, wherein, The interface passivation layer includes a first interface passivation layer and a second interface passivation layer, which are respectively formed on both sides of the silicon substrate. The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, which are respectively formed on the side of the first interface passivation layer away from the silicon substrate and the side of the second interface passivation layer away from the silicon substrate. The first doped semiconductor layer is doped with a Group 3 element, and the second doped semiconductor layer is doped with a Group 5 or Group 6 element. The area of ​​the first doped semiconductor layer is smaller or larger than the area of ​​the second doped semiconductor layer. The first doped semiconductor layer has a first antimony-containing layer in at least a portion of its region near the first interface passivation layer, the first antimony-containing layer containing antimony. The second doped semiconductor layer has a second antimony-containing layer in at least a portion of its region near the second interface passivation layer, the second antimony-containing layer containing antimony. The peak concentration of antimony in the first antimony-containing layer is a. 1p , and a 1p Equal to or greater than 1E13 atoms / cm 3 The peak concentration of antimony in the second antimony-containing layer is a. 1n , and a 1n Equal to or greater than 1E13 atoms / cm 3 .

19. The silicon solar cell according to claim 18, wherein, The concentration of antimony in the first antimony-containing layer is greater than or equal to 1E13 atoms / cm. 3 The thickness of the region is d 1p ; The concentration of antimony in the second antimony-containing layer is greater than or equal to 1E13 atoms / cm. 3 The region is of thickness d 1n , that is, d 1p ≥d 1n .

20. The silicon solar cell according to claim 19, wherein, The silicon substrate has a B in at least a portion of the region on the side near the first interface passivation layer. xp Elements, forming elements containing B xp layer; The silicon substrate has a B in at least a portion of the region on the side near the second interface passivation layer. xn Elements, forming elements containing B xn layer; The B-containing xp Layer B xp The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d of the region 2p 30nm and above; The B-containing xn Layer B xn The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d of the region 2n It is above 20nm.

21. The silicon solar cell according to any one of claims 3 and 6 to 14, wherein, The interface passivation layer includes a first interface passivation layer and a second interface passivation layer, which are formed on the same side of the silicon substrate. The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, which are formed on the side of the first interface passivation layer away from the silicon substrate and the side of the second interface passivation layer away from the silicon substrate, respectively. The first doped semiconductor layer is doped with a Group 3 element, and the second doped semiconductor layer is doped with a Group 5 or Group 6 element. The first interface passivation layer and the first doped semiconductor layer form a p-type region; the second interface passivation layer and the second doped semiconductor layer form an n-type region; The first doped semiconductor layer has a first antimony-containing layer in at least a portion of its region near the first interface passivation layer, the first antimony-containing layer containing antimony. The second doped semiconductor layer has a second antimony-containing layer in at least a portion of its region near the second interface passivation layer, the second antimony-containing layer containing antimony. The peak concentration of antimony in the first antimony-containing layer is a. 1p , and a 1p Equal to or greater than 1E13 atoms / cm 3 The peak concentration of antimony in the second antimony-containing layer is a. 1n , and a 1n Equal to or greater than 1E13 atoms / cm 3 .

22. The silicon solar cell according to claim 21, wherein, The concentration of antimony in the first antimony-containing layer is greater than or equal to 1E13 atoms / cm. 3 The thickness of the region is d 1p ; The concentration of antimony in the second antimony-containing layer is greater than or equal to 1E13 atoms / cm. 3 The thickness of the region is d 1n , that is, d 1p ≥d 1n .

23. The silicon solar cell according to claim 22, wherein, The silicon substrate has a B in at least a portion of the region on the side near the first interface passivation layer. xp Elements, forming elements containing B xp layer; The silicon substrate has a B in at least a portion of the region on the side near the second interface passivation layer. xn Elements, forming elements containing B xn layer; The B-containing xp Layer B xp The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d of the region 2p 30nm and above; The B-containing xn Layer B xn The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d of the region 2n It is above 20nm.

24. The silicon solar cell according to claim 20 or 23, wherein, d 2p / d 1p Greater than or equal to 1, preferably 10 to 1E8, more preferably 20 to 1E7. d 2n / d 1n Greater than or equal to 1, preferably 10 to 1E8, and more preferably 20 to 1E7; Preferred d 2p >d 2n , preferred d 2p -d 2n ≥5nm, preferably ≥10nm.

25. The silicon solar cell according to claim 22, wherein, There is a gap between the p-type and n-type regions. A substrate passivation layer is disposed in the gap between the p-type and n-type regions, and the substrate passivation layer covers the gap region of the silicon substrate that is not covered by the p-type and n-type regions. An antimony-containing region is formed in the region of the passivation layer near the silicon substrate, and the concentration of antimony in the antimony-containing region is a3, where a3 is greater than 1E13 atoms / cm. 3 The thickness d of the region 1钝化层 , d 1钝化层 ≤d 1n ≤d 1p , Preferably the d 1钝化层 ≥1nm.

26. The silicon solar cell according to claim 25, wherein, An intrinsic spacer region is provided between the p-type and n-type regions, and the intrinsic spacer region covers the spacer region of the silicon substrate that is not covered by the p-type and n-type regions. Along the thickness direction of the silicon substrate, in a direction away from the silicon substrate, the spacer region of the silicon substrate sequentially includes an intrinsic semiconductor layer containing antimony and an intrinsic semiconductor layer without antimony. Preferably, along the thickness direction of the silicon substrate, from the silicon substrate toward the back side of the silicon substrate, the intrinsic region interface passivation layer, the intrinsic semiconductor layer containing antimony, and the intrinsic semiconductor layer without antimony are sequentially included. The concentration of antimony in the intrinsic semiconductor layer containing antimony is a3, and a3 is greater than 1E13 atoms / cm. 3 The thickness of the region is d 1i , d 1i ≤d 1n ≤d 1p ; Preferably the d 1i ≥2nm; Preferably, the intrinsic region passivation layer contains antimony in the region near the silicon substrate, and the concentration of antimony in the intrinsic region passivation layer is a3, where a3 is greater than 1E13 atoms / cm³. 3 The thickness d of the region 1钝化层 d 1钝 化层 ≤d 1n ≤d 1p Preferably, the d 1钝化层 ≥2nm.

27. The silicon solar cell according to claim 26, wherein, An intrinsic region side interface passivation layer is provided between the intrinsic interval region and the p-type region or between the intrinsic interval region and the n-type region.

28. The silicon solar cell according to any one of claims 3 and 6 to 14, The doped semiconductor layer is an n-type doped semiconductor layer to form an n-type region. It also includes: p-region electrodes are formed on one side of the silicon substrate having an n-type doped semiconductor layer and are spaced apart from the n-type doped semiconductor layer. as well as A BSF layer is formed in the silicon substrate corresponding to the p-region electrode, and the BSF layer and the p-region electrode have the same metal element. The peak concentration of antimony in the antimony-containing layer is a. 1n , change a / a 1n Defined as u n u n The range is 0.8 to 1E10, preferably 2 to 1E9, further preferably 10 to 1E8, and most preferably 100 to 1E7.

29. The silicon solar cell according to claim 28, wherein, The silicon substrate has a B in at least a portion of the region on the side near the interface passivation layer. xn Elements, forming elements containing B xn Layer; the layer containing B xn Layer B xn The concentration of the element is greater than 1E17 atoms / cm 3 The thickness d of the region 2n It is above 20nm.

30. A solar cell module comprising a silicon solar cell according to any one of claims 1 to 29.

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