Array substrate, driving method therefor, display panel and display apparatus
By optimizing the array substrate design, reducing the number of data lines and gate drive circuits, and combining multiplexers and column flip technology, the problems of excessively large bezels and image quality in TFT-LCDs have been solved, achieving a display effect with narrow bezels and high refresh rates.
Patent Information
- Application Number
- PCT/CN2024/094706
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-22
- Publication Date
- 2025-12-26
AI Technical Summary
Existing thin-film transistor liquid crystal displays (TFT-LCDs) have insufficient space in their bezel design, resulting in excessively large bezels. Furthermore, dual-gate products suffer from image quality issues such as precharge differences and head-shaking patterns.
By adopting an array substrate design, narrow bezels and high image quality are achieved by reducing the number of data lines and gate drive circuits, combined with multiplexers and column flipping technology. The column flipping method is used to load data signals to solve the precharge difference problem.
It achieves reduced bezel width, improved image quality, reduced number of data cables and source driver ICs, increased refresh rate and charging rate, and avoids image quality defects such as swivel lines and color shift.
Smart Images
Figure CN2024094706_26122025_PF_FP_ABST
Abstract
Description
Array substrate, driving method thereof, display panel and display device TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of display, and in particular to an array substrate, a driving method thereof, a display panel and a display device. BACKGROUND
[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation and portability, and has been rapidly developed in recent years. It has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. Currently, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual displays, etc.
[0003] SUMMARY
[0004] The array substrate, the driving method thereof, the display panel and the display device provided by the present disclosure have the following specific solutions:
[0005] In one aspect, the present disclosure provides an array substrate, comprising:
[0006] A substrate, comprising a display area and a non-display area located on at least one side of the display area;
[0007] A plurality of sub-pixels arranged in an array in the display area, the size of the sub-pixels along the row direction being greater than the size of the sub-pixels along the column direction;
[0008] A gate drive circuit located in the non-display area, the gate drive circuit comprising a plurality of shift registers arranged in cascade, one shift register being electrically connected to at least part of the sub-pixels in each row of at least two rows;
[0009] A plurality of data lines extending along the column direction and arranged along the row direction, and two data lines being included between two adjacent columns of the sub-pixels, two sub-pixels corresponding to the same shift register in each column of the sub-pixels being electrically connected to different data lines;
[0010] A multiplexer is located in the non-display area, the multiplexer comprises a plurality of output interfaces electrically connected with the data lines, and a plurality of input interfaces connected with the source driving circuit, and the total number of the input interfaces is less than the total number of the output interfaces.
[0011] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the multiplexer comprises a first control line, a second control line, a plurality of first transistors and a plurality of second transistors; wherein,
[0012] The gate of the first transistor is electrically connected with the first control line, and the gate of the second transistor is electrically connected with the second control line;
[0013] The first pole of the first transistor is electrically connected with an odd-numbered data line, and the first pole of the second transistor is electrically connected with an even-numbered data line;
[0014] The second pole of the corresponding first transistor and the second pole of the corresponding second transistor are electrically connected to the same output end of the source driving circuit.
[0015] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the non-display area comprises a first non-display area provided with a binding pad, and a second non-display area and a third non-display area connected with the first non-display area respectively, and the gate driving circuit is located in the second non-display area and / or the third non-display area.
[0016] The array substrate further comprises a plurality of gate lines extending in a row direction and arranged in a column direction, one of the gate lines is electrically connected with at least part of the sub-pixels in each of two rows, and one of the gate lines is electrically connected with one of the shift registers in the second non-display area and / or one of the shift registers in the third non-display area.
[0017] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, every two adjacent rows of the sub-pixels form a group, and one of the gate lines is electrically connected with two rows of the sub-pixels in the same group.
[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the gate line corresponding to a group of the sub-pixels is located between the two rows of the sub-pixels in the group.
[0019] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, every two adjacent rows of the sub-pixels form a group, and the sub-pixels in the same group of adjacent columns are electrically connected with different gate lines.
[0020] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the sub-pixels in the odd columns in the same group are electrically connected to one of the gate lines, and the sub-pixels in the even columns are electrically connected to another of the gate lines.
[0021] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, each two adjacent rows of the sub-pixels form a group, and the sub-pixels in the same column in the same group are electrically connected to different gate lines.
[0022] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the sub-pixels of the same color in two adjacent groups are electrically connected to the same gate line.
[0023] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, two gate lines corresponding to one group of the sub-pixels are located on the two sides of the group.
[0024] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the non-display area includes a first non-display area in which a bonding pad is arranged, and a second non-display area and a third non-display area connected to the first non-display area respectively, and the gate drive circuit is located in the second non-display area and / or the third non-display area.
[0025] The array substrate further includes a plurality of gate lines extending in the row direction and arranged in the column direction, one of the gate lines is electrically connected to one row of the sub-pixels, and two of the gate lines are electrically connected to the same shift register in the second non-display area and / or the same shift register in the third non-display area.
[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, two rows of the sub-pixels corresponding to the same shift register form a group, and the two rows of the sub-pixels in the same group are arranged adjacently.
[0027] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, two rows of the sub-pixels corresponding to the same shift register form a group, and the two rows of the sub-pixels in the same group are arranged at intervals.
[0028] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, at least two adjacent sub-pixels arranged in the column direction form one pixel.
[0029] The two rows of the sub-pixels in the same group are separated by (m*n-1) rows of the sub-pixels, m is a positive integer, and n is the total number of the sub-pixels contained in the pixel.
[0030] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, each 2m*n adjacent sub-pixels in the same column are a cycle, the first-m*n sub-pixels in a cycle are electrically connected to the same data line, and the (m*n+1)-2m*n sub-pixels are electrically connected to another data line.
[0031] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of third transistors are further included in the display area, a first electrode of the third transistor is electrically connected to a sub-pixel electrode.
[0032] The sub-pixels in the same group and spaced apart from the gate line by a distance less than the row gap are directly electrically connected to the gate electrode of the corresponding third transistor.
[0033] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of third transistors and a plurality of connection lines are further included in the display area, a first electrode of the third transistor is electrically connected to a sub-pixel electrode.
[0034] The sub-pixels in the same group and spaced apart from the gate line by a distance greater than the row gap are electrically connected to the gate electrode of the corresponding third transistor through the connection line.
[0035] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sub-pixels include a plurality of red sub-pixels and a plurality of green sub-pixels, the red sub-pixels in the same column are electrically connected to the same data line, and the green sub-pixels are electrically connected to another data line.
[0036] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of third transistors are further included in the display area, a second electrode of the third transistor is electrically connected to the data line, and the third transistor is disposed on a side of a center axis of the sub-pixels in the same column extending in the column direction, which is close to the side of the data line to which the third transistor is electrically connected.
[0037] In another aspect, the embodiments of the present disclosure provide a display panel, which includes the array substrate provided by the embodiments of the present disclosure and an opposite substrate opposite to the array substrate.
[0038] In another aspect, the embodiments of the present disclosure provide a display device, which includes the display panel provided by the embodiments of the present disclosure.
[0039] In another aspect, the embodiments of the present disclosure provide a driving method of the array substrate, the array substrate includes 2k clock signal lines, a pixel includes k (k is an integer greater than or equal to 2) sub-pixels, and the driving method includes:
[0040] Load the scanning signal to the corresponding sub-pixel by sequentially passing each group of the shift register with every 2k shift register as a group; wherein,
[0041] In one of the two adjacent frame time, drive the shift register in the same group to provide scanning signal in the order of 1-2k, and in the other frame time, drive the shift register in the same group to provide scanning signal in the order of 2, 1, …, 2k, 2k-1. BRIEF DESCRIPTION OF DRAWINGS
[0042] Fig. 1 is a schematic diagram of one structure of an array substrate provided by the embodiment of the present disclosure;
[0043] Fig. 2 is a schematic diagram of another structure of an array substrate provided by the embodiment of the present disclosure;
[0044] Fig. 3 is a schematic diagram of an enlarged structure of Z1 region in Fig. 1 or Fig. 2;
[0045] Fig. 4 is a schematic diagram of one enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0046] Fig. 5 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0047] Fig. 6 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0048] Fig. 7 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0049] Fig. 8 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0050] Fig. 9 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0051] Fig. 10 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0052] Fig. 11 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0053] Fig. 12 is a schematic diagram of another enlarged structure of Z2 region in Fig. 1 or Fig. 2;
[0054] Fig. 13 is a schematic diagram of one enlarged structure of Z3 region in Fig. 1 or Fig. 2;
[0055] Fig. 14 is a timing diagram provided by the embodiment of the present disclosure;
[0056] Fig. 15 is a schematic diagram of one structure of a display panel provided by the embodiment of the present disclosure;
[0057] Fig. 16 is a schematic diagram of one structure of a display device provided by the embodiment of the present disclosure. Detailed Implementation
[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0059] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0060] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" another element or layer, no intervening element or layer is present. The term "and / or" includes any and all combinations of one or more of the associated listed items.
[0061] The Triple Gate product can achieve a reduction of 2 / 3 data (Source) line quantity, but due to the insufficient longitudinal (Y direction) space on the left and right sides for setting the gate driving circuit (GOA), the left and right borders are too large.
[0062] To at least improve the above technical problems existing in the related art, an array substrate is provided in the embodiments of the present disclosure. FIG. 1 shows a structural schematic diagram of an array substrate provided by the embodiments of the present disclosure, FIG. 2 shows another structural schematic diagram of an array substrate provided by the embodiments of the present disclosure, and FIG. 3 is an enlarged structural schematic diagram of a Z1 region in FIG. 1 or FIG. 2. As can be seen from FIGS. 1 to 3, the array substrate provided by the embodiments of the present disclosure includes:
[0063] A substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA. FIGS. 1 and 2 specifically show that the non-display area BB surrounds the display area AA. Optionally, the substrate 101 is a substrate allowing visible light to pass through, such as a glass, quartz, plastic, or the like.
[0064] A plurality of sub-pixels 102 are arranged in an array in the display area AA. The size of the sub-pixel 102 along the row direction X is greater than the size along the column direction Y, in other words, the sub-pixel 102 of the present disclosure is a horizontal pixel. In some embodiments, the sub-pixel 102 includes a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and the like, and the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B arranged in the second direction Y constitute a pixel. It should be noted that the same column from top to bottom is not limited to the order of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B shown in the figure, but can also be the order of the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R, the order of the blue sub-pixel B, the red sub-pixel R, and the green sub-pixel G, the order of the green sub-pixel G, the red sub-pixel R, and the blue sub-pixel B, and the like.
[0065] The gate driving circuit GOA is located in the non-display area BB, and the gate driving circuit GOA includes a plurality of shift registers (for example, G1-G3) arranged in cascade, and one shift register (for example, G1-G3) is electrically connected with at least part of the sub-pixels 102 in each row of the at least two rows. FIG. 3 specifically shows that one shift register (for example, G1-G3) is electrically connected with two rows of sub-pixels 102.
[0066] The plurality of data lines 103 extend along the column direction Y and are arranged along the row direction X, and two data lines 103 are included between two adjacent columns of sub-pixels 102, and two sub-pixels 102 corresponding to the same shift register (for example, G1-G3) in each column of sub-pixels 102 are electrically connected with different data lines 103; for example, the red sub-pixel R and the green sub-pixel G connected with the first column and the G1 shift register in FIG. 3 are respectively connected with the data lines 103 on the right side and the left side.
[0067] The multiplexer 104 is located in the non-display area BB, and the multiplexer 104 includes a plurality of output interfaces O electrically connected with the data lines 103, and a plurality of input interfaces I connected with the source driving circuit (Source IC), and the total number of the input interfaces I is less than the total number of the output interfaces O. It should be noted that the source driving circuit in the present case can be bound on the array substrate, or can be bound on the circuit board, and the circuit board is bound on the array substrate, which is not limited herein.
[0068] In the array substrate provided in the embodiments of the present disclosure, since at least two rows share one shift register (for example, G1-G3), the number of left and right shift registers (for example, G1-G3) can be reduced, and the effect of reducing the left and right side frames can be achieved. At the same time, the sub-pixels 102 are laid horizontally, and the number of data lines 103 can be reduced by 1 / 3, and the effects of low cost and reducing the lower frame can be achieved; in combination with the multiplexer 104, the effects of reducing the number of Source ICs and reducing the lower frame can be achieved.
[0069] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 3, the multiplexer 104 can include a first control line MUX1, a second control line MUX2, a plurality of first transistors T1 and a plurality of second transistors T2; wherein the gates of the plurality of first transistors T1 are electrically connected to the first control line MUX1, and the gates of the plurality of second transistors T2 are electrically connected to the second control line MUX2; the first poles of the first transistors T1 are output interfaces O electrically connected to odd-numbered data lines 103, and the first poles of the second transistors T2 are output interfaces O electrically connected to even-numbered data lines 103; the second poles of the corresponding first transistors T1 and the second poles of the corresponding second transistors T2 of two data lines 103 between two adjacent columns of sub-pixels 102 are collectively used as an input interface I and are electrically connected to the same output end (for example, S1-S3) of the source driving circuit. It is worth noting that the first data line 103 and the last data line 103 in the present disclosure can be electrically connected to the multiplexer 104 or can not be electrically connected to the multiplexer 104, which is not limited in the present disclosure.
[0070] Compared with the related three-gate product, the data line 103 of the pixel structure shown in FIG. 3 is increased by one, and for the increase of the data line 103, the multiplexer 104 in FIG. 3 is adopted in the present disclosure, so as to realize the same effect of reducing the number of Source IC and reducing the lower frame of the related three-gate product. In addition, the dual-gate product can realize the effect of reducing the number of data lines 103 by half and reducing the lower frame, but the related dual-gate structure has a problem of image quality due to the difference in pre-charging. In the pixel structure shown in FIG. 3 of the present disclosure, the data signal is loaded in the column inversion manner, which can realize the effect of point inversion, solve the problem of pre-charging difference, and improve the image quality.
[0071] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 1 and FIG. 2, the non-display area BB includes a first non-display area BB1 in which the binding terminals are arranged, and a second non-display area BB2 and a third non-display area BB3 connected to the first non-display area BB1 respectively, and the gate drive circuit GOA is located in the second non-display area BB2 and / or the third non-display area BB3. FIG. 4 to FIG. 10 are schematic diagrams of the enlarged structure of the Z2 area in FIG. 1 and FIG. 2. As can be seen from FIG. 3 to FIG. 10, the array substrate provided by the embodiments of the present disclosure can further include a plurality of gate lines 105 extending along the row direction X and arranged along the column direction Y, one gate line 105 can be electrically connected to at least part of the sub-pixels 102 in each of the two rows, and one gate line 105 is electrically connected to one shift register (for example, G1-G4) in the second non-display area BB2 and / or one shift register (for example, G1-G4) in the third non-display area BB3. In this way, the two rows of sub-pixels 102 can share one shift register (for example, G1-G4) through one gate line 105, thereby reducing the number of unilateral shift registers (for example, G1-G4) and achieving a narrow frame effect.
[0072] In some embodiments, the gate drive circuit GOA can be located in the second non-display area BB2 or the third non-display area BB3, and one gate line 105 is electrically connected to one shift register (for example, G1-G4) in the second non-display area BB2 or the third non-display area BB3. In other embodiments, the gate drive circuit GOA is located in the second non-display area BB2 and the third non-display area BB3 at the same time: one gate line 105 can be electrically connected to one shift register (for example, G1-G4) in the second non-display area BB2 and one shift register (for example, G1-G4) in the third non-display area BB3 at the same time; or, an odd number of gate lines 105 are electrically connected to the shift registers (for example, G1-G4) in the second non-display area BB2 one by one, and an even number of gate lines 105 are electrically connected to the shift registers (for example, G1-G4) in the third non-display area BB3 one by one.
[0073] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 3 and FIG. 4, every two adjacent rows of sub-pixels 102 form a group, and one gate line 105 can be electrically connected to the two rows of sub-pixels 102 in the same group, so that the two rows of sub-pixels 102 in the same group share one gate line 105, thereby reducing the number of shift registers to which the gate line 105 is electrically connected, and achieving a left-right narrow frame effect.
[0074] In some embodiments, to ensure a large aperture ratio, as shown in FIGS. 3 and 4, a set of sub-pixels 102 can be arranged between the two rows of sub-pixels 102 in the set. A common electrode line 106 can be arranged between the two sets of sub-pixels 102 in the same layer and of the same material as the gate lines 105. In the pixel structure shown in FIGS. 3 and 4, the data signal (Data) is loaded in a column inversion manner, and the effect of point inversion can be achieved.
[0075] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 5 to 10, each set of sub-pixels 102 includes two adjacent rows of sub-pixels 102. Two gate lines 105 corresponding to the set of sub-pixels 102 can be arranged on the upper and lower sides of the set of sub-pixels 102. To reduce the number of gate lines 105 and achieve a narrow frame effect, a common gate line 105 can be arranged between the two sets of sub-pixels 102, for example, the gate line 105 connected to G2 or G3. The common gate line 105 can be arranged in the row gap between the two sets of sub-pixels 102.
[0076] In some embodiments, as shown in FIGS. 5 to 8, the sub-pixels 102 in the same set of adjacent columns can be electrically connected to different gate lines 105, for example, the sub-pixels 102 in the odd-numbered columns in the set are electrically connected to one gate line 105 (for example, the upper gate line 105 in the set), and the sub-pixels 102 in the even-numbered columns are electrically connected to another gate line 105 (for example, the lower gate line 105 in the set). In the pixel structure shown in FIGS. 5 to 8, the data signal (Data) is loaded in a column inversion manner, and the effect of row inversion can be achieved.
[0077] In some embodiments, as shown in FIGS. 9 and 10, the sub-pixels 102 in the same set of columns can be electrically connected to different gate lines 105, for example, the sub-pixels 102 of the same color in the two adjacent sets are electrically connected to a common gate line 105 (for example, the gate line 105 connected to G2 or G3) between the two sets, and the sub-pixels 102 of different colors are electrically connected to the gate lines 105 (for example, the gate lines 105 connected to G1 and G4) on the two sides that are not shared. In the pixel structure shown in FIGS. 9 and 10, the data signal (Data) is loaded in a column inversion manner, and the effect of point inversion can be achieved.
[0078] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the enlarged structural schematic diagram of the Z2 region in FIGS. 1 and 2 can also be as shown in FIGS. 11 and 12. The enlarged structural schematic diagram of the Z3 region in FIGS. 1 and 2 can be as shown in FIG. 13. As shown in FIGS. 11 to 13, in the array substrate provided in the embodiments of the present disclosure, one gate line 105 can be electrically connected with one row of sub-pixels 102, and two gate lines 105 can be electrically connected with one shift register (for example, G1-G6) in the second non-display area BB2 and / or one shift register (for example, G1-G6) in the third non-display area BB3, so that two rows of sub-pixels 102 share one shift register (for example, G1-G6) through the two gate lines 105, thereby reducing the number of shift registers on one side and achieving a narrow frame effect. In the case where the two gate lines 105 are electrically connected with one shift register (for example, G1-G6) in the second non-display area BB2 and one shift register (for example, G1-G6) in the third non-display area BB3 at the same time, the two gate lines 105 are equivalent to being arranged in parallel, thereby reducing the resistance of the gate line 105 by half.
[0079] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 11 to 13, two rows of sub-pixels corresponding to one shift register (for example, G1-G6) form a group, and in FIG. 11, the two rows of sub-pixels 102 in the same group are arranged adjacently, and in FIGS. 12 and 13, the two rows of sub-pixels 102 in the same group are arranged at intervals. In the pixel architecture shown in FIG. 11, the data signal (Data) is loaded in a column inversion manner, and the effect of point inversion can be achieved. In the pixel architecture shown in FIGS. 12 and 13, the data signal (Data) is loaded in a column inversion manner, and the effect of inversion in units of at least one pixel can be achieved. To avoid short-circuiting of the gate line 105, the part of the gate line 105 extending along the row direction X can be located in the gate metal layer, and the part extending along the column direction Y can be located in the source-drain metal layer.
[0080] Continuing to refer to FIGS. 12 and 13, adjacent at least two sub-pixels 102 arranged along the column direction Y constitute a pixel P; to achieve the effect of flipping in units of at least one pixel P, the present disclosure provides that (m*n-1) rows of sub-pixels 102 can be arranged between two rows of sub-pixels 102 in the same group, m is a positive integer, and n is the total number of sub-pixels 102 contained in a pixel; in other words, the colors of the two rows of sub-pixels 102 in the same group can be the same. For example, in FIG. 12, m is 1, three sub-pixels 102 constitute a pixel P, n is equal to 3 accordingly, and two rows of sub-pixels 102 in the same group are separated by 2 rows of sub-pixels 102, so that the effect of flipping in units of one pixel P can be achieved; in FIG. 13, m is 2, three sub-pixels 102 constitute a pixel P, n is equal to 3 accordingly, and two rows of sub-pixels 102 in the same group are separated by 5 rows of sub-pixels 102, so that the effect of flipping in units of two pixels P can be achieved.
[0081] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 12 and 13, every 2m*n adjacent sub-pixels 102 in the same column constitute a cycle (both FIGS. 12 and 13 show a cycle of sub-pixels 102), the first to m*n sub-pixels 102 in the cycle are electrically connected to the same data line 103 (for example, the left data line 103), and the (m*n+1) to 2m*n sub-pixels 102 are electrically connected to another data line 103 (for example, the right data line 103). In this way, the data signal (Data) can be loaded in a column flipping manner, and the effect of flipping in units of at least one pixel P can be achieved.
[0082] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 3 to 13, a plurality of third transistors T3 and a plurality of connection lines 107 can also be arranged in the display area AA, the first electrode of the third transistor T3 is electrically connected to the sub-pixel electrode; for the sub-pixels 102 in the same group and spaced apart from the gate line 105 by a row gap, the gate electrode of the corresponding third transistor T3 can be directly electrically connected to the gate line 105, which can be referred to as a short gate connection; for the sub-pixels 102 in the same group and spaced apart from the gate line 105 by more than a row gap, the gate electrode of the corresponding third transistor T3 is electrically connected to the gate line 105 through the connection line 107, which can be referred to as a long gate connection.
[0083] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 4, 7 and 8, the red sub-pixels R in the same column can be electrically connected to the same data line 103, and the green sub-pixels G can be electrically connected to another data line 103, so that the data power consumption of the red and green pure color pictures can be reduced by half compared with the embodiment shown in FIG. 3.
[0084] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 3-13, the second electrode of the third transistor T3 is electrically connected to the data line 103, and the third transistor T3 is arranged on one side of the data line 102 close to the center axis MN (for example, the center axis MN of a column of sub-pixels 102 is shown in FIGS. 3-13) of the column of sub-pixels 102 extending along the column direction Y, so that the second electrode of the third transistor T3 and the data line 102 are in a short connection state, thereby facilitating the improvement of the aperture ratio.
[0085] The pixel architecture shown in FIGS. 3, 9 and 10 of the present disclosure has better image quality than related dual-gate products. For example, in the pixel architecture shown in FIG. 3, in the column inversion mode, for each data line 103, the connection order is red sub-pixel R, green sub-pixel G, and blue sub-pixel B, so there is no pre-charge in the pure color picture, and the mixed color picture is the same color without pre-charge, and there is no different pre-charge state of the same color in the horizontal or vertical direction. For RG mixed color, there is no pre-charge for the green sub-pixel G, and there is pre-charge for the red sub-pixel R, so there is no horizontal and vertical stripe defect. Because there is no vertical stripe defect, the charging rate requirement does not need to be very high, and at the same resolution, the number of gate lines 105 is small, so the 1H time is long, so it can achieve a higher refresh rate than related dual-gate products. Because the number of gate lines 105 is less than related dual-gate products, the left and right borders are also advantageous over related dual-gate products. Under the same frequency and resolution conditions, the charging rate is higher, so the size of the third transistor T3 in the display area AA can be smaller, and the data line 103 can be made narrower, achieving a larger pixel aperture than related dual-gate products.
[0086] However, in a mixed color picture (for example, an RG picture), because the green sub-pixel G is always without pre-charge, there may be color deviation problems when the charging rate is low. To solve the color deviation problem, the embodiments of the present disclosure provide a driving method for the above array substrate, the array substrate includes 2k clock signal lines, and the pixel includes k (k is an integer greater than or equal to 2) sub-pixels, and the driving method includes:
[0087] Each 2k group of shift registers is sequentially loaded with a scan signal for the corresponding sub-pixel through each group of shift registers; wherein,
[0088] In one of the adjacent two frame times (for example, odd frame), the shift registers in the same group are driven to provide the scan signal in the order of 1-2k, and in the other frame time (for example, even frame), the shift registers in the same group are driven to provide the scan signal in the order of 2, 1, …, 2k, 2k-1.
[0089] For ease of understanding, Figure 14 illustrates the working timing using an example where each pixel comprises 3 sub-pixels and the array substrate includes 6 clock signal lines CLK1 to CLK6. In Figure 14, "dum" represents an invalid signal that does not control the shift register to output the scan signal. As shown in Figure 14, during odd-numbered frames, the first clock signal line CLK1 to the sixth clock signal line CLK6 are turned on sequentially. Correspondingly, in a set of shift registers, the shift registers are driven in the order of stages 1 to 6 to provide the scan signal. During even-numbered frames, the second clock signal line CLK2, the first clock signal line CLK1, the fourth clock signal line CLK4, the third clock signal line CLK3, the sixth clock signal line CLK6, and the fifth clock signal line CLK5 are turned on sequentially. Correspondingly, in a set of shift registers, the shift registers are driven in the order of stages 2, 1, 4, 3, 6, and 5 to provide the scan signal. This allows for no pre-charging of the green sub-pixel G in odd-numbered frames and no pre-charging of the red sub-pixel R in even-numbered frames, achieving visual overlay of the two frames and offsetting color shift issues, while avoiding the risk of head-shaking patterns similar to those in related dual-gate products. Using this circuit timing scheme, the charging rate baseline of this disclosure can be further reduced, thus offering advantages in achieving refresh rate specifications. For the pixel architectures shown in Figures 4 to 8 and Figures 11 to 13, this driving scheme can balance the pre-charging of different color sub-pixels, thereby improving the horizontal and vertical lines caused by significant differences in pre-charging between different color sub-pixels.
[0090] Based on the same inventive concept, this disclosure provides a display panel. Figure 15 is a schematic diagram of the structure of the display panel provided in this disclosure. As shown in Figure 15, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle by which this display panel solves the problem is similar to the principle by which the array substrate solves the problem, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.
[0091] In some embodiments, as shown in FIG15, the display panel provided in this disclosure may further include a liquid crystal layer 003 disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0092] Based on the same inventive concept, the display device is provided by the embodiments of the present disclosure. FIG. 16 is a structural schematic diagram of a display device provided by the embodiments of the present disclosure. As shown in FIG. 16, the display device of the present disclosure comprises the display panel PNL provided by the embodiments of the present disclosure, and a backlight module BLU located at the light-in side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can comprise a lamp bar, a reflector sheet, a light guide plate, a diffusion sheet, a prism group and the like, and the lamp bar is located at one side of the light guide plate in the thickness direction. The direct type backlight module can comprise a matrix light source, a reflector sheet, a diffusion plate and a brightness enhancement film and the like which are stacked at the light-out side of the matrix light source, and the reflector sheet comprises an opening which is located opposite to each lamp bead in the matrix light source. The lamp bead in the lamp bar and the lamp bead in the matrix light source can be a light emitting device (LED), for example, a quantum dot light emitting device.
[0093] In some embodiments, the lamp bead can also be a micro light emitting device (for example, Mini LED, Micro LED) and the like. The micro light emitting device in the order of sub-millimeter or even micrometer and the organic light emitting device (OLED) are all self-luminous devices. Like the organic light emitting device, the micro light emitting device has a series of advantages such as high brightness, ultra-low delay, super large visual angle and the like. Moreover, since the inorganic light emitting device emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life and better resistance to high and low temperatures compared with the organic light emitting device which emits light based on organic matter. When the micro light emitting device is used as a backlight source, it can realize more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the screen bright and dark areas, and optimize the visual experience.
[0094] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigation device, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or arrange different components.
[0095] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who are informed of the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.
[0096] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, The application relates to a display panel, comprising: a substrate, comprising a display area and a non-display area on at least one side of the display area; a plurality of sub-pixels arranged in an array in the display area, the size of the sub-pixels along the row direction being greater than the size of the sub-pixels along the column direction; a gate drive circuit in the non-display area, the gate drive circuit comprising a plurality of shift registers arranged in cascade, one of the shift registers being electrically connected to at least part of the sub-pixels in each row of at least two rows; a plurality of data lines extending along the column direction and arranged along the row direction, and two of the data lines being included between two adjacent columns of the sub-pixels, two of the sub-pixels in each column of the sub-pixels corresponding to the same shift register being electrically connected to different data lines; a multiplexer in the non-display area, the multiplexer comprising a plurality of output interfaces electrically connected to the data lines, and a plurality of input interfaces connected to a source drive circuit, the total number of the input interfaces being less than the total number of the output interfaces.
2. The array substrate of claim 1, wherein, The multiplexer comprises a first control line, a second control line, a plurality of first transistors and a plurality of second transistors; wherein, the gates of the plurality of first transistors are electrically connected to the first control line, and the gates of the plurality of second transistors are electrically connected to the second control line; the first poles of the first transistors are electrically connected to odd-numbered data lines, and the first poles of the second transistors are electrically connected to even-numbered data lines; the second poles of the corresponding first transistors and the second poles of the corresponding second transistors of two of the data lines between two adjacent columns of the sub-pixels are electrically connected to the same output end of the source drive circuit.
3. The array substrate of claim 1 or 2, wherein, The non-display area comprises a first non-display area in which a binding pad is arranged, and a second non-display area and a third non-display area connected to the first non-display area respectively, and the gate drive circuit is arranged in the second non-display area and / or the third non-display area. The array substrate further comprises a plurality of gate lines extending along the row direction and arranged along the column direction, one of the gate lines being electrically connected to at least part of the sub-pixels in each of two rows, and one of the gate lines being electrically connected to one of the shift registers in the second non-display area and / or one of the shift registers in the third non-display area.
4. The array substrate of claim 3, wherein, Each of two adjacent rows of the sub-pixels forms a group, and one of the gate lines is electrically connected to the two rows of the sub-pixels in the same group.
5. The array substrate of claim 4, wherein, The gate line corresponding to one group of the sub-pixels is located between the two rows of the sub-pixels in the group.
6. The array substrate of claim 3, wherein, Each of two adjacent rows of the sub-pixels forms a group, and the sub-pixels in adjacent columns in the same group are electrically connected to different gate lines.
7. The array substrate of claim 6, wherein, The sub-pixels in the odd-numbered columns in the same group are electrically connected to one of the gate lines, and the sub-pixels in the even-numbered columns are electrically connected to another of the gate lines.
8. The array substrate of claim 3, wherein, Each of two adjacent rows of the sub-pixels forms a group, and the sub-pixels in the same column in the same group are electrically connected to different gate lines.
9. The array substrate of claim 8, wherein, The sub-pixels of the same color in adjacent groups are electrically connected to the same gate line.
10. The array substrate according to any one of claims 6 to 9, wherein, The two gate lines corresponding to one group of the sub-pixels are located on the two sides of the group.
11. The array substrate of claim 1 or 2, wherein, The non-display area includes a first non-display area in which a binding pad is arranged, and a second non-display area and a third non-display area connected to the first non-display area respectively, and the gate drive circuit is arranged in the second non-display area and / or the third non-display area. The array substrate further includes a plurality of gate lines extending along the row direction and arranged along the column direction, one of the gate lines is electrically connected to one row of the sub-pixels, and two of the gate lines are electrically connected to the same shift register in the second non-display area and / or the same shift register in the third non-display area.
12. The array substrate of claim 11, wherein, Two rows of the sub-pixels corresponding to the same shift register form a group, and two rows of the sub-pixels in the same group are arranged adjacently.
13. The array substrate of claim 11, wherein, Two rows of the sub-pixels corresponding to the same shift register form a group, and two rows of the sub-pixels in the same group are arranged at intervals.
14. The array substrate of claim 13, wherein, At least two adjacent sub-pixels arranged along the column direction form one pixel. The interval between two rows of the sub-pixels in the same group is (m*n-1) rows of the sub-pixels, m is a positive integer, and n is the total number of the sub-pixels in the pixel.
15. The array substrate of claim 14, wherein, Every 2m*n adjacent sub-pixels in the same column form a cycle, the first m*n sub-pixels in one cycle are electrically connected to one data line, and the (m*n+1)th to 2m*n sub-pixels are electrically connected to another data line.
16. The array substrate according to any one of claims 4 to 10, 12 to 15, wherein, Further comprising a plurality of third transistors arranged in the display area, a first electrode of the third transistor is electrically connected to a sub-pixel electrode. The gate of the third transistor corresponding to the sub-pixel in the same group and spaced apart from the gate line by a row gap is directly electrically connected to the gate line.
17. The array substrate according to any one of claims 6 to 10 and 16, wherein, Further comprising a plurality of third transistors and a plurality of connection lines arranged in the display area, a first electrode of the third transistor is electrically connected to a sub-pixel electrode. The gate of the third transistor corresponding to the sub-pixel in the same group and spaced apart from the gate line by a row gap is electrically connected to the gate line through the connection line.
18. The array substrate of any one of claims 1 to 17, wherein, The plurality of sub-pixels include a plurality of red sub-pixels and a plurality of green sub-pixels, the red sub-pixels in the same column are electrically connected to one data line, and the green sub-pixels are electrically connected to another data line.
19. The array substrate of any one of claims 1 to 18, wherein, Further comprising a plurality of third transistors arranged in the display area, a second electrode of the third transistor is electrically connected to the data line, and the third transistor is arranged on one side of the center axis of the sub-pixels in the same column along the column direction and close to the data line to which the third transistor is electrically connected.
20. A display panel, wherein, The array substrate as claimed in any one of claims 1 to 19, and a counter substrate arranged opposite to the array substrate.
21. A display device, wherein, The display panel as claimed in claim 20.
22. A method of driving an array substrate as claimed in any one of claims 1 to 19, wherein, The array substrate includes 2k clock signal lines, a pixel includes k (k is an integer greater than or equal to 2) sub-pixels, and the driving method includes: Each 2k shift registers form a group, and each group of the shift registers is sequentially loaded with a scanning signal for corresponding sub-pixels; wherein, The array substrate includes 2k clock signal lines, a pixel includes k (k is an integer greater than or equal to 2) sub-pixels, and the driving method includes: In one of the two adjacent frame times, the shift register in the same group is driven in the order of 1-2k to provide the scanning signal, and in the other frame time, the shift register in the same group is driven in the order of 2, 1, …, 2k, 2k-1 to provide the scanning signal.