Display panel and display apparatus

Abstract

Disclosed in the present application are a display panel and a display apparatus. A first conductive layer comprises a plurality of data lines located in a display area. A second conductive layer is located on one side of the first conductive layer and comprises a plurality of first fan-out sections which are located in the display area and intersect with the plurality of data lines, one first fan-out section being connected to one data line. A third conductive layer is disposed between the first conductive layer and the second conductive layer and comprises a shielding portion. An overlapping portion between one first fan-out section and at least one data line which intersect with and are insulated from each other overlaps with the shielding portion.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Fanout in AA (FIAA) technology is an important technology for display panel to realize narrow frame. The principle of FIAA technology is to set part of fanout lines in the display area to reduce the area of non-display area occupied by fanout lines. Currently, for the display panel using FIAA technology, display panel may have display problems during display.

[0003] Therefore, it is necessary to provide a technical solution to improve the display problem of the display panel using FIAA technology. SUMMARY

[0004] The present application provides a display panel and a display device to improve the display problem of the display panel and the display device.

[0005] In a first aspect, some embodiments of the present application provide a display panel having a display area, the display panel comprising a substrate, a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer is disposed on the substrate and comprises a plurality of data lines located in the display area. The second conductive layer is disposed on the substrate and located on one side of the first conductive layer and comprises a plurality of first fanout segments located in the display area. The plurality of first fanout segments respectively intersect with the plurality of data lines, and one first fanout segment is connected with one data line. The third conductive layer is disposed between the first conductive layer and the second conductive layer and comprises a shielding portion. The overlapping part between one first fanout segment and at least one data line intersecting with the first fanout segment and insulated from the first fanout segment overlaps with the shielding portion.

[0006] In a second aspect, some embodiments of the present application provide a display device comprising the display panel of any of the above embodiments. ADVANTAGEOUS EFFECTS

[0007] In some embodiments of the display panel and display device provided in the present application, the first conductive layer includes a plurality of data lines in the display area. The second conductive layer includes a plurality of first fan-out segments in the display area. The third conductive layer is disposed between the first conductive layer and the second conductive layer and includes a shielding portion. Each of the plurality of first fan-out segments intersects with a data line, and one first fan-out segment is connected with one data line. The overlapping portion between one first fan-out segment and at least one data line which are insulated from and intersect with each other overlaps with the shielding portion. In this way, the shielding portion plays a shielding role between one first fan-out segment and at least one data line which are insulated from and intersect with each other, improves the problem of parasitic capacitance between one first fan-out segment and at least one data line which are insulated from and intersect with each other, and improves the problem of display failure of the display panel and display device caused by crosstalk of data signals. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a schematic diagram of a planar structure of a display panel according to some embodiments of the present application.

[0009] FIG. 2 is a schematic diagram of a cross-sectional structure along the A-A' cutting line shown in FIG. 1.

[0010] FIG. 3 is a schematic diagram of a pixel circuit of a display panel according to some embodiments of the present application.

[0011] FIG. 4A is a schematic diagram of a planar structure of a first semiconductor layer in FIG. 2.

[0012] FIG. 4B is a schematic diagram of a planar structure of a fourth conductive layer in FIG. 2.

[0013] FIG. 4C is a schematic diagram of a planar structure of a sixth conductive layer in FIG. 2.

[0014] FIG. 4D is a schematic diagram of a planar structure of a second semiconductor layer in FIG. 2.

[0015] FIG. 4E is a schematic diagram of a planar structure of a fifth conductive layer in FIG. 2.

[0016] FIG. 4F is a schematic diagram of a planar structure of a second conductive layer in FIG. 2.

[0017] FIG. 4G is a schematic diagram of a planar structure of a third conductive layer in FIG. 2.

[0018] FIG. 4H is a schematic diagram of a planar structure of a first conductive layer in FIG. 2.

[0019] FIG. 5 is a schematic diagram of a planar structure of the film layers shown in FIGS. 4A to 4H.

[0020] FIG. 6 is a partial planar layout diagram of the first conductive layer, the second conductive layer, and the third conductive layer in FIG. 2 according to some embodiments of the present application.

[0021] Fig. 7 is a partial plan layout of the second, fourth and fifth conductive layers in Fig. 2 according to some embodiments of the present application.

[0022] Reference signs are as follows:

[0023] 100, display panel; 100a, display area; 100b, non-display area;

[0024] 11, 11a, 11b, data line; 12, fan-out line; 121, first fan-out segment; 122, second fan-out segment; 13, driving unit; 14, shielding portion;

[0025] 20, pixel circuit; T1, driving transistor; T2, write transistor; T4, initialization transistor; T3, compensation transistor; C, capacitor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, first reset transistor; T8, second reset transistor;

[0026] 301, first scan signal line; 302, second scan signal line; 302a, second lower scan signal line; 302b, second upper scan signal line; 303, third scan signal line; 303a, third lower scan signal line; 303b, third upper scan signal line; 304, fourth scan signal line; 305, light-emitting control signal line; 306, first initialization signal line; 306a, first lower initialization signal line; 306b, first upper initialization signal line; 307, second initialization signal line; 308, third initialization signal line; 308a, third lower initialization signal line; 308b, third upper initialization signal line; 309, positive power voltage signal line; 3091, longitudinal main body portion;

[0027] 40, array layer; 401, first conductive layer; 402, second conductive layer; 403, third conductive layer; 404, fourth conductive layer; 405, fifth conductive layer; 406, sixth conductive layer;

[0028] 407, first semiconductor layer; 4071, driving active layer; 4072, write active layer; 4073, first light-emitting active layer; 4074, second light-emitting active layer; 4075, first reset active layer; 4076, second reset active layer;

[0029] 408, second semiconductor layer; 4081, initialization active layer; 4082, compensation active layer;

[0030] 409, first insulating layer; 410, second insulating layer; 411, third insulating layer; 412, fourth insulating layer; 413, fifth insulating layer; 414, sixth insulating layer; 415, seventh insulating layer; 416, eighth insulating layer; 417, buffer layer;

[0031] 50, light emitting device layer; 51, light emitting device; 60, substrate. Embodiments of the present application

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0033] Please refer to FIG. 1 to FIG. 3, FIG. 4A to FIG. 4H, FIG. 5 to FIG. 7, FIG. 1 is a schematic diagram of a planar structure of a display panel according to some embodiments of the present application, FIG. 2 is a schematic diagram of a cross-sectional structure along the A-A' cutting line shown in FIG. 1, FIG. 3 is a schematic diagram of a circuit of a pixel circuit of a display panel according to some embodiments of the present application, FIG. 4A is a schematic diagram of a planar structure of a first semiconductor layer in FIG. 2, FIG. 4B is a schematic diagram of a planar structure of a fourth conductive layer in FIG. 2, FIG. 4C is a schematic diagram of a planar structure of a sixth conductive layer in FIG. 2, FIG. 4D is a schematic diagram of a planar structure of a second semiconductor layer in FIG. 2, FIG. 4E is a schematic diagram of a planar structure of a fifth conductive layer in FIG. 2, FIG. 4F is a schematic diagram of a planar structure of a second conductive layer in FIG. 2, FIG. 4G is a schematic diagram of a planar structure of a third conductive layer in FIG. 2, FIG. 4H is a schematic diagram of a planar structure of a first conductive layer in FIG. 2, FIG. 5 is a schematic diagram of a planar structure of the film layers shown in FIG. 4A to FIG. 4H stacked, FIG. 6 is a partial planar layout diagram of the first conductive layer, the second conductive layer and the third conductive layer in FIG. 2 according to some embodiments of the present application, and FIG. 7 is a partial planar layout diagram of the second conductive layer, the fourth conductive layer and the fifth conductive layer in FIG. 2 according to some embodiments of the present application.

[0034] As shown in FIG. 1, the display panel 100 has a display area 100a and a non-display area 100b surrounding the display area 100a. The display panel 100 includes a plurality of data lines 11 and a plurality of fan-out lines 12 in the display area 100a. One fan-out line 12 is connected with one data line 11, and the black dot marked by L in FIG. 1 schematically shows that one fan-out line 12 is connected with one data line 11. The display panel 100 further includes a driving unit 13 arranged in the non-display area 100b, and the driving unit 13 can include a driving chip. The plurality of fan-out lines 12 extend to the non-display area 100b and are connected with the driving unit 13. The data signals output by the driving unit 13 are transmitted to the corresponding connected data lines 11 through the fan-out lines 12. In this way, part of the fan-out lines 12 is arranged in the display area 100a, which reduces the area occupied by the part of the fan-out lines 12 in the non-display area 100b, and is conducive to reducing the size of the non-display area 100b of the display panel 100, so that the display panel 100 can realize a lower bezel.

[0035] A fan-out line 12 includes a first fan-out segment 121 and a second fan-out segment 122. The first fan-out segment 121 is connected to a data line 11, and the second fan-out segment 122 is connected between the first fan-out segment 121 and the driving unit 13 and extends from the display area 100a to the non-display area 100b. The first fan-out segments 121 are respectively intersected with the data lines 11. Thus, the first fan-out segment 121 is connected to the data line 11 and is insulated from other data lines 11. For example, the first fan-out segment 121a is connected to the data line 11a and is insulated from the data line 11b.

[0036] In some embodiments, the first fan-out segment 121 and the second fan-out segment 122 can include a straight line segment, as shown in FIG. 1. In this way, the manufacturing process of the fan-out line 12 can be simplified.

[0037] In some embodiments, the first fan-out segment 121 and the second fan-out segment 122 can include a broken line segment, which includes at least two connected straight line segments.

[0038] In other embodiments, the first fan-out segment 121 and the second fan-out segment 122 can also include a curved line segment.

[0039] In other embodiments, each of the first fan-out segment 121 and the second fan-out segment 122 can also include a plurality of straight line segments. For example, the first fan-out segment 121 can include a main body part and a connecting part, and the connecting part connects two adjacent main body parts. The plurality of main body parts can be arranged along a first direction. One main body part includes two longitudinal segments extending along a first direction and one transverse segment connecting the two longitudinal segments, and the first direction intersects the second direction, i.e., the main body part has an H-shaped structure.

[0040] In some embodiments, the first fan-out segment 121 can extend along a first direction x, and the second fan-out segment 122 can extend along a second direction y, and the first direction x intersects the second direction y. In some embodiments, the first direction x is perpendicular to the second direction y. It can be understood that the included angle between the first direction x and the second direction y can be an acute angle or an obtuse angle.

[0041] As shown in FIG. 2, the display panel 100 includes a substrate 60, an array layer 40, and a light emitting device layer 50. The array layer 40 is disposed on the substrate 60, and the light emitting device layer 50 is disposed on a side of the array layer 40 away from the substrate 60.

[0042] As shown in FIG. 2 and FIG. 3, the array layer 40 includes a pixel circuit 20. The light emitting device layer 50 includes a light emitting device 51, which can be an organic light emitting diode or an inorganic light emitting diode. The pixel circuit 20 is connected to the light emitting device 51 to control the light emitting device 51 to emit light.

[0043] As shown in FIG. 4B, FIG. 4C, FIG. 4E to FIG. 4G, the display panel 100 further comprises a positive power voltage signal line 309 (as shown in FIG. 4G), a negative power voltage signal line (not shown), a first initialization signal line 306 (as shown in FIG. 4B and FIG. 4F), a first scan signal line 301 (as shown in FIG. 4B), a second scan signal line 302 (as shown in FIG. 4C and FIG. 4E), and a third scan signal line 303 (as shown in FIG. 4C and FIG. 4E), which are located in the array layer 40 and the light emitting device layer 50 and connected with the pixel circuit 20. Among them, the positive power voltage signal line 309 transmits a positive power voltage signal VDD. The negative power voltage signal line transmits a negative power voltage signal VSS. The first initialization signal line 306 transmits a first initialization signal VI1. The first scan signal line 301 transmits a first scan signal Pscan1. The second scan signal line 302 transmits a second scan signal Nscan1. The third scan signal line 303 transmits a third scan signal Nscan2.

[0044] In some embodiments, as shown in FIG. 3, the pixel circuit 20 comprises a driving transistor T1, a writing transistor T2, an initialization transistor T4, a compensation transistor T3, and a capacitor Cst.

[0045] In some embodiments, the initialization transistor T4 and the compensation transistor T3 can both be n-type transistors, and the driving transistor T1 and the writing transistor T2 can both be p-type transistors.

[0046] In some embodiments, the initialization transistor T4 and the compensation transistor T3 can both be metal oxide transistors, and the driving transistor T1 and the writing transistor T2 can both be low-temperature polysilicon transistors. In this way, the leakage current of the initialization transistor T4 and the compensation transistor T3 is reduced, and the flicker problem of the display panel 100 when displaying at low frequency is improved.

[0047] In other embodiments, the driving transistor T1, the writing transistor T2, the initialization transistor T4, and the compensation transistor T3 can all be low-temperature polysilicon transistors.

[0048] The current generated when the driving transistor T1 is turned on drives the light emitting device 51 to emit light.

[0049] The source and drain of the writing transistor T2 are connected between a data line 11 and one of the source and drain of the driving transistor T1, and the gate of the writing transistor T2 is connected with the first scan signal line 301. In this way, when the writing transistor T2 is turned on under the action of the first scan signal Pscan1 transmitted by the first scan signal line 301, the data signal Data transmitted by the data line 11 can be transmitted to one of the source and drain of the driving transistor T1.

[0050] The source and drain of the initialization transistor T4 are connected between the first initialization signal line 306 and the gate of the driving transistor T1, and the gate of the initialization transistor T4 is connected to the second scan signal line 302. In this way, when the initialization transistor T4 is turned on under the action of the second scan signal Nscan1 transmitted by the second scan signal line 302, the first initialization signal VI1 transmitted by the first initialization signal line 306 can be transmitted to the gate of the driving transistor T1 to perform initialization processing on the potential of the gate of the driving transistor T1.

[0051] The compensation transistor T3 is connected between the gate of the driving transistor T1 and the other one of the source and drain of the driving transistor T1, and the gate of the compensation transistor T3 is connected to the third scan signal line 303. In this way, when the compensation transistor T3 is turned on under the action of the third scan signal Nscan2 transmitted by the third scan signal line 303, the gate of the driving transistor T1 is connected to the other one of the source and drain of the driving transistor T1.

[0052] The two plates of the capacitor Cst are respectively connected to the positive power voltage signal line 309 and the gate of the driving transistor T1.

[0053] In some embodiments, as shown in FIG. 3, the pixel circuit 20 can further include a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 can each be a P-type low-temperature polysilicon transistor. As shown in FIGS. 4B and 5, the display panel 100 can further include a light-emitting control signal line 305 that transmits a light-emitting control signal EM. The source and drain of the first light-emitting control transistor T5 are connected between the positive power voltage signal line 309 and one of the source and drain of the driving transistor T1. The source and drain of the second light-emitting control transistor T6 are connected between the light-emitting device 51 and the other one of the source and drain of the driving transistor T1. The gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 are each connected to the light-emitting control signal line 305.

[0054] In some embodiments, the pixel circuit 20 can further include a first reset transistor T7. The first reset transistor T7 plays a role of resetting the anode of the light emitting device 51. As shown in FIGS. 4B, 4E and 5, the display panel 100 further includes a fourth scan signal line 304 transmitting a fourth scan signal Pscan2 and a second initialization signal line 307 transmitting a second initialization signal VI2. One of the source and drain of the first reset transistor T7 is connected to the second initialization signal line 307, the other of the source and drain of the first reset transistor T7 is connected between the light emitting device 51 and the other of the source and drain of the driving transistor T1, and the gate of the first reset transistor T7 is connected to the fourth scan signal line 304.

[0055] In some embodiments, the second initialization signal line 307 and the first initialization signal line 306 can be different signal lines. In this way, the first reset transistor T7 and the initialization transistor T4 can be independently controlled.

[0056] In other embodiments, the second initialization signal line 307 and the first initialization signal line 306 can also be the same signal line, i.e., the second initialization signal line 307 and the first initialization signal line 306 are the same signal line. In this way, the process of the pixel circuit 20 is simplified.

[0057] In some embodiments, the pixel circuit 20 further includes a second reset transistor T8. The second reset transistor T8 plays a role of initializing the potential of one of the source and drain of the driving transistor T1 to improve the display effect of the display panel 100 in low frequency display. As shown in FIGS. 4C and 4F, the display panel 100 further includes a third initialization signal line 308 transmitting a third initialization signal VI3. The source and drain of the second reset transistor T8 are connected between the third initialization signal line 308 and one of the source and drain of the driving transistor T1, and the gate of the second reset transistor T8 is connected to the fourth scan signal line 304. In this way, the first reset transistor T7 and the second reset transistor T8 are both controlled by the fourth scan signal Pscan2 transmitted by the fourth scan signal line 304.

[0058] In some embodiments, the first reset transistor T7 and the second reset transistor T8 can both be p-type low-temperature polysilicon transistors.

[0059] The pixel circuit 20 shown in FIG. 3 includes 8 transistors and one capacitor, which can ensure that the display panel 100 has good display effects in high frequency and low frequency.

[0060] The array layer 40 includes conductive layers, insulating layers and semiconductor layers, and part of the structure of the pixel circuit 20 is located in these film layers.

[0061] As shown in FIG. 2, in some embodiments, the array layer 40 includes a first conductive layer 401, a second conductive layer 402, and a third conductive layer 403. The first conductive layer 401 to the third conductive layer 403 can each include a metal.

[0062] As shown in FIGS. 2 and 4H, the first conductive layer 401 is disposed on the substrate 60 and includes a plurality of data lines 11 disposed in the display area 100a.

[0063] As shown in FIGS. 2 and 4F, the second conductive layer 402 is disposed on the substrate 60 and located at one side of the first conductive layer 401, and includes a plurality of first fan-out segments 121 disposed in the display area 100a. One first fan-out segment 121 is connected with one data line 11 through a via hole penetrating through an insulating layer, so that one fan-out line 12 is connected with one data line 11.

[0064] As shown in FIG. 2, the third conductive layer 403 is disposed between the first conductive layer 401 and the second conductive layer 402, and includes a shielding portion 14. As shown in FIG. 6, an overlapping portion (a portion marked by a dashed box CD1 in FIG. 6) between one first fan-out segment 121 and at least one data line 11 insulated from and intersecting with the one first fan-out segment 121 overlaps with the shielding portion 14. In this way, the shielding portion 14 plays a shielding role between one first fan-out line 12 and at least one data line 11 insulated from and intersecting with the one first fan-out line 12, improves the problem of parasitic capacitance between one first fan-out line 12 and at least one data line 11 insulated from and intersecting with the one first fan-out line 12, and improves the problem of display failure of the display panel 100 caused by data signal crosstalk.

[0065] It should be noted that when one first fan-out segment 121 and at least one data line 11 insulated from and intersecting with the one first fan-out segment 121 overlap, a projection of the one first fan-out segment 121 on the substrate 60 overlaps with a projection of the at least one data line 11 on the substrate 60. Also, when an overlapping portion between one first fan-out segment 121 and at least one data line 11 insulated from and intersecting with the one first fan-out segment 121 overlaps with the shielding portion 14, a projection of the overlapping portion CD1 on the substrate 60 overlaps with a projection of the shielding portion 14 on the substrate 60. The direction of the projection is the direction in which the first conductive layer 401 points to the substrate 60.

[0066] It should also be noted that in the related art, when one first fan-out segment and at least one data line insulated from and intersecting with the one first fan-out segment overlap, the data signal transmitted by the one first fan-out segment jumps, and the jump causes the data signal transmitted by the data line in a floating state to have a crosstalk problem through the parasitic capacitance between the data line and the first fan-out segment, and further causes a display failure problem.

[0067] In some embodiments, as shown in FIG. 6, a projection, on the substrate 60, of an overlapping portion between a first fan-out segment 121 and at least one data line 11 insulated from and intersecting the first fan-out segment 121, is located within a projection, on the substrate 60, of the shielding portion 14. In this way, the data crosstalk problem of the first fan-out segment 121 and the at least one data line 11 due to parasitic capacitance is better improved, and the display effect of the display panel 100 is improved.

[0068] In some embodiments, in a case where the display panel 100 includes a direct-current signal line such as a positive power voltage signal line 309 and a negative power voltage signal line, the direct-current signal line can include the shielding portion 14. In this way, at least part of the direct-current signal line that transmits a direct-current signal functions as the shielding portion 14. Moreover, at least part of the direct-current signal line in the display panel 100 can be used as the shielding portion 14, and thus the shielding portion 14 does not need to be additionally provided, the display panel 100 is simplified in manufacturing process, and the display defect problem of the display panel 100 due to data signal crosstalk is improved.

[0069] In some embodiments, as shown in FIG. 2, FIG. 4G, and FIG. 6, the positive power voltage signal line 309 includes the shielding portion 14. In this way, the positive power voltage signal line 309 in the display panel 100 is used as the shielding portion 14, and the manufacturing process of the display panel 100 is simplified. In a case where the shielding portion 14 includes the positive power voltage signal line 309, the positive power voltage signal line 309 is located in the third conductive layer 403.

[0070] It should be noted that, since the positive power voltage signal line 309 is located in the third conductive layer 403, the positive power voltage signal line 309 is provided in the entire display area 100a, and it is easier to use at least part of the positive power voltage signal line 309 as the shielding portion 14.

[0071] In some embodiments, as shown in FIG. 4G, FIG. 5, and FIG. 6, the positive power voltage signal line 309 includes a longitudinal main body portion 3091 and the shielding portion 14 that are connected to each other, the longitudinal main body portion 3091 has the same extension direction (second direction y) as the data line 11, the longitudinal main body portion 3091 is arranged to be offset from the data line 11, and the shielding portion 14 has the same extension direction (first direction x intersecting the second direction y) as the first fan-out segment 121. In this way, the extension direction of the shielding portion 14 intersects the extension direction of the longitudinal main body portion 3091, and the shielding portion 14 is a part of the longitudinal main body portion 3091.

[0072] It should be noted that, as shown in FIG. 5 and FIG. 6, the longitudinal main body portion 3091 is arranged to be offset from the data line 11 means that a projection, on the substrate 60, of the longitudinal main body portion 3091 does not overlap a projection, on the substrate 60, of the data line 11.

[0073] In some embodiments, as shown in FIG. 4G, the shield portion 14 can have a rectangular shape. In this way, the manufacturing process of the shield portion 14 can be simplified. In other embodiments, the shield portion 14 can also have an irregular shape.

[0074] In some embodiments, as shown in FIGS. 4F to 4H and FIG. 6, the shield portion 14 can have a dimension d1 along the first direction x that is greater than a dimension d2 of the data line 11 along the first direction x, and the shield portion 14 can have a dimension d3 along the second direction y that is greater than a dimension d4 of the first fan-out segment 121 along the second direction y. In this way, the shield portion 14 can cover the overlapping portion between the data line 11 and the first fan-out segment 121.

[0075] In other embodiments, a portion of the longitudinal body portion 3091 can also be used as the shield portion 14 when the longitudinal body portion 3091 overlaps with a data line 11. In this case, the longitudinal body portion 3091 can have a dimension along the width direction of the data line 11 (e.g., the first direction x) that is greater than the width of the data line 11.

[0076] In some embodiments, the positive power voltage signal line 309 can also include a transverse body portion (not shown) extending along the first direction x, and the transverse body portion can connect adjacent longitudinal body portions 3091. In this way, the positive power voltage signal line 309 can have a grid shape, so as to reduce the resistance voltage drop of the positive power voltage signal line 309 and improve the uniformity of the impedance of the positive power voltage signal line 309 in different regions.

[0077] In other embodiments, at least a portion of the transverse body portion can also be used as the shield portion 14 when the transverse body portion overlaps with the first fan-out segment 121. In this case, the transverse body portion can have a dimension along the width direction of the first fan-out segment 121 (e.g., the second direction y) that is greater than the width of the first fan-out segment 121.

[0078] In other embodiments, at least one of the first initialization signal line 306, the second initialization signal line 307, and the third initialization signal line 308 can include the shield portion 14. In this way, at least a portion of one of the first initialization signal line 306 to the third initialization signal line 308 that transmits a constant voltage signal can also be used as the shield portion 14. In this case, the at least one of the first initialization signal line 306, the second initialization signal line 307, and the third initialization signal line 308 is located in the third conductive layer 403. In a specific embodiment, the direct current signal line can include the first initialization signal line 306. For example, any one of the first initialization signal line 306, the second initialization signal line 307, and the third initialization signal line 308 can include the shield portion 14.

[0079] It is to be noted that the extending direction of the first to third initialization signal lines 306 to 308 can be the same as the extending direction of the first fan-out segments 121. In a case where at least part of one of the first to third initialization signal lines 306 to 308 is used as the shield portion 14, the orthogonal projection of the first fan-out segments 121 on the substrate 60 can be located within the orthogonal projection of one of the first to third initialization signal lines 306 to 308 on the substrate 60.

[0080] In some embodiments, as shown in FIG. 2, the first conductive layer 401 is located on the side of the second conductive layer 402 away from the substrate 60. In this way, the spacing between the data lines 11 and other conductive layers (the conductive layers between the first conductive layer 401 and the substrate 60) under the first conductive layer 401 can be increased, the parasitic capacitance between the data lines 11 and the signal lines in the other conductive layers can be reduced, the problem of data signal crosstalk of the data lines 11 due to the parasitic capacitance can be further improved, and thus the display defect problem of the display panel 100 due to the data signal crosstalk can be improved.

[0081] In some embodiments, the plurality of second fan-out segments 122 can be located at different conductive layers from the plurality of first fan-out segments 121. For example, the first conductive layer 401 further includes a plurality of second fan-out segments 122 spaced apart from the plurality of data lines 11, i.e., the plurality of data lines 11 and the plurality of second fan-out segments 122 are arranged at the same layer. In a case where the first conductive layer 401 is located on the side of the second conductive layer 402 away from the substrate 60, the parasitic capacitance between the second fan-out segments 122 and other signal lines can also be reduced, the problem of data signal crosstalk of the second fan-out segments 122 due to the parasitic capacitance can be further improved, and thus the display defect problem of the display panel 100 due to the data signal crosstalk can be improved.

[0082] In other embodiments, the plurality of second fan-out segments 122 can be located at the same conductive layer as the plurality of first fan-out segments 121. For example, the second conductive layer 402 can include the plurality of second fan-out segments 122. In this way, the connection between the first fan-out segments 121 and the second fan-out segments 122 is simpler.

[0083] In some embodiments, as shown in FIG. 2, the array layer 40 further includes a first insulating layer 409 and a second insulating layer 410. The first insulating layer 409 is arranged between the second conductive layer 402 and the third conductive layer 403. The second insulating layer 410 is arranged between the third conductive layer 403 and the first conductive layer 401.

[0084] In some embodiments, as shown in FIG. 2, the array layer 40 further includes a third insulating layer 411. The third insulating layer 411 is arranged between the first conductive layer 401 and the light-emitting device layer 50.

[0085] In some embodiments, the first insulating layer 409, the second insulating layer 410, and the third insulating layer 411 can each be an organic insulating layer. In this way, the distance between two adjacent ones of the first conductive layer 401 to the third conductive layer 403 and the light emitting device layer 50 can be increased to reduce parasitic capacitance, and the three insulating layers can function well in planarization to improve the light emitting effect of the light emitting device of the light emitting device layer 50.

[0086] In some embodiments, as shown in FIGS. 2, 4A, and 4D, the display panel 100 further includes a first semiconductor layer 407 and a second semiconductor layer 408.

[0087] As shown in FIG. 2, the first semiconductor layer 407 is disposed between the second conductive layer 402 and the substrate 60 and between the first conductive layer 401 and the substrate 60, and includes polycrystalline silicon. A buffer layer 417 is disposed between the first semiconductor layer 407 and the substrate 60. The second semiconductor layer 408 is disposed between the second conductive layer 402 and the substrate 60 and between the first conductive layer 401 and the substrate 60, and is located on a side of the first semiconductor layer 407 facing away from the substrate 60, and includes a metal oxide, including but not limited to indium gallium zinc oxide, etc. In this way, the display panel 100 includes two different semiconductor layers.

[0088] In the case where the pixel circuit 20 includes a polycrystalline silicon transistor and a metal oxide transistor, the first semiconductor layer 407 includes an active layer of the polycrystalline silicon transistor, and the second semiconductor layer 408 includes an active layer of the metal oxide transistor.

[0089] Exemplarily, as shown in FIGS. 4A and 5, the first semiconductor layer 407 can include a driving active layer 4071 of a driving transistor T1, a writing active layer 4072 of a writing transistor T2, a first light emitting active layer 4073 of a first light emitting control transistor T5, a second light emitting active layer 4074 of a second light emitting control transistor T6, a first reset active layer 4075 of a first reset transistor T7, and a second reset active layer 4076 of a second reset transistor T8. As shown in FIGS. 4D and 5, the second semiconductor layer 408 can include an initialization active layer 4081 of an initialization transistor T4 and a compensation active layer 4082 of a compensation transistor T3.

[0090] In some embodiments, as shown in FIG. 2, the array layer 40 further includes a fourth conductive layer 404 and a fifth conductive layer 405.

[0091] The fourth conductive layer 404 is disposed between the second conductive layer 402 and the substrate 60. As shown in FIG. 4B, the fourth conductive layer 404 includes scan lines, including at least one of the first to fourth scan signal lines 301 to 304 and the light emitting control signal line 305.

[0092] Exemplarily, as shown in FIG. 4B, the fourth conductive layer 404 includes the first scan signal line 301, the fourth scan signal line 304, and the light-emitting control signal line 305 arranged at intervals. The first scan signal line 301, the fourth scan signal line 304, and the light-emitting control signal line 305 all extend along the first direction x. As shown in FIG. 5, the first scan signal line 301 overlaps the write active layer 4072 of the write transistor T2. The fourth scan signal line 304 overlaps the first reset active layer 4075 of the first reset transistor T7 and the second reset active layer 4076 of the second reset transistor T8. The light-emitting control signal line 305 overlaps the first light-emitting active layer 4073 of the first light-emitting control transistor T5 and the second light-emitting active layer 4074 of the second light-emitting control transistor T6.

[0093] The fifth conductive layer 405 is disposed between the fourth conductive layer 404 and the second conductive layer 402, and includes an initialization signal line including at least one of the first initialization signal line 306 to the third initialization signal line 308. Exemplarily, as shown in FIG. 4E, the fifth conductive layer 405 includes the second initialization signal line 307.

[0094] In some embodiments, the scan line of the fourth conductive layer 404 overlaps the first fan-out section 121, and the overlapping portion between the scan line of the fourth conductive layer 404 and the first fan-out section 121 overlaps the initialization signal line of the fifth conductive layer 405. Exemplarily, as shown in FIG. 7, the fourth scan signal line 304 overlaps the second initialization signal line 307 in the overlapping portion between the fourth scan signal line 304 and the first fan-out section 121. In this way, the second initialization signal line 307 functions as a shield to improve signal crosstalk caused by parasitic capacitance between the fourth scan signal line 304 and the first fan-out section 121, and to improve the display defect problem due to signal crosstalk.

[0095] In some embodiments, as shown in FIG. 2, the array layer 40 further includes a sixth conductive layer 406. The sixth conductive layer 406 is located between the fourth conductive layer 404 and the fifth conductive layer 405. As shown in FIG. 4C, the sixth conductive layer 406 can include the third initialization signal line 308, the second scan signal line 302, and the third scan signal line 303 arranged at intervals.

[0096] Exemplarily, as shown in FIG. 2, the fourth conductive layer 404 is located on the side of the first semiconductor layer 407 away from the substrate 60. The fourth insulating layer 412 is arranged between the fourth conductive layer 404 and the first semiconductor layer 407. The sixth conductive layer 406 is located on the side of the fourth conductive layer 404 away from the substrate 60. The fifth insulating layer 413 is arranged between the sixth conductive layer 406 and the fourth conductive layer 404. The sixth conductive layer 406 is located between the second semiconductor layer 408 and the fourth conductive layer 404, and the sixth insulating layer 414 is arranged between the sixth conductive layer 406 and the second semiconductor layer 408. The fifth conductive layer 405 is located between the second semiconductor layer 408 and the second conductive layer 402, and the seventh insulating layer 415 is arranged between the fifth conductive layer 405 and the second semiconductor layer 408. The eighth insulating layer 416 is arranged between the fifth conductive layer 405 and the second conductive layer 402.

[0097] In some embodiments, as shown in FIG. 4B and FIG. 4F, the first initialization signal line 306 can include a first lower initialization signal line 306a located in the fourth conductive layer 404 and a first upper initialization signal line 306b located in the second conductive layer 402, the first lower initialization signal line 306a and the first upper initialization signal line 306b being connected through a via in the insulating layer.

[0098] In some embodiments, as shown in FIG. 4C and FIG. 4F, the third initialization signal line 308 can include a third lower initialization signal line 308a located in the sixth conductive layer 406 and a third upper initialization signal line 308b located in the second conductive layer 402, the third lower initialization signal line 308a and the third upper initialization signal line 308b being connected through a via in the insulating layer.

[0099] In some embodiments, as shown in FIG. 4C and FIG. 4E, the second scan signal line 302 includes a second lower scan signal line 302a located in the sixth conductive layer 406 and a second upper scan signal line 302b located in the fifth conductive layer 405, the second lower scan signal line 302a and the second upper scan signal line 302b being connected through a via in the insulating layer. As shown in FIG. 5, the second lower scan signal line 302a and the second upper scan signal line 302b both overlap with the initialization active layer 4081 of the initialization transistor T4.

[0100] In some embodiments, as shown in FIG. 4C and FIG. 4E, the third scan signal line 303 includes a third lower scan signal line 303a located in the sixth conductive layer and a third upper scan signal line 303b located in the fifth conductive layer 405, the third lower scan signal line 303a and the third upper scan signal line 303b being connected through a via in the insulating layer. As shown in FIG. 5, the third lower scan signal line 303a and the third upper scan signal line 303b both overlap with the compensation active layer 4082 of the compensation transistor T3.

[0101] Based on the same inventive concept, some embodiments of the present application also provide a display device. The display device comprises the display panel 100 of any of some embodiments described above.

[0102] In summary, for the display panel and the display device of some embodiments of the present application, the shielding part plays a shielding role between the mutually insulated and intersecting first fan-out lines and the data lines, improves the problem of parasitic capacitance formed between the mutually insulated and intersecting first fan-out lines and the data lines, and improves the problem of display defects caused by the crosstalk of the data signal.

[0103] The above description of the embodiments is only used to help understand the technical solutions of the present application and its core idea; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, wherein, The display panel has a display area, and the display panel comprises: a substrate; a first conductive layer disposed on the substrate and comprising a plurality of data lines in the display area; a second conductive layer disposed on the substrate and located on one side of the first conductive layer and comprising a plurality of first fan-out segments in the display area, the plurality of first fan-out segments respectively intersecting the plurality of data lines, and one first fan-out segment being connected to one data line; and a third conductive layer disposed between the first conductive layer and the second conductive layer and comprising a shielding portion; wherein an overlapping portion between one first fan-out segment and at least one data line intersecting the first fan-out segment and insulated from the first fan-out segment overlaps the shielding portion.

2. The display panel of claim 1, wherein, The display panel further comprises a direct current signal line, and the direct current signal line comprises the shielding portion.

3. The display panel of claim 2, wherein, The direct current signal line comprises a positive power voltage signal line.

4. The display panel of claim 3, wherein, The positive power voltage signal line comprises a longitudinal main body portion and the shielding portion connected to each other, the longitudinal main body portion has the same extension direction as the data lines, the longitudinal main body portion is arranged away from the data lines, and the shielding portion has the same extension direction as the first fan-out segments.

5. The display panel of claim 1, wherein, The display panel further comprises: a first initialization signal line, a second initialization signal line, and a third initialization signal line; and a pixel circuit comprising: a drive transistor; a write transistor, a source and a drain of the write transistor being connected between one data line and one of a source and a drain of the drive transistor; an initialization transistor, a source and a drain of the initialization transistor being connected between the first initialization signal line and a gate of the drive transistor; a light emitting device connected to the other of the source and the drain of the drive transistor; a first reset transistor, one of a source and a drain of the first reset transistor being connected to the second initialization signal line, and the other of the source and the drain of the first reset transistor being connected between the light emitting device and the other of the source and the drain of the drive transistor; and a second reset transistor, a source and a drain of the second reset transistor being connected between the third initialization signal line and one of the source and the drain of the drive transistor; wherein at least one of the first initialization signal line, the second initialization signal line, and the third initialization signal line comprises the shielding portion.

6. The display panel of claim 1, wherein, The first conductive layer is located on a side of the second conductive layer away from the substrate.

7. The display panel of claim 6, wherein, The first conductive layer further comprises a plurality of second fan-out segments spaced apart from the plurality of data lines, the plurality of second fan-out segments having an extension direction intersecting an extension direction of the plurality of first fan-out segments, and one second fan-out segment being connected to one first fan-out segment.

8. The display panel of claim 6, wherein, The display panel further comprises: a fourth conductive layer disposed between the second conductive layer and the substrate and comprising a scan signal line; a fifth conductive layer disposed between the fourth conductive layer and the second conductive layer and comprising an initialization signal line; The scanning signal line overlaps the first fan-out segment, and an overlapping portion between the scanning signal line and the first fan-out segment overlaps the initialization signal line.

9. The display panel of claim 1, wherein, The display panel further comprises: a first semiconductor layer disposed between the second conductive layer and the substrate and between the first conductive layer and the substrate, and comprising polysilicon; and a second semiconductor layer disposed between the second conductive layer and the substrate and between the first conductive layer and the substrate, and located on a side of the first semiconductor layer away from the substrate, and comprising metal oxide.

10. A display device, wherein, The display device comprises a display panel having a display area, the display panel comprising: a substrate; a first conductive layer disposed on the substrate and comprising a plurality of data lines located in the display area; a second conductive layer disposed on the substrate and located on a side of the first conductive layer, and comprising a plurality of first fan-out segments located in the display area, the plurality of first fan-out segments respectively intersecting the plurality of data lines, and one first fan-out segment being connected to one data line; and a third conductive layer disposed between the first conductive layer and the second conductive layer, and comprising a shielding portion; wherein an overlapping portion between one first fan-out segment and at least one data line insulated from the one first fan-out segment overlaps the shielding portion.

11. The display device of claim 10, wherein, The display panel further comprises a direct current signal line, and the direct current signal line comprises the shielding portion.

12. The display device of claim 11, wherein, The direct current signal line comprises a positive power voltage signal line.

13. The display device of claim 12, wherein, The positive power voltage signal line comprises a longitudinal main body portion and the shielding portion connected to each other, the longitudinal main body portion has the same extension direction as the data lines, the longitudinal main body portion is arranged staggered with respect to the data lines, and the shielding portion has the same extension direction as the first fan-out segments.

14. The display device of claim 10, wherein, The display panel further comprises: a first initialization signal line, a second initialization signal line, and a third initialization signal line; and a pixel circuit comprising: a driving transistor; a write transistor, a source and a drain of the write transistor being connected between one data line and one of a source and a drain of the driving transistor; an initialization transistor, a source and a drain of the initialization transistor being connected between the first initialization signal line and a gate of the driving transistor; a light emitting device connected to the other of the source and the drain of the driving transistor; a first reset transistor, one of a source and a drain of the first reset transistor being connected to the second initialization signal line, and the other of the source and the drain of the first reset transistor being connected between the light emitting device and the other of the source and the drain of the driving transistor; and a second reset transistor, a source and a drain of the second reset transistor being connected between the third initialization signal line and one of the source and the drain of the driving transistor; wherein at least one of the first initialization signal line, the second initialization signal line, and the third initialization signal line comprises the shielding portion.

15. The display device of claim 10, wherein, The first conductive layer is located on a side of the second conductive layer away from the substrate.

16. The display device of claim 15, wherein, The first conductive layer further comprises a plurality of second fan-out segments spaced apart from the plurality of data lines, the plurality of second fan-out segments have an extending direction intersecting with the extending direction of the plurality of first fan-out segments, and one of the second fan-out segments is connected with one of the first fan-out segments.

17. The display device of claim 15, wherein, The display panel further comprises: a fourth conductive layer disposed between the second conductive layer and the substrate and comprising scan signal lines; a fifth conductive layer disposed between the fourth conductive layer and the second conductive layer and comprising initialization signal lines; wherein the scan signal lines overlap with the first fan-out segments, and the overlapping part between the scan signal lines and the first fan-out segments overlaps with the initialization signal lines.

18. The display device of claim 10, wherein the display panel further comprises: a first semiconductor layer disposed between the second conductive layer and the substrate and between the first conductive layer and the substrate and comprising polysilicon; and a second semiconductor layer disposed between the second conductive layer and the substrate and between the first conductive layer and the substrate and located on the side of the first semiconductor layer away from the substrate and comprising metal oxide.

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