Semiconductor structure, and semiconductor device and forming method therefor

Abstract

A semiconductor structure, and a semiconductor device and a forming method therefor. The semiconductor structure comprises: a substrate; first trench groups, located in the substrate, each first trench group comprising first trenches; and a trench communication part, which communicates adjacent first trenches. The semiconductor structure has good performance.

Description

Semiconductor structures and semiconductor devices and their fabrication methods

[0001] This application claims priority to Chinese Patent Application No. 202410644060.0, filed on May 20, 2024, entitled "Semiconductor Structure and Semiconductor Device and Method of Forming the Same Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and semiconductor device and a method for forming the same. Background Technology

[0003] Interposers are the medium through which chips and modules transmit signals in 2.5D and 3D semiconductor packaging, enabling interconnection between chips and with the packaging substrate. Silicon interposers, due to their superior fine-pitch wiring capabilities and through-silicon via (TSV) interconnection capabilities, can meet high-density I / O requirements and play a crucial role in 2.5D and 3D semiconductor packaging.

[0004] To meet the demands of high computing power and high speed, Siinterposers typically require the design of a large number of silicon capacitors. These silicon capacitors play an important role in power and signal integrity, ensuring the power supply stability or high-frequency impedance characteristics of the device.

[0005] Summary of the Invention

[0006] Based on this, and in response to the above problems, this disclosure provides a semiconductor structure and a semiconductor device and a method for forming the same.

[0007] This disclosure provides a semiconductor structure, including: a substrate; a first trench group located within the substrate; at least two first trench groups arranged along a second direction X'; the first trench group includes a first trench; a connecting trench portion connecting adjacent first trenches located in a third direction Y; the second direction X' and the third direction Y have an angle.

[0008] Because of the presence of the connecting trench, the above semiconductor structure can ensure that the substrate has low structural stress, low warpage, and good surface flatness.

[0009] The semiconductor structure comprises: a first trench group arranged in the substrate, a plurality of first trench groups arranged along a first direction X; a second trench group arranged in the substrate, a plurality of second trench groups arranged along the first direction X; wherein the first trench group and the second trench group are arranged in an array, and two second trench groups along the first direction X are separated by the first trench group; the first direction X, the second direction X' and the third direction Y are in the same plane, the first direction X is perpendicular to the third direction Y, the second direction X' intersects the first direction X and the third direction Y, and the angle between the second direction X' and the third direction Y is an acute angle.

[0010] The semiconductor structure further reduces the overall structural stress of the substrate, and the overall warping degree of the substrate is smaller and the surface flatness is better.

[0011] In one of the embodiments, the first trench extends along the third direction Y, and the second trench group comprises a second trench extending along the first direction X.

[0012] In one of the embodiments, the number of the first trenches in each first trench group is N, and the communication trench part comprises a communication trench, and the number of the communication trenches is greater than or equal to N / 2. In this way, the structural stress of the substrate is smaller, and the reliability is higher.

[0013] In one of the embodiments, the communication trench extends along the third direction Y, and the communication trench and the first trench adjacent to the communication trench along the upper and lower directions of the third direction Y are collinearly aligned.

[0014] In one of the embodiments, the number ratio of the first trench group and the second trench group is close to 1.

[0015] In one of the embodiments, along the third direction Y, the second trench group comprises a side surface located at the edge thereof, and the first trench group comprises a plurality of end surfaces located at the end of the first trench; and the side surface and the end surface are flush along the first direction X.

[0016] In one of the embodiments, along the third direction Y, there is a first gap between two adjacent second trench groups; along the first direction X, there is a second gap between the first trench group and the adjacent second trench group; and the size of the first gap is greater than the size of the second gap.

[0017] The semiconductor structure comprises: an extension trench part connected with the first trench group, the extension trench part comprising an extension trench extending along the third direction Y, the extension trench being in communication with the first trench and collinearly aligned along the third direction Y.

[0018] The semiconductor structure increases the proportion of the trenches in the substrate, increases the specific surface area of the trench structure in the substrate, and increases the capacitance value density of the silicon capacitor in the substrate due to the existence of the extension trench part.

[0019] In one of the embodiments, the top and bottom of the first trench have a first width and a second width, respectively, and the top and bottom of the second trench have a third width and a fourth width, respectively, the first width and the second width being substantially the same, and the third width and the fourth width being substantially the same. The structure that the top and bottom of the trench have substantially the same width makes the continuity of the capacitor material good, the thickness uniformity good, the capacitance density of the silicon capacitor high, and the leakage current small.

[0020] In one of the embodiments, the first width and the third width are in the range of 0.3-1.6um.

[0021] In one of the embodiments, the first trench has a first depth, and the second trench has a third depth, the first depth being greater than the third depth.

[0022] The present disclosure also provides a semiconductor device, comprising: a substrate;

[0023] a first trench group located in the substrate; at least two groups of the first trench group are arranged along a second direction X'; the first trench group comprises a plurality of first trenches; a communication trench part that communicates the first trenches located adjacent to each other in a third direction Y; a second trench group located in the substrate, a plurality of second trench groups are arranged along a first direction X; wherein the second trench group and the first trench group are arranged in an array, two second trench groups in the first direction X are separated by the first trench group; a capacitor stack stacked on the first trench group, the second trench group and the communication trench part, wherein the capacitor stack continuously extends on the side wall and the bottom surface of the first trench group, the second trench group and the communication trench part; the first direction X, the second direction X' and the third direction Y are located in the same plane, the first direction X is perpendicular to the third direction Y, the second direction X' intersects the first direction X and the third direction Y, and the angle between the second direction X' and the third direction Y is an acute angle.

[0024] In one of the embodiments, the capacitor stack has a protrusion at the position where the side wall and the bottom surface intersect. The protrusion is provided to make the thickness of the capacitor stack at this position have better continuity and uniformity, and thus the leakage current of the silicon capacitor is smaller.

[0025] In one of the embodiments, it further comprises a first contact plug, the capacitor stack comprises an upper electrode and a lower electrode, and a plurality of first contact plugs are located in the edge region of the substrate, and the edge region has only one of the upper electrode or the lower electrode.

[0026] In one of the embodiments, it further comprises a second contact plug, wherein along the third direction, there is a first gap between two adjacent second trench groups; along the third direction, there is a third gap between the adjacent first trench group and the second trench group; and the second contact plug is located on the first gap and the third gap. By providing the second contact plug at the positions of the first gap and the third gap, more and shorter conductive paths are additionally provided, the resistance of the interconnection structure is reduced, and the equivalent resistance of the entire silicon capacitor is reduced.

[0027] The present disclosure also provides a method for forming a semiconductor device, comprising: providing a substrate; forming a first trench group, a second trench group and a communication trench part in the substrate; forming a capacitor stack, the capacitor stack being stacked on the first trench group, the second trench group and the communication trench part, wherein the capacitor stack continuously extends on the sidewalls and the bottom surface of the first trench group, the second trench group and the communication trench part.

[0028] In one embodiment, when forming the first trench group, the second trench group and the communication trench part in the substrate, a dummy trench is also formed on the outer edge of the substrate. The dummy trench can avoid the problem of uneven width of the formed trenches.

[0029] In one embodiment, the capacitor stack forms a protrusion at the position where the sidewall and the bottom surface meet.

[0030] In one embodiment, when forming the capacitor stack, an upper electrode, a dielectric layer and a lower electrode are also formed, the lower electrode continuously extends to cover the surface of the substrate, and the upper electrode and the dielectric layer do not continuously extend to cover the surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1A, FIG. IB, FIG. 3-FIG. 5 are top views of the semiconductor structure of the present disclosure.

[0032] FIG. 6 is a sectional view of the semiconductor structure of the present disclosure.

[0033] FIG. 7, FIG. 8 are sectional views of the semiconductor device of the present disclosure.

[0034] FIG. 9A-FIG. 9E are top views of the semiconductor device of the present disclosure.

[0035] FIG. 10A-FIG. 10D are sectional views of the structure corresponding to the method for forming the semiconductor device of the present disclosure. DETAILED DESCRIPTION

[0036] The technical solutions of the present disclosure will be further described in detail below in combination with the drawings and embodiments. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] In the following paragraphs, the present disclosure will be described in more detail with reference to the accompanying drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting in the description of the embodiments of the present disclosure.

[0038] It can be understood that the meanings of "on", "over", and "above" in the present disclosure should be interpreted in the broadest way, such that "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0039] In the embodiments of the present disclosure, the terms "first", "second", "third", and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0040] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, the layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between a top surface and a bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0041] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0042] The main function of the silicon capacitor decoupling capacitor is to reduce noise and decoupling, so the larger the capacitance value density of the silicon capacitor is required, and the smaller the equivalent resistance and leakage current of the interconnection structure are required, and at the same time, the overall structure of the Si interposer is required to have good reliability, high surface flatness, and small warpage.

[0043] Therefore, the semiconductor structure of the technical solutions of the present disclosure will be described in detail below in combination with the drawings and specific embodiments.

[0044] Referring to FIGS. 1A and 1B, the present disclosure provides a semiconductor structure, comprising: a substrate 1; a first trench group 2 located in the substrate 1; at least two first trench groups 2 are arranged along a second direction X'; the first trench group 2 comprises a plurality of first trenches 20; a communication trench part 3 communicates the first trenches 20 located adjacent to each other in a third direction Y.

[0045] The substrate 1 can include but is not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate. When the substrate 1 is a single crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a doped silicon substrate, and further can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The substrate 1 can include but is not limited to an organic substrate, a glass substrate, a ceramic substrate, a metal substrate.

[0046] The semiconductor structure comprises at least two first trench groups 2, the two first trench groups 2 are arranged in staggered manner, the staggered manner is parallel to the second direction X'. Referring to the top view of the semiconductor structure shown in FIG. 1A and FIG. 1B, the connecting line connecting the features at the same position on the two first trench groups 2 is parallel to the second direction X'. For example, the connecting line connecting the center point O of one first trench group 2 with the center point O' of another first trench group 2 is parallel to the second direction X', where the center points O and O' can be fictitious points and can not belong to the structural features on the first trench group 2; or the connecting line connecting the corner point A of one first trench group 2 with the corner point B of another first trench group 2 is parallel to the second direction X'.

[0047] Here, for the convenience of description, as shown in FIG. 1 and FIG. 1B, the first direction X, the second direction X' and the third direction Y are defined to be located in the same plane, the first direction X is perpendicular to the third direction Y, the second direction X' intersects with the first direction X and the third direction Y, and the included angle θ between the second direction X' and the third direction Y is an acute angle.

[0048] The first trench group 2 comprises a plurality of first trenches 20, for example, the first trench 20 is a rectangular trench, the plurality of first trenches 20 of each first trench group 2 are parallel to each other, and each first trench 20 extends along the third direction Y. The shape and extension direction of the first trench 20 can also be other embodiments, such as the shape of the first trench 20 is a circular arc trench (not shown in the figure), which is not limited here.

[0049] The rectangular trench required by the present disclosure can be a standard right-angled rectangle, a rounded rectangle (the rectangular end or the right-angled position is a circular arc), or even an approximate ellipse. The rectangular shape does not constitute a limitation to the trench, for example, the rectangular trench extending along the third direction Y can be the center line of the trench extending along the third direction.

[0050] The semiconductor structure further comprises a communication trench part 3, the communication trench part 3 communicates the first trenches 20 located adjacent in the third direction Y. Because at least two first trench groups 2 are arranged in staggered manner, there are upper and lower adjacent first trenches along the third direction Y at the position where the two first trench groups 2 are close to each other. The communication trench part 3 comprises a plurality of communication trenches 30, and the plurality of communication trenches 30 communicate the upper and lower adjacent first trenches 20 along the third direction Y.

[0051] The existence of the communication trench part 3 and the communication trench 30 can ensure that the structure stress of the substrate 1 is small and the reliability is high, especially the warping degree of the substrate 1 perpendicular to the third direction Y is small, the surface flatness of the substrate 1 is good, and the metal interconnection structure in the substrate 1 is reliable, thereby ensuring the interconnection reliability of the substrate 1 and the chip or module or other substrate package.

[0052] Each of the communication trenches 30 extends along the third direction Y, as an example, when each of the first trenches 20 extends along the third direction Y, the communication trench 30, together with the two first trenches 20 adjacent to it along the third direction Y, are collinearly communicated.

[0053] In one embodiment, the number of the first trenches 20 in each of the first trench groups 2 is N, and the number of the communication trenches 30 in each of the communication trench groups 3 is M, where the included angle θ between the second direction X' and the third direction Y is an acute angle including zero, and when the included angle θ is zero, the number M of the communication trenches 30 is equal to the number N of the first trenches 20. At this time, the two first trench groups 2 adjacent along the third direction Y are completely connected by the communication trench group 3.

[0054] In other embodiments, the number M of the communication trenches 30 is at least a natural number 1, that is, there is at least one communication trench 30 between the two first trench groups 2 adjacent along the third direction Y. In order to make the structure stress of the substrate 1 smaller and the reliability higher, in preferred embodiments, the number M of the communication trenches 30 is greater than or equal to N / 2.

[0055] As an example, FIG. 1 only shows the two first trench groups 2 adjacent along the third direction Y and the corresponding communication trench group 3 and the communication trenches 30 thereof, the first trenches 20 extend along the third direction Y, the communication trenches 30 extend along the third direction Y, the collinearly communicated first trenches 20 and the communication trenches 30 are rectangular trenches, and the number M of the communication trenches 30 is equal to half of the number N of the first trenches 20. However, this example does not constitute a specific implementation limitation.

[0056] Referring to FIG. 2, the semiconductor structure provided by the present disclosure further comprises: a second trench group 4 located in the substrate 1, and a plurality of second trench groups 4 are arranged along the first direction X; wherein the second trench group 4 and the first trench group 2 are arrayed, and the two second trench groups 4 arranged along the first direction X are separated by the first trench group 2, or the two first trench groups 2 adjacent along the first direction X are separated by the second trench group 4, and the first trench group 2 and the second trench group 4 are arranged in a vertical and horizontal staggered manner. In this embodiment, the arrangement mode of the plurality of first trench groups 2 is set according to any embodiment of the semiconductor structure in FIG. 1, which will not be described here.

[0057] In another embodiment, a plurality of second trench groups 4 are arranged along the second direction X', forming a second trench group array. Referring to the embodiment shown in FIG. 1, a plurality of first trench groups 2 are arranged along the second direction X', forming a first trench group array. The first trench group array and the second trench group array are arranged in a staggered manner along the first direction X, and the two second trench group arrays arranged along the first direction X are separated by one first trench group array, or the two first trench groups 2 arranged along the first direction X are separated by the second trench group 4, and the first trench group 2 and the second trench group 4 are arranged in a vertical and horizontal staggered manner.

[0058] In the two embodiments, at least part of the first grooves 20 in the first groove group 2 are interconnected by the communicating groove portion 3, and the first groove group 2 and the second groove group 4 are arranged in a cross manner, which further ensures that the overall structural stress of the substrate 1 is small, and in particular, the warping of the substrate 1 in the direction perpendicular to the first direction X is also reduced, and the overall warping of the substrate 1 is smaller, and the surface flatness is better.

[0059] As a preferred embodiment, the ratio of the number of the first groove group 2 to the number of the second groove group 4 in the substrate 1 is close to 1, the first groove group 2 and the second groove group 4 are arranged in a cross manner, and at least part of the first grooves 20 in the first groove group 2 are interconnected by the communicating groove portion 3. The ratio close to 1 can further reduce the overall structural stress of the substrate 1, and ensure the surface flatness and warping of the substrate 1.

[0060] With reference to FIG. 2, the second groove group 4 includes a plurality of second grooves 40. As an example, the second grooves 40 are rectangular grooves, the plurality of second grooves 40 in each second groove group 4 are parallel to each other, and each second groove 40 extends along the first direction X. The shape and extension direction of the second grooves 40 can also be other embodiments, such as circular arc grooves, wavy line grooves (not shown in the figure). It can be understood that FIG. 2 only gives a preferred example, and the implementation is not limited.

[0061] With reference to FIG. 3, in the third direction Y, there is a first gap 61 between adjacent second groove groups 4, and the size is D1 as shown in the figure; along the first direction X, there is a second gap 62 between adjacent second groove groups 4 and the first groove group 2, and the size is D2 as shown in the figure; the size D1 of the first gap 61 is greater than the size D2 of the second gap 62. As an example, as shown in FIG. 3, the second grooves 40 are rectangular grooves, the plurality of second grooves 40 in each second groove group 4 are parallel to each other, and each second groove 40 extends along the first direction X. At this time, the size of the first gap 61 between adjacent second groove groups 4 is unique, and is equal in the third direction Y, that is, the two second grooves 40 in the adjacent positions of the adjacent second groove groups 4 are parallel. For the shape and extension direction of the second grooves 40 are other embodiments, such as circular arc grooves, wavy line grooves (not shown in the figure), at this time, the size of the first gap 61 between adjacent second groove groups 4 is not unique, and can not be equal in the third direction Y.

[0062] In the embodiment, the size D1 of the first gap 61 is larger than the size D2 of the second gap 62, but it should be understood that the second gap 62 does not limit the first gap 61, the size D1 of the first gap 61 is larger than the size D2 of the second gap 62, that is, the space of the first gap 61 is larger than the space of the second gap 62, and it is more convenient and has more freedom to arrange other interconnection structures in the position of the first gap 61, such as the arrangement and size of the interconnection structure. Those skilled in the art should understand that other interconnection structures can also be arranged in the space of the second gap 62, and the embodiment does not constitute a limitation.

[0063] With continuous reference to FIG. 3, the second grooves 40 are rectangular grooves, the multiple second grooves 40 of each second groove group 4 are parallel to each other, and each second groove 40 extends along the first direction X. In the third direction Y, the second groove group 4 includes a side surface located at the edge thereof, which is a side edge in the top view. Since the second grooves 40 are rectangular grooves, the side edge is a straight line extending along the first direction X. In the third direction Y, there is a first gap 61 between adjacent second groove groups 4, and at this time, the size D1 of the first gap 61 between the adjacent second groove groups 4 is the same.

[0064] In the embodiment, the end face of the first groove 20 is provided at the end of the first groove 20, and the end faces of the multiple first grooves 20 of each first groove group 2 are flush in the first direction X. For example, the end faces of the multiple first grooves 20 located at the upper end of the first groove 20 are flush along the third direction Y, or the end faces of the multiple first grooves 20 located at the lower end of the first groove 20 are flush.

[0065] As an example, the first grooves 20 are rectangular grooves, the multiple first grooves 20 of each first groove group 2 are parallel to each other, and each first groove 20 extends along the third direction Y. The rectangular groove has a long side and a wide side, and the end face is provided at the wide side of the first groove 20, and the multiple end faces on the same side along the third direction Y are flush.

[0066] In the embodiment, the second groove group 4 has a side surface of the edge of the second groove 40 located at the edge thereof, and since the first groove 20 has multiple end faces flush on the same side in the third direction Y, the side surface and the multiple end faces are also flush in the first direction X. Alternatively, along the third direction Y, there are adjacent first groove groups 2 and second groove groups 4, the first groove 20 has multiple end faces flush on the same side in the third direction Y, the second groove group 4 has a side surface located at the edge thereof, and the side surface and the end face have a third gap 63 in the third direction Y. As shown in FIG. 3, the size D1 of the first gap 61 is equal to the size D3 of the third gap 63. The position of the third gap 63 provides more space for subsequent arrangement of other interconnection structures. It can be understood that the size D1 of the first gap 61 and the size D3 of the third gap 63 can be equal or not equal, for example, D1 is larger than D3. Here, only a preferred example is given, and the implementation is not specifically limited.

[0067] Referring to FIG. 4, the semiconductor structure further comprises an extension trench portion 5 disposed in the third gap 63, the extension trench portion 5 is connected with the first trench group 2, wherein the extension trench portion 5 comprises a plurality of extension trenches 50, the extension trenches 50 are communicated with the first trenches 20.

[0068] As an example, the first trench 20 is a rectangular trench, the plurality of first trenches 20 of each first trench group 2 are parallel to each other, and each first trench 20 extends along the third direction Y. The extension trench 50 is a rectangular trench, the plurality of extension trenches 50 of each extension trench portion 5 are parallel to each other, and each extension trench 50 extends along the third direction Y. When the extension trench portion 5 is connected with the first trench group 2, the corresponding extension trench 50 is communicated with the first trench 20, and the communicated extension trench 50 and the first trench 20 are collinearly aligned along the third direction Y.

[0069] The shape and extension direction of the first trench 20 and the extension trench 50 can also be other embodiments, such as the shape of the first trench 20 and the extension trench 50 can be a circular arc trench or a wavy line trench (not shown in the figure), and when the extension trench portion 5 is connected with the first trench group 2, the corresponding extension trench 50 is connected with the first trench 20, and the two are communicated with each other at the connection. It can be understood that FIG. 4 only gives a preferred example, and the implementation is not specifically limited.

[0070] In the embodiments of the present disclosure, the existence of the communicated trench portion 3 and the extension trench portion 5 increases the proportion of the trenches in the substrate 1 (or the interposer or Si interposer) in the space of the substrate 1, and increases the specific surface area (the ratio of the sum of the side wall and bottom surface areas of the trenches to the sum of the volumes of the trenches) of the trench structure in the substrate 1. The capacitance value density (the size of the capacitance value per unit area from the top view) of the silicon capacitor made in the substrate 1 is larger. It should be noted that the connection of the communicated trench portion 3 and the first trench group 2 firstly ensures that the structural stress of the substrate 1 is smaller, and secondly increases the capacitance value density of the silicon capacitor in the substrate 1.

[0071] In the present embodiment, the extension trench portion 5 is communicated with the first trench group 2, because the characteristic size (such as length, width) of the extension trench portion 5 is usually relatively small, and if it is not communicated with the first trench group 2, the difficulty of process manufacturing is increased. Therefore, the communication of the extension trench portion 5 and the first trench group 2 is only given as a preferred example, and the implementation is not specifically limited. That is, the semiconductor structure comprises an extension trench portion 5, the extension trench portion 5 is located between the first trench group 2 and the second trench group 4 adjacent along the third direction Y, and the extension trench portion 5 can be communicated with or not communicated with the first trench group 2.

[0072] In another embodiment, as shown in Fig. 5, the extension groove part 5 is arranged at the third gap 63, and there are two third gaps 63 on the two sides adjacent to the first gap 61, the extension groove part 5 can be arranged at both of the two third gaps 63, or only arranged at one of the third gaps 63 as shown in Fig. 4, or arranged according to actual needs, the purpose is to increase the capacitance density of the silicon capacitor in the substrate 1.

[0073] Fig. 6 is a cross-sectional view of the substrate 1 in Fig. 5 along the directions of E-E', F-F', and G-G', the cross-sectional view along the direction of E-E' is the cross-section of the first groove group 2, the cross-sectional view along the direction of F-F' is the cross-section of the second groove group 4, and the cross-sectional views along the directions of G-G' from left to right are the extension groove part 5, the communication groove part 3, and the extension groove part 5 respectively. Among them, the cross-section along the direction of E-E' is close to the cross-section along the direction of G-G'.

[0074] As an example, as shown in Fig. 5, the top view of the extension groove 50, the communication groove 30, the second groove 40, and the first groove 20 is a rectangular groove, and the width of the rectangle is basically consistent. Referring to Fig. 6, along the depth Z direction, the width of the top and the width of the bottom of the rectangle are basically consistent. Here, the positions of the top and the bottom are a relative position concept, and the specific positions are not limited.

[0075] The basically consistent or approximately equal in the disclosure refers to that the sizes can be completely the same, or within a certain tolerance range, and the specific tolerance size can be determined according to the actual processing technology requirements, and the basically consistent is within the preset tolerance range.

[0076] As shown in Fig. 6, the top and the bottom of the first groove 20 respectively have a first width W1 and a second width W2, and the first width W1 and the second width W2 are basically consistent. The top and the bottom of the second groove 40 respectively have a third width W3 and a fourth width W4, and the third width W3 and the fourth width W4 are basically consistent. In this embodiment, the first width W1 and the third width W3 are also basically consistent, and the first width and the third width are preferably in the range of 0.2-1.6um, which can be any size of 0.2um, 0.3um, 0.5um, 0.9um, 1.2um, 1.5um, 1.6um, of course, it can also be other ranges greater than 1.6um or less than 0.2um, and under the preferred conditions of the embodiment, the capacitance density of the silicon capacitor obtained in the range of 0.2-1.6um is high.

[0077] In the disclosure, the structure that the width of the top and the bottom of the groove is basically consistent, such structure is easier for subsequent filling of the capacitor material, the filled capacitor material has good continuity and thickness consistency, the silicon capacitor has high capacitance density and small leakage current.

[0078] Continuing to refer to FIG. 6, the depth of the embodiment is in the fourth direction Z direction.

[0079] In the E-E' direction cross-sectional view, the depths of the plurality of first grooves 20 of the first groove group 2 are different, wherein the first grooves 20 have a first depth H1 near the position where the first grooves 20 communicate with the extension groove part 5, and the first depths H1 of the plurality of first grooves 20 are substantially uniform; the first grooves 20 have a second depth H2 near the position where the first grooves 20 communicate with the connection groove part 3, and the second depths H2 of the plurality of first grooves 20 are substantially uniform; and the second depth H2 is greater than the first depth H1.

[0080] In the F-F' direction cross-sectional view, the second grooves 40 of the second groove group 4 have a third depth H3, and the third depths H3 of the plurality of second grooves 40 are substantially uniform.

[0081] In the G-G' direction cross-sectional view, the fourth depths H4 of the plurality of communication grooves 30 of the communication groove part 3 are substantially uniform, and the fifth depths H5 of the plurality of extension grooves 50 of the extension groove part 5 are substantially uniform.

[0082] Among them, as shown by the dashed line in FIG. 6, the third depth H3 is the smallest; the first depth H1 and the fifth depth H5 are substantially uniform, both of which are greater than the third depth H3; the second depth H2 and the fourth depth H4 are substantially uniform, both of which are greater than the first depth H1.

[0083] In the present disclosure, the second groove group 4 (corresponding to the third depth H3), the extension groove part 5 (corresponding to H5), the first groove group 2 (corresponding to H1, H2), and the communication groove part 3 (corresponding to H4) are etched to form grooves, which can form a structure in which the depths of the second grooves 40, the extension grooves 50, the first grooves 20, and the communication grooves 30 increase in turn. It can be understood here that if there is no communication groove part 3 and extension groove part 5, the depths of the grooves formed by synchronous etching of the second groove group 4 and the first groove group 2 will be substantially uniform, and in the present embodiment, the presence of the communication groove part 3 and the extension groove part 5 makes the depth of the first groove group 2 increase more than before, thereby increasing the capacitance density of the silicon capacitor.

[0084] The present disclosure also provides a semiconductor device, comprising: any of the semiconductor structures disclosed above; and a capacitor stack stacked in the semiconductor structure; wherein the capacitor stack continuously extends on the sidewalls and bottom surfaces of the first groove group 2, the communication groove part 3, or the first groove group 2, the communication groove part 3, and the second groove group 4, or the first groove group 2, the communication groove part 3, the second groove group 4, and the extension groove part 5.

[0085] In one embodiment, the semiconductor structure comprises: a substrate 1; a first trench group 2 located in the substrate 1; at least two first trench groups 2 are arranged along a second direction X'; the first trench group 2 comprises a plurality of first trenches 20; a communication trench part 3 which communicates the first trenches 20 located in the third direction Y.

[0086] In one embodiment, the semiconductor structure further comprises: a second trench group 4 located in the substrate 1, a plurality of second trench groups 4 are arranged along a first direction X; wherein the second trench group 4 and the first trench group 2 are arrayed, and two second trench groups 4 arranged along the first direction X are separated by the first trench group 2.

[0087] In one embodiment, the semiconductor structure further comprises: an extension trench part 5 connected with the first trench group 2, wherein the extension trench part 5 comprises a plurality of extension trenches 50, and the extension trenches 50 are communicated with the first trenches 20.

[0088] As an example, the capacitor stack is a three-layer structure including a lower electrode layer, a dielectric layer, and an upper electrode layer, or a five-layer structure of electrode layer 1, dielectric layer 1, electrode layer 2, dielectric layer 2, and electrode layer 3, or a more layer structure. Each electrode layer here can be a single layer or a multi-layer sub-electrode layer, and can be a layered structure or a composite structure composed of multiple, same or different sub-electrode layers. Each dielectric layer here can be a single layer or a multi-layer sub-dielectric layer, and can be a layered structure or a composite structure composed of multiple, same or different sub-dielectric layers.

[0089] The material of the electrode layer here can be metal or conductive non-metal, and the material of the dielectric layer can be insulator or semiconductor. For example, the electrode material can be one or more of tungsten, copper, aluminum, gold, silver, or titanium nitride, doped polysilicon, and the dielectric layer material can be one or more of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, lanthanum oxide, and niobium oxide.

[0090] Referring to FIG. 7, taking a number of first trenches 20 of the first trench group 2 in the T region shown in FIG. 6 as an example, the capacitor stack continuously extends on the sidewall and bottom surface of the first trench 20, and the capacitor stack includes a lower electrode 71, a dielectric layer 81, and an upper electrode 72, wherein the lower electrode 71, the dielectric layer 81, and the upper electrode 72 successively cover the sidewall and bottom surface of the first trench 20, and each of the lower electrode 71, the dielectric layer 81, and the upper electrode 72 also continuously or discontinuously covers the top surface between the corresponding trenches, which is the surface of the substrate 1 in the top view. The capacitor stack shown only includes three layers of the lower electrode 71, the dielectric layer 81, and the upper electrode 72, and in fact, more layers of structure can be provided, such as a five-layer or more-layer stacked capacitor stack formed by further stacking dielectric layers and electrode layers on the lower electrode 71, the dielectric layer 81, and the upper electrode 72. The more the number of layers is, the greater the capacitance density is, but the corresponding leakage current, process difficulty, and cost are also increased, and a controllable balance needs to be found, which is not limited herein.

[0091] The upper electrode and the lower electrode can be a single-layer conductive material structure, or a multi-layer electrode structure of the same or different conductive materials, or a composite conductive material electrode structure formed by different conductive materials, which is not limited herein. Similarly, the dielectric layer can be a high-k material, or a multi-layer dielectric layer structure of the same or different dielectric materials, or a composite dielectric layer structure formed by different dielectric materials, which is not limited herein.

[0092] Here, before the lower electrode 71 is provided, at least one insulating layer 100 is provided on the sidewall and bottom surface of the first trench 20 or the entire trench surface, for preventing metal diffusion or improving the leakage current of the trench sidewall. The material of the insulating layer 100 can be one or more of silicon oxide, silicon nitride, silicon carbon nitride, and silicon oxynitride, or one or more of tantalum, tantalum nitride, titanium nitride, and tungsten nitride.

[0093] Here, the upper electrode 72 can successively cover the sidewall and bottom surface of the first trench 20 after the dielectric layer 81, and then a supplemental electrode layer 721 is filled in the remaining trench space of the first trench 20; or the upper electrode 72 can directly fill the first trench 20.

[0094] As shown in FIGS. 6 and 7, due to the structure that the width of the top and bottom of the trench is basically the same, when the capacitor stack continuously extends on the sidewall and bottom surface of the first trench 20 (as an example), the material layers of the lower electrode 71, the dielectric layer 81, and the upper electrode 72 have good continuity, i.e., the layers of the capacitor stack continuously cover the sidewall and bottom surface of the trench with few defects; the thickness uniformity of the layers of the capacitor stack on the top and bottom of the trench is good, and can be basically the same; such a silicon capacitor has high capacitance density and small leakage current.

[0095] As an example, referring to FIG. 8, which is an enlarged view of region I of FIG. 7, region I has a region Q at the location where the sidewall 201 of the first trench 20 meets the bottom surface 202. As shown in FIG. 8, the lower electrode 71, the dielectric layer 81, and the upper electrode 72 have a protrusion at the location of region Q, i.e., the layers of the capacitor stack are recessed toward the insulating layer 100 at the location of region Q. As shown in FIG. 8, the material layer of the lower electrode 71 has different widths at different locations of the first trench 20, the width of the material layer at the top and bottom of the trench is substantially uniform, and the width of the material layer at the location of region Q is increased. The present embodiment takes the first trench 20 as an example for description, and protrusions can also be provided at the locations where the sidewalls of other trenches of the semiconductor device meet the bottom surfaces. At these locations, the thickness of the layers of the capacitor stack can be discontinuous, or even have defects such as cracks and holes. The provision of the protrusions makes the thickness of the capacitor stack at these locations more continuous and uniform, and thus the leakage current of the silicon capacitor is smaller.

[0096] Referring to FIGS. 9A-9B, the semiconductor device further includes a plurality of first contact plugs 90, one end of each of the plurality of first contact plugs 90 being connected to the upper electrode 72 or the lower electrode 71, and the other end of each of the plurality of first contact plugs 90 being connected to other conductive structures outside the semiconductor device.

[0097] As shown in FIGS. 9A and 9B, the plurality of first contact plugs 90 are distributed in the edge regions of the substrate 1 (e.g., the P1 region and the P2 region shown in FIG. 9A), and there are no trenches in these regions of the substrate 1, in which the upper electrode 72 or the lower electrode 71 continuously or discontinuously covers these regions. Here, the upper electrode 72 is shown in a semi-transparent manner for better clarity of the view. In the P2 region of the substrate 1, only the lower electrode 71 is exposed, and there is no dielectric layer or upper electrode on the lower electrode 71. In the P1 region, there can be only the upper electrode 72, or there can be both the upper electrode 72 and the dielectric layer 81 and the lower electrode 72 (not shown in the figures). In the regions of the substrate 1 other than the P1 region and the P2 region, there are both the upper electrode 72 and the dielectric layer 81 and the lower electrode 72. In the P1 region and the P2 region, the plurality of first contact plugs 90 are respectively electrically connected to the upper electrode 72 and the lower electrode 71. By arranging the first contact plugs 90 in the edge regions of the substrate 1 where there are no trenches, and directly exposing the upper electrode 72 or the lower electrode 71 in the edge regions, or having only the upper electrode or the lower electrode in the edge regions, the lower electrode 71 can be electrically connected to the first contact plugs 90 without opening a window in the later stage, i.e., without etching to open a window in the upper electrode or the dielectric layer to form the window of the first contact plug 90, which avoids damage to the lower electrode due to inaccurate stopping of the window opening on the lower electrode, and the process is simple and reliable.

[0098] As an example, when the lower electrode 71, the dielectric layer 81, and the upper electrode 72 each continuously cover the top surface between the trenches and the surface of the substrate 1, all the first contact plugs 90 connected with the upper electrode 72 are vertically led out and then connected together, and all the first contact plugs 90 connected with the lower electrode 71 are vertically led out and then connected together, so that the silicon capacitor can achieve the maximum capacitance.

[0099] In some other embodiments, when the lower electrode 71, the dielectric layer 81, and the upper electrode 72 each discontinuously cover the top surface between the trenches and the surface of the substrate 1, the first contact plugs 90 can be electrically connected in different ways to adjust the capacitance of each trench capacitor or form a plurality of trench capacitors in parallel or series.

[0100] In these embodiments, the capacitor stack is only shown to include the lower electrode 71, the dielectric layer 81, and the upper electrode 72. If there are more layers of the capacitor stack, such as five layers, seven layers, or even more, a plurality of first contact plugs 90 are arranged in different areas and connected with different electrode layers in the capacitor stack at one end. Therefore, the examples do not constitute a limitation on the number of electrode layers in the capacitor stack and the position of the first contact plug 90.

[0101] Referring to FIG. 9C, the semiconductor device further includes a second contact plug 91, a plurality of second contact plugs 91 being connected with the upper electrode 72 or the lower electrode 71 at one end and connected with other conductive structures outside at the other end.

[0102] As shown in FIG. 3, in this embodiment, there are first gaps 61 and third gaps 63 between the first trench group 2 and the second trench group 4.

[0103] As shown in FIG. 9C, the plurality of second contact plugs 91 are uniformly distributed at the positions of the first gaps 61 and the third gaps 63, where the upper electrode 72 or the lower electrode 71 continuously or discontinuously covers the first gaps 61 and the third gaps 63. In order to electrically isolate the upper electrode 72 and the lower electrode 71, the positions of the first gaps 61 and the third gaps 63 can have only the upper electrode 72 in some areas (such as the P3 area shown in FIG. 9C) and only the lower electrode 71 in some areas (such as the P4 area shown in FIG. 9C), and the plurality of second contact plugs 91 are respectively electrically connected with the upper electrode 72 and the lower electrode 71; in the P3 area, there are the dielectric layer 81 and the lower electrode 71 successively below the upper electrode 72, which are not shown in the figure. The connection relationship between the second contact plugs 91 at the positions of the first gaps 61 and the third gaps 63 and the upper electrode 72 or the lower electrode 71 is only an example, such as the connection of the second contact plugs 91 in the P3 area with the upper electrode 72 and the connection of the second contact plugs 91 in the P4 area with the lower electrode 71, but does not constitute a specific limitation, and a person skilled in the art can flexibly arrange according to actual needs.

[0104] As an example, all the second contact plugs 91 connected with the upper electrode 72 (such as the second contact plugs 91 in the P3 region shown in FIG. 9C) are vertically led out and connected together, and are connected with the first contact plugs 90 in the P1 region; all the second contact plugs 91 connected with the lower electrode 71 (such as the second contact plugs 91 in the P4 region shown in FIG. 9C) are vertically led out and connected together, and are connected with the first contact plugs 90 in the P2 region, so that the silicon capacitor can achieve the maximum capacitance.

[0105] By arranging the second contact plugs 91 at the positions of the first gap 61 and the third gap 63, more and shorter conductive paths are additionally provided, the resistance of the interconnection structure is greatly reduced, the equivalent resistance of the entire silicon capacitor is reduced, and the leakage current is reduced.

[0106] Similarly, there are embodiments in which, as shown in FIG. 4, there are first gaps 61 and third gaps 63 between the first trench groups 2 and the second trench groups 4; or as shown in FIG. 5, there are first gaps 61 between the first trench groups 2 and the second trench groups 4. In FIGS. 9D and 9E, the plurality of second contact plugs 91 are uniformly distributed at the positions of the first gap 61 and the third gap 63, wherein the upper electrode 72 or the lower electrode 71 continuously or discontinuously covers these regions. When there is an extended trench portion 5 at the position of the third gap 63, a second contact plug 91 can not be arranged above the third gap 63, because a window of the upper electrode 72 and the dielectric layer 81 can need to be opened at this time. Alternatively, only a second contact plug 91 can be arranged at the position of the third gap 63 with the extended trench portion 5, and the second contact plug 91 is connected with the upper electrode (not shown in the figure), so that the opening of the window of the upper electrode 72 and the dielectric layer 81 is not involved.

[0107] The disclosure also provides a method for forming a semiconductor device, comprising: providing a substrate 1; forming a first trench group 2, a second trench group 4, and a communication trench portion 3 in the substrate 1; and forming a capacitor stack, wherein the capacitor stack is stacked on the first trench group 2, the second trench group 4, and the communication trench portion 3, and the capacitor stack continuously extends on the sidewalls 201 and the bottom surface 202 of the first trench group 2, the second trench group 4, and the communication trench portion 3.

[0108] In the method, at least two first trench groups 2 are arranged along a second direction; each first trench group 2 comprises a first trench 20; the communication trench portion 3 communicates the first trenches 20 located adjacent to each other in a third direction; and a plurality of second trench groups 4 are arranged along a first direction; wherein the second trench groups 4 and the first trench groups 2 are arranged in an array, and two second trench groups 4 are separated by a first trench group 2 in the first direction; the first direction, the second direction, and the third direction are located in the same plane, the first direction is perpendicular to the third direction, the second direction intersects the first direction and the third direction, and the angle between the second direction and the third direction is an acute angle.

[0109] The method comprises the following steps:

[0110] Step 1: providing a substrate 1.

[0111] The provided substrate 1 has opposite front and back surfaces, which are parallel to each other. The back surface of the substrate 1 can have a circuit structure, which can include but is not limited to device layers, metal interconnection layers, dielectric layers, etc.

[0112] Step 2: forming a first trench group 2, a second trench group 4 and a communication trench part 3 on the front surface of the substrate 1.

[0113] This step includes: as shown in FIGS. 10A-10D, first, forming a certain thickness of a sacrificial layer 200 and a certain thickness of a mask layer 300 on the surface of the substrate 1 in sequence; then, removing part of the mask layer 300 by lithography to form a mask layer 300 after lithography in the top view pattern of the first trench group 2, the second trench group 4 and the communication trench part 3; then etching the sacrificial layer 200 to the surface of the substrate 1 with the mask layer 300 as a template; finally, removing the mask layer 300, and continuing to etch and remove part of the material of the substrate 1 downward with the sacrificial layer 200 as a template to form the first trench group 2, the second trench group 4 and the communication trench part 3.

[0114] In other embodiments, an extension trench part 5 is also formed, and the extension trench part 5 is formed simultaneously with the first trench group 2, the second trench group 4 and the communication trench part 3.

[0115] In this embodiment, removing part of the mask layer 300 also includes patterning and lithographing the mask layer 300 with a certain width of the edge of the substrate 1. Finally, as shown in FIG. 10D, when the substrate 1 including the first trench group 2, the second trench group 4 and the communication trench part 3 is formed, there is a virtual trench 400 on the outer edge of the substrate 1. The virtual trench 400 is used to balance the problem of slow etching rate of the first trench group 2 and the second trench group 4 located at the edge of the substrate 1, so as to avoid the problem of uneven width of each trench formed.

[0116] In this embodiment, as shown in FIG. 10D, after etching and removing part of the material of the substrate 1 downward with the sacrificial layer 200 as a template, the sacrificial layer 200 is left with a certain thickness, which is smaller than the initial thickness of the sacrificial layer 200. The sacrificial layer 200 left with a certain thickness can prevent the risk of sidewall collapse between trenches due to the long length of the trenches when forming rectangular trenches.

[0117] In this embodiment, the method of removing part of the material of the substrate 1 includes but is not limited to laser etching, mechanical etching, chemical etching, or includes but is not limited to wet etching, dry etching, BOSCH etching, wherein BOSCH etching is more likely to form a trench with a vertical sidewall.

[0118] The first groove group 2, the second groove group 4 and the communication groove part 3 can be formed by synchronous etching or asynchronous etching. The synchronous etching refers to that the patterns of the first groove group 2, the second groove group 4 and the communication groove part 3 in the sacrificial layer 200 are all formed and the surface of the substrate 1 is exposed, and then the same etching process parameters are used, for example, the Bosch etching, in which the process parameters are the same at different positions of the substrate 1, including the etching gas concentration, the plasma concentration and the speed, etc. For example, the laser etching, in which the process parameters are the same at different positions of the substrate 1, such as that the laser is perpendicular to the material surface of the substrate 1, the laser energy and the time are the same, etc. In the synchronous etching, if the size characteristics of the structures are the same, for example, the diameters of the multiple circular holes are the same or the length and width characteristics (or the length multiplied by the width) of the rectangle are the same from the top view, the depths of the grooves formed in the same time can be the same. However, in the embodiment, because the communication groove part 3 connects the adjacent first groove group 2, the depths of the grooves formed by the synchronous etching of the first groove group 2 and the second groove group 4 can be different, as shown in FIG. 6.

[0119] The respective grooves of the first groove group 2, the second groove group 4, the communication groove part 3 and the extension groove part 5 have corresponding sidewalls 201 and bottom surfaces 202 with the same or similar structures, and the widths of the sidewalls 201 at different depth positions can be basically consistent. The bottom surface 202 can be a horizontal bottom surface or a downwardly recessed circular arc bottom surface, as shown in FIG. 8.

[0120] The material of the mask layer 300 includes but is not limited to one or a combination of polycrystalline silicon, photoresist, metal film and polyimide, etc. The material of the sacrificial layer 200 includes but is not limited to one or a combination of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbide, etc.

[0121] Step 3: depositing a capacitor stack on the substrate 1, including depositing the capacitor stack on the first groove group 2, the second groove group 4 and the communication groove part 3, wherein the capacitor stack continuously extends to the sidewalls 201 and the bottom surfaces 202 of the first groove group 2, the second groove group 4 and the communication groove part 3. The capacitor stack also covers the surface of the front surface of the substrate 1.

[0122] In other embodiments, the capacitor stack is also deposited in the extension groove part 5, and the capacitor stack continuously extends to the sidewalls 201 and the bottom surfaces 202 of the extension groove part 5.

[0123] Wherein, before depositing the capacitor stack, further comprising: depositing an insulating layer 100 on the sidewall 201 and bottom surface 202 of the first trench group 2, the second trench group 4 and the communication trench part 3, as shown in FIG. 7, FIG. 8; or oxidizing the substrate 1 to form the insulating layer 100 on the sidewall 201 and bottom surface 202 of the first trench group 2, the second trench group 4 and the communication trench part 3 to form a thin layer of insulating layer 100 with a certain thickness.

[0124] Wherein, each trench of the first trench group 2, the second trench group 4 and the communication trench part 3 has a sidewall 201 and a bottom surface 202, and the insulating layer 100 has a protrusion at the intersection of the sidewall 201 and the bottom surface 202, i.e. the insulating layer 100 is inwardly recessed towards the substrate 1 at the intersection, as shown in FIG. 8. As another embodiment, the inward recess is formed before the formation of the insulating layer 100, i.e. each trench of the first trench group 2, the second trench group 4 and the communication trench part 3 has a sidewall 201 and a bottom surface 202, and the intersection of the sidewall 201 and the bottom surface 202 has a feature of being inwardly recessed towards the substrate 1, i.e. the trench is inwardly recessed at the intersection (not shown). The protrusion can be obtained by adjusting the last etching parameter or several etching parameters, such as extending the time of the last etching or several etchings to increase the scallop shape, and multiple scallop shapes form the inward recess of the trench.

[0125] Wherein, the capacitor stack at least includes three layers of lower electrode 71, dielectric layer 81 and upper electrode 72, or more layers of electrode layer, dielectric layer and electrode layer, and the lower electrode 71, the dielectric layer 81 and the upper electrode 72 have a protrusion at the intersection of the sidewall 201 and the bottom surface 202, i.e. each layer of the capacitor stack is inwardly recessed towards the substrate 1 at the intersection, as shown in FIG. 8.

[0126] Wherein, when the capacitor stack covers the surface of the front surface of the substrate 1, the lower electrode 71 continuously extends to cover the surface of the front surface of the substrate 1; the dielectric layer 81 discontinuously extends to cover the surface of the front surface of the lower electrode 71, and the discontinuous area exposes the lower electrode 71 for subsequent fabrication of a contact plug; and the upper electrode 72 discontinuously extends to cover the surface of the front surface of the dielectric layer 81, and the upper electrode 72 and the dielectric layer 81 are completely covered, i.e. the patterns of the two are the same, as shown in FIG. 9A-9E, and the discontinuous area of the upper electrode 72 is the same as the discontinuous area of the dielectric layer 81. In this step, the capacitor stack formed on the surface of the front surface of the substrate 1 has exposed the lower electrode 71, i.e. there is no need to etch to open the upper electrode or the dielectric layer to form a window of the first contact plug 90, avoiding the damage to the lower electrode caused by the inaccurate stopping on the lower electrode when opening the window, and the process is simple and reliable.

[0127] Step 4: forming the first contact plug 90 and the second contact plug 91, including: forming the first contact plug 90 and the second contact plug 91 on the exposed area of the lower electrode 71 by the dielectric layer 81, and forming the first contact plug 90 and the second contact plug 91 on the surface of the upper electrode 72, as shown in FIGS. 9A-9E.

[0128] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

2. The semiconductor structure of claim 1, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

3. The semiconductor structure of claim 2, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

4. The semiconductor structure of claim 1, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

5. The semiconductor structure of claim 4, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

6. The semiconductor structure of claim 2, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

7. The semiconductor structure of claim 2, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

8. The semiconductor structure of claim 2, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

9. The semiconductor structure of claim 8, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

10. The semiconductor structure of claim 3, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

11. The semiconductor structure of claim 10, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

12. The semiconductor structure of claim 2, wherein, The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction.

13. A semiconductor device, characterized by comprising: The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, and wherein a plurality of communicating trench sections (3) are arranged to communicate the first trenches in the third direction. The application further relates to a substrate (1) and a plurality of first trench groups (2) arranged in a second direction in the substrate, wherein each of the first trench groups comprises a plurality of first trenches (20) arranged in a third direction, A capacitor stack (71, 81, 72) is stacked on the first trench group, the second trench group and the communication trench part, wherein the capacitor stack continuously extends on the sidewalls and the bottom surface of the first trench group, the second trench group and the communication trench part. The first direction, the second direction and the third direction are in the same plane, the first direction and the third direction are perpendicular, the second direction intersects with the first direction and the third direction, and the angle between the second direction and the third direction is an acute angle.

14. The semiconductor device of claim 13, wherein, The capacitor stack has a protrusion at the position where the sidewall and the bottom surface intersect.

15. The semiconductor device of claim 13, wherein, The capacitor stack further comprises a first contact plug, and the capacitor stack comprises an upper electrode and a lower electrode, and a plurality of the first contact plugs are located in the edge region of the substrate, and the edge region only has one of the upper electrode or the lower electrode.

16. The semiconductor device of claim 13, wherein, The capacitor stack further comprises a second contact plug, wherein along the third direction, there is a first gap between two adjacent second trench groups; along the third direction, there is a third gap between the adjacent first trench group and the second trench group; and the second contact plug is located on the first gap and the third gap.

17. A method of forming a semiconductor device, comprising: The capacitor stack comprises: providing a substrate (1); forming a first trench group (2), a second trench group (4) and a communication trench part (3) in the substrate; forming a capacitor stack (71, 81, 72) stacked on the first trench group, the second trench group and the communication trench part, wherein the capacitor stack continuously extends on the sidewalls and the bottom surface of the first trench group, the second trench group and the communication trench part.

18. The method of claim 17, wherein When forming the first trench group, the second trench group and the communication trench part in the substrate, a virtual trench is further formed on the outer edge of the substrate.

19. The method of claim 17, wherein The capacitor stack forms a protrusion at the position where the sidewall and the bottom surface intersect.

20. The method of claim 17, wherein When forming the capacitor stack, an upper electrode, a dielectric layer and a lower electrode are further formed, the lower electrode continuously extends to cover the surface of the substrate, and the upper electrode and the dielectric layer discontinuously extend to cover the surface of the substrate.

Images