Memory access control method and apparatus, system, storage medium, and program product

Abstract

The present application relates to the technical field of computers, and discloses a memory access control method and apparatus, a system, a storage medium, and a program product. The computer system comprises a plurality of IOMMUs, and the method comprises: allocating a shared memory resource to the plurality of IOMMUs, wherein the shared memory resource comprises a shared memory; and performing access control with respect to the shared memory by means of the plurality of IOMMUs sharing the shared memory resource. Thus, performing memory access control by means of the plurality of IOMMUs sharing a shared memory page table, enables a single computer system to be simultaneously provided with various types of IOMMUs and various types of buses, including a mesh interconnect bus, while still ensuring memory access control reliability.

Description

Memory access control method, device, system, storage medium and program product

[0001] The present application claims priority to the Chinese patent application No. 202410650648.7, filed on May 23, 2024, and entitled "Memory access control method, device, system, storage medium and program product", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computers, and in particular to a memory access control method, device, system, storage medium and program product. BACKGROUND

[0003] An input / output memory management unit (IOMMU) is a hardware device used to manage the access of external devices (referred to as peripherals) to computer memory (referred to as memory) of a computer system. For example, when a peripheral device accesses the memory, the IOMMU converts the input / output virtual address (IOVA) of the peripheral device into a physical address (PA) of the memory, so as to access the memory based on the PA of the memory. Through the virtualized IOVA, the memory access control of the peripheral device is realized, thereby enhancing the security and stability of the computer system.

[0004] Currently, a single IOMMU cannot meet the address conversion needs of multiple peripherals of a computer system, which requires the computer system to be equipped with multiple IOMMU. In some cases, the computer system may need to be equipped with IOMMU provided by different manufacturers, but the IOMMU provided by different manufacturers often have their unique functions and characteristics. How to more reasonably control the memory access of the peripherals in the case of being equipped with multiple IOMMU has become a difficulty for the computer system. SUMMARY

[0005] The present application provides a memory access control method, device, system, storage medium and program product, which can more reasonably control the memory access of peripherals in the case of the computer system being equipped with multiple IOMMU. The technical solution is as follows:

[0006] In a first aspect, a memory access control method is provided, applied to a computer system, the computer system comprising multiple IOMMU, the method comprising: allocating a common memory resource to the multiple IOMMU, the common memory resource comprising a common memory; and controlling the access to the common memory by the multiple IOMMU sharing the common memory resource.

[0007] The present solution controls memory access by having multiple IOMMUs share a common memory page table, so that a computer system can be equipped with multiple types of IOMMUs and multiple types of buses, including mesh interconnect buses, while ensuring the reliability of memory access control.

[0008] The common memory resource further includes a common memory page table, and the allocating the common memory resource to the multiple IOMMUs includes writing a base address of the common memory page table to each of the multiple IOMMUs, where the base address of the common memory page table represents the common memory. That is, the computer system allocates a common memory page table to the multiple IOMMUs, so that the multiple IOMMUs share the common memory page table to control memory access of the peripherals connected to the multiple IOMMUs.

[0009] In a possible implementation, the computer system further includes an IOMMU framework, and an IOMMU virtual driver is registered in the IOMMU framework, and the method is implemented by using the IOMMU virtual driver. That is, in order to be compatible with the IOMMU framework in the related art, the present solution can be implemented by using an IOMMU virtual driver.

[0010] In a possible implementation, in the case where the method is implemented by using an IOMMU virtual driver, the method further includes registering the IOMMU virtual driver on the IOMMU framework, creating an IOMMU virtual instance for the IOMMU virtual driver, creating an IOMMU instance for each of the multiple IOMMUs, and registering the created multiple IOMMU instances on the IOMMU virtual instance.

[0011] Further, the controlling the common memory by the multiple IOMMUs sharing the common memory resource includes obtaining, by the IOMMU virtual instance, a configuration request about a first memory resource in the common memory resource, determining an IOMMU instance as an IOMMU proxy instance from the multiple IOMMU instances, and delivering the configuration request of the first memory resource to the IOMMU proxy instance, and executing the configuration request of the first memory resource by the IOMMU proxy instance. That is, the request is distributed by selecting a proxy.

[0012] In a possible implementation, the plurality of IOMMUs are also respectively assigned with private memory resources, and the private memory resources of the plurality of IOMMUs can each include the related information of the first memory resource. In this case, the performing, by the IOMMU proxy instance, the configuration request of the first memory resource includes updating the private memory resource of an IOMMU proxy by the IOMMU proxy instance to configure the first memory resource, where the IOMMU proxy refers to an IOMMU corresponding to the IOMMU proxy instance. The method further includes synchronizing, by the IOMMU virtual instance, the update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance in the plurality of IOMMU instances, to instruct the other IOMMU instances to synchronize the configuration of the first memory resource by updating the private memory resource of the corresponding IOMMU. That is, when a certain IOMMU instance modifies the corresponding private memory resource, the modification operation needs to be synchronized to other IOMMU instances, so that the information included in the private memory resources of the plurality of IOMMU instances is consistent.

[0013] For example, the common memory resource further includes a common memory page table, and the configuration request of the first memory resource indicates an application or release of the first memory in the common memory. The performing, by the IOMMU proxy instance, the configuration request of the first memory resource includes updating the cached memory page table item of the IOMMU proxy and updating the common memory page table by the IOMMU proxy instance to apply or release the first memory, where the IOMMU proxy refers to an IOMMU corresponding to the IOMMU proxy instance, and the cached memory page table item includes part of the page table items in the common memory page table. The method further includes synchronizing, by the IOMMU virtual instance, the update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance in the plurality of IOMMU instances, to instruct the other IOMMU instances to synchronize the application or release of the first memory by updating the cached memory page table item of the corresponding IOMMU. The cached memory page table item of the IOMMU belongs to the private memory resource of the corresponding IOMMU.

[0014] In a possible implementation, the computer system further includes a direct memory access (DMA) framework, and the configuration request of the first memory resource is a request delivered by the DMA framework to the IOMMU virtual instance. That is, the DMA framework directly delivers a DMA software request to the IOMMU virtual instance across the IOMMU framework. In this way, the present solution can be compatible with the IOMMU framework in the related art.

[0015] In a possible implementation, the computer system further includes a plurality of buses, the plurality of IOMMUs includes a plurality of IOMMUs, the plurality of buses correspond to the plurality of IOMMUs one-to-one, the plurality of IOMMUs respectively connect at least one peripheral device through a corresponding bus, the plurality of IOMMUs respectively correspond to an IOMMU driver, the IOMMU driver includes a driver interface, and the method further includes: registering, for each peripheral device connected to the plurality of buses, a driver interface of an IOMMU to which the peripheral device is connected, and the peripheral device is configured to send a memory access request about the common memory through the registered driver interface.

[0016] The driver interface of the IOMMU registered for the peripheral device is stored in a device model of the peripheral device, and the method further includes: constructing a bus model corresponding to each bus of the plurality of buses, and constructing a device model of a peripheral device connected to each bus under the bus model corresponding to the bus. The registering, for each peripheral device connected to the plurality of buses, of the driver interface of the IOMMU to which the peripheral device is connected includes: registering, for each bus, the driver interface of the IOMMU connected to the bus in the bus model; and registering, through the bus model, the driver interface of the IOMMU connected to the bus in the device model under the bus model, and the peripheral device is configured to send a memory access request about the common memory through the registered driver interface in the corresponding device model. That is, the present solution directly registers various IOMMU driver interfaces to the corresponding bus model and device model across the IOMMU framework.

[0017] The plurality of buses includes at least one of a mesh interconnection bus and a tree bus. That is, the present solution supports both the mesh interconnection bus and the tree bus, and can support both types of buses at the same time.

[0018] In a possible implementation, a first peripheral device in the computer system is connected to at least two IOMMUs of the plurality of IOMMUs, the at least two IOMMUs are of the same type, and the method further includes: in a case where a memory access request of the first peripheral device is detected, determining one IOMMU as a second IOMMU from the at least two IOMMUs, the memory access request of the first peripheral device indicating reading or writing of a second memory in the common memory; and reading or writing the second memory through the second IOMMU. That is, any one of the plurality of IOMMUs can process a memory access request of a first peripheral device based on a common memory page table, to ensure that address translation does not fail.

[0019] In a second aspect, a memory access control apparatus is provided, which has functions to implement the behaviors of the memory access control method in the first aspect. The memory access control apparatus comprises one or more modules for implementing the memory access control method provided in the first aspect.

[0020] In a third aspect, a computer system is provided, which comprises a processor and a plurality of IOMMUs, and the processor is configured to execute the memory access control method provided in the first aspect.

[0021] In a fourth aspect, a computer device is provided, which comprises a processor and a memory, the memory is configured to store a program for executing the memory access control method provided in the first aspect, and store data related to implementing the memory access control method provided in the first aspect. The processor is configured to execute the program stored in the memory. The computer device can further comprise a communication bus for establishing a connection between the processor and the memory. The computer device further comprises a plurality of IOMMUs.

[0022] In a fifth aspect, a computer readable storage medium is provided, which stores instructions, when executed on a computer, cause the computer to execute the memory access control method provided in the first aspect.

[0023] In a sixth aspect, a computer program product is provided, which comprises instructions, when executed on a computer, cause the computer to execute the memory access control method provided in the first aspect.

[0024] The technical effects obtained by the second to sixth aspects are similar to those obtained by the corresponding technical means in the first aspect, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is an architecture diagram of a computer system related to a memory access method provided in an embodiment of the present application;

[0026] FIG. 2 is a schematic diagram of a computer system under a mesh interconnection bus provided in an embodiment of the present application;

[0027] FIG. 3 is a schematic diagram of a computer system under a tree bus provided in an embodiment of the present application;

[0028] FIG. 4 is an IOMMU management architecture diagram provided in an embodiment of the present application;

[0029] FIG. 5 is another IOMMU management architecture diagram provided in an embodiment of the present application;

[0030] FIG. 6 is a software and hardware architecture diagram of a computer system according to an embodiment of the present application;

[0031] FIG. 7 is a software and hardware architecture diagram of another computer system according to an embodiment of the present application;

[0032] FIG. 8 is a software and hardware architecture diagram of another computer system according to an embodiment of the present application;

[0033] FIG. 9 is a structural schematic diagram of a computer device according to an embodiment of the present application;

[0034] FIG. 10 is a flowchart of a memory access control method according to an embodiment of the present application;

[0035] FIG. 11 is a software and hardware system diagram when an operating system is initialized according to an embodiment of the present application;

[0036] FIG. 12 is a flowchart when an operating system is initialized according to an embodiment of the present application;

[0037] FIG. 13 is a structural schematic diagram of a memory access control apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] In order to facilitate understanding, first, the implementation environment of the memory access method according to the embodiments of the present application will be introduced.

[0040] FIG. 1 is an architecture diagram of a computer system related to a memory access method according to an embodiment of the present application. Referring to FIG. 1, the computer system includes a plurality of IOMMUs 101, a plurality of peripherals 102, a bus system 103 and a memory 104. The plurality of IOMMUs 101 are communicatively connected with the plurality of peripherals 102 through the bus system 103. Among them, one peripheral 102 is connected with at least one IOMMU 101, and one IOMMU 101 is connected with at least one peripheral 102.

[0041] The computer system is used to perform memory access control on the plurality of peripherals 102 through the plurality of IOMMUs 101 according to the memory access method according to the embodiments of the present application. That is, the computer system allocates common memory resources to the plurality of IOMMUs 101, the common memory resources including common memory in the memory 104, and the computer system performs access control on the common memory through the plurality of IOMMUs 101 sharing the common memory resources.

[0042] The plurality of IOMMUs 101 includes at least one IOMMU, such as a plurality of IOMMUs from different manufacturers. The plurality of peripherals 102 includes one or more devices, such as a solid state drive (SSD), a network interface card (NIC), a neural processing unit (NPU) or a graphics processing unit (GPU), a mouse, a keyboard, and the like. The memory 104 includes a dynamic random access memory (DRAM) and the like. The bus system 103 includes at least one bus. The at least one bus includes at least one of a mesh interconnect bus and a tree bus. The tree bus is, for example, a peripheral component interconnect express (PCIE) bus and the like.

[0043] FIG. 2 is a schematic diagram of a computer system under a mesh interconnect bus according to an embodiment of the present application. The computer system can be the computer system shown in FIG. 1. The computer system includes a plurality of IOMMUs, a plurality of peripherals, a memory, and a mesh interconnect bus. Each of the plurality of IOMMUs is connected to each of the plurality of peripherals through the mesh interconnect bus. In the embodiment of the present application, each IOMMU under the mesh interconnect bus can be connected to peripherals of different types, and one peripheral can be connected to IOMMUs of different types. That is, the present solution enables a plurality of types of IOMMUs to coexist under one operating system (OS).

[0044] FIG. 3 is a schematic diagram of a computer system under a tree bus according to an embodiment of the present application. The computer system can be the computer system shown in FIG. 1. The computer system includes a plurality of IOMMUs, a plurality of peripherals, a memory, and a tree bus. Each of the plurality of peripherals is connected to one of the plurality of IOMMUs through the tree bus. In the embodiment of the present application, the types of peripherals connected to each IOMMU under the tree bus can be the same or different.

[0045] In related technologies, the type of bus is a tree bus, and one OS allows the existence of one type of bus and IOMMU, and cannot be compatible with a plurality of types of IOMMU at the same time, resulting in different types of peripherals being unable to work together in the same OS.

[0046] In order to be compatible with the memory access control scheme in the prior art, in the embodiment of the present application, an IOMMU management module is registered in the existing IOMMU framework of the computer system in the form of a virtual driver, and the present scheme is implemented by using the IOMMU management module. In other words, the embodiment of the present application provides an IOMMU management module, which is an IOMMU virtual driver, and the present scheme is implemented by registering the IOMMU virtual driver in the IOMMU framework. This will be described in the following.

[0047] FIG. 4 is an IOMMU management architecture provided by the embodiment of the present application. The IOMMU management architecture can be applied to any computer system in the embodiments of FIGS. 1 to 3. Referring to FIG. 4, the IOMMU management architecture includes a bus management framework, an IOMMU framework, an IOMMU management module, and memory resources.

[0048] The IOMMU framework registers an existing IOMMU driver corresponding to an existing IOMMU, and the IOMMU framework reports a driver interface of the existing IOMMU driver to the bus management framework. The existing IOMMU driver manages IOMMU instances created for each existing IOMMU, and each of the IOMMU instances is allocated with independent memory resources, including an independent memory page table (referred to as a page table for short), and each existing IOMMU is used to perform memory access control on a peripheral connected to the corresponding IOMMU by using the corresponding memory page table. The existing IOMMU is connected to the peripheral through a tree bus.

[0049] The IOMMU management module is registered on the IOMMU framework in the form of a virtual driver, for example, the computer system creates a corresponding IOMMU virtual instance for the IOMMU management module, and the IOMMU virtual instance is registered on the IOMMU framework. The IOMMU management module registers a new IOMMU driver corresponding to a new IOMMU, and the IOMMU management module is used to cross the IOMMU framework and directly report a driver interface of the new IOMMU driver to the bus management framework, and the bus management framework registers the driver interface of the new IOMMU driver to the corresponding peripheral, so as to enable an OS to support different types of IOMMU. The new IOMMU driver manages IOMMU instances created for each new IOMMU, and the IOMMU instances share a common memory resource, including a common memory page table, and each new IOMMU is used to perform memory access control on a peripheral connected to the corresponding IOMMU by using the common memory page table. The new IOMMU is connected to the peripheral through a mesh interconnection bus or a tree bus.

[0050] FIG. 5 is another IOMMU management architecture provided by the embodiments of the present application. FIG. 5 is a refinement of the IOMMU management module in FIG. 4 according to function. Referring to FIG. 5, the IOMMU management module includes a driver registration sub-module, a request distribution sub-module, and an instance management sub-module.

[0051] The driver registration sub-module is configured to report the driver interface of the added IOMMU driver directly to the bus management framework across the IOMMU framework. The request distribution sub-module is configured to distribute the request received by the IOMMU management module (or IOMMU virtual instance) to the added multiple IOMMU instances. Each of the added IOMMU instances is configured to respond to the received request. In the case of modifying the private memory resource and / or the common memory resource based on the received request, the added IOMMU instance is further configured to synchronize the modification operation of the IOMMU instance to other added IOMMU instances, to instruct the other added IOMMU instances to synchronize the modification of the related information in the respective private memory resource.

[0052] The private memory resource of each of the added IOMMU instances can include the related information of part of the common memory resource. For example, the common memory resource includes a common memory page table, and the private memory resource of each of the added IOMMU instances can include part of the page table entries in the common memory page table (such as a translation look-aside buffer (TLB)). Through the synchronization of the private memory resource, the memory page table entries recorded by the added multiple IOMMU instances are kept consistent, so as to ensure that each of the added IOMMU can accurately perform address translation based on the respective recorded memory page table entries.

[0053] The instance management sub-module is configured to interface with the IOMMU framework upwardly and manage the added multiple IOMMU instances downwardly. Further, the instance management sub-module is configured to configure the common memory resource for each of the added IOMMU instances and write the related information of the common memory resource into each of the added IOMMU instances. The common memory resource includes, for example, a common memory page table, and the instance management sub-module is configured to write the base address of the common memory page table into the hardware register of each of the added IOMMU instances, so that the added multiple IOMMU instances can share the common memory page table, which facilitates the application to the mesh interconnection bus architecture.

[0054] It should be understood that the embodiments of the present application divide the IOMMU management module into three sub-modules only for the purpose of illustrating some functions of the IOMMU management module, and do not mean that the IOMMU management module must be divided into the three sub-modules. In addition, the functions of the three sub-modules can be implemented by adding an IOMMU driver and / or by an IOMMU virtual instance. For example, the functions of the instance management sub-module can be implemented by the IOMMU virtual instance and the added IOMMU driver together, for example, the IOMMU virtual instance is connected to the IOMMU framework upward and manages multiple IOMMU instances downward, and the added IOMMU driver writes the base address of the common memory page table into the hardware register of the added IOMMU. The functions of the request distribution sub-module can be implemented by the IOMMU virtual instance. That is, the IOMMU virtual instance is used to distribute the received requests to the added multiple IOMMU instances.

[0055] As can be seen from FIG. 4 and FIG. 5, the embodiments of the present application can not affect the existing process, and the existing IOMMU driver can still be directly connected to the IOMMU framework.

[0056] FIG. 6 is a software and hardware architecture diagram of a computer system provided by an embodiment of the present application. The computer system can be any computer system in the embodiments of FIG. 1 to FIG. 5. Referring to FIG. 6, the hardware part of the computer system includes an existing bus (such as a tree bus), an added bus (such as a mesh interconnection bus), an existing IOMMU, an added IOMMU, a peripheral (such as an I / O device), a memory, and a DMA controller, etc. The software part of the computer system includes a DMA framework, an IOMMU framework, an IOMMU management module, an IOMMU driver (including an existing IOMMU driver and an added IOMMU driver), an IOMMU instance (including an existing IOMMU instance and an added IOMMU instance), a bus management module, a bus model (including a model of the existing bus and a model of the added bus), and a device model (i.e. a model of the peripheral).

[0057] Taking FIG. 6 as an example of distinguishing the software and hardware of the architecture shown in FIG. 5, the bus management framework in FIG. 5 can include the bus management module, the bus model, and the device model in FIG. 6. The IOMMU framework is used to report the driving interface of the existing IOMMU driver to the bus management module, the bus management module is used to register the driving interface of the existing IOMMU driver and the added IOMMU to the respective bus model, and each bus model registers the driving interface to the corresponding device model.

[0058] The DMA controller is configured to receive a memory access request of a peripheral device, and deliver the memory access request of the peripheral device to the IOMMU. The IOMMU is configured to perform memory access control on the peripheral device based on the memory access request of the peripheral device by using a memory page table allocated for the corresponding IOMMU instance. In the embodiments of the present application, the memory access request of the peripheral device can be referred to as a DMA hardware request. Each of the existing IOMMUs performs address translation on the received memory access request based on the respective memory page table, and each of the newly added IOMMUs performs address translation on the received memory access request based on the common memory page table. The memory access request of the peripheral device is configured to request reading or writing of the memory. For example, the memory access request of the peripheral device connected to the newly added IOMMU is configured to request reading or writing of the common memory.

[0059] The DMA framework is configured to receive a DMA software request of a process in the computer system. For the DMA software request of the existing IOMMU instance, the DMA framework is further configured to deliver the DMA software request to the IOMMU framework. The IOMMU framework is configured to deliver the corresponding DMA software request to the corresponding IOMMU instance, and the IOMMU instance is configured to respond to the received DMA software request. For the DMA software request of the newly added IOMMU instance, the DMA framework is configured to directly deliver the corresponding DMA software request to the IOMMU virtual instance. The IOMMU virtual instance is configured to distribute the received DMA software request to the newly added plurality of IOMMU instances. The DMA software request is configured to request application or release of the target memory, and the DMA software request can also be referred to as a configuration request for the target memory resource. For example, a process requests to release a first memory resource in the common memory resource, and the target memory is the first memory.

[0060] FIG. 7 is a software and hardware architecture diagram of another computer system according to an embodiment of the present application. The computer system can be any of the computer systems in the embodiments of FIGS. 1 to 6. Referring to FIG. 7, the computer system includes a software system and a hardware system, which can be the software system and the hardware system of a server. The software system at least includes an IOMMU framework, a bus management framework, and an IOMMU management module. The hardware system at least includes a system on chip (SOC) chip, a memory, peripheral devices (including newly added peripheral devices and existing peripheral devices), and buses (including a mesh interconnection bus and a tree bus). The SOC chip includes a CPU, a platform bus (abbreviated as a pf bus in the figure), and IOMMUs (including newly added IOMMUs and existing IOMMUs). The newly added peripheral devices are connected to the newly added IOMMUs through the mesh interconnection bus, and the existing peripheral devices are connected to the existing IOMMUs through the tree bus. The IOMMUs are connected to the CPU through the platform bus, and the CPU is further connected to the memory.

[0061] Figure 8 is a software and hardware architecture diagram of another computer system according to an embodiment of the present application. The computer system can be any of the computer systems in the embodiments of Figures 1-7. Referring to Figure 8, the computer system includes a software system and a hardware system, which includes an SOC chip, a memory, eight peripherals, and two buses. The eight peripherals are referred to as peripheral 1, peripheral 2, peripheral 3, …, peripheral 7, and peripheral 8. The two buses include a mesh interconnect bus and a PCIE bus. The PCIE bus includes a PCIE1 bus and a PCIE2 bus. The SOC chip includes a CPU, a platform bus, and four IOMMUs, which are referred to as IOMMU-A1, IOMMU-A2, IOMMU-B1, and IOMMU-B2. Peripheral 1, peripheral 2, peripheral 3, and peripheral 4 are connected to IOMMU-B1 and IOMMU-B2 through the mesh interconnect bus. Peripheral 5 and peripheral 6 are connected to IOMMU-A1 through the PCIE1 bus, and peripheral 7 and peripheral 8 are connected to IOMMU-A2 through the PCIE2 bus. The software system includes a bus management framework, an IOMMU framework, an IOMMU management module, an IOMMU-A driver, and an IOMMU-B driver. The IOMMU-A driver is the driver of IOMMU-A1 and IOMMU-A2, and the IOMMU-B driver is the driver of IOMMU-B1 and IOMMU-B2. The IOMMU-B driver is registered with the IOMMU management module, and the IOMMU-A driver is registered with the IOMMU framework.

[0062] Figures 4-8 are not intended to limit the embodiments of the present application. For example, in other embodiments, all IOMMUs in a computer system are connected to peripherals through a mesh interconnect bus, and the present solution is implemented by modifying an existing IOMMU framework or providing a brand new IOMMU framework.

[0063] It should be understood that the system architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It is known to those of ordinary skill in the art that, as system architecture evolves and new business scenarios emerge, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0064] Figure 9 is a structural schematic diagram of a computer device according to an embodiment of the present application. In a possible implementation, the computer device includes any of the computer systems shown in Figures 1-8. The computer device includes one or more processors 901, a communication bus 902, a memory 903, and one or more communication interfaces 904. The computer device also includes a plurality of IOMMUs and a plurality of peripherals, etc., as in any of the embodiments of Figures 1-8.

[0065] The processor 901 is a general central processing unit (CPU), a network processing (NP), a microprocessor, or one or more integrated circuits used to implement the schemes of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. In a possible implementation, the PLD is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0066] The communication bus 902 is used to transmit information between the above components. In a possible implementation, the communication bus 902 is divided into an address bus, a data bus, a control bus and the like. For ease of representation, only one thick line is shown in the figure, but it does not mean that there is only one bus or only one type of bus. For example, the communication bus 902 includes at least one of a mesh interconnection bus and a tree bus.

[0067] In a possible implementation, the memory 903 is a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disk (including a compact disc read-only memory (CD-ROM), a compact disk, a laser disk, a digital versatile disk, a Blu-ray disk and the like), a magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but is not limited thereto. The memory 903 exists independently and is connected to the processor 901 through the communication bus 902, or the memory 903 is integrated with the processor 901.

[0068] The communication interface 904 uses any transceiver-like mechanism for communicating with other devices or communication networks. The communication interface 904 includes a wired communication interface, and in one possible implementation, a wireless communication interface. The wired communication interface is, for example, an Ethernet interface. In one possible implementation, the Ethernet interface is an optical interface, an electrical interface, or a combination thereof. The wireless communication interface is, for example, a wireless local area networks (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0069] In some embodiments, the computer device includes multiple processors, such as processor 901 and processor 905 as shown in FIG. 9. Each of these processors is a single-core processor, or a multi-core processor. In one possible implementation, the processor herein refers to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0070] In a specific implementation, as an example, the computer device further includes peripherals, such as output device 906 and input device 907. The output device 906 communicates with the processor 901 and is capable of displaying information in various ways. For example, the output device 906 is a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 907 communicates with the processor 901 and is capable of receiving user input in various ways. For example, the input device 907 is a mouse, a keyboard, a touch screen device, or a sensor device.

[0071] In some embodiments, the memory 903 is used to store program code 910 for implementing the solutions of the present application, and the processor 901 is capable of executing the program code 910 stored in the memory 903. The program code includes one or more software modules, and the computer device is capable of implementing the memory access control method provided in the embodiments of FIG. 10 by means of the processor 901 and the program code 910 in the memory 903.

[0072] FIG. 10 is a flowchart of a memory access control method according to an embodiment of the present application. The method is applied to a computer system, which can be any of the computer systems in the embodiments of FIGS. 1 to 8. In the embodiment of the present application, the computer system includes multiple IOMMUs. Please refer to FIG. 10, the method includes the following steps.

[0073] Step 1001: The computer system allocates a common memory resource to the multiple IOMMUs, where the common memory resource includes a common memory.

[0074] In order to enable memory access control in the case that the computer system is configured with multiple IOMMUs, in the embodiment of the present application, the computer system allocates common memory resources to the multiple IOMMUs, so that the multiple IOMMUs share the common memory resources to perform memory access control on the common memory. In this way, the present solution can be applied to a mesh interconnection bus.

[0075] In the case that the common memory resources further include a common memory page table, the computer system allocating the common memory resources to the multiple IOMMUs includes: writing a base address of the common memory page table to each of the multiple IOMMUs, the base address of the common memory page table representing the common memory. That is, the computer system allocates the common memory page table to the multiple IOMMUs, so that the multiple IOMMUs share the common memory page table to perform memory access control on the peripherals connected to the multiple IOMMUs.

[0076] In this way, the present solution can be applied to a mesh interconnection bus, that is, the peripheral is connected to each of the multiple IOMMUs through the mesh interconnection bus. Regardless of which IOMMU the memory access request of the peripheral is transmitted to, the IOMMU can accurately perform address translation on the memory access request based on the common memory page table. In the related art, multiple IOMMUs are respectively allocated with an independent memory page table, and a peripheral can only be connected to one IOMMU through a tree bus. If the peripheral is connected to multiple IOMMUs through a mesh interconnection bus, the memory access request of the peripheral can be transmitted to any one of the multiple IOMMUs. However, since the memory page tables managed by the multiple IOMMUs are independent, there will inevitably be a problem that the IOMMU receiving the memory access request cannot correctly perform address translation, that is, address translation will be incorrect. It can be seen that, by allocating the common memory page table to the multiple IOMMUs, the present solution solves the problem of page table management under a mesh interconnection bus.

[0077] As can be seen from the above, the computer system further includes an IOMMU framework. In order to be compatible with the existing IOMMU framework, the present solution is implemented by using an IOMMU virtual driver. That is, the IOMMU virtual driver is registered in the IOMMU framework in the embodiment of the present application, and the existing IOMMU framework is compatible by means of the virtual driver, without affecting the existing IOMMU framework and the bus system.

[0078] The computer system registers the IOMMU virtual driver to the IOMMU framework, and creates an IOMMU virtual instance for the IOMMU virtual driver, and registers the IOMMU virtual instance to the IOMMU framework. In addition, the computer system also creates an IOMMU instance for each of the plurality of IOMMUs, registers the created plurality of IOMMU instances to the IOMMU virtual instance, and manages the plurality of IOMMU instances through the IOMMU virtual instance. That is, in the embodiment of the present application, the IOMMU virtual instance is connected to the IOMMU framework upwardly, and manages the plurality of IOMMU instances downwardly.

[0079] In a possible implementation, the IOMMU virtual instance configures a common memory resource for the plurality of IOMMUs, and writes the information of the common memory resource to the plurality of IOMMUs through the IOMMU virtual driver, such as writing the information to the hardware registers of the plurality of IOMMUs.

[0080] The common memory resource includes a common memory page table, and the IOMMU virtual driver writes the base address of the common memory page table to the plurality of IOMMUs.

[0081] In a possible implementation, the common memory resource includes a common configuration resource in addition to the common memory page table, such as including some common configuration data.

[0082] Step 1001 can be a step performed by the computer system in the process of initializing the operating system. That is, the configuration of the common memory resource is completed in the initialization stage of the operating system. Next, the initialization stage of the operating system is briefly introduced.

[0083] FIGS. 11 and 12 are a schematic diagram of a software and hardware system during initialization of an operating system and a flowchart of the initialization of the operating system, according to an embodiment of the present application. Taking the computer system including a plurality of newly added IOMMUs and a plurality of existing IOMMUs as an example, referring to FIGS. 11 and 12, the process of initializing the operating system in the computer system includes the following steps.

[0084] 1. The operating system initializes the bus, creates a bus model, and the respective IOMMUs on the platform bus are successively online, and the corresponding IOMMU drivers are called. The IOMMUs involved in this embodiment include existing IOMMUs, virtual IOMMUs (such as the IOMMU management modules shown in FIGS. 4 to 8), and newly added IOMMUs.

[0085] 2. If the online device is an existing IOMMU, the existing IOMMU driver is invoked to initialize an IOMMU instance (referred to as an existing IOMMU instance) for each existing IOMMU. If the online device is a virtual IOMMU, the IOMMU virtual driver is invoked to initialize an IOMMU virtual instance for the virtual IOMMU. If the online device is a new IOMMU, after the initialization of the virtual IOMMU is completed, the new IOMMU driver is invoked to initialize an IOMMU instance (referred to as a new IOMMU instance) for each new IOMMU.

[0086] 3. The existing IOMMU driver applies for respective page table resources for each existing IOMMU instance. The virtual IOMMU applies for a common page table resource for the IOMMU virtual instance.

[0087] 4. The new IOMMU driver obtains information about the common page table resource from the virtual IOMMU and configures the information into the hardware register of each new IOMMU instance. For example, the common memory resource includes a common memory page table, and the hardware register of each new IOMMU stores the same base address of the memory page table, thereby realizing page table sharing. The existing IOMMU driver configures information about the page table resource applied for each existing IOMMU instance into the hardware register of the corresponding IOMMU. The hardware register of each existing IOMMU stores different addresses of the page table resource.

[0088] 5. The existing IOMMU driver reports the existing IOMMU instance and the driver interface of the existing IOMMU driver to the IOMMU framework. The IOMMU management module reports the IOMMU virtual instance to the IOMMU framework. The new IOMMU driver reports the new IOMMU instance and the driver interface of the new IOMMU driver to the IOMMU virtual instance, which is responsible for management.

[0089] 6. The IOMMU virtual instance directly registers the driver interface of each new IOMMU to the corresponding bus, thereby realizing the effect of different buses carrying different driver methods. The driver interface of the existing IOMMU is broadcasted and registered to all buses by the IOMMU framework.

[0090] 7. Each bus initializes a device model according to the IOMMU driver interface thereof and registers each IOMMU driver interface to the corresponding peripheral. That is, each peripheral is sequentially uploaded, the corresponding IOMMU driver is invoked, a corresponding device model is created under the corresponding bus model, and each IOMMU driver interface is registered to the corresponding device model.

[0091] In the embodiments of the present application, the plurality of IOMMUs in step 1001 can include the newly added IOMMU in the embodiments of FIG. 4 to FIG. 8. That is, the computer system can include more IOMMUs in addition to the plurality of IOMMUs in step 1001.

[0092] Step 1002: The computer system performs access control on the common memory by the plurality of IOMMUs sharing the common memory resource.

[0093] For example, the computer system performs access control on the common memory by the plurality of IOMMUs sharing the common memory resource, including: obtaining, by an IOMMU virtual instance, a configuration request about a first memory resource in the common memory resource, determining an IOMMU instance as an IOMMU proxy instance from the plurality of IOMMU instances, and delivering the configuration request of the first memory resource to the IOMMU proxy instance, and executing the configuration request of the first memory resource by the IOMMU proxy instance. That is, the IOMMU virtual instance has the function of request distribution, and performs memory access control through request distribution.

[0094] In a possible implementation, the plurality of IOMMUs are also respectively assigned with private memory resources, and the private memory resources of the plurality of IOMMUs can each include related information of the first memory resource. The IOMMU proxy instance executes the configuration request of the first memory resource, including: updating the private memory resource of the IOMMU proxy to configure the first memory resource. Wherein, the IOMMU proxy refers to the IOMMU corresponding to the IOMMU proxy instance.

[0095] After the IOMMU proxy instance updates the private memory resource of the IOMMU proxy, the IOMMU virtual instance also synchronizes the update operation of the IOMMU proxy instance to other IOMMU instances in the plurality of IOMMU instances except the IOMMU proxy instance, to instruct other IOMMU instances to synchronize the configuration of the first memory resource by updating the private memory resource of the corresponding IOMMU. That is, when a certain IOMMU instance modifies the corresponding private memory resource, the modification operation needs to be synchronized to other IOMMU instances, so that the information included in the private memory resources corresponding to the plurality of IOMMU instances is consistent.

[0096] For example, the common memory resource further includes a common memory page table, and the configuration request of the first memory resource indicates an application or release of the first memory in the common memory. The IOMMU agent instance executes the configuration request of the first memory resource, including: the IOMMU agent instance updates the memory page table item cached by the IOMMU agent and updates the common memory page table to apply or release the first memory, and the cached memory page table item includes part of the page table item in the common memory page table. The IOMMU virtual instance synchronizes the update operation of the IOMMU agent instance to other IOMMU instances except the IOMMU agent instance in the plurality of IOMMU instances, to instruct other IOMMU instances to synchronize the application or release of the first memory by updating the corresponding IOMMU cached memory page table item. Wherein, the IOMMU cached memory page table item belongs to the private memory resource of the corresponding IOMMU.

[0097] In the embodiment of the present application, the computer system further includes a DMA framework, and the configuration request of the first memory resource is a DMA software request delivered by the DMA framework to the IOMMU virtual instance. That is, the DMA framework directly delivers the DMA software request to the IOMMU virtual instance across the IOMMU framework. In this way, the present solution can be compatible with the IOMMU framework in the related art.

[0098] For example, the DMA applies for memory as an IO device, the DMA framework finally calls the IOMMU driver corresponding to the driving interface registered by the IO device, sends the request of the IO device to the IOMMU virtual instance, the IOMMU virtual instance selects an IOMMU instance as an IOMMU agent instance, the IOMMU agent instance modifies the common memory page table and flushes the private cache (i.e. the cached memory page table item). The IOMMU virtual instance broadcasts the operation of flushing the cache to other non-agent instances, to instruct other non-agent instances to synchronize and flush the private cache. Thus, the public data and the private data between the plurality of IOMMU instances are synchronized.

[0099] In a possible implementation, the computer system further includes a plurality of buses, the plurality of IOMMU in step 1001 includes a plurality of IOMMU, the plurality of buses correspond to the plurality of IOMMU one by one, the plurality of IOMMU respectively connect at least one peripheral device through a corresponding bus, the plurality of IOMMU respectively correspond to an IOMMU driver, and the IOMMU driver includes a driving interface. Based on this, the computer system further registers the driving interface of the IOMMU connected by the peripheral device for each peripheral device connected to the plurality of buses. Wherein, the peripheral device is used to send a memory access request about the common memory through the registered driving interface.

[0100] Taking the multiple IOMMUs in step 1001 as an example of the newly added IOMMUs in the embodiments of FIG. 4 to FIG. 8, the IOMMU drivers corresponding to the multiple IOMMUs are referred to as newly added IOMMU drivers, and the driving interfaces of the newly added IOMMU drivers cross the IOMMU framework and are directly registered to the bus and the peripheral device.

[0101] In the embodiments of the present application, the driving interfaces of the IOMMUs registered by the computer system to the peripheral devices are stored in the device models of the peripheral devices. In the initialization stage, the computer system constructs bus models corresponding to the multiple buses respectively, and constructs device models of the peripheral devices connected to the corresponding buses respectively under the bus models corresponding to the multiple buses. The computer system registers the driving interfaces of the IOMMUs connected to each peripheral device connected to the multiple buses in the following manner: registering the driving interfaces of the IOMMUs connected to the corresponding buses to each bus model; and registering the driving interfaces of the IOMMUs connected to the corresponding buses to the device models under the corresponding bus models through each bus model. The peripheral devices send memory access requests about the common memory through the driving interfaces registered in the corresponding device models. That is, the present scheme directly registers the IOMMU driving interfaces to the corresponding bus models and device models across the IOMMU framework.

[0102] The multiple buses include at least one of a mesh interconnection bus and a tree bus.

[0103] Under the mesh interconnection bus, at least two IOMMUs of the multiple IOMMUs are connected to a first peripheral device in the computer system, and the types of the at least two IOMMUs are the same. In the case of detecting a memory access request of the first peripheral device, the computer system determines one IOMMU as a second IOMMU from the at least two IOMMUs, and reads or writes a second memory through the second IOMMU. The memory access request of the first peripheral device indicates reading or writing the second memory in the common memory. That is, any one of the multiple IOMMUs can process the memory access request of the first peripheral device based on the common memory page table.

[0104] Next, taking FIG. 8 in the foregoing as an example, the process of the peripheral device performing memory access after the operating system is initialized in the embodiments of the present application is exemplarily introduced.

[0105] The DMA requests (i.e., memory access requests) of the peripheral devices connected to the PCIE bus in FIG. 8 are translated (i.e., address converted) by IOMMU-A. For example, the DMA requests of the peripheral device 5 and the device 6 are translated by IOMMU-A1, and the DMA requests of the peripheral device 7 and the peripheral device 8 are translated by IOMMU-A2. IOMMU-A1 and IOMMU-A2 apply for different page table resources by the IOMMU-A driver, and read different page tables during translation.

[0106] The DMA request of the peripheral device (i.e., peripheral devices 1-4) connected to the mesh interconnection bus is translated by IOMMU-B1 or IOMMU-B2 according to the routing condition of the bus. The specific implementation of the routing is known in the art, and thus is not described herein.

[0107] Taking the routing of a certain DMA request of the peripheral device connected to the mesh interconnection bus to IOMMU-B1 as an example, the memory page table entry recorded by IOMMU-B1 is from the common memory page table. After IOMMU-B1 translates the DMA request, the physical address obtained is sent to the memory controller, and the memory controller reads or writes the corresponding memory data based on the physical address.

[0108] Suppose that the same DMA request is also routed to IOMMU-B2. Since the memory page table entry recorded by IOMMU-B2 is also from the common memory page table, and is consistent with the corresponding page table entry recorded by IOMMU-B1, the translation result of IOMMU-B2 is consistent with that of IOMMU-B1, which is as expected.

[0109] In summary, in the embodiments of the present application, the common use of the common memory page table by the multiple IOMMUs is used to perform memory access control, so that one computer system can be equipped with multiple types of IOMMUs and multiple types of buses, including the mesh interconnection bus, while ensuring the reliability of memory access control.

[0110] In a specific implementation, the embodiments of the present application provide a multi-IOMMU management framework (i.e., IOMMU framework + IOMMU management module), which realizes the effect of aggregating and managing multiple IOMMU instances by a software framework, and enables the IOMMU to translate all devices under the mesh interconnection bus by means of sharing of page table resources. The resource synchronization of multiple IOMMU instances is ensured by means of request distribution, so as to ensure the normal work of the hardware. At the same time, by directly registering the interfaces of each IOMMU to the corresponding bus and peripheral device, the multiple types of IOMMU are managed in a bus isolation manner.

[0111] The same public memory page table is configured for the plurality of IOMMU, so that the plurality of IOMMU share the page table, the redundant page table and the write table frequency are reduced under the mesh topology bus, the memory access efficiency is improved, and the IOMMU can be used for the mesh interconnection bus. By selecting the IOMMU agent, the request distribution, and the broadcast refresh operation, data synchronization of the plurality of IOMMU instances is realized, so that the plurality of types of IOMMU can be used for the mesh interconnection bus. By means of the virtual device and the virtual drive, the IOMMU management module is connected to the existing IOMMU framework, the original framework is non-invasively modified, and the request distribution processing effect is realized. By creating a bus, the corresponding drive interface is registered for the newly created bus, so that different buses are mounted with different IOMMU drive interfaces, and a plurality of types of IOMMU coexist in one OS.

[0112] Fig. 13 is a structural schematic diagram of a memory access control apparatus 1300 provided by an embodiment of the present application. The apparatus 1300 can be realized by software, hardware, or a combination of both, as part or all of a computer device or a computer system. The computer device can be the computer device shown in Fig. 9, and the computer system can be any of the computer systems in the embodiments of Figs. 1 to 12. In the embodiment of the present application, the apparatus 1300 is included in a computer system, and the computer system further includes a plurality of IOMMU. Referring to Fig. 13, the apparatus 1300 includes an allocation module 1301 and an access control module 1302.

[0113] The allocation module 1301 is configured to allocate a public memory resource to the plurality of IOMMU. The public memory resource includes a public memory.

[0114] The access control module 1302 is configured to perform access control on the public memory by the plurality of IOMMU sharing the public memory resource.

[0115] In a possible implementation, the public memory resource further includes a public memory page table, and the allocation module 1301 includes:

[0116] A first processing submodule is configured to write a base address of the public memory page table to the plurality of IOMMU respectively. The base address of the public memory page table represents the public memory.

[0117] In a possible implementation, the computer system further includes an IOMMU framework, and an IOMMU virtual drive is registered in the IOMMU framework. The steps performed by the apparatus 1300 are realized by using the IOMMU virtual drive.

[0118] In a possible implementation, the apparatus 1300 further includes:

[0119] The first processing module is configured to register the IOMMU virtual driver to the IOMMU framework, create an IOMMU virtual instance for the IOMMU virtual driver, create an IOMMU instance for each of the plurality of IOMMUs, and register the plurality of created IOMMU instances to the IOMMU virtual instance.

[0120] The access control module 1302 comprises:

[0121] The second processing submodule is configured to acquire a configuration request for the first memory resource in the common memory resource through the IOMMU virtual instance, determine one IOMMU instance as an IOMMU proxy instance from the plurality of IOMMU instances, and pass the configuration request for the first memory resource to the IOMMU proxy instance, and execute the configuration request for the first memory resource through the IOMMU proxy instance.

[0122] In a possible implementation, the plurality of IOMMUs are also respectively assigned with private memory resources, and the private memory resources of the plurality of IOMMUs can each include related information of the first memory resource;

[0123] The second processing submodule is specifically configured to:

[0124] The first memory resource is configured by updating the private memory resource of the IOMMU proxy through the IOMMU proxy instance, wherein the IOMMU proxy refers to an IOMMU corresponding to the IOMMU proxy instance;

[0125] The access control module 1302 further comprises:

[0126] The third processing submodule is configured to synchronize the update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance in the plurality of IOMMU instances, so as to instruct the other IOMMU instances to synchronize the configuration of the first memory resource by updating the private memory resource of the corresponding IOMMU.

[0127] In a possible implementation, the common memory resource further includes a common memory page table, and the configuration request for the first memory resource indicates an application or release of the first memory in the common memory;

[0128] The second processing submodule is specifically configured to:

[0129] The first memory is applied for or released by updating the cached memory page table item and the common memory page table through the IOMMU proxy instance, wherein the IOMMU proxy refers to an IOMMU corresponding to the IOMMU proxy instance, and the cached memory page table item includes part of the page table items in the common memory page table;

[0130] The access control module 1302 further comprises:

[0131] a third processing submodule, configured to synchronize, by an IOMMU virtual instance, an update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance in the plurality of IOMMU instances, to instruct the other IOMMU instances to synchronize the application or release of the first memory by updating memory page table items of a corresponding IOMMU cache.

[0132] In a possible implementation, the computer system further includes a DMA framework, and the configuration request of the first memory resource is a request delivered by the DMA framework to the IOMMU virtual instance.

[0133] In a possible implementation, the computer system further includes a plurality of buses, the plurality of IOMMU includes a plurality of IOMMU, the plurality of buses correspond to the plurality of IOMMU one by one, the plurality of IOMMU are respectively connected to at least one peripheral device through a corresponding bus, the plurality of IOMMU respectively correspond to an IOMMU driver, the IOMMU driver includes a driver interface, and the apparatus 1300 further includes:

[0134] a second processing module, configured to register, for each peripheral device connected to the plurality of buses, a driver interface of an IOMMU connected to the peripheral device, and the peripheral device is configured to send a memory access request about the common memory through the registered driver interface.

[0135] In a possible implementation, the driver interface of the IOMMU registered by the peripheral device is stored in a device model of the peripheral device, and the apparatus 1300 further includes:

[0136] a model construction module, configured to construct a bus model corresponding to each bus in the plurality of buses, and construct a device model of a peripheral device connected to the corresponding bus under the bus model corresponding to the bus.

[0137] the second processing module includes:

[0138] a first registration submodule, configured to register, for the bus model, a driver interface of an IOMMU connected to the corresponding bus.

[0139] a second registration submodule, configured to register, for the bus model, the driver interface of the IOMMU connected to the corresponding bus to a device model under the bus model, and the peripheral device is configured to send a memory access request about the common memory through the registered driver interface in the corresponding device model.

[0140] In a possible implementation, at least two IOMMU in the plurality of IOMMU are connected to a first peripheral device in the computer system, and the at least two IOMMU are of the same type, and the apparatus 1300 further includes:

[0141] The determining module is configured to determine one IOMMU as the second IOMMU from the at least two IOMMUs when detecting a memory access request of the first peripheral device, the memory access request of the first peripheral device indicating reading or writing a second memory in the common memory;

[0142] The memory access module is configured to read or write the second memory through the second IOMMU.

[0143] In a possible implementation, the plurality of buses includes at least one of a mesh interconnection bus and a tree bus.

[0144] In the embodiments of the present application, the memory access control is performed by means of the plurality of IOMMUs sharing the common memory page table, so that one computer system can be equipped with a plurality of types of IOMMUs and a plurality of types of buses, including a mesh interconnection bus, while ensuring the reliability of the memory access control.

[0145] It should be noted that the memory access control device provided in the above embodiments is only used as an example for illustrating the division of the functional modules, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the memory access control device and the memory access control method provided in the above embodiments belong to the same concept, and the specific implementation process is described in the method embodiments, which will not be repeated here.

[0146] In the above embodiments, all or part can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer instructions generate all or part of the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another via wired (for example: coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example: infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer, or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (for example: floppy disk, hard disk, magnetic tape), optical media (for example: digital versatile disc (DVD)) or semiconductor media (for example: solid state disk (SSD)) etc. It should be noted that the computer-readable storage medium mentioned in the embodiments of the present application can be a non-volatile storage medium, in other words, it can be a non-transitory storage medium.

[0147] It should be understood that "at least one" mentioned herein refers to one or more, and "multiple" refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; "and / or" herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, "first", "second" and the like are used to distinguish the same or similar items with basically the same function and role in the embodiments of the present application. Those skilled in the art can understand that "first", "second" and the like do not limit the number and execution order, and "first", "second" and the like do not necessarily mean different.

[0148] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the embodiments of the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0149] The above describes the embodiments provided by the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory access control method characterized by, The method is applied to a computer system comprising a plurality of input / output memory management units (IOMMU), and comprises: allocating a common memory resource to the plurality of IOMMU, the common memory resource comprising a common memory; controlling access to the common memory by the plurality of IOMMU sharing the common memory resource.

2. The method of claim 1, wherein, The common memory resource further comprises a common memory page table, and the step of allocating a common memory resource to the plurality of IOMMU comprises: writing a base address of the common memory page table to each of the plurality of IOMMU, the base address of the common memory page table representing the common memory.

3. The method of claim 1 or 2, wherein, The computer system further comprises an IOMMU framework in which an IOMMU virtual driver is registered, and the method is implemented by using the IOMMU virtual driver.

4. The method of claim 3, wherein, The method further comprises: registering the IOMMU virtual driver to the IOMMU framework, creating an IOMMU virtual instance for the IOMMU virtual driver, creating an IOMMU instance for each of the plurality of IOMMU, and registering the created plurality of IOMMU instances to the IOMMU virtual instance; controlling access to the common memory by the plurality of IOMMU sharing the common memory resource comprises: obtaining, by the IOMMU virtual instance, a configuration request for a first memory resource in the common memory resource, determining an IOMMU instance as an IOMMU proxy instance from the plurality of IOMMU instances, and passing the configuration request for the first memory resource to the IOMMU proxy instance, and executing the configuration request for the first memory resource by the IOMMU proxy instance.

5. The method of claim 4, wherein, The plurality of IOMMU are further respectively allocated with private memory resources, and the private memory resources of the plurality of IOMMU can each comprise related information of the first memory resource; executing the configuration request for the first memory resource by the IOMMU proxy instance comprises: configuring the first memory resource by updating a private memory resource of an IOMMU proxy by the IOMMU proxy instance, the IOMMU proxy being an IOMMU corresponding to the IOMMU proxy instance; The method further comprises: synchronizing, to IOMMU instances other than the IOMMU proxy instance among the plurality of IOMMU instances, an update operation of the IOMMU proxy instance, to instruct the other IOMMU instances to synchronize configuration of the first memory resource by updating private memory resources of corresponding IOMMU.

6. The method of claim 4 or 5, wherein, The common memory resource further comprises a common memory page table, and the configuration request for the first memory resource indicates application or release of a first memory in the common memory; executing the configuration request for the first memory resource by the IOMMU proxy instance comprises: updating, by the IOMMU proxy instance, a cached memory page table item of the IOMMU proxy and a public memory page table to apply for or release the first memory, the IOMMU proxy referring to an IOMMU corresponding to the IOMMU proxy instance, the cached memory page table item including part of the page table items in the public memory page table; The method further comprises: synchronizing, by the IOMMU virtual instance, the update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance among the plurality of IOMMU instances, to instruct the other IOMMU instances to synchronize the application for or release of the first memory by updating the cached memory page table item of the corresponding IOMMU.

7. The method according to any one of claims 4 to 6, wherein, The computer system further comprises a direct memory access (DMA) framework, and the configuration request of the first memory resource is a request delivered by the DMA framework to the IOMMU virtual instance.

8. The method according to any one of claims 1 to 7, wherein, The computer system further comprises a plurality of buses, and the plurality of IOMMU comprises a plurality of IOMMU, the plurality of buses correspond to the plurality of IOMMU one by one, the plurality of IOMMU respectively connect at least one peripheral device through a corresponding bus, the plurality of IOMMU respectively correspond to an IOMMU driver, the IOMMU driver comprises a driver interface, and the method further comprises: registering, for each peripheral device connected to the plurality of buses, a driver interface of an IOMMU connected to the corresponding peripheral device, and the peripheral device is configured to send a memory access request related to the public memory through the registered driver interface.

9. The method of claim 8, wherein, The driver interface of the IOMMU registered by the peripheral device is stored in a device model of the peripheral device, and the method further comprises: constructing a bus model corresponding to each of the plurality of buses, and constructing a device model of a peripheral device connected to a corresponding bus under the bus model corresponding to the bus; The method further comprises: registering, for each peripheral device connected to the plurality of buses, a driver interface of an IOMMU connected to the corresponding peripheral device, and the peripheral device is configured to send a memory access request related to the public memory through the registered driver interface. The first peripheral device in the computer system is connected to at least two IOMMU in the plurality of IOMMU, the at least two IOMMU are of the same type, and the method further comprises:

10. The method of claim 8 or 9, wherein, In a case where a memory access request of the first peripheral device is detected, one IOMMU is determined as a second IOMMU from the at least two IOMMU, the memory access request of the first peripheral device instructing reading or writing of a second memory in the public memory; reading or writing the second memory by the second IOMMU. The plurality of buses comprises at least one of a mesh interconnection bus and a tree bus.

11. The method according to any one of claims 8 to 10, wherein, The computer system further comprises a plurality of input / output memory management units (IOMMU), and the device comprises:

12. A memory access control apparatus, characterized by comprising: ​ an allocation module configured to allocate a common memory resource to the plurality of IOMMUs, the common memory resource comprising a common memory; an access control module configured to perform access control on the common memory by the plurality of IOMMUs sharing the common memory resource.

13. The apparatus of claim 12, wherein, The common memory resource further comprises a common memory page table, and the allocation module comprises: a first processing submodule configured to write a base address of the common memory page table to each of the plurality of IOMMUs, the base address of the common memory page table representing the common memory.

14. The apparatus of claim 12 or 13, wherein, The computer system further comprises an IOMMU framework in which an IOMMU virtual driver is registered, and the steps performed by the apparatus are implemented by using the IOMMU virtual driver.

15. The apparatus of claim 14, wherein, The apparatus further comprises: a first processing module configured to register the IOMMU virtual driver to the IOMMU framework, create an IOMMU virtual instance for the IOMMU virtual driver, create an IOMMU instance for each of the plurality of IOMMUs, and register the plurality of IOMMU instances created to the IOMMU virtual instance; The access control module comprises: a second processing submodule configured to obtain a configuration request for a first memory resource in the common memory resource through the IOMMU virtual instance, determine an IOMMU instance as an IOMMU proxy instance from the plurality of IOMMU instances, and pass the configuration request for the first memory resource to the IOMMU proxy instance, and execute the configuration request for the first memory resource through the IOMMU proxy instance.

16. The apparatus of claim 15, wherein, The plurality of IOMMUs are further respectively allocated with private memory resources, and the private memory resources of the plurality of IOMMUs can each comprise related information of the first memory resource; The second processing submodule is specifically configured to: configure the first memory resource by updating a private memory resource of an IOMMU proxy through the IOMMU proxy instance, the IOMMU proxy being an IOMMU corresponding to the IOMMU proxy instance; The access control module further comprises: a third processing submodule configured to synchronize an update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance from the plurality of IOMMU instances, to instruct the other IOMMU instances to synchronize the configuration of the first memory resource by updating a private memory resource of a corresponding IOMMU.

17. The apparatus of claim 15 or 16, wherein, The common memory resource further comprises a common memory page table, and the configuration request for the first memory resource indicates an application or release of a first memory in the common memory; The second processing submodule is specifically configured to: apply or release the first memory by updating a cached memory page table item of an IOMMU proxy and updating the common memory page table through the IOMMU proxy instance, the IOMMU proxy being an IOMMU corresponding to the IOMMU proxy instance, and the cached memory page table item comprising part of the common memory page table; The access control module further comprises: The third processing submodule is configured to synchronize the update operation of the IOMMU proxy instance to other IOMMU instances except the IOMMU proxy instance in the plurality of IOMMU instances through the IOMMU virtual instance, so as to instruct the other IOMMU instances to synchronize the application or release of the first memory by updating the memory page table item of the corresponding IOMMU cache.

18. The apparatus of any one of claims 15-17, wherein, The computer system further comprises a direct memory access (DMA) framework, and the configuration request of the first memory resource is a request delivered by the DMA framework to the IOMMU virtual instance.

19. The apparatus of any one of claims 12-18, wherein, The computer system further comprises a plurality of buses, and the plurality of IOMMU comprises a plurality of IOMMU, the plurality of buses correspond to the plurality of IOMMU one by one, the plurality of IOMMU are connected to at least one peripheral device through a corresponding bus respectively, the plurality of IOMMU correspond to an IOMMU driver respectively, and the IOMMU driver comprises a driver interface. The second processing module is configured to register the driver interface of the IOMMU connected to each peripheral device in the plurality of buses for the peripheral device, and the peripheral device is configured to send a memory access request about the common memory through the registered driver interface.

20. The apparatus of claim 19, wherein, The driver interface of the IOMMU registered for the peripheral device is stored in a device model of the peripheral device, and the apparatus further comprises: A model construction module is configured to construct a bus model corresponding to each bus in the plurality of buses, and construct a device model of the peripheral device connected to the corresponding bus under the bus model corresponding to the bus respectively. The second processing module comprises: A first registration submodule is configured to register the driver interface of the IOMMU connected to the corresponding bus in the bus model; A second registration submodule is configured to register the driver interface of the IOMMU connected to the corresponding bus in the device model under the bus model through the bus model, and the peripheral device is configured to send a memory access request about the common memory through the registered driver interface in the corresponding device model.

21. The apparatus of claim 19 or 20, wherein, The first peripheral device in the computer system is connected to at least two IOMMU in the plurality of IOMMU, the at least two IOMMU are of the same type, and the apparatus further comprises: A determination module is configured to determine one IOMMU as a second IOMMU from the at least two IOMMU in a case where a memory access request of the first peripheral device is detected, the memory access request of the first peripheral device indicating reading or writing of a second memory in the common memory; A memory access module is configured to read or write the second memory through the second IOMMU.

22. The apparatus of any one of claims 19-21, wherein, The plurality of buses comprises at least one of a mesh interconnection bus and a tree bus.

23. A computer system, characterized in that The computer system comprises a processor and a plurality of input / output memory management units (IOMMU), and the processor is configured to perform the steps of the method in any one of claims 1-11.

24. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is executed by the processor to implement the method in any one of claims 1-11.

25. A computer program product, characterised in that, The computer program product stores computer instructions which, when executed by a processor, implement the method of any one of claims 1-11.

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