Back contact cell and preparation method therefor

Abstract

The present application provides a back contact cell and a preparation method therefor. The preparation method comprises the following steps: obtaining a silicon substrate, wherein the silicon substrate is provided with a substrate front surface and a substrate back surface which are opposite to each other; performing double-sided polishing on the silicon substrate; preparing a first polarity stack on one side of the substrate back surface of the polished silicon substrate; removing a part of the first polarity stack to expose a plurality of first opening regions on the substrate back surface, and obtaining a first battery intermediate piece; performing double-sided texturing on the first battery intermediate piece; preparing a front anti-reflection region to obtain a second battery intermediate piece; performing double-sided polishing on the second battery intermediate piece with the protection of the front anti-reflection region on one side of the substrate front surface so as to obtain a third battery intermediate piece; and preparing a second polarity stack. The preparation method for the back contact cell and the cell of the present application can improve the photoelectric conversion efficiency of the cell by efficiently simplifying the process.

Description

Back contact cell and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaics, and in particular to a back contact cell and a preparation method thereof. BACKGROUND

[0002] For the current large-scale production of TOPCon cells, the disadvantage is that the front surface recombination loss is large, and in addition, the strong parasitic absorption of the front surface also hinders the further improvement of the efficiency of HJT cells. Unlike the traditional double-sided electrode contact cell, the biggest feature of the back contact cell (BC cell) is that the metal electrode is located on the back surface of the cell, and the front surface is not blocked by the metal electrode, which improves the light utilization rate. Therefore, combining the passivation structures of TOPCon and HJT cells on the BC structure to form a hybrid back contact cell will have higher conversion efficiency.

[0003] The hybrid cell structure currently studied is generally that the back TOPCon region is a polished topography, and the back heterojunction region and the front surface are both formed into a textured topography at the same time. The purpose of this is to make the back heterojunction region and the front surface textured at the same time, and the process flow is relatively simple. However, since the interface area of the textured surface is increased more than that of the polished surface, and the interface defects and carrier recombination of the pyramids on the textured surface are more serious than those of the polished surface, the passivation effect of the back heterojunction passivation region does not reach the best, which affects the cell efficiency.

[0004] In addition, if amorphous silicon is used for passivation on the front surface of the HBC cell, the parasitic absorption is serious, which will greatly affect the short-circuit current. Although the use of C and O doped polysilicon can reduce a part of the front surface parasitic absorption, but since the doped polysilicon layer will also diffuse impurity atoms into the silicon substrate, it will also cause recombination centers, which will cause loss to the front passivation. On the other hand, the back contact cell collects carriers on the back surface, and the construction of the front high-low junction is not conducive to the transport of most carriers on the back surface, thereby affecting the current of the cell. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a back contact cell and a preparation method thereof, which can improve the photoelectric conversion efficiency of the cell through efficient and simplified process.

[0006] To solve the above technical problems, the application provides a preparation method of a back contact battery, the battery back surface of the battery has first polarity areas and second polarity areas arranged adjacent to each other, and the preparation method comprises the following steps: obtaining a silicon substrate, the silicon substrate has opposite substrate front surface and substrate back surface, wherein the substrate front surface is closer to the light surface of the battery than the substrate back surface; polishing the silicon substrate on both sides; preparing a first polarity stack on the substrate back surface side of the polished silicon substrate; removing part of the first polarity stack to expose a plurality of first opening areas of the substrate back surface, and obtaining a first battery intermediate part, wherein the first opening areas are used for preparing the second polarity areas, and the areas of the substrate back surface outside the first opening areas are used for preparing the first polarity areas; performing double-side texturing on the first battery intermediate part; preparing a front surface anti-reflection area on the substrate front surface side of the textured first battery intermediate part to obtain a second battery intermediate part; polishing the second battery intermediate part on both sides by means of the protection of the substrate front surface side of the front surface anti-reflection area to obtain a third battery intermediate part; and preparing a second polarity stack on the substrate back surface side of the third battery intermediate part, the polarity of the second polarity stack is opposite to that of the first polarity stack, and the second polarity stack covers at least the plurality of first opening areas on the substrate back surface.

[0007] Optionally, the step of preparing the first polarity stack on the substrate back surface side of the polished silicon substrate comprises: preparing a first passivation layer and a first doped semiconductor layer with the same or opposite doping type as the silicon substrate on the substrate back surface side, and the first doped semiconductor layer comprises polysilicon.

[0008] Optionally, the step of preparing the first passivation layer and the first doped semiconductor layer comprises: preparing a tunneling oxide layer by low-pressure chemical vapor deposition to obtain the first passivation layer, and preparing an intrinsic amorphous silicon layer or a polysilicon layer and then performing high-temperature diffusion doping and crystallization to obtain the first doped semiconductor layer; or preparing a tunneling oxide layer by plasma-enhanced chemical vapor deposition to obtain the first passivation layer, and preparing an in-situ doped intrinsic amorphous silicon layer or a polysilicon layer and then performing high-temperature annealing crystallization to obtain the first doped semiconductor layer.

[0009] Optionally, it further comprises forming a substrate doped layer on the substrate back surface side of the silicon substrate at the same time of preparing the first passivation layer and the first doped semiconductor layer.

[0010] Optionally, the step of preparing the first polarity stack on the back surface of the silicon substrate further comprises preparing an insulating layer, the insulating layer comprises at least one or more of phosphorus-silicon glass or boron-silicon glass, silicon oxide, silicon nitride, silicon oxynitride.

[0011] Optionally, the step of removing part of the first polarity stack to expose a plurality of first opening regions on the back side of the substrate comprises removing part of the first polarity stack by means of laser, printing mask layer and / or alkaline polishing etching.

[0012] Optionally, the method further comprises simultaneously removing one or more layers of material deposited on the front side of the substrate and / or plated around the edge of the silicon substrate, which have the same material as the first polarity stack, while removing part of the first polarity stack.

[0013] Optionally, the step of preparing a second polarity stack on the back side of the substrate of the third cell intermediate comprises preparing a second passivation layer and a second doped semiconductor layer having the same or opposite doping type as the silicon substrate, and the second passivation layer comprises intrinsic amorphous silicon, and the second doped semiconductor layer comprises amorphous silicon and / or doped microcrystalline silicon.

[0014] Optionally, the method further comprises: preparing the second passivation layer and the second doped semiconductor layer on the back side of the substrate of the third cell intermediate; and removing part of the second passivation layer and the second doped semiconductor layer in the region corresponding to the first polarity region to expose a plurality of second opening regions of the first polarity stack and obtain a fourth cell intermediate.

[0015] Optionally, a conductive layer is prepared on the back side of the substrate of the fourth cell intermediate, and the conductive layer comprises zinc oxide, indium oxide, tin oxide, or transparent conductive oxide doped with one or more of zinc, indium, and tin.

[0016] Optionally, the method further comprises preparing an electrode on the conductive layer in the second opening region.

[0017] Optionally, the method further comprises: in the region corresponding to the first polarity region and including the second polarity stack, further removing part of the second polarity stack to expose a plurality of third opening regions of the first polarity stack.

[0018] Optionally, the step of preparing a front side anti-reflection region on the front side of the substrate of the first cell intermediate after texturing comprises depositing an anti-reflection layer, the thickness of the anti-reflection layer along the first direction perpendicular to the silicon substrate is 40-100 nm, and the anti-reflection layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0019] Optionally, the step of double-side polishing the second cell interposer with the protection of the front side of the substrate by the front anti-reflection region includes: thinning the thickness of the anti-reflection layer by 10nm-35nm from the deposition thickness while polishing the back side of the substrate of the second cell interposer, and the thickness of the anti-reflection layer after thinning is 30nm-90nm.

[0020] Optionally, the step of double-side polishing the second cell interposer with the protection of the front side of the substrate by the front anti-reflection region includes: thinning the thickness of the anti-reflection layer by 10%-87.5% from the deposition thickness while polishing the back side of the substrate of the second cell interposer.

[0021] Optionally, the step of preparing the front anti-reflection region on the front side of the substrate of the first cell interposer after texturing further includes: depositing an aluminum oxide layer before depositing the anti-reflection layer, the thickness of the aluminum oxide layer along the first direction is 3nm-20nm.

[0022] Another aspect of the present application further provides a back contact cell prepared according to the preparation method of any one of the embodiments of the present application.

[0023] Another aspect of the present application further provides a back contact cell, comprising: a silicon substrate having opposite substrate front side and substrate back side, wherein the substrate front side is closer to the light-facing side of the cell than the substrate back side; a front anti-reflection region on the substrate front side, the front anti-reflection region comprising an anti-reflection layer; a first polarity region and a second polarity region adjacently and spacedly arranged on the substrate back side, wherein the first polarity region comprises a first passivation layer and a first doped semiconductor layer, the second polarity region comprises a second passivation layer and a second doped semiconductor layer opposite in polarity to the first doped semiconductor layer, and the second passivation layer comprises intrinsic amorphous silicon, and the second doped semiconductor layer comprises amorphous silicon and / or doped microcrystalline silicon, wherein the substrate front side is textured, and the area of the substrate back side where the second polarity region is located is polished.

[0024] Optionally, the area of the substrate back side where the second polarity region is located is a polished surface prepared with the protection of the front side of the substrate by the front anti-reflection region.

[0025] Optionally, the area of the first polarity region in the back surface of the substrate is a polished surface, wherein the first passivation layer comprises a tunneling oxide, and the thickness of the first passivation layer along a first direction perpendicular to the silicon substrate is 0.5-2 nm; and / or the first doped semiconductor layer comprises doped polysilicon, and the thickness of the first doped semiconductor layer along the first direction is 10-250 nm; and / or the thickness of the second passivation layer is 5-25 nm; and / or the thickness of the second doped semiconductor layer is 5-60 nm.

[0026] Optionally, the front surface anti-reflection region further comprises an aluminum oxide layer between the front surface of the substrate and the anti-reflection layer, wherein the thickness of the aluminum oxide layer along a first direction perpendicular to the silicon substrate is 3-20 nm; and / or the anti-reflection layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the thickness of the anti-reflection layer along the first direction is 30-90 nm.

[0027] Optionally, the thickness of the anti-reflection layer along the first direction is obtained by thinning a deposition thickness by 5-35 nm, or by thinning the deposition thickness by 10%-87.5% during the preparation process.

[0028] Compared with the prior art, the present application has the following advantages: the back contact cell and the preparation method thereof provided by the present application can design the back surface of the cell substrate as a full polishing pattern, and simultaneously realize a composite passivation material layer on the front surface through special design of the process steps. The preparation process of the present application is efficient and simple, further reduces the interface defects and carrier recombination of the heterojunction passivation region on the back surface of the cell, and cooperates with the front surface anti-reflection region (preferably simultaneously having passivation and anti-reflection effects) to further improve the photoelectric conversion efficiency of the cell.

[0029] SUMMARY

[0030] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute apart of this application, illustrate embodiments of the present application, and together with the description serve to explain the principles of the present application.

[0031] In the drawings:

[0032] Fig. 1 is a flowchart of a preparation method of a back contact cell according to an embodiment of the present application;

[0033] Fig. 2 is a structural schematic diagram of a back contact cell according to an embodiment of the present application.

[0034] Preferred embodiments of the present application

[0035] In order to illustrate the technical solutions of the embodiments of the present application more clearly, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description only show some examples or embodiments of the present application, and those skilled in the art can further apply the present application to other similar situations without any creative effort, based on the drawings. The same reference signs in the drawings represent the same structure or operation, unless otherwise clear from the context or otherwise indicated.

[0036] As shown in the present application and claims, unless the context clearly indicates otherwise, the words "one", "an", "a", and / or "the" do not mean "only one", but can include a plurality or "one or more" unless the context clearly indicates otherwise. Generally, the terms "comprising" and "including" only indicate the inclusion of the steps and elements explicitly identified in the context, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.

[0037] Unless specifically stated otherwise, the relative arrangement of components and steps, numerical expressions, and numerical values set forth in the embodiments are not meant to limit the scope of the present application. It should be understood that the dimensions of the various parts shown in the drawings are not necessarily to scale for the sake of convenience of description. The techniques, methods, and devices known to those skilled in the relevant art can not be discussed in detail, but should be considered as part of the authorized description, if appropriate. In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, and not as a limitation. Therefore, other examples of the exemplary embodiments can have different values. It should be noted that similar reference signs and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0038] In the description of the present application, it should be understood that the orientation words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal", and "top, bottom" indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise indicated, these orientation words do not indicate and imply that the indicated device or element must have a particular orientation or be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the scope of protection of the present application; the orientation words "inner, outer" refer to the inner and outer relative to the contour of the components themselves.

[0039] For purposes of the description hereinafter, spatial or directional terms, such as, for example, "above", "below", "upper", "lower", and the like, can be used with reference to the illustrated embodiment. Such terms are intended only to reflect relative positional relationships between the components, and / or their orientations, as illustrated in the drawings. It will be appreciated, however, that an embodiment can be fabricated in other orientations than those explicitly illustrated and / or described herein. Accordingly, the exemplary terms "above" and "below" can encompass both orientations as illustrated in the drawings, and other like orientations.

[0040] In addition, it should be noted that terminology from the field of the art is used herein for the purpose of describing the application. However, the terminology is merely selected from the field of the art for the purpose of describing the application and should not be understood as limiting the scope of the application. Moreover, it is to be understood that the terminology can be substituted by other terminology from the field of the art without departing from the scope of the application. Furthermore, it should be noted that the use of "first", "second", and the like in the description herein is merely intended to differentiate between similar objects unless otherwise indicated. Unless otherwise indicated, the use of these terms is not intended to limit the scope of the application. Moreover, although the terms used in the present specification are selected from generally known and used terms, some of the terms mentioned in the description of the present application can be newly generated terms by the inventor or a replacement of jargon commonly used by a portion of the field, and of course, the meanings of these terms and should be understood from the context of the relevant portion in the description of the present application.

[0041] It will be understood that when a component, is referred to as being "on", "connected to", "coupled with" or "in contact with" another component, it can be directly on, connected, coupled with or in contact with the other component, or one or more intervening components can also be present. In contrast, when a component is referred to as being "directly on", "directly connected to", "directly coupled with", or "directly in contact with" another component, there are no intervening components present. By the same token, when a first component is referred to as being "electrically in contact with" or "electrically coupled with" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path can include capacitors, coupled inductors, and / or other components that allow current to flow, even if there is no direct contact between conductive components.

[0042] Referring to FIG. 1, a method 10 for preparing a back contact cell is provided. The cell prepared according to the method 10 has first polarity regions and second polarity regions arranged adjacent to each other on the back surface of the cell. The method 10 can improve the photoelectric conversion efficiency of the cell by simplifying the process. It should be understood that the foregoing or the following operations are not necessarily performed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously. Meanwhile, other operations can be added to or removed from these processes.

[0043] According to FIG. 1, the method 10 includes the following steps:

[0044] Step 101 is to obtain a silicon substrate having opposite substrate front surface and substrate back surface, wherein the substrate front surface is closer to the light-receiving surface of the cell than the substrate back surface;

[0045] Step 102 is to polish the silicon substrate on both sides;

[0046] Step 103 is to prepare a first polarity stack on the substrate back surface side of the polished silicon substrate;

[0047] Step 104 is to remove part of the first polarity stack to expose a plurality of first opening regions on the substrate back surface, and obtain a first cell intermediate piece, wherein the first opening regions are used to prepare the second polarity regions, and the regions on the substrate back surface other than the first opening regions are used to prepare the first polarity regions;

[0048] Step 105 is to texturize the first cell intermediate piece on both sides;

[0049] Step 106 is to prepare a front surface anti-reflection region on the substrate front surface side of the textured first cell intermediate piece to obtain a second cell intermediate piece;

[0050] Step 107 is to polish the second cell intermediate piece on both sides by means of the protection of the front surface anti-reflection region on the substrate front surface side to obtain a third cell intermediate piece; and

[0051] Step 108 is to prepare a second polarity stack on the substrate back surface side of the third cell intermediate piece, the polarity of the second polarity stack being opposite to that of the first polarity stack, and the second polarity stack covering at least the plurality of first opening regions on the substrate back surface.

[0052] For better understanding of the method 10 and its preferred variant embodiments, a back contact cell 20 (hereinafter referred to as "cell 20") is first introduced below with reference to FIG. 2. The cell 20 can be prepared by any of the methods for preparing a back contact cell provided in the present application, or can be prepared by other means, which are not limited in the present application.

[0053] According to FIG. 2, the battery 20 has a silicon substrate 200 with an opposite substrate front surface 201 and a substrate back surface 202, wherein the substrate front surface 201 is closer to the light-facing surface of the battery 20 relative to the substrate back surface 202, and the incident direction of the light ray S is shown in FIG. 2. The battery 20 further includes a front surface anti-reflection region 21 on the substrate front surface 201. The front surface anti-reflection region 21 in this embodiment preferably includes both an aluminum oxide layer 211 and an anti-reflection layer 212, and the anti-reflection layer 212 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that adding the aluminum oxide layer 211 between the substrate front surface 201 and the anti-reflection layer 212 can make the front surface anti-reflection region 21 have a more optimal effect, and specifically, the aluminum oxide layer 211 can further improve the passivation effect of the front surface of the battery 20 by being in contact with the anti-reflection layer 212. However, the present application is not limited thereto, and in some variant embodiments, the front surface anti-reflection region 21 on the substrate front surface 201 can only include the anti-reflection layer 212.

[0054] Further, the battery 20 further includes a first polarity region S1 and a second polarity region S2 adjacent and spaced apart on the substrate back surface 202, wherein the first polarity region S1 includes a first passivation layer 221 and a first doped semiconductor layer 222, the second polarity region S2 includes a second passivation layer 231 and a second doped semiconductor layer 232 opposite in polarity to the first doped semiconductor layer 222, and the second passivation layer 231 includes intrinsic amorphous silicon, and the second doped semiconductor layer 232 includes amorphous silicon and / or doped microcrystalline silicon. As can be seen from FIG. 2, the substrate front surface 201 of the battery 20 in this embodiment is a textured surface, and the area on the substrate back surface 202 where the second polarity region S2 is located is a polished surface. Since the intrinsic amorphous silicon heterojunction passivation region in the second polarity region S2 of the battery 20 is prepared on the polished surface, the interface defects and carrier recombination in the back surface region of the battery 20 can be reduced, and the overall photoelectric conversion efficiency of the battery 20 can be improved.

[0055] Further specifically, in the present embodiment, the region of the substrate back surface 202 where the first polarity region S1 is located is also a polished surface, wherein the first passivation layer 221 comprises a tunneling oxide, and the first doped semiconductor layer 222 comprises doped polysilicon. Preferably, along the first direction Z perpendicular to the silicon substrate 200, each functional layer has a thickness in the following range: the first passivation layer 221 is 0.5 nm to 2 nm; and / or the first doped semiconductor layer 222 is 10 nm to 250 nm; and / or the second passivation layer 231 is 5 nm to 25 nm; and / or the second doped semiconductor layer 232 is 5 nm to 60 nm. In addition, on the substrate front surface 201, the aluminum oxide layer 211 and the anti-reflective layer 212 also each have the following preferred thickness range along the first direction Z: the aluminum oxide layer 211 is 3 nm to 20 nm; and / or the anti-reflective layer 212 is 30 nm to 90 nm. Preferably, the thickness of the anti-reflective layer 212 in the present embodiment has a further range of 65 nm to 85 nm. On this basis, whether the thickness of the anti-reflective layer 212 is in the larger range of 30 nm to 90 nm, or in the range of 65 nm to 85 nm, the anti-reflective layer 212 included in a preferred embodiment of the present application is obtained after thinning the initial deposition thickness by 5 nm to 35 nm, or by 10% to 87.5%, preferably by 10% to 50%, in the preparation process of the cell 20. This will be further described below.

[0056] For the cell 20, in the present embodiment, the region of the substrate back surface 202 where the second polarity region S2 is located is a polished surface prepared by protecting the substrate front surface 201 side by the front anti-reflective region 21. The following will take the preparation of FIG. 2 using the method 10 shown in FIG. 1 and its preferred variant embodiments as an example to describe the details of the method 10 and some preferred detail preparation methods.

[0057] Firstly, in combination with FIG. 1 and FIG. 2, step 101 is specifically implemented as obtaining a silicon substrate 200, which has opposite substrate front surface 201 and substrate back surface 202, wherein the substrate front surface 201 is closer to the light-receiving surface of the cell 20 than the substrate back surface 202. Step 102 is polishing the silicon substrate 200 on both sides. Step 103 is preparing a first polarity stack (including a substrate doped layer 220, a first passivation layer 221 and a first doped polysilicon layer 222, etc.) on the substrate back surface 202 side of the polished silicon substrate 200. Step 104 is removing part of the first polarity stack to expose a plurality of first opening regions O1 of the substrate back surface 202, and obtaining a first cell intermediate piece, wherein the first opening regions O1 are used to prepare a second polarity region S2, and the regions of the substrate back surface 202 outside the first opening regions O1 are used to prepare a first polarity region S1. Step 105 is texturing the first cell intermediate piece on both sides. Step 106 is preparing a front surface anti-reflection region 21 on the substrate front surface 201 side of the textured first cell intermediate piece, to obtain a second cell intermediate piece. Step 107 is polishing the second cell intermediate piece on both sides by means of the protection of the substrate front surface 201 side by the front surface anti-reflection region 21, to obtain a third cell intermediate piece. Step 108 is preparing a second polarity stack (including a second passivation layer 231 and a second doped semiconductor layer 232, etc.) on the substrate back surface 202 side of the third cell intermediate piece, the polarity of the second polarity stack is opposite to that of the first polarity stack, and the second polarity stack at least covers the plurality of first opening regions O1 on the substrate back surface 202.

[0058] Further preferably, the above-mentioned step 103 can be further implemented as preparing a first passivation layer 221 and a first doped semiconductor layer 221 with the same or opposite doping type as the silicon substrate 200 on the substrate back surface 202 side, and the first doped semiconductor layer 221 includes polysilicon. Preferably, the steps of preparing the first passivation layer and the first doped semiconductor layer in the present application include: preparing a tunneling oxide layer (i.e. the first passivation layer 221) and an intrinsic amorphous silicon layer or a polysilicon layer by low-pressure chemical vapor deposition, and then performing high-temperature diffusion doping and crystallization (i.e. obtaining the first doped semiconductor layer 222); or preparing a tunneling oxide layer (i.e. the first passivation layer 221) and an in-situ doped intrinsic amorphous silicon layer or a polysilicon layer by plasma-enhanced chemical vapor deposition, and then performing high-temperature annealing crystallization (i.e. obtaining the first doped semiconductor layer 222).

[0059] According to FIG. 2, the silicon substrate 200 further has a substrate doped layer 220 on the substrate back surface 202 side, and in the above-mentioned method, when step 103 is implemented, it further includes forming the substrate doped layer 220 on the substrate back surface 202 side of the silicon substrate 200 at the same time as preparing the first passivation layer 221 and the first doped semiconductor layer 222.

[0060] Further, Fig. 2 shows that the back side 202 of the substrate further has an insulating layer 224. The step of preparing the first polarity stack on the back side 202 of the silicon substrate 200 can further include a step of preparing the insulating layer 224, which includes at least one or more of phosphor-silicate glass, boron-silicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0061] In combination with Fig. 1 and Fig. 2, the step of removing part of the first polarity stack to expose the plurality of first opening regions O1 of the back side 202 of the substrate in step 104 includes removing part of the first polarity stack by means of laser, printing mask layer, and / or alkaline polishing etching. In the step of removing the first polarity stack, preferably, the method 10 can be further implemented to simultaneously remove one or more layers of material having the same material as the first polarity stack deposited on the front side 201 of the substrate and / or plated around the edge of the silicon substrate 200 while removing part of the first polarity stack. Further specifically, in the embodiment shown in Fig. 2, part of the insulating layer 224, or the insulating layer 224 and part of the first doped semiconductor layer 222 corresponding to the second polarity region S2 of the back side 202 of the substrate can be removed by means of laser or printing mask layer first. Then, the first doped semiconductor layer 222, the first passivation layer 221, and the substrate doped layer 220 corresponding to the second polarity region S2 of the back side 202 of the substrate can be removed by means of alkaline polishing etching, which further includes simultaneously removing the first doped semiconductor layer 222, the first passivation layer 221, and the insulating layer 224 deposited on the front side 201 of the substrate and / or plated around the edge of the silicon substrate 200.

[0062] Referring back to Fig. 1, the step of preparing the second polarity stack on the back side 202 of the substrate of the third cell intermediate in step 108 includes preparing a second passivation layer 231 and a second doped semiconductor layer 232, wherein the second passivation layer 231 includes intrinsic amorphous silicon, and the second doped semiconductor layer 232 includes amorphous silicon and / or doped microcrystalline silicon. Further preferably, the second passivation layer 231 and the second doped semiconductor layer 232 are prepared on the back side 202 of the substrate of the third cell intermediate in an integral manner, and part of the second passivation layer 231 and the second doped semiconductor layer 232 are removed in regions corresponding to the first polarity region S1 to expose the plurality of second opening regions O2 of the first polarity stack and obtain a fourth cell intermediate. Through this step, in the finally prepared cell 20, it can be seen that, in the first polarity region S1, there is part of the second polarity stack extending from the second polarity region S2 to the first polarity region S1.

[0063] It should be noted that the present application does not limit the doping type of the silicon substrate 200, the first doped semiconductor layer 222 and the second doped semiconductor layer 232, for example, the doping type of the silicon substrate 200 can be N-type or P-type, and the doping type of the first doped semiconductor layer 222 and the second doped semiconductor layer 232 can also be N-type or P-type respectively, and the doping type between the first doped semiconductor layer 222 and the second doped semiconductor layer 232 is different. In a preferred embodiment of the present application, the silicon substrate 200 is provided with N-type doping, the first doped semiconductor layer 222 is provided with N-type doping, and the second doped semiconductor layer 232 is provided with P-type doping, which can be considered as having a more optimal battery structure.

[0064] Further, in the battery 20 shown in FIG. 2, the side of the substrate back surface 202 also has a conductive layer 24. After implementing the above-mentioned step 108, the method 10 can be further implemented to prepare a conductive layer 24 on the entire side of the substrate back surface 202 of the fourth battery intermediate part. The conductive layer 24 includes zinc oxide, indium oxide, tin oxide, or a transparent conductive oxide doped with one or more elements of zinc, indium, and tin. For example, the thickness of the conductive layer 24 along the first direction Z can be set to 10-150 nm. The preparation method of the conductive layer 24 includes physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0065] Continuing to refer to FIG. 2, the battery 20 further includes a plurality of first electrodes 251 and second electrodes 252. The above-mentioned method 10 prepares electrodes including the first electrodes 251 and the second electrodes 252 on the conductive layer 24 of the second opening area O2 on the basis of preparing the conductive layer 24. For example, the preparation method of the first electrodes 251 and the second electrodes 252 includes screen printing silver paste, inkjet printing silver paste, and electroplating.

[0066] Further preferably, the method 10 can be further implemented to include a region of the second polarity stack in the region corresponding to the first polarity region S1, and further remove part of the second polarity stack to expose a plurality of third opening regions O3 of the first polarity stack. In this way, the second polarity region S2 and the first polarity region S1 can be insulated. For example, the preparation method of the third opening region O3 includes laser etching or ink printing mask, and is matched with wet chemical etching.

[0067] On the basis of the above description, in the present embodiment, the step 106 shown in FIG. 1 preferably specifically includes: depositing an anti-reflection layer 212, the deposition thickness of the anti-reflection layer 212 along the first direction Z is 40-100 nm, and the anti-reflection layer 212 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. For example, the anti-reflection layer 212 can be deposited by PECVD in CVD.

[0068] On this basis, the step 107 shown in FIG. 1 for double-side polishing the second battery intermediate workpiece by means of the front-side anti-reflection region of the substrate front side specifically includes: while polishing the substrate back side 202 of the second battery intermediate workpiece, the thickness of the anti-reflection layer 212 is thinned by 10 nm-35 nm, preferably by 10 nm-20 nm from the initial deposition thickness, and finally reaches a thickness range of 30 nm-90 nm, preferably a range of 65 nm-85 nm. On the other hand, in some embodiments, by controlling the polishing process, the anti-reflection layer 212 is thinned by 10%-87.5% from the initial deposition thickness, preferably by 10%-50%, to obtain a thickness range of 30 nm-90 nm or 65 nm-85 nm. By controlling the thickness change of the front-side anti-reflection layer 212 when double-side polishing is performed in this step 107, the thickness of the front-side anti-reflection layer 212 can be thinned to the ideal thickness range from the initial deposition thickness, while the back side is polished to form the area where the second polarity stack region to be prepared later.

[0069] According to FIG. 2, in the front-side anti-reflection region 21 of the substrate front side 201, there is also an aluminum oxide layer 211 between the substrate front side 201 and the anti-reflection layer 212. The step 107 can be further implemented as depositing the aluminum oxide layer 211 before depositing the anti-reflection layer 212, and the thickness of the aluminum oxide layer 211 along the first direction Z is 3 nm-20 nm. Exemplarily, the step of depositing the aluminum oxide layer 211 includes atomic layer deposition ALD.

[0070] The above method 10 of the present application and the battery 20 prepared thereby, the front side uses AlOx / SiNx passivation to achieve front-side optical lossless, and the silicon substrate 200 does not generate diffusion-induced recombination centers. At the same time in the preparation process, the front-side SiNx anti-reflection layer can be used as a front-side protective layer in the process to achieve a back-side full-polishing structure, further reducing the interface defects and carrier recombination of the back-side heterojunction passivation region, and the superposition of the front-side and back-side structures can further improve the photoelectric conversion efficiency of the HBC battery. Compared with the battery structure in the related art, the efficiency of the battery 20 in the present application is increased by 0.25-0.3%.

[0071] The above description has described the basic concepts. Obviously, for those skilled in the art, the above application disclosure is only used as an example, and does not constitute a limitation on the present application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the present application. Such modifications, improvements and corrections are suggested in the present application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present application.

[0072] Also, the use of "a" or "an" to describe an item or feature of the application should be understood to refer to one or more of the items specified, unless otherwise indicated. As such, "a" or "an" should be understood to mean "at least one", "one or more" or "one or more than one". Also, the use of "another" to describe an item or feature of the application should be understood to refer to one or more of the items specified, unless otherwise indicated.

[0073] It should also be noted that, as used in the specification and the claims, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As such, the terms "comprises", "comprising", "includes", "including" and the like, means "including but not limited to". Additionally, the terms "coupled", "coupling" and the like, mean to be directly or indirectly connected, and are not necessarily limited to a direct connection.

[0074] Some embodiments use numerical designations to describe components, quantities of attributes. It should be understood that such numerical designations used in the description of embodiments are, in some examples, modified by the adjectives "about", "approximately", or "generally". Unless otherwise indicated, "about", "approximately" or "generally" means that the number in question is allowed to vary by ±20%. Accordingly, numerical values used in the specification and claims are approximations which can vary depending on the desired properties sought to be obtained by the individual embodiment. In some embodiments, numerical values are determined by the number of significant figures used by the skilled artisan to describe the quantity in question. Although the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, can contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0075] While the application has been described with reference to the currently preferred embodiments, those skilled in the art will recognize that changes can be made within the spirit of the application, and it is intended to include all changes coming within the scope of the appended claims.

Claims

1. A method of manufacturing a back contact cell, the cell back surface of which has first and second polarity regions arranged in adjacent spaced-apart rows, characterised in that, The preparation method comprises the following steps: obtaining a silicon substrate having opposite substrate front and substrate back surfaces, wherein the substrate front surface is closer to the light-receiving surface of the cell than the substrate back surface; double-side polishing the silicon substrate; preparing a first polarity stack on the substrate back surface side of the polished silicon substrate; removing part of the first polarity stack to expose a plurality of first opening regions of the substrate back surface and obtain a first cell intermediate, wherein the first opening regions are used for preparing the second polarity region and the regions of the substrate back surface outside the first opening regions are used for preparing the first polarity region; double-side texturing the first cell intermediate; preparing a front surface anti-reflection region on the substrate front surface side of the textured first cell intermediate to obtain a second cell intermediate; double-side polishing the second cell intermediate by means of the front surface anti-reflection region on the substrate front surface side to obtain a third cell intermediate; and preparing a second polarity stack on the substrate back surface side of the third cell intermediate, the polarity of the second polarity stack being opposite to that of the first polarity stack, and the second polarity stack covering at least the plurality of first opening regions on the substrate back surface.

2. The production method according to claim 1, wherein The step of preparing a first polarity stack on the substrate back surface side of the polished silicon substrate comprises preparing a first passivation layer and a first doped semiconductor layer having the same or opposite doping type as the silicon substrate on the substrate back surface side, and the first doped semiconductor layer comprises polysilicon.

3. The production method according to claim 2, wherein The steps of preparing the first passivation layer and the first doped semiconductor layer comprise: preparing a tunneling oxide layer by low-pressure chemical vapor deposition to obtain the first passivation layer, and preparing an intrinsic amorphous silicon layer or a polysilicon layer and then performing high-temperature diffusion doping and crystallization to obtain the first doped semiconductor layer; or preparing a tunneling oxide layer by plasma-enhanced chemical vapor deposition to obtain the first passivation layer, and preparing an in-situ doped intrinsic amorphous silicon layer or a polysilicon layer and then performing high-temperature annealing crystallization to obtain the first doped semiconductor layer.

4. The production method according to claim 3, wherein It also comprises forming a substrate doping layer on the substrate back surface side of the silicon substrate at the same time as preparing the first passivation layer and the first doped semiconductor layer.

5. The production method according to claim 2, wherein The step of preparing a first polarity stack on the substrate back surface of the silicon substrate further comprises preparing an insulating layer comprising at least one or more of phosphosilicate glass, borosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

6. The production method according to claim 1, wherein The step of removing part of the first polarity stack to expose a plurality of first opening regions of the substrate back surface comprises removing part of the first polarity stack by means of laser, printing mask layer, and / or alkaline polishing etching.

7. The production method according to claim 6, wherein It also comprises synchronously removing one or more material layers having the same material as the first polarity stack deposited on the substrate front surface and / or plated around the edges of the silicon substrate side at the same time as removing part of the first polarity stack.

8. The production method according to claim 1, wherein The step of preparing the second polarity stack on the substrate back side of the third cell intermediate includes: preparing a second passivation layer and a second doped semiconductor layer with the same or opposite doping type of the silicon substrate, and the second passivation layer includes intrinsic amorphous silicon, and the second doped semiconductor layer includes amorphous silicon and / or doped microcrystalline silicon.

9. The production method according to claim 8, wherein Further comprising: The second passivation layer and the second doped semiconductor layer are prepared on the substrate back side of the third cell intermediate; And The second passivation layer and the second doped semiconductor layer are removed in the region corresponding to the first polarity region to expose a plurality of second opening regions of the first polarity stack and obtain a fourth cell intermediate.

10. The production method according to claim 9, wherein Further comprising: The conductive layer includes zinc oxide, indium oxide, tin oxide, or transparent conductive oxide doped with one or more of zinc, indium, and tin.

11. The production method according to claim 10, wherein Further comprising: The electrode is prepared on the conductive layer of the second opening region.

12. The production method according to claim 9, wherein Further comprising: The second polarity stack in the region corresponding to the first polarity region is further removed to expose a plurality of third opening regions of the first polarity stack.

13. The production method according to any one of claims 1 to 12, wherein The step of preparing the front surface anti-reflection region on the substrate front side of the first cell intermediate after texturing includes: depositing an anti-reflection layer with a deposition thickness of 40-100 nm along a first direction perpendicular to the silicon substrate, and the anti-reflection layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

14. The production method according to claim 13, wherein The step of double-side polishing the second cell intermediate with the protection of the front surface anti-reflection region on the substrate front side includes: thinning the thickness of the anti-reflection layer by 10-35 nm from the deposition thickness while polishing the substrate back side of the second cell intermediate, and the thickness of the thinned anti-reflection layer is 30-90 nm.

15. The production method according to claim 13, wherein The step of double-side polishing the second cell intermediate with the protection of the front surface anti-reflection region on the substrate front side includes: thinning the thickness of the anti-reflection layer by 10%-87.5% from the deposition thickness while polishing the substrate back side of the second cell intermediate.

16. The production method according to claim 13, wherein The step of preparing the front surface anti-reflection region on the substrate front side of the first cell intermediate after texturing further includes: depositing an aluminum oxide layer with a thickness of 3-20 nm along the first direction before depositing the anti-reflection layer.

17. A back contact cell characterized in that, The cell is prepared according to the preparation method of any one of claims 1-16.

18. A back contact cell characterized by, Comprising: a silicon substrate having opposite substrate front and substrate back sides, wherein the substrate front side is closer to the light-receiving surface of the cell than the substrate back side; a front surface anti-reflection region on the substrate front side, the front surface anti-reflection region including an anti-reflection layer; The first and second polarity regions are arranged in adjacent intervals on the back surface of the substrate, wherein the first polarity region comprises a first passivation layer and a first doped semiconductor layer, the second polarity region comprises a second passivation layer and a second doped semiconductor layer opposite in polarity to the first doped semiconductor layer, and the second passivation layer comprises intrinsic amorphous silicon, and the second doped semiconductor layer comprises amorphous silicon and / or doped microcrystalline silicon, The front surface of the substrate is a textured surface, and the area on the back surface of the substrate where the second polarity region is located is a polished surface.

19. The back contact cell of claim 18, wherein, The area on the back surface of the substrate where the second polarity region is located is a polished surface, which is prepared by protection of the front surface of the substrate by the front anti-reflective region.

20. The back contact cell of claim 18 or 19, wherein, The area on the back surface of the substrate where the first polarity region is located is a polished surface, wherein The first passivation layer comprises a tunneling oxide, and the thickness of the first passivation layer along a first direction perpendicular to the silicon substrate is 0.5-2 nm; and / or The first doped semiconductor layer comprises doped polysilicon, and the thickness of the first doped semiconductor layer along the first direction is 10-250 nm; and / or The thickness of the second passivation layer is 5-25 nm; and / or The thickness of the second doped semiconductor layer is 5-60 nm.

21. The back contact cell of claim 18 or 19, wherein, The front anti-reflective region further comprises an aluminum oxide layer between the front surface of the substrate and the anti-reflective layer, wherein The thickness of the aluminum oxide layer along a first direction perpendicular to the silicon substrate is 3-20 nm; and / or The anti-reflective layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the thickness of the anti-reflective layer along the first direction is 30-90 nm.

22. The back contact cell of claim 21, wherein, The thickness of the anti-reflective layer along the first direction is obtained by thinning a deposition thickness by 5-35 nm, or by 10%-87.5% in the preparation process.

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