Pixel circuit, pixel driving method, and display device

Abstract

The present disclosure provides a pixel circuit, a pixel driving method, and a display device. The pixel circuit comprises a driving circuit, a first energy storage circuit, a second energy storage circuit, a data writing circuit and a compensation control circuit. A display period of the pixel circuit comprises a compensation stage and a writing stage which are independent of each other. In the writing stage, the data writing circuit writes a data voltage into a first node under the control of a writing control signal. In the compensation stage, under the control of a compensation control signal, the compensation control circuit controls the first node to be connected to a third node. When the pixel circuit of the present disclosure works, the compensation stage and the writing stage are independent of each other; in the writing stage, the data writing circuit performs data voltage writing; in the compensation stage, the compensation control circuit performs threshold voltage compensation, so that threshold voltage compensation is no longer limited by periodic time; and threshold voltage compensation and data writing are separated from each other, thereby achieving high-frequency driving display.

Description

Pixel circuit, pixel driving method and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410654738.3, filed on May 24, 2024 in China, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0004] With the rapid development of AMOLED (Active-matrix organic light-emitting diode), medium and large size tablets and notebooks become important development directions in the future. Customers have increasingly strong demand for high-frequency display. The existing pixel circuit simultaneously performs threshold voltage compensation and data voltage writing. High-frequency technology causes one row time compression, which cannot well compensate the threshold voltage of the driving transistor in the driving circuit, and cannot realize high-frequency driving. SUMMARY

[0005] The main purpose of the present disclosure is to provide a pixel circuit, a pixel driving method and a display device, which solve the problem that the related pixel circuit simultaneously performs threshold voltage compensation and data voltage writing, high-frequency technology causes one row time compression, which cannot well compensate the threshold voltage of the driving transistor in the driving circuit, and cannot realize high-frequency driving.

[0006] In one aspect, the embodiments of the present disclosure provide a pixel circuit, comprising a driving circuit, a first energy storage circuit, a second energy storage circuit, a data writing circuit and a compensation control circuit; a display period of the pixel circuit comprises a compensation phase and a writing phase which are independent of each other;

[0007] The control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second node, and the second end of the driving circuit is electrically connected with a third node; the driving circuit is used for generating a driving current under the control of the potential of the first node;

[0008] The first end of the first energy storage circuit is electrically connected with the first node, and the second end of the first energy storage circuit is electrically connected with the second node; the first energy storage circuit is used for storing electric energy;

[0009] The second energy storage circuit is electrically connected with the second node, and is used for maintaining the potential of the second node;

[0010] The data writing circuit is electrically connected with a writing control end, a data line and the first node respectively, and is configured to write a data voltage provided by the data line to the first node under control of a writing control signal provided by the writing control end in a writing stage.

[0011] The compensation control circuit is electrically connected with a compensation control end, the first node and the third node respectively, and is configured to control the first node and the third node to be in communication under control of a compensation control signal provided by the compensation control end in the compensation stage.

[0012] Optionally, the pixel circuit further comprises a first initialization circuit.

[0013] The first initialization circuit is electrically connected with the compensation control end, a first initial voltage end and the first node respectively, and is configured to control the first initial voltage end and the first node to be in communication or disconnected under control of the compensation control signal.

[0014] Optionally, the pixel circuit further comprises a second initialization circuit.

[0015] The second initialization circuit is electrically connected with a reset control end, a second initial voltage end and the second node respectively, and is configured to control the second initial voltage end and the second node to be in communication or disconnected under control of a reset control signal provided by the reset control end.

[0016] Optionally, the pixel circuit further comprises a first light-emitting control circuit, a second light-emitting control circuit and a light-emitting element.

[0017] The first light-emitting control circuit is electrically connected with a light-emitting control end, a power voltage end and the second node respectively, and is configured to control the power voltage end and the second node to be in communication or disconnected under control of a light-emitting control signal provided by the light-emitting control end.

[0018] The second light-emitting control circuit is electrically connected with the light-emitting control end, the third node and a first pole of the light-emitting element respectively, and is configured to control the third node and the first pole of the light-emitting element to be in communication or disconnected under control of the light-emitting control signal.

[0019] A second pole of the light-emitting element is electrically connected with a first voltage end.

[0020] Optionally, the pixel circuit further comprises a third initialization circuit.

[0021] The third initialization circuit is electrically connected with the reset control end, the third initial voltage end and the first pole of the light emitting element respectively, and is used for controlling the connection or disconnection between the third initial voltage end and the first pole of the light emitting element under the control of the reset control signal provided by the reset control end.

[0022] Optionally, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor.

[0023] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the second node.

[0024] The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the direct current voltage end.

[0025] Optionally, the driving circuit comprises a driving transistor, the data writing circuit comprises a first transistor, and the compensation control circuit comprises a second transistor.

[0026] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node.

[0027] The gate of the first transistor is electrically connected with the writing control end, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with the first node.

[0028] The gate of the second transistor is electrically connected with the compensation control end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the third node.

[0029] Optionally, the first initialization circuit comprises a third transistor.

[0030] The gate of the third transistor is electrically connected with the compensation control end, the first pole of the third transistor is electrically connected with the first initial voltage end, and the second pole of the third transistor is electrically connected with the first node.

[0031] Optionally, the second initialization circuit comprises a fourth transistor.

[0032] The gate of the fourth transistor is electrically connected with the reset control end, the first pole of the fourth transistor is electrically connected with the second initial voltage end, and the second pole of the fourth transistor is electrically connected with the second node.

[0033] Optionally, the first light emitting control circuit comprises a fifth transistor and a sixth transistor.

[0034] A gate of the fifth transistor is electrically connected with the light-emitting control end, a first electrode of the fifth transistor is electrically connected with the power voltage end, and a second electrode of the fifth transistor is electrically connected with the second node.

[0035] A gate of the sixth transistor is electrically connected with the light-emitting control end, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the first electrode of the light-emitting element.

[0036] Optionally, the third initialization circuit includes a seventh transistor.

[0037] A gate of the seventh transistor is electrically connected with the reset control end, a first electrode of the seventh transistor is electrically connected with the third initial voltage end, and a second electrode of the seventh transistor is electrically connected with the first electrode of the light-emitting element.

[0038] Optionally, the third transistor is an oxide transistor.

[0039] Optionally, the first transistor and the second transistor are oxide transistors.

[0040] In a second aspect, the pixel driving method is applied to the pixel circuit, and a display period of the pixel circuit includes a compensation phase and a writing phase which are independent of each other; and the pixel driving method includes the following steps.

[0041] In the compensation phase, the compensation control circuit controls the communication between the first node and the third node under the control of a compensation control signal.

[0042] In the writing phase, the data writing circuit writes the data voltage provided by the data line into the first node under the control of a writing control signal.

[0043] In a third aspect, the display device includes the pixel circuit.

[0044] The pixel circuit in the display device is independent of each other in the compensation phase and the writing phase, the data writing circuit writes the data voltage in the writing phase, and the compensation control circuit compensates the threshold voltage in the compensation phase, so that the threshold voltage compensation is no longer limited by the period time, the threshold voltage compensation and the data writing are separated from each other, and high-frequency driving display is realized. BRIEF DESCRIPTION OF DRAWINGS

[0045] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0046] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0047] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0048] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0050] FIG. 6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0051] FIG. 7 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6;

[0052] FIG. 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0053] FIG. 9 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0055] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0056] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0057] As shown in FIG. 1, the pixel circuit according to the embodiments of the present disclosure includes a driving circuit 10, a first energy storage circuit 11, a second energy storage circuit 12, a data writing circuit 13 and a compensation control circuit 14; the display period of the pixel circuit includes a compensation phase and a writing phase which are independent of each other;

[0058] The control end of the driving circuit 10 is electrically connected with a first node N1, the first end of the driving circuit 10 is electrically connected with a second node N2, the second end of the driving circuit 10 is electrically connected with a third node N3, and the driving circuit is used to generate a driving current under the control of the potential of the first node N1;

[0059] The first energy storage circuit 11 is electrically connected with the first node N1, and the second end of the first energy storage circuit 11 is electrically connected with the second node N2, and the first energy storage circuit 11 is used for storing electric energy.

[0060] The second energy storage circuit 12 is electrically connected with the second node N2, and is used for maintaining the electric potential of the second node N2.

[0061] The data writing circuit 13 is electrically connected with a writing control end GW, a data line DL and the first node N1 respectively, and is used for writing, in a writing stage, a data voltage provided by the data line DL into the first node N1 under the control of a writing control signal provided by the writing control end GW.

[0062] The compensation control circuit 14 is electrically connected with a compensation control end GI, the first node N1 and the third node N3 respectively, and is used for controlling the communication between the first node N1 and the third node N3 under the control of a compensation control signal provided by the compensation control end GI in the compensation stage.

[0063] In at least one embodiment of the present disclosure, the data writing circuit 13 is directly electrically connected with N1.

[0064] At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, when working, the display period of the pixel circuit includes a compensation stage and a writing stage which are independent of each other;

[0065] In the compensation stage, the compensation control circuit 14 controls the communication between the first node N1 and the third node N3 under the control of the compensation control signal.

[0066] In the writing stage, the data writing circuit 13 directly writes the data voltage provided by the data line DL into the first node N1 under the control of the writing control signal.

[0067] At least one embodiment of the pixel circuit of the present disclosure, when working, the compensation stage and the writing stage are independent of each other, in the writing stage, the data writing circuit performs data voltage writing, and directly writes the data voltage into the first node; in the compensation stage, the compensation control circuit performs threshold voltage compensation, so that the threshold voltage compensation is no longer limited by the period time, the threshold voltage compensation and the data writing are separated from each other, and high-frequency driving display is realized.

[0068] At least one embodiment of the pixel circuit of the present disclosure further includes a first initialization circuit.

[0069] The first initialization circuit is electrically connected with the compensation control end, a first initial voltage end and the first node respectively, and is used for controlling the communication or disconnection between the first initial voltage end and the first node under the control of the compensation control signal.

[0070] In specific implementation, the pixel circuit further includes a first initialization circuit configured to write a first initial voltage into the first node under control of a compensation control signal, so as to reset the potential of the first node.

[0071] As shown in FIG. 2, based on at least one embodiment of the pixel circuit shown in FIG. 1, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 21.

[0072] The first initialization circuit 21 is electrically connected with the compensation control terminal GI, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to control the first initial voltage terminal I1 and the first node N1 to be in communication or disconnected under control of a compensation control signal.

[0073] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit.

[0074] The second initialization circuit is electrically connected with a reset control terminal, a second initial voltage terminal and the second node respectively, and is configured to control the second initial voltage terminal and the second node to be in communication or disconnected under control of a reset control signal provided by the reset control terminal.

[0075] In specific implementation, the pixel circuit can further include a second initialization circuit configured to write a second initial voltage provided by the second initial voltage terminal into the second node under control of a reset control signal, so as to reset the potential of the second node.

[0076] As shown in FIG. 3, based on at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 31.

[0077] The second initialization circuit 31 is electrically connected with a reset control terminal GC, a second initial voltage terminal I2 and the second node N2 respectively, and is configured to control the second initial voltage terminal I2 and the second node N2 to be in communication or disconnected under control of a reset control signal provided by the reset control terminal GC.

[0078] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit and a light-emitting element.

[0079] The first light-emitting control circuit is electrically connected with a light-emitting control terminal, a power voltage terminal and the second node respectively, and is configured to control the power voltage terminal and the second node to be in communication or disconnected under control of a light-emitting control signal provided by the light-emitting control terminal.

[0080] The second light-emitting control circuit is electrically connected with the light-emitting control end, the third node and the first electrode of the light-emitting element respectively, and is used for controlling the communication or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal.

[0081] The second electrode of the light-emitting element is electrically connected with the first voltage end.

[0082] In specific implementation, the pixel circuit can further include a first light-emitting control circuit and a second light-emitting control circuit, and the first light-emitting control circuit and the second light-emitting control circuit can perform light-emitting control.

[0083] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 41, a second light-emitting control circuit 42 and a light-emitting element E1.

[0084] The first light-emitting control circuit 1 is electrically connected with the light-emitting control end EM, the power voltage end ELVDD and the second node N2 respectively, and is used for controlling the communication or disconnection between the power voltage end ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control end EM.

[0085] The second light-emitting control circuit 42 is electrically connected with the light-emitting control end EM, the third node N3 and the first electrode of the light-emitting element E1 respectively, and is used for controlling the communication or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the light-emitting control signal.

[0086] The second electrode of the light-emitting element E1 is electrically connected with the first voltage end V1.

[0087] The pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit.

[0088] The third initialization circuit is electrically connected with a reset control end, a third initial voltage end and the first electrode of the light-emitting element respectively, and is used for controlling the communication or disconnection between the third initial voltage end and the first electrode of the light-emitting element under the control of a reset control signal provided by the reset control end.

[0089] In specific implementation, the pixel circuit can further include a third initialization circuit, and the third initialization circuit writes a third initial voltage provided by a third initial voltage end to the first electrode of the light-emitting element under the control of a reset control signal, so as to clear the residual charges of the first electrode of the light-emitting element.

[0090] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 51.

[0091] The third initialization circuit 51 is electrically connected with the reset control end GC, the third initial voltage end I3 and the first electrode of the light emitting element E1, for controlling the connection or disconnection between the third initial voltage end I3 and the first electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control end GC.

[0092] Optionally, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor.

[0093] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the second node.

[0094] The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the direct current voltage end.

[0095] Optionally, the direct current voltage end can be a power voltage end.

[0096] Optionally, the driving circuit comprises a driving transistor, the data writing circuit comprises a first transistor, and the compensation control circuit comprises a second transistor.

[0097] The gate of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node.

[0098] The gate of the first transistor is electrically connected with the writing control end, the first electrode of the first transistor is electrically connected with the data line, and the second electrode of the first transistor is electrically connected with the first node.

[0099] The gate of the second transistor is electrically connected with the compensation control end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node.

[0100] Optionally, the first initialization circuit comprises a third transistor.

[0101] The gate of the third transistor is electrically connected with the compensation control end, the first electrode of the third transistor is electrically connected with the first initial voltage end, and the second electrode of the third transistor is electrically connected with the first node.

[0102] Optionally, the second initialization circuit comprises a fourth transistor.

[0103] The gate of the fourth transistor is electrically connected with the reset control end, the first electrode of the fourth transistor is electrically connected with the second initial voltage end, and the second electrode of the fourth transistor is electrically connected with the second node.

[0104] Optionally, the first light-emitting control circuit comprises a fifth transistor and a sixth transistor.

[0105] The gate of the fifth transistor is electrically connected with the light-emitting control end, the first pole of the fifth transistor is electrically connected with the power voltage end, and the second pole of the fifth transistor is electrically connected with the second node.

[0106] The gate of the sixth transistor is electrically connected with the light-emitting control end, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element.

[0107] Optionally, the third initialization circuit comprises a seventh transistor.

[0108] The gate of the seventh transistor is electrically connected with the reset control end, the first pole of the seventh transistor is electrically connected with the third initial voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

[0109] In at least one embodiment of the present disclosure, the third transistor is an oxide transistor.

[0110] In at least one embodiment of the present disclosure, the first transistor and the second transistor are oxide transistors.

[0111] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the first energy storage circuit comprises a first capacitor C1, the second energy storage circuit comprises a second capacitor C2, and the light-emitting element is an organic light-emitting diode O1.

[0112] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the second node N2.

[0113] The first end of the second capacitor C2 is electrically connected with the second node N2, and the second end of the second capacitor C2 is electrically connected with the power voltage end ELVDD.

[0114] The driving circuit comprises a driving transistor DT, the data writing circuit comprises a first transistor T1, and the compensation control circuit comprises a second transistor T2.

[0115] The gate of the driving transistor DT is electrically connected with the first node N1, the source of the driving transistor DT is electrically connected with the second node N2, and the drain of the driving transistor DT is electrically connected with the third node N3.

[0116] The gate of the first transistor T1 is electrically connected with a write control end GW, the source of the first transistor T1 is electrically connected with a data line DL, and the drain of the first transistor T1 is electrically connected with the first node N1;

[0117] The gate of the second transistor T2 is electrically connected with a compensation control end GI, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the third node N3;

[0118] The first initialization circuit comprises a third transistor T3.

[0119] The gate of the third transistor T3 is electrically connected with the compensation control end GI, the source of the third transistor T3 is electrically connected with the first initial voltage end I1, and the drain of the third transistor T3 is electrically connected with the first node N1.

[0120] The second initialization circuit comprises a fourth transistor T4.

[0121] The gate of the fourth transistor T4 is electrically connected with the reset control end GC, the source of the fourth transistor T4 is electrically connected with the second initial voltage end I2, and the drain of the fourth transistor T4 is electrically connected with the second node N2.

[0122] The first light-emitting control circuit comprises a fifth transistor T5 and a sixth transistor T6.

[0123] The gate of the fifth transistor T5 is electrically connected with a light-emitting control end EM, the source of the fifth transistor T5 is electrically connected with a power voltage end ELVDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2.

[0124] The gate of the sixth transistor T6 is electrically connected with the light-emitting control end EM, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of the organic light-emitting diode O1. The cathode of O1 is electrically connected with a low voltage end ELVSS.

[0125] The third initialization circuit comprises a seventh transistor T7.

[0126] The gate of the seventh transistor T7 is electrically connected with the reset control end GC, the source of the seventh transistor T7 is electrically connected with the third initial voltage end I3, and the drain of the seventh transistor T7 is electrically connected with the anode of O1.

[0127] In at least one embodiment of the pixel circuit shown in FIG. 6, all the transistors are p-type transistors.

[0128] In at least one embodiment of the pixel circuit shown in FIG. 6, the drain of T1 is directly electrically connected with the first node N1.

[0129] FIG. 7 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6.

[0130] In at least one embodiment of the pixel circuit shown in FIG. 6, the voltage value of the first initial voltage Vinit1 provided by I1 is greater than or equal to 0V and less than or equal to 5V, the voltage value of the second initial voltage Vinit2 provided by I2 is greater than or equal to -5V and less than or equal to 0V, the voltage value of the third initial voltage Vinit3 provided by I3 is greater than or equal to 0V and less than or equal to 10V, the voltage value of the power voltage signal provided by ELVDD is greater than or equal to 0V and less than or equal to 5V, the voltage value of the low voltage signal provided by ELVSS is greater than or equal to -5V and less than or equal to 0V;

[0131] The capacitance value C1z of C1 can be greater than or equal to 50fF and less than or equal to 300fF, the capacitance value C1z of C2 can be greater than or equal to 50fF and less than or equal to 300fF, C2z / C1z is greater than or equal to 1 / 5 and less than or equal to 1.

[0132] As shown in FIG. 7, in the working of at least one embodiment of the pixel circuit shown in FIG. 6, the display period can include the reset stage S1, the compensation stage S2, the write stage S3 and the light-emitting stage S4 arranged in sequence;

[0133] In the reset stage S1, EM provides a high voltage signal, GW provides a high voltage signal, GC provides a low voltage signal, GI provides a high voltage signal, T4 is open, T7 is open, DT is open, I2 provides the second initial voltage Vinit2 to N2, I3 provides the third initial voltage Vinit3 to the anode of O1, and the residual charge of the anode of O1 is cleared; T3, T2, T1, T5 and T6 are all off;

[0134] In the compensation stage S2, GI provides a low voltage signal, T3 and T2 are open, I1 provides the first initial voltage Vinit1 to N1, and the potentials of N1 and N3 are both Vinit1;

[0135] At the beginning of the compensation stage S2, DT is open, C1 is charged by Vinit1, the potential of N2 is changed, until the potential of N2 becomes Vinit1-Vth, DT is off, and Vth is the threshold voltage of DT;

[0136] In the compensation stage S2, GC, GW and EM all provide high voltage signals, T1, T5, T6, T7 and T4 are all off;

[0137] In the write stage S3, the GW provides a low voltage signal, T1 is turned on, the DL provides a data voltage Vdata to N1, DT is in an on state, and the potential of N2 is equal to Vinit1-Vth-(C2z / (C1z+C2z))x(Vinit1-Vdata); wherein C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0138] In the write stage S3, the GI, GC and EM provide high voltage signals, T3, T2, T1, T5, T6, T7 and T4 are turned off.

[0139] In the light emitting stage S4, the EM provides a low voltage signal, T5 and T6 are turned on, the anode potential of O1 is Vo1+Vss, and the potential of N2 is Vdd; wherein Vss is the voltage value of the low voltage signal provided by ELVSS, Vdd is the voltage value of the power voltage signal provided by ELVDD, and Vo1 is the on voltage of O1; the potential of N1 is Vdata+Vdd-Vinit1+Vth+(C2z / (C1z+C2z))x(Vinit1-Vdata); at this time, the gate-source voltage Vgs of DT is equal to Vdata-Vinit1+Vth+(C2z / (C1z+C2z))x(Vinit1-Vdata), and Id is equal to Kx(Vdata-Vinit1+(C2z / (C1z+C2z))x(Vinit1-Vdata)) 2 ; wherein Id is the driving current generated by DT, and K is the current coefficient of DT.

[0140] The difference between at least one embodiment of the pixel circuit shown in FIG. 8 and at least one embodiment of the pixel circuit shown in FIG. 6 is as follows: T1, T2 and T3 are n-type transistors, and T1, T2 and T3 are all IGZO transistors.

[0141] In at least one embodiment of the pixel circuit shown in FIG. 8, the drain of T1 is directly electrically connected with the first node N1.

[0142] FIG. 9 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8.

[0143] In at least one embodiment of the pixel circuit shown in FIG. 8, T1, T2 and T3 can all be IGZO transistors, which prevents N1 from leaking through T1, T2 and T3 and improves the low-frequency Flicker phenomenon.

[0144] In at least one embodiment of the pixel circuit shown in FIG. 8, the first initial voltage Vinit1 provided by I1 has a voltage value greater than or equal to 0V and less than or equal to 5V, the second initial voltage Vinit2 provided by I2 has a voltage value greater than or equal to -5V and less than or equal to 0V, the third initial voltage Vinit3 provided by I3 has a voltage value greater than or equal to 0V and less than or equal to 10V, the power voltage signal provided by ELVDD has a voltage value greater than or equal to 0V and less than or equal to 5V, and the low voltage signal provided by ELVSS has a voltage value greater than or equal to -5V and less than or equal to 0V.

[0145] The capacitance value C1z of C1 can be greater than or equal to 50fF and less than or equal to 300fF, the capacitance value C1z of C2 can be greater than or equal to 50fF and less than or equal to 300fF, and C2z / C1z is greater than or equal to 1 / 5 and less than or equal to 1.

[0146] As shown in FIG. 9, in at least one embodiment of the pixel circuit shown in FIG. 8, during operation, the display period can include a reset stage S1, a compensation stage S2, a write stage S3 and an emission stage S4 arranged in sequence.

[0147] In the reset stage S1, EM provides a high voltage signal, GW provides a low voltage signal, GC provides a low voltage signal, GI provides a low voltage signal, T4 is open, T7 is open, DT is open, I2 provides the second initial voltage Vinit2 to N2 and N3, I3 provides the third initial voltage Vinit3 to the anode of O1, and the residual charge at the anode of O1 is cleared; T3, T2, T1, T5 and T6 are all off.

[0148] In the compensation stage S2, GI provides a high voltage signal, T3 and T2 are open, I1 provides the first initial voltage Vinit1 to N1, and the potentials of N1 and N3 are both Vinit1.

[0149] At the beginning of the compensation stage S2, DT is open, C1 is charged by Vinit1, the potential of N2 is changed, until the potential of N2 becomes Vinit1-Vth, and DT is off, where Vth is the threshold voltage of DT.

[0150] In the compensation stage S2, GC and EM both provide a high voltage signal, GW provides a low voltage signal, and T1, T5, T6, T7 and T4 are all off.

[0151] In the write stage S3, GW provides a high voltage signal, T1 is open, DL provides the data voltage Vdata to N1, and DT is in an open state, and the potential of N2 and the potential of N3 are equal to Vinit1-Vth-(C2z / (C1z+C2z))×(Vinit1-Vdata); where C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0152] In the write stage S3, the GI provides a low voltage signal, the GC and the EM provide a high voltage signal, T3, T2, T1, T5, T6, T7 and T4 are turned off;

[0153] In the light emitting stage S4, the EM provides a low voltage signal, T5 and T6 are turned on, the anode potential of O1 is Vo1+Vss, the potential of N2 is Vdd; wherein Vss is the voltage value of the low voltage signal provided by the ELVSS, Vdd is the voltage value of the power voltage signal provided by the ELVDD, Vo1 is the on voltage of O1; the potential of N1 is Vdata+Vdd-Vinit1+Vth+(C2z / (C1z+C2z))×(Vinit1-Vdata); at this time, the gate-source voltage Vgs of DT is equal to Vdata-Vinit1+Vth+(C2z / (C1z+C2z))×(Vinit1-Vdata), and Id is equal to K×(Vdata-Vinit1+(C2z / (C1z+C2z))×(Vinit1-Vdata)) 2 ; wherein Id is the driving current generated by DT, and K is the current coefficient of DT.

[0154] The pixel driving method provided in the embodiments of the present disclosure is applied to the pixel circuit described above, and a display period of the pixel circuit includes a compensation stage and a write stage which are independent of each other; the pixel driving method includes the following steps.

[0155] In the compensation stage, a compensation control circuit controls the communication between the first node and the third node under the control of a compensation control signal.

[0156] In the write stage, a data writing circuit writes a data voltage provided by a data line into the first node under the control of a write control signal.

[0157] In at least one embodiment of the present disclosure, in the write stage, the data writing circuit directly writes the data voltage into the first node under the control of the write control signal.

[0158] In the pixel driving method provided in at least one embodiment of the present disclosure, the compensation stage and the write stage are independent of each other, in the write stage, the data writing circuit performs data voltage writing, and in the compensation stage, the compensation control circuit performs threshold voltage compensation, so that the threshold voltage compensation is no longer limited by the period time, the threshold voltage compensation and the data writing are separated from each other, and high-frequency driving display is achieved.

[0159] The display device provided in the embodiments of the present disclosure includes the pixel circuit described above.

[0160] The above are preferred embodiments of the present disclosure, and it should be pointed out that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present disclosure, and these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a first energy storage circuit, a second energy storage circuit, a data writing circuit and a compensation control circuit; a display period of the pixel circuit comprises a compensation phase and a writing phase which are independent of each other; a control end of the driving circuit is electrically connected with a first node, a first end of the driving circuit is electrically connected with a second node, and a second end of the driving circuit is electrically connected with a third node; the driving circuit is used for generating a driving current under the control of an electric potential of the first node; a first end of the first energy storage circuit is electrically connected with the first node, and a second end of the first energy storage circuit is electrically connected with the second node; the first energy storage circuit is used for storing electric energy; the second energy storage circuit is electrically connected with the second node and is used for maintaining an electric potential of the second node; the data writing circuit is electrically connected with a writing control end, a data line and the first node respectively, and is used for writing a data voltage provided by the data line into the first node under the control of a writing control signal provided by the writing control end in the writing phase; the compensation control circuit is electrically connected with a compensation control end, the first node and the third node respectively, and is used for controlling the communication between the first node and the third node under the control of a compensation control signal provided by the compensation control end in the compensation phase.

2. The pixel circuit of claim 1, wherein, Further comprising a first initialization circuit; the first initialization circuit is electrically connected with the compensation control end, a first initial voltage end and the first node respectively, and is used for controlling the communication or disconnection between the first initial voltage end and the first node under the control of the compensation control signal.

3. The pixel circuit of claim 1, wherein, Further comprising a second initialization circuit; the second initialization circuit is electrically connected with a reset control end, a second initial voltage end and the second node respectively, and is used for controlling the communication or disconnection between the second initial voltage end and the second node under the control of a reset control signal provided by the reset control end.

4. The pixel circuit of claim 1, wherein, Further comprising a first light emitting control circuit, a second light emitting control circuit and a light emitting element; the first light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the second node respectively, and is used for controlling the communication or disconnection between the power voltage end and the second node under the control of a light emitting control signal provided by the light emitting control end; the second light emitting control circuit is electrically connected with the light emitting control end, the third node and a first pole of the light emitting element respectively, and is used for controlling the communication or disconnection between the third node and the first pole of the light emitting element under the control of the light emitting control signal; a second pole of the light emitting element is electrically connected with a first voltage end.

5. The pixel circuit of claim 4, wherein, Further comprising a third initialization circuit; the third initialization circuit is electrically connected with a reset control end, a third initial voltage end and the first pole of the light emitting element respectively, and is used for controlling the communication or disconnection between the third initial voltage end and the first pole of the light emitting element under the control of a reset control signal provided by the reset control end.

6. The pixel circuit of claim 1, wherein, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor. A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node. A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to a direct current voltage terminal.

7. The pixel circuit of claim 1, wherein, The driving circuit includes a driving transistor, the data writing circuit includes a first transistor, and the compensation control circuit includes a second transistor. A gate of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the second node, and a second electrode of the driving transistor is electrically connected to the third node. A gate of the first transistor is electrically connected to a writing control terminal, a first electrode of the first transistor is electrically connected to a data line, and a second electrode of the first transistor is electrically connected to the first node. A gate of the second transistor is electrically connected to a compensation control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

8. The pixel circuit of claim 2, wherein, The first initialization circuit includes a third transistor. A gate of the third transistor is electrically connected to the compensation control terminal, a first electrode of the third transistor is electrically connected to the first initial voltage terminal, and a second electrode of the third transistor is electrically connected to the first node.

9. The pixel circuit of claim 3, wherein, The second initialization circuit includes a fourth transistor. A gate of the fourth transistor is electrically connected to the reset control terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the second node.

10. The pixel circuit of claim 4, wherein, The first light emitting control circuit includes a fifth transistor and a sixth transistor. A gate of the fifth transistor is electrically connected to a light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the power voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node. A gate of the sixth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to a first electrode of the light emitting element.

11. The pixel circuit of claim 5, wherein, The third initialization circuit includes a seventh transistor. A gate of the seventh transistor is electrically connected to the reset control terminal, a first electrode of the seventh transistor is electrically connected to the third initial voltage terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

12. The pixel circuit of claim 8, wherein, The third transistor is an oxide transistor.

13. The pixel circuit of claim 7, wherein, The first transistor and the second transistor are oxide transistors.

14. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 13, wherein a display period of the pixel circuit comprises a compensation phase and a write phase which are independent of each other. The pixel driving method includes: In the compensation stage, the compensation control circuit controls the communication between the first node and the third node under the control of a compensation control signal. In the writing stage, the data writing circuit writes a data voltage provided by a data line into the first node under the control of a writing control signal.

15. A display device including the pixel circuit according to any one of claims 1 to 13.

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