Embedded packaging structure, power supply, and manufacturing method

Abstract

Embodiments of the present application provide an embedded packaging structure, comprising a substrate frame, an inductor, a first capacitor, a second capacitor, a first chip, and a first plastic packaging layer. The inductor is embedded in the substrate frame; a first accommodating recess is formed at a first side of the inductor, and the first side is close to the upper surface of the substrate frame; a second accommodating recess is formed at a second side of the inductor, and the second side is close to the lower surface of the substrate frame; the first capacitor is arranged in the first accommodating recess; the second capacitor is arranged in the second accommodating recess; the first chip is surface-attached to the upper surface of the substrate frame and is covered by the first plastic packaging layer; and an electrical link is provided between the first capacitor and the first chip.

Description

Embedded package structure, power supply and manufacturing method

[0001] The present application claims priority to the Chinese patent application No. CN202410649907.4, filed on May 23, 2024, and entitled "Embedded package structure, power supply and manufacturing method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic component packaging, and in particular to an embedded package structure, a power supply and a manufacturing method. BACKGROUND

[0003] With the continuous evolution of power module towards smaller area and higher integration, embedded chip packaging technology (ECP) has been applied, which is a packaging method of embedding chips or components into a substrate.

[0004] With the iteration and upgrading of products, referring to FIG. 1, ECP packaging is derived from embedded chip, capacitor to embedded inductor. In this technology, the inductor is placed in the through hole of the substrate to form an embedded inductor structure. Among them, the capacitor and other resistors and chips are surface-mounted on the surface of the substrate. In order to protect these surface-mounted devices and enhance the connection between them and the substrate, it is necessary to seal the surface-mounted devices on the substrate using organic plastic packaging material to form a protective layer. The thickness of this plastic packaging depends on the maximum thickness of the surface-mounted devices (in order to cover all surface-mounted devices).

[0005] However, in some scenarios, the thickness of the capacitor is greater than the thickness of the chip, resulting in an increase in the thermal resistance of the chip to heat upward, which cannot achieve the ideal heat dissipation effect. SUMMARY

[0006] The present application provides an embedded package structure, a power supply and a manufacturing method for improving the heat dissipation efficiency of the chip.

[0007] The first aspect of the present application provides an embedded package structure:

[0008] The embedded package structure comprises a substrate frame, an inductor, a first capacitor, a second capacitor, a first chip and a first plastic packaging layer. The inductor is embedded in the substrate frame. The first side of the inductor is provided with a first accommodating groove, and the first side is close to the upper surface of the substrate frame. The second side of the inductor is provided with a second accommodating groove, and the second side is close to the lower surface of the substrate frame. The first capacitor is arranged in the first accommodating groove, and the second capacitor is arranged in the second accommodating groove. The first chip is surface-mounted on the upper surface of the substrate frame and is wrapped by the first plastic packaging layer. An electrical link is arranged between the first capacitor and the first chip.

[0009] In the application, since the capacitor is embedded in the substrate frame and the chip is attached to the surface of the substrate frame, the first plastic encapsulation layer does not need to match the thickness of the capacitor, thereby improving the heat dissipation efficiency of the chip. In addition, since the capacitor is arranged in the groove on both sides of the inductor, the integration of the capacitor is improved.

[0010] In a possible implementation, the electrical link between the first capacitor and the first chip is arranged in a vertical direction, and the vertical direction is a direction perpendicular to the upper surface and the lower surface of the substrate frame.

[0011] In the application, the electrical link between the first capacitor and the first chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by a too long link compared with a horizontally arranged link.

[0012] In a possible implementation, the embedded packaging structure further includes a second chip and a second plastic encapsulation layer, the second chip is attached to the lower surface of the substrate frame and is encapsulated by the second plastic encapsulation layer, and an electrical link is arranged between the second capacitor and the second chip.

[0013] In the application, both surfaces of the embedded packaging structure can attach chips, thereby further improving the integration.

[0014] In a possible implementation, the electrical link between the second capacitor and the second chip is arranged in a vertical direction, and the vertical direction is a direction perpendicular to the upper surface and the lower surface of the substrate frame.

[0015] In the application, the electrical link between the second capacitor and the second chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by a too long link compared with a horizontally arranged link.

[0016] In a possible implementation, the embedded packaging structure further includes a first pin, and the first pin is arranged on the left side and the right side of the substrate frame.

[0017] In the application, the embedded packaging structure can output a pin from the side, thereby improving the flexibility of the connection between the embedded packaging structure and other electronic devices.

[0018] In a possible implementation, the embedded packaging structure further includes a second pin, and the second pin is arranged on the upper surface and the lower surface of the substrate frame.

[0019] In the application, the embedded packaging structure can also output a pin from the upper and lower surfaces, thereby further improving the integration.

[0020] The second aspect of the application provides a power supply.

[0021] The power supply includes the embedded packaging structure in the first aspect.

[0022] The third aspect of the present application provides a manufacturing method, comprising:

[0023] The inductor, the first capacitor and the tubular hard resin are pasted on the first film material, the first side of the inductor is provided with the first accommodating groove, the first side is close to the upper surface of the substrate frame, the second side of the inductor is provided with the second accommodating groove, the second side is close to the lower surface of the substrate frame, the first capacitor is arranged in the second accommodating groove, and the inductor is arranged in the cavity formed by the tubular hard resin and the first film material. The second capacitor is pasted on the second film material, and the second film material is pasted on the upper surface of the tubular hard resin, so that the second capacitor is arranged in the first accommodating groove. Liquid resin is injected into the cavity until the liquid resin completely fills the first accommodating groove, the second accommodating groove and the cavity. The first film material and the second film material are removed to obtain a preliminary substrate frame. The resin material is compressed on the upper surface and the lower surface of the preliminary substrate frame to obtain the substrate frame. The first chip is pasted on the upper surface of the substrate frame, and the first chip is wrapped by the first plastic sealing layer. An electrical link is arranged between the first chip and the first capacitor.

[0024] In the present application, the capacitor is embedded in the substrate frame by the above manufacturing method, and the chip is pasted on the surface of the substrate frame, so that the first plastic sealing layer does not need to match the thickness of the capacitor, thereby improving the heat dissipation efficiency of the chip. In addition, since the capacitors are arranged in the accommodating grooves on both sides of the inductor, the integration of the capacitors is improved.

[0025] In a possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, and the vertical direction is perpendicular to the upper surface and the lower surface of the substrate frame.

[0026] In the present application, the electrical link between the first capacitor and the first chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by the too long link compared with the horizontally arranged link.

[0027] In a possible implementation, the method further comprises:

[0028] The second chip is pasted on the lower surface of the substrate frame, and the second chip is wrapped by the second plastic sealing layer. An electrical link is arranged between the second chip and the second capacitor.

[0029] In the present application, the double surfaces of the embedded packaging structure can paste chips, further improving the integration.

[0030] In a possible implementation, the electrical link between the second chip and the second capacitor is arranged in a vertical direction.

[0031] In the present application, the electrical link between the second capacitor and the second chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by the too long link compared with the horizontally arranged link.

[0032] The fourth aspect of the present application provides a manufacturing method, comprising:

[0033] The first capacitor is attached to the first film material, and the first capacitor is arranged in the cavity formed by the tubular hard resin and the first film material.

[0034] The second capacitor is attached to the second film material, and the second film material is attached to the upper surface of the tubular hard resin, so that the second capacitor is arranged in the cavity. The magnetic slurry is injected into the cavity until the magnetic slurry completely fills the cavity. The first film material and the second film material are removed to obtain a preliminary substrate frame. The resin material is compressed on the upper surface and the lower surface of the preliminary substrate frame to obtain a substrate frame. The first chip is attached to the upper surface of the substrate frame, and the first chip is wrapped by the first plastic sealing layer. An electrical link is arranged between the first chip and the first capacitor.

[0035] In the present application, the capacitor is embedded in the substrate frame by the above manufacturing method, and the chip is attached to the surface of the substrate frame. Therefore, the first plastic sealing layer does not need to match the thickness of the capacitor, thereby improving the heat dissipation efficiency of the chip. After the magnetic slurry solidifies, an inductor is formed, and the inductor has two accommodating grooves, each of which is arranged with a capacitor, thereby improving the integration of the capacitor arrangement. In addition, the inductor can be manufactured by injecting the magnetic slurry, thereby reducing the manufacturing cost of the inductor.

[0036] In a possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, which is perpendicular to the upper surface and the lower surface of the substrate frame.

[0037] In the present application, the electrical link between the first capacitor and the first chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by the long link compared with the horizontally arranged link.

[0038] In a possible implementation, the method further comprises:

[0039] The second chip is attached to the lower surface of the substrate frame, and the second chip is wrapped by the second plastic sealing layer. An electrical link is arranged between the second chip and the second capacitor.

[0040] In the present application, the double-sided embedded packaging structure can be attached with chips, thereby further improving the integration.

[0041] In a possible implementation, the electrical link between the second chip and the second capacitor is arranged in a vertical direction.

[0042] In the present application, the electrical link between the second capacitor and the second chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by the long link compared with the horizontally arranged link.

[0043] The fifth aspect of the present application provides a manufacturing method, comprising:

[0044] The inductor, the first capacitor and the tubular hard resin are pasted on the first film material, the first side of the inductor is provided with the first accommodating groove, the first side is close to the upper surface of the substrate frame, the second side of the inductor is provided with the second accommodating groove, the second side is close to the lower surface of the substrate frame, the first capacitor is arranged in the second accommodating groove, and the inductor is arranged in the cavity formed by the tubular hard resin and the first film material. Liquid resin is injected into the cavity until the liquid resin completely fills the first accommodating groove and half of the cavity. The second capacitor is pasted on the second film material, and the second film material is pasted on the upper surface of the tubular hard resin, so that the second capacitor is arranged in the first accommodating groove. Liquid resin is injected into the cavity until the liquid resin completely fills the second accommodating groove and the cavity. The first film material and the second film material are removed to obtain a preliminary substrate frame. The resin material is compressed on the upper surface and the lower surface of the preliminary substrate frame to obtain the substrate frame. The first chip is pasted on the upper surface of the substrate frame, and the first chip is wrapped by the first plastic sealing layer, and an electrical link is arranged between the first chip and the first capacitor.

[0045] In the present application, by the above manufacturing method, the capacitor is buried in the substrate frame, and the chip is pasted on the surface of the substrate frame, so that the first plastic sealing layer does not need to match the thickness of the capacitor, thereby improving the heat dissipation efficiency of the chip. In addition, since the two side accommodating grooves of the inductor are provided with the capacitor, the integration of the capacitor is improved.

[0046] In a possible implementation manner, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, and the vertical direction is perpendicular to the upper surface and the lower surface of the substrate frame.

[0047] In the present application, the electrical link between the first capacitor and the first chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by the too long horizontally arranged link.

[0048] In a possible implementation manner, the method further comprises:

[0049] The second chip is pasted on the lower surface of the substrate frame, and the second chip is wrapped by the second plastic sealing layer, and an electrical link is arranged between the second chip and the second capacitor.

[0050] In the present application, the double sides of the buried packaging structure can paste the chip, and the integration is further improved.

[0051] In a possible implementation manner, the electrical link between the second chip and the second capacitor is arranged in a vertical direction.

[0052] In the present application, the electrical link between the second capacitor and the second chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by too long link compared with horizontally arranged link.

[0053] The sixth aspect of the present application provides a manufacturing method, comprising:

[0054] The first capacitor and the tubular resin are attached to the first film material, and the first capacitor is arranged in the cavity formed by the tubular hard resin and the first film material.

[0055] The second capacitor is attached to the second film material, and the second film material is attached to the upper surface of the tubular hard resin, so that the second capacitor is arranged in the cavity. Magnetic paste is injected into the cavity until the magnetic paste completely fills the cavity. The first film material and the second film material are removed to obtain a preliminary substrate frame. The resin material is compressed on the upper surface and the lower surface of the preliminary substrate frame to obtain a substrate frame. The first chip is attached to the upper surface of the substrate frame, and the first chip is wrapped by the first plastic sealing layer, and an electrical link is arranged between the first chip and the first capacitor.

[0056] In the present application, the manufacturing method described above allows the capacitor to be embedded in the substrate frame, and the chip is attached to the surface of the substrate frame, so that the first plastic sealing layer does not need to match the thickness of the capacitor, thereby improving the heat dissipation efficiency of the chip. When the magnetic paste solidifies to form an inductor, the inductor forms a receiving groove on both sides, and a capacitor is arranged in each receiving groove, thereby improving the integration of the capacitor. In addition, since the inductor can be manufactured by injecting magnetic paste, the manufacturing cost of the inductor is reduced.

[0057] In a possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, which is perpendicular to the upper surface and the lower surface of the substrate frame.

[0058] In the present application, the electrical link between the first capacitor and the first chip is arranged vertically, which avoids the problems of large parasitic parameters and high electrical stress risk caused by too long link compared with horizontally arranged link.

[0059] In a possible implementation, the method further comprises:

[0060] The second chip is attached to the lower surface of the substrate frame, and the second chip is wrapped by the second plastic sealing layer, and an electrical link is arranged between the second chip and the second capacitor.

[0061] In the present application, both sides of the embedded packaging structure can attach chips, which further improves the integration.

[0062] In a possible implementation, the electrical link between the second chip and the second capacitor is arranged in a vertical direction.

[0063] In the present application, the electrical link between the second capacitor and the second chip is arranged vertically, which avoids the problem of large parasitic parameters and high electrical stress risk caused by too long link compared with horizontally arranged link. BRIEF DESCRIPTION OF DRAWINGS

[0064] Fig. 1 is a schematic diagram of a prior art packaging structure;

[0065] Fig. 2 is a schematic diagram of a prior art power module;

[0066] Fig. 3 is another schematic diagram of a prior art power module;

[0067] Fig. 4 is a schematic diagram of a buried packaging structure in the present application;

[0068] Fig. 5 is a schematic diagram of a buried packaging structure in the present application;

[0069] Fig. 6 is a schematic diagram of a buried packaging structure in the present application;

[0070] Fig. 7 is a schematic diagram of a power module in the present application;

[0071] Figs. 8 to 23 are schematic diagrams of manufacturing a buried packaging structure in the present application. DETAILED DESCRIPTION

[0072] The embodiments of the present application will be described below in conjunction with the accompanying drawings. It is obvious that the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. It is known to those skilled in the art that the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems as technology develops and new scenarios appear.

[0073] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product, or device.

[0074] In order to facilitate the understanding of the present application, the concepts involved in the present application are introduced as follows:

[0075] ECP: ECP is an advanced packaging process. In this packaging process, chips or components are embedded inside the substrate, rather than simply placed on top of the substrate. This technology embeds chips or components into the substrate using a multi-step manufacturing process and connects them using plated copper vias. The main advantages of ECP packaging are that it enables higher miniaturization, reliable interconnection, higher performance, and improved protection of integrated components. It is widely used in various high-tech fields such as medical technology, consumer electronics, and smartphones. In particular, in the field of smartphones, ECP packaging technology enables thinner circuit board designs, allowing for larger volume and longer-lasting battery applications. Additionally, chargers using ECP technology can also speed up battery charging. Unlike traditional wafer reconstitution plastic packaging processes, ECP processes do not use liquid or powder plastic packaging materials, but instead use a wrapping plastic film. By replacing wafer packaging with a wrapping leveling process, ECP technology enables ultra-thin packaging of chips and avoids the creation of voids during wrapping. At the same time, this process can effectively reduce chip offset problems and achieve large fan-out packaging of small-sized chips.

[0076] Capacitors: In ECP packaging, capacitors play several key roles:

[0077] Power filtering and decoupling: Capacitors in ECP packaging are often used for power filtering and decoupling. They can absorb and release transient energy in the circuit, thereby stabilizing the power supply voltage and reducing the impact of power supply noise on circuit performance. Signal conditioning: Capacitors play a role in signal transmission by adjusting the waveform, frequency response, and phase relationship of signals, making them better suited for subsequent circuit processing requirements. Energy storage: Capacitors can store electric charge and release it when needed. In ECP packaging, capacitors can be used to provide the required transient energy at critical moments, such as starting current or other high peak current requirements. Timing control: In some applications, capacitors are also used for timing control functions. By controlling the charging and discharging process of capacitors, the time sequence of certain events in the circuit can be precisely controlled. Electromagnetic shielding: Capacitors can also be used for electromagnetic shielding to reduce the impact of electromagnetic interference on circuit performance. They can absorb and disperse electromagnetic field energy, protecting the circuit from external electromagnetic noise. In ECP packaging, the selection and layout of capacitors need to consider the specific requirements of the circuit, working conditions, and space limitations of the packaging. Suitable capacitor types and parameters can improve the stability and performance of the circuit, ensuring reliable operation of ECP packaging in complex environments.

[0078] Inductors: Inductors in ECP packaging play the following key roles:

[0079] Filtering: Inductors are commonly used in ECP packages for filtering circuits. They effectively block high-frequency noise signals, allowing only low-frequency signals to pass through, thus stabilizing the signals in the circuit and reducing noise interference.

[0080] Energy Storage: Inductors have the characteristic of storing magnetic field energy. When the current changes, the inductor can absorb or release energy, which helps to smooth the current fluctuations in the circuit and prevent damage caused by sudden current changes.

[0081] Impedance Matching: In ECP packages, inductors can be used to adjust the impedance of the circuit, making the impedance between the signal source and the load match, thus improving the efficiency of signal transmission.

[0082] Resonant Circuit: Inductors combined with capacitors can form a resonant circuit, which is very useful in certain specific applications such as frequency selection, signal amplification, etc.

[0083] Embedded Inductors: Embedded inductors in ECP packages are a technology that embeds inductor components inside the package substrate. Instead of simply placing inductors on the surface of the package, they are directly integrated into the internal structure of the package substrate. Through specific manufacturing processes, inductor coils are embedded in the substrate material, achieving close integration of inductor components with the package substrate.

[0084] Embedded inductors have the following advantages:

[0085] Space Optimization: Since the inductor is directly embedded inside the package substrate, it does not require additional space to be placed on the surface of the package, thus saving valuable circuit board space.

[0086] Performance Improvement: The close integration of embedded inductors with the package substrate can reduce signal transmission loss and interference, improving the overall performance of the circuit.

[0087] Reliability Enhancement: Since the inductor is encapsulated inside the substrate, it is less affected by external environmental interference, thus improving the reliability of the circuit.

[0088] Electromagnetic Compatibility: The design of embedded inductors can more effectively control electromagnetic radiation, reduce electromagnetic interference (EMI), and improve the electromagnetic compatibility of the circuit. Embedded inductors are widely used in ECP packages for electronic devices that require high performance, high reliability, and compact space, such as smartphones, wearable devices, high-speed communication devices, etc. The use of this technology helps to improve the performance, efficiency and reliability of these devices, and promotes the further development of electronic technology.

[0089] Inductor winding: Inductor winding refers to a group of coils with specific functions, which is the basic component of an inductor. Winding has single-layer and multi-layer. Single-layer winding has two forms of dense winding (one circle of wire next to another when winding) and interval winding (each circle of wire is separated by a certain distance when winding); multi-layer winding has many forms such as layered flat winding, random winding, honeycomb winding method, etc.

[0090] Inductor winding plays an important role in the circuit, such as energy storage and release, filtering, signal transmission, and power regulation, etc. When current passes through the inductor coil, a magnetic field is generated in the winding, which stores electromagnetic energy. When the current stops flowing through the coil, the magnetic field collapses and releases the stored energy. By selecting the appropriate inductance value, the inductor coil can block the passage of high-frequency signals, so that the circuit only transmits the required signal frequency range. In addition, inductor coils can also be used for signal transmission and power regulation.

[0091] Parasitic parameters: Parasitic parameters refer to unnecessary elements existing in electronic components or circuits, which are usually caused by the physical characteristics of wires, circuit boards and other circuit elements. These parasitic parameters will adversely affect the normal operation of components or circuits, usually manifested as power consumption, signal transmission rate limitation or signal quality influence, etc.

[0092] Electrical stress: Electrical stress is a measure of the force generated by the change of electric field intensity in dielectric, specifically the force between two parallel charged surfaces in dielectric under the action of electric field. When the electric field intensity changes in the dielectric, the charge distribution in the dielectric will change, which will cause the electric field force in the dielectric, so that there will be a certain stress in the dielectric, which is called electrical stress.

[0093] Please refer to Figure 2, the design scheme of an existing power module is to lay electronic components such as chips (IC), capacitors (C), resistors (R) and inductors (L) on the printed circuit board (PCB) for power supply and control. This power module occupies a very large area of the PCB, which is not conducive to miniaturization and integration.

[0094] Referring to FIG. 3, another existing design scheme of a power module is to embed a chip (IC), a capacitor (C) and a resistor (R) into a substrate to form an ECP module, and then to attach an inductor (L) on the surface of the ECP module to construct a power module with a three-dimensional stacked structure. Although the stacked arrangement of the inductor (L) can reduce the occupied area to a certain extent, and the high integration of the device can result in small parasitic parameters, as the main heat source of the power module, the chip (IC) is integrated in the ECP module, and the chip (IC) is wrapped by a dielectric layer around, which results in poor heat dissipation capacity of the power module, and the heat dissipation channel of the chip (IC) needs to be dissipated through the substrate of the ECP, which is also limited. Therefore, as the product iterates and upgrades, a design scheme as shown in FIG. 1 is proposed, but this scheme still has the shortcomings of difficult chip heat dissipation, large parasitic parameters between the capacitor and the chip, high electrical stress risk, and insufficient overall integration.

[0095] Referring to FIG. 4, the application provides a buried packaging structure, which is a sectional view of the buried packaging structure, including a substrate frame 401, an inductor 402, an inductor winding 4021, one or more first capacitors 403, one or more second capacitors 404, one or more first chips 405, a first plastic encapsulation layer 406, a copper layer 407 (black line segments in the figure except the inductor winding 4021, not all marked), a first pin 4071, and a second pin 4072. The inductor 402 is embedded in the substrate frame 401, the first side of the inductor 402 is provided with a first accommodating groove 4021, and the second side of the inductor 402 is provided with a second accommodating groove 4022, wherein the first side is close to the upper surface of the substrate frame 401, and the second side is close to the lower surface of the substrate frame 401. The inductor 402 can be provided in the shape of "H" as shown in FIG. 4, or can also be provided in other shapes, as long as the first accommodating groove 4021 and the second accommodating groove 4022 are provided. The first capacitor 403 is arranged in the first accommodating groove 4021, and the second capacitor 404 is arranged in the second accommodating groove 4022. The first chip 405 is surface-mounted on the upper surface of the substrate frame 401 and is wrapped by the first plastic encapsulation layer 406. Through such arrangement, the capacitor does not need to be surface-mounted on the upper surface of the substrate, and the thickness of the first plastic encapsulation layer 406 is greatly reduced since it only needs to match the thickness of the first chip 405, thereby enabling the first chip 405 to obtain good heat dissipation effect. An electrical link is arranged between the first capacitor 404 and the first chip 405, which in an optional manner can be arranged in a vertical direction, i.e., a direction perpendicular to the upper surface and the lower surface of the substrate frame, thereby shortening the length of the electrical link and effectively avoiding problems of large parasitic parameters and high electrical stress risk. The first pin 4071 and the second pin 4072 are arranged on the side surface of the substrate frame 401. It should be noted that the number of the above-mentioned first accommodating grooves 4021 can also be multiple, wherein one first capacitor 403 is arranged in each first accommodating groove 4021; similarly, the number of the above-mentioned second accommodating grooves 4022 can also be multiple, wherein one second capacitor 404 is arranged in each second accommodating groove 4022.

[0096] Referring to FIG. 5, another embedded packaging structure is provided, which is a sectional view of the embedded packaging structure, including a substrate frame 401, an inductor 402, an inductor winding 4021, one or more first capacitors 403, one or more second capacitors 404, one or more first chips 405, a first plastic encapsulation layer 406, a copper layer 407, first pins 4071, second pins 4072, one or more second chips 408, and a second plastic encapsulation layer 409. Similarly, the inductor 402 is embedded in the substrate frame 401, the first side of the inductor 402 is provided with a first accommodating groove 4021, and the second side of the inductor 402 is provided with a second accommodating groove 4022, wherein the first side is close to the upper surface of the substrate frame 401, and the second side is close to the lower surface of the substrate frame 401. The inductor 402 can be provided in the shape of "H" as shown in FIG. 4, or can also be provided in other shapes, as long as the first accommodating groove 4021 and the second accommodating groove 4022 are provided. The first capacitor 403 is arranged in the first accommodating groove 4021, and the second capacitor 404 is arranged in the second accommodating groove 4022. The first chip 405 is surface-mounted on the upper surface of the substrate frame 401 and is wrapped by the first plastic encapsulation layer 406. Through such an arrangement, the capacitors no longer need to be surface-mounted on the upper surface of the substrate, and the thickness of the first plastic encapsulation layer 406 is greatly reduced since it only needs to match the thickness of the first chip 405, thereby enabling the first chip 405 to obtain good heat dissipation effect. An electrical link is arranged between the first capacitor 404 and the first chip 405, which in an optional manner can be arranged in the vertical direction, thereby shortening the length of the electrical link and effectively avoiding problems of large parasitic parameters and high electrical stress risk. The second chip 408 is surface-mounted on the lower surface of the substrate frame 401 and is wrapped by the second plastic encapsulation layer 409. An electrical link is arranged between the second capacitor 404 and the second chip 408, which in an optional manner can be arranged in the vertical direction, thereby shortening the length of the electrical link and effectively avoiding problems of large parasitic parameters and high electrical stress risk. The first pins 4071 and the second pins 4072 are arranged on the side surface of the substrate frame 401. In this embedded packaging structure, the upper surface and the lower surface of the substrate frame 401 are both surface-mounted with chips, thereby improving the integration. It should be noted that the number of the above-mentioned first accommodating grooves 4021 can also be multiple, wherein one first capacitor 403 is arranged in each first accommodating groove 4021; similarly, the number of the above-mentioned second accommodating grooves 4022 can also be multiple, wherein one second capacitor 404 is arranged in each second accommodating groove 4022.

[0097] Referring to FIG. 6, on the basis of the embedded packaging structure shown in FIG. 5, the embedded packaging structure further includes pins 4073 and 4074 arranged on the upper surface and the lower surface of the substrate frame 401, respectively, thereby further improving the integration. Through the pins 4074, the embedded packaging structure of the present application can be connected with a PCB bottom plate.

[0098] It should be noted that in the foregoing various embedded packaging structures, one or more of the chips can be arranged in an exposed heat dissipation manner, and the chips can be arranged in a front-up or front-down manner.

[0099] The application also provides a power supply including the embedded packaging structure of any one of the foregoing structures of FIGS. 4-6. In one possible implementation, referring to FIG. 7, the power supply includes a PCB substrate and the embedded packaging structure mounted on the PCB substrate, and in addition, the PCB substrate includes circuits and electronic devices thereof, which are not shown here for brevity of description.

[0100] The foregoing describes the embedded packaging structure of the application, and the following describes a manufacturing process of the embedded packaging structure of the application.

[0101] Referring to FIG. 8, the second capacitor 404 is first attached to the first film 410, and then the inductor 402 is also attached to the first film 410, and the inductor 402 is further provided with an inductor winding 4021, and at this time, the second capacitor 404 is arranged in the second accommodating groove 4022 of the inductor. The first film 410 is further provided with a tubular hard resin 4011, and the tubular hard resin 4011 and the first film 410 together constitute a filling cavity. After the second capacitor 404 and the inductor 402 are attached to the first film 410, liquid resin is injected into the filling cavity until the liquid resin completely fills the second accommodating groove 4022 and fills to a half height of the filling cavity.

[0102] Referring to FIG. 9, then, the first capacitor 403 is attached to the second film 411, and then the second film 411 is attached to the inductor 402, and at this time, the first capacitor 403 is arranged in the first accommodating groove 4021 of the inductor 402. Then, the liquid resin 4012 is continuously injected into the filling cavity until the liquid resin 4012 completely fills the first accommodating groove 4021 and the entire filling cavity.

[0103] After that, please refer to FIG. 10, after the liquid resin 4012 is completely solidified, the first film material 410 and the second film material 411 are removed, and the hard resin 4013 and the hard resin 4014 are laminated, thereby forming a substrate frame. Then, build up processing is performed inside the substrate frame to build the copper layer 407, the pin 4071 and the pin 4072. The build up processing generally refers to a kind of additive manufacturing process, which is a technology commonly used in multi-layer board manufacturing. The additive manufacturing process is originally derived from the SLC process of IBM. Based on the traditional double-sided board, this method increases the number of layers of the multi-layer board through a series of steps such as liquid photosensitive pre-qual, semi-hardening and photosensitive resolution, chemical copper and electroplated copper, full increase of conductor layer, line imaging and etching, etc. This method can eliminate the cost of expensive mechanical drilling, and the aperture can be reduced to below 10 mil. In the ECP package, the application of build up processing is mainly to increase the number of layers or complexity of the substrate to meet the specific packaging requirements. By using build up processing, the product size can be reduced without affecting the overall performance, and it also helps to dissipate heat and protect the peripheral components.

[0104] Please refer to FIG. 11, after the build up processing is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406.

[0105] The above describes one manufacturing process of the embedded packaging structure in the present application. The following describes another manufacturing process of the embedded packaging structure in the present application:

[0106] Similar to the foregoing FIG. 8, the second capacitor 404 is first attached to the first film material 410, and then the inductor 402 is also attached to the first film material 410, at this time the second capacitor 404 is arranged in the second accommodating groove 4022 of the inductor. The tubular hard resin 4011 is also arranged on the first film material 410, and the tubular hard resin 4011 and the first film material 410 together constitute a filling chamber. After the second capacitor 404 and the inductor 402 are attached to the first film material 410, liquid resin is injected into the filling chamber until the liquid resin completely fills the second accommodating groove 4022 and fills to half the height of the filling chamber.

[0107] Similar to the foregoing FIG. 9, then the first capacitor 403 is attached to the second film material 411, and then the second film material 411 is attached to the inductor 402, at this time the first capacitor 403 is arranged in the first accommodating groove 4021 of the inductor 402. Then continue to inject the liquid resin 4012 into the filling chamber until the liquid resin 4012 completely fills the first accommodating groove 4021 and the entire filling chamber.

[0108] Similar to the foregoing Fig. 10, after the liquid resin 4012 is completely solidified, the first film 410 and the second film 411 are removed, and the hard resin 4013 and the hard resin 4014 are pressed to form a substrate frame. Then, build up processing is performed inside the substrate frame to build the copper layer 407, the pin 4071 and the pin 4072.

[0109] Referring to Fig. 12, after the build up processing is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406. The second chip 408 is attached to the lower surface of the substrate frame, and the second chip 408 is protected by the second plastic encapsulation layer 409.

[0110] The following continues to introduce another manufacturing process of the embedded package structure in the present application:

[0111] Similar to the foregoing Fig. 8, the second capacitor 404 is first attached to the first film 410, and then the inductor 402 is also attached to the first film 410, at this time the second capacitor 404 is arranged in the second accommodating groove 4022 of the inductor. The tubular hard resin 4011 is also arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together constitute a filling chamber. After the second capacitor 404 and the inductor 402 are attached to the first film 410, liquid resin is injected into the filling chamber until the liquid resin completely fills the second accommodating groove 4022 and fills to half the height of the filling chamber.

[0112] Similar to the foregoing Fig. 9, then the first capacitor 403 is attached to the second film 411, and then the second film 411 is attached to the inductor 402, at this time the first capacitor 403 is arranged in the first accommodating groove 4021 of the inductor 402. Then the liquid resin 4012 continues to be injected into the filling chamber until the liquid resin 4012 completely fills the first accommodating groove 4021 and the entire filling chamber.

[0113] Similar to the foregoing Fig. 10, after the liquid resin 4012 is completely solidified, the first film 410 and the second film 411 are removed, and the hard resin 4013 and the hard resin 4014 are pressed to form a substrate frame. Then, build up processing is performed inside the substrate frame to build the copper layer 407, the pin 4071 and the pin 4072.

[0114] Referring to Fig. 13, after the build up processing is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406. The second chip 408 is attached to the lower surface of the substrate frame, and the second chip 408 is protected by the second plastic encapsulation layer 409, and further the pin 4073 and the pin 4074 are made.

[0115] In the manufacturing process described above, the inductor is directly embedded in the substrate frame. In another implementation, the inductor can also be formed in the substrate frame through a potting process, which is described as follows:

[0116] Referring to FIG. 14, the second capacitor 404 and the inductor winding 501 are first attached to the first film 410. The tubular hard resin 4011 is also arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together form a filling chamber. After the second capacitor 404 and the inductor winding 501 are attached to the first film 410, the magnetic slurry 402 is injected into the filling chamber until the magnetic slurry 402 fills half of the height of the filling chamber.

[0117] Referring to FIG. 15, then, the first capacitor 403 is attached to the second film 411, and the second film 411 is attached to the tubular hard resin 4011. Then, the magnetic slurry 402 is continuously injected into the filling chamber until the magnetic slurry 402 completely fills the entire filling chamber.

[0118] In a possible implementation, after the second capacitor 404 and the inductor winding 501 are attached to the first film 410 in the manner shown in FIG. 14, the magnetic slurry can not be injected first, but the second film 411 and the first capacitor 403 are further arranged in the manner shown in FIG. 15, and then the magnetic slurry is completely filled in the entire filling chamber at one time.

[0119] Referring to FIG. 16, after the magnetic slurry 402 completely solidifies, the inductor 402 is formed. The first film 410 and the second film 411 are removed, and the hard resin 4013 and the hard resin 4014 are pressed to form the substrate frame. Then, the build up process is performed inside the substrate frame to build the copper layer 407, the pin 4071 and the pin 4072.

[0120] Referring to FIG. 17, after the build up process is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406.

[0121] Another manufacturing process of the embedded package structure in the present application is described as follows:

[0122] Similar to Fig. 14, first, the second capacitor 404 and the inductor winding 501 are attached to the first film 410, and a tubular hard resin 4011 is arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together form a filling cavity. After the second capacitor 404 and the inductor winding 501 are attached to the first film 410, the magnetic slurry 402 is injected into the filling cavity until the magnetic slurry 402 fills to half the height of the filling cavity.

[0123] Similar to Fig. 15, then, the first capacitor 403 is attached to the second film 411, and then the second film 411 is attached to the tubular hard resin 4011. Then, the magnetic slurry 402 is continuously injected into the filling cavity until the magnetic slurry 402 completely fills the entire filling cavity.

[0124] Similar to Fig. 16, after the magnetic slurry 402 completely solidifies, the inductor 402 is formed, the first film 410 and the second film 411 are removed, and the hard resin 4013 and the hard resin 4014 are compressed to form a substrate frame. Then, build-up processing is performed inside the substrate frame to build the copper layer 407, the pin 4071, and the pin 4072.

[0125] Referring to Fig. 18, after the build-up processing is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406. The second chip 408 is attached to the lower surface of the substrate frame, and the second chip 408 is protected by the second plastic encapsulation layer 409.

[0126] Next, another manufacturing process of the embedded packaging structure in the present application will be introduced:

[0127] Similar to Fig. 14, first, the second capacitor 404 and the inductor winding 501 are attached to the first film 410, and a tubular hard resin 4011 is arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together form a filling cavity. After the second capacitor 404 and the inductor winding 501 are attached to the first film 410, the magnetic slurry 402 is injected into the filling cavity until the magnetic slurry 402 fills to half the height of the filling cavity.

[0128] Similar to Fig. 15, then, the first capacitor 403 is attached to the second film 411, and then the second film 411 is attached to the tubular hard resin 4011. Then, the magnetic slurry 402 is continuously injected into the filling cavity until the magnetic slurry 402 completely fills the entire filling cavity.

[0129] After the magnetic paste 402 is completely solidified, the first film 410 and the second film 411 are removed, and the hard resin 4013 and the hard resin 4014 are pressed to form the substrate frame. Then, the build up process is performed inside the substrate frame to build the copper layer 407, the pin 4071 and the pin 4072.

[0130] Referring to FIG. 19, after the build up process is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406. The second chip 408 is attached to the lower surface of the substrate frame, and the second chip 408 is protected by the second plastic encapsulation layer 409, and the pin 4073 and the pin 4074 are formed.

[0131] Another manufacturing process of the embedded package structure in the present application is introduced as follows:

[0132] Referring to FIG. 20, the second capacitor 404 is first attached to the first film 410, and then the inductor 402 is also attached to the first film 410, and the inductor winding 4021 is arranged in the inductor 402. At this time, the second capacitor 404 is arranged in the second accommodating groove 4022 of the inductor. The tubular hard resin 4011 is arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together form the filling cavity.

[0133] Referring to FIG. 21, then, the first capacitor 403 is attached to the second film 411, and then the second film 411 is attached to the inductor 402, and at this time, the first capacitor 403 is arranged in the first accommodating groove 4021 of the inductor 402. Then, the liquid resin 4012 is injected into the filling cavity through the injection hole until the liquid resin 4012 completely fills the first accommodating groove 4021, the second accommodating groove 4022 and the entire filling cavity.

[0134] After the liquid resin 4012 is completely solidified, the first film 410 and the second film 411 are removed, and the hard resin 4013 and the hard resin 4014 are pressed to form the substrate frame. Then, the build up process is performed inside the substrate frame to build the copper layer 407, the pin 4071 and the pin 4072.

[0135] After the build up process is completed, the first chip 405 is attached to the upper surface of the substrate frame, and the first chip 405 is protected by the first plastic encapsulation layer 406.

[0136] Another manufacturing process is introduced as follows:

[0137] Similar to the foregoing Fig. 20, first, the second capacitor 404 is surface-mounted on the first film 410, and then the inductor 402 is also surface-mounted on the first film 410, and the inductor winding 4021 is arranged in the inductor 402, at this time, the second capacitor 404 is arranged in the second accommodating groove 4022 of the inductor. The tubular hard resin 4011 is arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together constitute a filling cavity.

[0138] Similar to the foregoing Fig. 21, then, the first capacitor 403 is surface-mounted on the second film 411, and then the second film 411 is surface-mounted on the inductor 402, at this time, the first capacitor 403 is arranged in the first accommodating groove 4021 of the inductor 402. Then, the liquid resin 4012 is injected into the filling cavity through the injection hole until the liquid resin 4012 completely fills the first accommodating groove 4021, the second accommodating groove 4022 and the entire filling cavity.

[0139] The subsequent process is similar to the foregoing Figs. 10 and 12, and will not be described here.

[0140] In another manufacturing process, similar to the foregoing Fig. 20, first, the second capacitor 404 is surface-mounted on the first film 410, and then the inductor 402 is also surface-mounted on the first film 410, and the inductor winding 4021 is arranged in the inductor 402, at this time, the second capacitor 404 is arranged in the second accommodating groove 4022 of the inductor. The tubular hard resin 4011 is arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together constitute a filling cavity.

[0141] Similar to the foregoing Fig. 21, then, the first capacitor 403 is surface-mounted on the second film 411, and then the second film 411 is surface-mounted on the inductor 402, at this time, the first capacitor 403 is arranged in the first accommodating groove 4021 of the inductor 402. Then, the liquid resin 4012 is injected into the filling cavity through the injection hole until the liquid resin 4012 completely fills the first accommodating groove 4021, the second accommodating groove 4022 and the entire filling cavity.

[0142] The subsequent process is similar to the foregoing Figs. 10 and 13, and will not be described here.

[0143] Next, another manufacturing process is introduced:

[0144] Referring to Fig. 22, first, the second capacitor 404 and the inductor winding 501 are surface-mounted on the first film 410, and the tubular hard resin 4011 is arranged on the first film 410, and the tubular hard resin 4011 and the first film 410 together constitute a filling cavity.

[0145] Referring to FIG. 23, the first capacitor 403 is then attached to the second film 411, and the second film 411 is then attached to the tubular hard resin 4011. The magnetic slurry 402 is then injected into the filling cavity until the magnetic slurry 402 completely fills the filling cavity.

[0146] The subsequent processes are similar to those described above with respect to FIG. 16 and FIG. 17, and will not be described again here.

[0147] Another manufacturing process of the embedded package structure in the present application will be described as follows:

[0148] Similar to the above-described FIG. 22, the second capacitor 404 and the inductor winding 501 are first attached to the first film 410, and the tubular hard resin 4011 is disposed on the first film 410, and the tubular hard resin 4011 and the first film 410 together form a filling cavity.

[0149] Similar to the above-described FIG. 23, the first capacitor 403 is then attached to the second film 411, and the second film 411 is then attached to the tubular hard resin 4011. The magnetic slurry 402 is then injected into the filling cavity until the magnetic slurry 402 completely fills the filling cavity.

[0150] The subsequent processes are similar to those described above with respect to FIG. 16 and FIG. 18, and will not be described again here.

[0151] Another manufacturing process of the embedded package structure in the present application will be described as follows:

[0152] Similar to the above-described FIG. 22, the second capacitor 404 and the inductor winding 501 are first attached to the first film 410, and the tubular hard resin 4011 is disposed on the first film 410, and the tubular hard resin 4011 and the first film 410 together form a filling cavity.

[0153] Similar to the above-described FIG. 23, the first capacitor 403 is then attached to the second film 411, and the second film 411 is then attached to the tubular hard resin 4011. The magnetic slurry 402 is then injected into the filling cavity until the magnetic slurry 402 completely fills the filling cavity.

[0154] The subsequent processes are similar to those described above with respect to FIG. 16 and FIG. 19, and will not be described again here.

[0155] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described again here.

[0156] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. The division of the units is merely a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0157] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0158] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0159] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such an understanding, the technical solutions of the present application essentially, or the part that makes a contribution to the prior art, or all or a part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a magnetic disk or an optical disk, and various other media that can store program codes.

Claims

1. A buried package structure, characterized by, The buried package structure comprises a substrate frame, an inductor, a first capacitor, a second capacitor, a first chip and a first plastic encapsulation layer. The inductor is embedded in the substrate frame, a first side of the inductor is provided with a first accommodating groove, the first side is close to an upper surface of the substrate frame, a second side of the inductor is provided with a second accommodating groove, the second side is close to a lower surface of the substrate frame. The first capacitor is arranged in the first accommodating groove, and the second capacitor is arranged in the second accommodating groove. The first chip is attached to the upper surface of the substrate frame and is wrapped by the first plastic encapsulation layer. An electrical link is arranged between the first capacitor and the first chip.

2. The embedded package structure of claim 1, wherein, The electrical link between the first capacitor and the first chip is arranged in a vertical direction, the vertical direction being perpendicular to the upper surface and the lower surface of the substrate frame.

3. The embedded package structure of claim 1 or 2, wherein, The buried package structure further comprises a second chip and a second plastic encapsulation layer. The second chip is attached to the lower surface of the substrate frame and is wrapped by the second plastic encapsulation layer. An electrical link is arranged between the second capacitor and the second chip.

4. The embedded package structure of claim 3, wherein, The electrical link between the second capacitor and the second chip is arranged in a vertical direction, the vertical direction being perpendicular to the upper surface and the lower surface of the substrate frame.

5. The embedded package structure of any one of claims 1-4, wherein, The buried package structure further comprises a first pin, the first pin being arranged on the left side surface and the right side surface of the substrate frame.

6. The embedded package structure of claim 5, wherein, The buried package structure further comprises a second pin, the second pin being arranged on the upper surface and the lower surface of the substrate frame.

7. A power supply, characterized by, The power supply comprises the buried package structure according to any one of claims 1 to 6.

8. A manufacturing method characterized by comprising: The buried package structure comprises: An inductor, a first capacitor and a tubular hard resin are attached to a first film material, a first side of the inductor is provided with a first accommodating groove, the first side is close to an upper surface of the substrate frame, a second side of the inductor is provided with a second accommodating groove, the second side is close to a lower surface of the substrate frame, the first capacitor is arranged in the second accommodating groove, and the inductor is arranged in a cavity formed by the tubular hard resin and the first film material; A second capacitor is attached to the second film material, and the second film material is attached to an upper surface of the tubular hard resin, so that the second capacitor is arranged in the first accommodating groove; Liquid resin is injected into the cavity until the liquid resin completely fills the first accommodating groove, the second accommodating groove and the cavity; The first film material and the second film material are removed to obtain a preliminary substrate frame; Resin material is compressed on the upper surface and the lower surface of the preliminary substrate frame to obtain a substrate frame; A first chip is attached to the upper surface of the substrate frame, and the first chip is wrapped by a first plastic encapsulation layer, an electrical link is arranged between the first chip and the first capacitor.

9. The method of claim 8, wherein, The electrical link between the first chip and the first capacitor is arranged in a vertical direction.

10. The method according to claim 8 or 9, characterized in that, The method further comprises: A second chip is attached to the lower surface of the substrate frame, and the second chip is wrapped by a second plastic encapsulation layer, an electrical link is arranged between the second chip and the second capacitor.

11. The method of claim 10, wherein, The electrical link between the second chip and the second capacitor is arranged in a vertical direction.

12. A manufacturing method characterized by comprising: The method comprises: attaching a first capacitor on a first film material, the first capacitor being disposed in a cavity formed by the tubular hard resin and the first film material; attaching a second capacitor on a second film material, and attaching the second film material on an upper surface of the tubular hard resin, so that the second capacitor is disposed in the cavity; injecting magnetic slurry into the cavity until the magnetic slurry completely fills the cavity; removing the first film material and the second film material to obtain a preliminary substrate frame; bonding a resin material on an upper surface and a lower surface of the preliminary substrate frame to obtain a substrate frame; attaching a first chip on an upper surface of the substrate frame, and wrapping the first chip with a first plastic encapsulation layer, an electrical link being provided between the first chip and the first capacitor.

13. The method of claim 12, wherein, The electrical link between the first chip and the first capacitor is provided in a vertical direction.

14. The method according to claim 12 or 13, characterized in that, The method further comprises: attaching a second chip on a lower surface of the substrate frame, and wrapping the second chip with a second plastic encapsulation layer, an electrical link being provided between the second chip and the second capacitor.

15. The method of claim 14, wherein, The electrical link between the second chip and the second capacitor is provided in a vertical direction.

Images