Display panel, driving method for pixel circuit in display panel, and display device

Abstract

Provided are a display panel, a driving method for a pixel circuit in a display panel, and a display device, relating to the technical field of display. In the pixel circuit, a switching circuit, a control circuit and a driving circuit can cooperate with each other to transmit a light-emitting driving signal to a light-emitting element on the basis of different signals such as a switching control signal, a reference power supply signal, a gate driving signal, and a light-emitting control signal, to drive the light-emitting element to emit light. Therefore, by flexibly configuring a switching control signal, when the light-emitting element is driven to emit light, the switching circuit can control a reference power line to be decoupled from a first node, so that the potential variations at a control end and an output end of the driving circuit are equal, thereby avoiding offset of a light-emitting driving signal transmitted by the driving circuit, and ensuring that the light-emitting element is reliably driven to emit light.

Description

Display panel, driving method of pixel circuit thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410644826.5, filed on May 23, 2024, and entitled "Display panel, driving method of pixel circuit thereof and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, and in particular, to a display panel, a driving method of a pixel circuit thereof, and a display device. BACKGROUND

[0003] A display panel generally includes a substrate and a plurality of pixels on the substrate. Each pixel includes a pixel circuit and a light emitting element, the pixel circuit is coupled with the light emitting element and is used to drive the light emitting element to emit light, so that the display panel displays a picture.

[0004] In the related art, the pixel circuit generally includes a control circuit and a driving circuit, and the control circuit includes two capacitors. The control circuit can control the data line to transmit a data signal to the control end of the driving circuit based on a gate driving signal provided by a gate line, can control the output end of the driving circuit to be conductive with the light emitting element based on a light emitting control signal provided by a light emitting control line, and can adjust the potential of the output end and the control end of the driving circuit based on a driving power signal provided by a driving power line. The driving circuit can transmit a light emitting driving signal to the light emitting element through the output end based on the data signal received by the control end and the driving power signal received by the input end, so as to drive the light emitting element to emit light. SUMMARY

[0005] Embodiments of the present application provide a display panel, a driving method of a pixel circuit thereof, and a display device. The technical solutions are as follows:

[0006] In one aspect, a display panel is provided, which includes a substrate and a plurality of pixels on one side of the substrate. The pixel includes a pixel circuit and a light emitting element, and the pixel circuit includes:

[0007] A switching circuit is coupled with a switching control line, a reference power line and a first node respectively, and is used to control the on-off of the reference power line and the first node in response to a switching control signal provided by the switching control line.

[0008] The control circuit is coupled with the gate line, the data line, the first light-emitting control line, the first node, the second node, the third node and the fourth node respectively, and is configured to adjust the potential of the third node based on a reference power signal provided by the reference power line when the reference power line and the first node are turned on, and adjust the potential of the second node, control the on-off of the data line and the second node in response to a gate drive signal provided by the gate line, and control the on-off of the third node and the fourth node in response to a first light-emitting control signal provided by the first light-emitting control line; the fourth node is coupled with the first electrode of the light-emitting element, and the second electrode of the light-emitting element is coupled with a pull-down power line.

[0009] The driving circuit has a control end coupled with the second node, an input end coupled with a driving power line, and an output end coupled with the third node, and is configured to transmit a light-emitting driving signal to the third node based on a driving power signal provided by the driving power line and the potential of the second node.

[0010] In the pixel circuit of at least two pixels, the pixel circuits of the at least two pixels share one of the switch circuits.

[0011] Optionally, the plurality of pixel arrays are arranged; in at least one row of pixels, the pixel circuits of at least two pixels share one of the switch circuits.

[0012] Optionally, in one row of pixels, the pixel circuits of a part of pixels and the pixel circuits of another part of pixels share different switch circuits respectively, and the different switch circuits are located on two sides of the one row of pixels in the pixel row direction.

[0013] Optionally, the substrate has a display area and an edge area at least partially surrounding the display area.

[0014] The switch circuit shared by the pixel circuits of the at least two pixels is located in the edge area or in the display area.

[0015] Optionally, the display panel further comprises a gate drive circuit located on one side of the substrate and in the edge area, the gate drive circuit being coupled with the gate line and configured to provide the gate drive signal to the gate line.

[0016] The switch circuit shared by the pixel circuits of the at least two pixels is located in the edge area and located on a side of the gate drive circuit close to the display area or on a side of the gate drive circuit away from the display area.

[0017] Optionally, the switch circuit comprises a switch transistor.

[0018] A gate of the switch transistor is coupled with the switch control line, a first pole of the switch transistor is coupled with the reference power supply line, and a second pole of the switch transistor is coupled with the first node.

[0019] Optionally, the switch circuit comprises a first switch transistor and a second switch transistor; and the switch control line comprises a first switch control line and a second switch control line.

[0020] A gate of the first switch transistor and a gate of the second switch transistor are coupled with the first switch control line and the second switch control line respectively, a first pole of the first switch transistor and a first pole of the second switch transistor are coupled with the reference power supply line, and a second pole of the first switch transistor and a second pole of the second switch transistor are coupled with the first node.

[0021] Optionally, the control circuit is further coupled between the driving power supply line and the input end of the driving circuit, and is further coupled with a second light-emitting control line and configured to control the driving power supply line and the input end of the driving circuit in response to a second light-emitting control signal provided by the second light-emitting control line; and the control circuit comprises:

[0022] An adjusting sub-circuit is coupled with the first node, the second node and the third node respectively, and configured to adjust a potential of the third node based on the reference power supply signal when the reference power supply line and the first node are turned on, and adjust a potential of the second node;

[0023] A data writing sub-circuit is coupled with the gate line, the data line and the second node respectively, and configured to control the data line and the second node in response to the gate driving signal;

[0024] A first light-emitting control sub-circuit is coupled with the first light-emitting control line, the third node and the fourth node respectively, and configured to control the third node and the fourth node in response to the first light-emitting control signal;

[0025] A second light-emitting control sub-circuit is coupled with the second light-emitting control line, the driving power supply line and the input end of the driving circuit respectively, and configured to control the driving power supply line and the input end of the driving circuit in response to the second light-emitting control signal.

[0026] Optionally, the adjusting sub-circuit comprises a first capacitor and a second capacitor; the data writing sub-circuit comprises a data writing transistor; the first light-emitting control sub-circuit comprises a first light-emitting control transistor; and the second light-emitting control sub-circuit comprises a second light-emitting control transistor.

[0027] a first plate of the first capacitor is coupled with the second node, and a second plate of the first capacitor is coupled with the third node;

[0028] a first plate of the second capacitor is coupled with the first node, and a second plate of the second capacitor is coupled with the third node;

[0029] a gate of the data write transistor is coupled with the gate line, a first electrode of the data write transistor is coupled with the data line, and a second electrode of the data write transistor is coupled with the second node;

[0030] a gate of the first light emitting control transistor is coupled with the first light emitting control line, a first electrode of the first light emitting control transistor is coupled with the third node, and a second electrode of the first light emitting control transistor is coupled with the fourth node;

[0031] a gate of the second light emitting control transistor is coupled with the second light emitting control line, a first electrode of the second light emitting control transistor is coupled with the driving power line, and a second electrode of the second light emitting control transistor is coupled with the input terminal of the driving circuit.

[0032] Optionally, the pixel circuit further comprises:

[0033] a first reset circuit, coupled with a first reset line, a first initial power line, and at least one target node of the third node and the fourth node respectively, and configured to control the first initial power line and the at least one target node in response to a first reset signal provided by the first reset line;

[0034] a second reset circuit, coupled with a second reset line, a reference power line, and the second node respectively, and configured to control the reference power line and the second node in response to a second reset signal provided by the second reset line.

[0035] Optionally, the first reset circuit comprises a first reset transistor, and the second reset circuit comprises a second reset transistor;

[0036] a gate of the first reset transistor is coupled with the first reset line, a first electrode of the first reset transistor is coupled with the first initial power line, and a second electrode of the first reset transistor is coupled with the at least one target node;

[0037] a gate of the second reset transistor is coupled with the second reset line, a first electrode of the second reset transistor is coupled with the reference power line, and a second electrode of the second reset transistor is coupled with the second node.

[0038] Optionally, in the case that the target node is the fourth node, the pixel circuit further comprises:

[0039] a third reset circuit coupled with the first reset line, the second initial power supply line and the third node respectively, and configured to control the second initial power supply line and the third node in response to the first reset signal.

[0040] Optionally, the third reset circuit comprises a third reset transistor.

[0041] a gate of the third reset transistor is coupled with the first reset line, a first pole of the third reset transistor is coupled with the second initial power supply line, and a second pole of the third reset transistor is coupled with the third node.

[0042] Optionally, the switch control line is shared by the gate line, the first reset line or the second reset line.

[0043] Optionally, the reference power supply line is shared by the driving power supply line, the reference power supply line, the first initial power supply line or the second initial power supply line.

[0044] Optionally, the driving circuit comprises a driving transistor.

[0045] a gate of the driving transistor is coupled with the second node as a control terminal of the driving circuit, a first pole of the driving transistor is coupled with the driving power supply line as an input terminal of the driving circuit, and a second pole of the driving transistor is coupled with the third node as an output terminal of the driving circuit.

[0046] In another aspect, a driving method of a pixel circuit in a display panel is provided, which is applied to the pixel circuit of the display panel as described in the above aspect; the method comprises:

[0047] in a non-emitting stage, a switch control signal provided by the switch control line has a first potential, the switch circuit controls the reference power supply line and the first node to be conductive in response to the switch control signal with the first potential, and the control circuit adjusts the potential of the third node and the potential of the second node based on a reference power signal provided by the reference power supply line;

[0048] in an emitting stage, a switch control signal provided by the switch control line has a second potential, and the switch circuit controls the reference power supply line and the first node to be decoupled in response to the switch control signal with the second potential.

[0049] In still another aspect, a display device is provided, which comprises a power supply assembly and the display panel as described in the above aspect.

[0050] The power supply assembly is coupled with the display panel and configured to supply power for the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0052] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0053] FIG. 2 is a structural schematic diagram of a pixel in a display panel according to an embodiment of the present application;

[0054] FIG. 3 is a structural schematic diagram of a pixel in another display panel according to an embodiment of the present application;

[0055] FIG. 4 is a structural schematic diagram of a pixel in yet another display panel according to an embodiment of the present application;

[0056] FIG. 5 is a structural schematic diagram of a pixel in still another display panel according to an embodiment of the present application;

[0057] FIG. 6 is a structural schematic diagram of a pixel in still another display panel according to an embodiment of the present application;

[0058] FIG. 7 is a circuit structural schematic diagram of a pixel in a display panel according to an embodiment of the present application;

[0059] FIG. 8 is a circuit structural schematic diagram of a pixel in another display panel according to an embodiment of the present application;

[0060] FIG. 9 is a circuit structural schematic diagram of a pixel in yet another display panel according to an embodiment of the present application;

[0061] FIG. 10 is a circuit structural schematic diagram of a pixel in still another display panel according to an embodiment of the present application;

[0062] FIG. 11 is a circuit structural schematic diagram of a pixel in still another display panel according to an embodiment of the present application;

[0063] FIG. 12 is a circuit structural schematic diagram of a pixel in still another display panel according to an embodiment of the present application;

[0064] FIG. 13 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present application;

[0065] FIG. 14 is a signal timing diagram of a pixel circuit according to an embodiment of the present application;

[0066] FIG. 15 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0068] It can be understood that the transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present application are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable, and the source is referred to as the first pole and the drain is referred to as the second pole, or the drain is referred to as the first pole and the source is referred to as the second pole. According to the mode in the drawings, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present application can include any one of a P-type transistor and an N-type transistor or a combination thereof. Among them, the P-type transistor is turned on when the gate is low voltage, and is turned off when the gate is high voltage, and the N-type transistor is turned on when the gate is high voltage, and is turned off when the gate is low voltage. In addition, the plurality of signals in each embodiment correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent that the first potential or the second potential has a specific value.

[0069] For the pixel circuit, due to the influence of the capacitive coupling effect therein, when driving the light emitting element to emit light, the potentials of the control end and the output end of the driving circuit change unequally. In this way, the light emitting driving signal transmitted by the driving circuit is also offset, so that the light emitting element cannot be reliably driven to emit light, and the display quality of the display panel is deteriorated.

[0070] Based on this, the embodiments of the present application provide a display panel, which can solve the problem of deterioration of the display quality of the display panel caused by the offset of the light emitting driving signal transmitted by the driving circuit in the related art. FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application. As shown in FIG. 1, the display panel includes a substrate 10 and a plurality of pixels 00 located on one side of the substrate 10. Based on FIG. 1, a structural schematic diagram of a pixel shown in FIG. 2 can be seen that each pixel 00 includes a pixel circuit 01 and a light emitting element 02, and the pixel circuit 01 includes a switching circuit 011, a control circuit 012 and a driving circuit 013.

[0071] The switch circuit 011 is coupled (i.e., electrically connected) to the switch control line VC(k), the reference power supply line V1 and the first node N1, respectively. The switch circuit 011 is configured to control the connection between the reference power supply line V1 and the first node N1 in response to a switch control signal provided by the switch control line VC(k).

[0072] For example, the switch circuit 011 is configured to control the connection between the reference power supply line V1 and the first node N1 to be connected when the switch control signal provided by the switch control line VC(k) has a first potential, so that the reference power signal provided by the reference power supply line V1 can be transmitted to the first node N1. In addition, the switch circuit 011 is configured to control the connection between the reference power supply line V1 and the first node N1 to be disconnected when the switch control signal provided by the switch control line VC(k) has a second potential, so that the first node N1 is in a floating state.

[0073] Optionally, the first potential can be an active potential, the second potential can be an inactive potential, and the first potential can be a high potential relative to the second potential. Thus, it can be known that the transistor in the pixel circuit provided by the embodiment of the present application can be an N-type transistor with a high active potential. Of course, in some other embodiments, the first potential can be a low potential relative to the second potential, and the corresponding transistor can be a P-type transistor with a low active potential. The following embodiments are the same, and will not be described one by one.

[0074] The control circuit 012 is coupled to the gate line Gate(k), the data line Dj, the first light-emitting control line EM1(k), the first node N1, the second node N2, the third node N3 and the fourth node N4, respectively. The control circuit 012 is configured to adjust the potential of the third node N3 based on the reference power signal provided by the reference power supply line V1 when the reference power supply line V1 and the first node N1 are connected, and adjust the potential of the second node N2, for controlling the connection between the data line Dj and the second node N2 in response to the gate drive signal provided by the gate line Gate(k), and for controlling the connection between the third node N3 and the fourth node N4 in response to the first light-emitting control signal provided by the first light-emitting control line EM1(k).

[0075] The fourth node N4 is coupled to the first pole of the light-emitting element 02, and the second pole of the light-emitting element 02 is coupled to the pull-down power supply line ELVSS. Optionally, the light-emitting element 02 can be an organic light-emitting diode (OLED), the first pole of the light-emitting element 02 can be an anode, and the second pole of the light-emitting element 02 can be a cathode. Of course, the anode and the cathode can be interchanged.

[0076] For example, the control circuit 012 can control the data line Dj to be coupled to the second node N2 when the gate drive signal provided by the gate line Gate(k) has the first potential, so that the data signal provided by the data line Dj can be transmitted to the second node N2. Also, the control circuit 012 can control the data line Dj to be decoupled from the second node N2 when the gate drive signal provided by the gate line Gate(k) has the second potential.

[0077] Similarly, the control circuit 012 can control the third node N3 to be coupled to the fourth node N4 when the first emission control signal provided by the first emission control line EM1(k) has the first potential, so that the signal transmitted to the third node N3 can be further transmitted to the fourth node N4, and thus to the first electrode of the light emitting element 02. Also, the control circuit 012 can control the third node N3 to be decoupled from the fourth node N4 when the first emission control signal provided by the first emission control line EM1(k) has the second potential.

[0078] In addition, the control circuit 012 can adjust the potential of the third node N3 based on the reference power signal provided by the reference power line V1 when the reference power line V1 is coupled to the first node N1, and adjust the potential of the second node N2.

[0079] The control terminal of the drive circuit 013 is coupled to the second node N2, the input terminal of the drive circuit 013 is coupled to the drive power line ELVDD, and the output terminal of the drive circuit 013 is coupled to the third node N3. The drive circuit 013 is configured to transmit a light emitting drive signal to the third node N3 based on the drive power signal provided by the drive power line ELVDD and the potential of the second node N2.

[0080] On this basis, when the control circuit 012 controls the third node N3 to be coupled to the fourth node N4 (i.e., the first electrode of the light emitting element 02), the light emitting drive signal transmitted to the third node N3 by the drive circuit 013 can be further transmitted to the first electrode of the light emitting element 02. In turn, the light emitting element 02 can emit light under the action of the potential difference between the light emitting drive signal received by the first electrode and the pull-down power signal provided by the pull-down power line ELVSS received by the second electrode. At this time, it can be considered that a path is formed between the drive power line ELVDD and the pull-down power line ELVSS. It can be understood that, for the scenario in which the light emitting element 02 is an OLED, the light emitting drive signal can refer to a drive current. The drive circuit 013 generally includes a drive transistor.

[0081] Optionally, the driving power signal provided by the driving power line ELVDD can have a high potential, and the pull-down power signal provided by the pull-down power line ELVSS can have a low potential. Here, the high potential and the low potential are relative. Moreover, the reference power line V1 and the driving power line ELVDD can be shared.

[0082] In some embodiments, the pixel circuit 01 does not include the switch circuit 011, i.e., the control circuit 012 adjusts the potential of the third node N3 based on the reference power signal provided by the reference power line V1 (e.g., the driving power signal provided by the driving power line ELVDD) at any time. However, in the light emitting stage in which the driving circuit 013 drives the light emitting element 02 to emit light, the voltage on the signal line (e.g., the data line Dj) will be coupled to the second node N2, while the potential of the third node N3 will not change by the same amount. Thus, the potential difference between the control terminal and the output terminal of the driving circuit 013 cannot be maintained, i.e., the gate-source voltage difference Vgs of the driving transistor included in the driving circuit 013 cannot be maintained. Further, this can cause the driving current transmitted by the driving circuit 013 to the light emitting element 02 to deviate or drift, which cannot reliably drive the light emitting element 02 to emit light, and which can degrade the display quality of the display panel.

[0083] In the embodiments of the present application, however, the pixel circuit 01 includes the switch circuit 011, and the switch circuit 011 is configured to control the connection / disconnection between the reference power line V1 and the first node N1 in response to the switch control signal provided by the switch control line VC(k). Thus, the switch control signal can be flexibly set, e.g., the potential of the switch control signal can be set to the second potential in the light emitting stage, so that the switch circuit 011 controls the disconnection between the reference power line V1 and the first node N1, i.e., the first node N1 is in a floating state, which ensures that the potential of the second node N2 changes by the same amount as the potential of the third node N3, and further ensures that the driving current transmitted by the driving circuit 013 to the light emitting element 02 is stable, which reliably drives the light emitting element 02 to emit light, and which can improve the display quality of the display panel.

[0084] In addition, in the embodiments of the present application, as shown in FIG. 2, the pixel circuits 01 of at least two pixels can share the same switch circuit 011. For example, referring to FIG. 2, it is schematically shown that the pixel circuits 01 of two pixels located in the same row and adjacent to each other share the same switch circuit 011. Thus, the structure can be simplified, which is conducive to the improvement of the display panel PPI. Here, PPI refers to the number of pixels per inch of the display panel, which is used to represent the resolution of the display panel. That is, the display panel provided by the embodiments of the present application not only has good display quality, but also has greatly improved PPI.

[0085] It can be understood that the plurality of pixels 00 can be arranged in an array as shown in FIG. 1. Correspondingly, k in the embodiments of the present application can refer to the kth row, and k can be greater than or equal to 1 and less than or equal to the total number of rows of pixels. For example, assuming that the display panel includes 1000 rows of pixels, k can be greater than or equal to 1 and less than or equal to 1000. j can refer to the jth column, and j can be greater than or equal to 1 and less than or equal to the total number of columns of pixels. For example, assuming that the display panel includes 2000 columns of pixels, j can be greater than or equal to 1 and less than or equal to 2000.

[0086] In summary, the embodiments of the present application provide a display panel. The display panel includes a plurality of pixels, and the pixel circuit of each pixel includes a switching circuit, a control circuit and a driving circuit. The switching circuit can control the conduction between the reference power supply line and the first node under the control of the switching control signal. The control circuit can adjust the potential of the third node based on the reference power supply signal provided by the reference power supply line when the switching circuit controls the conduction between the reference power supply line and the first node, and adjust the potential of the second node. In addition, the control circuit can cooperate with the driving circuit to transmit a light-emitting driving signal to the light-emitting element to drive the light-emitting element to emit light. In this way, the switching control signal can be flexibly set, so that when the light-emitting element is driven to emit light, the switching circuit can control the disconnection of the reference power supply line and the first node, thereby making the potential change of the control end and the output end of the driving circuit equal, avoiding the shift of the light-emitting driving signal transmitted by the driving circuit, and ensuring reliable driving of the light-emitting element to emit light. That is, the display effect of the display panel can be ensured to be good.

[0087] In addition, in the embodiments of the present application, because the pixel circuits of at least two pixels share the same switching circuit, the pixel circuit structure can be simplified, so that the display effect of the display panel is ensured to be good, and the resolution of the display panel can be high, that is, the resolution of the display panel can be greatly improved.

[0088] Optionally, as can be seen in combination with FIG. 1, the plurality of pixels 00 described in the embodiments of the present application can be arranged in an array. That is, the display panel can include a plurality of rows and a plurality of columns of pixels 00.

[0089] On this basis, as can be seen in combination with FIG. 2, in the embodiments of the present application, the pixel circuits 01 of at least two pixels 00 in at least one row of pixels 00 can share the same switching circuit 011. Of course, in some other embodiments, the pixel circuits 01 of two or more rows of pixels 00 can share the same switching circuit 011, and the pixel circuits 01 of two or more columns of pixels 00 can also share the same switching circuit 011.

[0090] Optionally, for one row of pixels 00, the pixel circuits 01 of a part of the pixels 00 and the pixel circuits 01 of another part of the pixels 00 can share different switch circuits 011 respectively, and the different switch circuits 011 can be located at two sides of the one row of pixels 00 in the pixel row direction. That is, in combination with FIG. 1, for one row of pixels 00, one switch circuit 011 can be arranged at each of the left and right edges of the substrate 10 in the display panel, so as to be shared by a part of the pixels 00 and another part of the pixels 00 in the one row of pixels 00. In this way, compared with the pixel circuits 01 in one row of pixels 00 sharing the switch circuit 011 located at one side, the problem of large parasitic capacitance and poor signal transmission accuracy caused by too long connection line can be avoided.

[0091] It can be understood that one row of pixels 00 can be divided into a left half part of pixels 00 close to the left edge and a right half part of pixels 00 close to the right edge. The pixel circuits 01 of the left half part of pixels 00 can share the switch circuit 011 arranged at the left edge, and the pixel circuits 01 of the right half part of pixels 00 can share the switch circuit 011 arranged at the right edge. In this way, the wiring can be facilitated to be simplified.

[0092] Optionally, in one row of pixels 00, the number of a part of the pixels 00 sharing different switch circuits 011 and another part of the pixels 00 can be the same. That is, assuming that one row of pixels 00 includes 1000 pixels, 500 pixels in the left half part can be taken as a part of the pixels 00, and the pixel circuits 01 thereof can share the switch circuit 011 arranged at the left edge; and 500 pixels in the right half part can be taken as another part of the pixels 00, and the pixel circuits 01 thereof can share the switch circuit 011 arranged at the right edge.

[0093] Optionally, in combination with FIG. 2, the substrate 10 can have a display area A1 and an edge area A2 at least partially surrounding the display area A1.

[0094] In the embodiment of the present application, the switch circuit 011 shared by the pixel circuits 01 of at least two pixels 00 can be located in the edge area A2. In this way, the display area A1 can not have the switch circuit 011 and the switch control line VC(k) connected thereto, and the PPI of the display area A1 in the display panel can be further improved. Of course, in some embodiments, the shared switch circuit 011 can also be located in the display area A1.

[0095] It can be understood that the edge area A2 here does not mean that no light emitting element 02 is arranged.

[0096] Optionally, the display panel can further include a gate driving circuit on one side of the substrate 10 and in the edge area A2, also referred to as GOA circuit. The GOA circuit can be coupled with the gate line Gate(k) and can be configured to provide a gate driving signal to the gate line Gate(k). Herein, GOA refers to gate driver on array (GOA) technology.

[0097] The switch circuit 011 shared by the pixel circuits 01 of the at least two pixels 00 can be located in the edge area A2 and can be located on the side of the GOA circuit close to the display area A1 or can be located on the side of the GOA circuit away from the display area A1. That is, the edge area A2 where the switch circuit 011 is located can refer to the area between the GOA circuit and the display area A1, or can refer to any area between the display area A1 and the edge of the display panel, such as the area on the side of the GOA circuit away from the display area A1.

[0098] Optionally, the control circuit 012 according to the embodiments of the present application can be further coupled between the driving power supply line ELVDD and the input end of the driving circuit 013, and can be further coupled with the second light emitting control line EM2(k) and can be configured to control the on-off of the driving power supply line ELVDD and the input end of the driving circuit 013 in response to the second light emitting control signal provided by the second light emitting control line EM2(k).

[0099] For example, the control circuit 012 can control the driving power supply line ELVDD and the input end of the driving circuit 013 to be conductive when the potential of the second light emitting control signal provided by the second light emitting control line EM2(k) is the first potential, so that the driving power signal provided by the driving power supply line ELVDD can be transmitted to the input end of the driving circuit 013. In addition, the control circuit 012 can control the driving power supply line ELVDD and the input end of the driving circuit 013 to be decoupled when the potential of the second light emitting control signal provided by the second light emitting control line EM2(k) is the second potential.

[0100] On this basis, FIG. 3 shows a structural schematic diagram of another pixel. As shown in FIG. 3, the control circuit 012 can include an adjusting sub-circuit 0121, a data writing sub-circuit 0122, a first light emitting control sub-circuit 0123 and a second light emitting control sub-circuit 0124.

[0101] The adjusting sub-circuit 0121 can be coupled with the first node N1, the second node N2 and the third node N3 respectively. The adjusting sub-circuit 0121 can be configured to adjust the potential of the third node N3 and the potential of the second node N2 based on the reference power signal when the reference power supply line V1 and the first node N1 are conductive.

[0102] It can be understood that the two adjusting sub-circuits 0121 shown in FIG. 3 only represent parts of the adjusting sub-circuit 0121 at different positions, and do not represent that the pixel circuit includes two adjusting sub-circuits 0121.

[0103] The data writing sub-circuit 0122 can be coupled with the gate line Gate(k), the data line Dj and the second node N2 respectively. The data writing sub-circuit 0122 can be configured to control the data line Dj and the second node N2 to be connected or disconnected in response to the gate driving signal.

[0104] For example, the data writing sub-circuit 0122 can control the data line Dj and the second node N2 to be connected when the potential of the gate driving signal is the first potential, and can control the data line Dj and the second node N2 to be disconnected when the potential of the gate driving signal is the second potential.

[0105] The first light emitting control sub-circuit 0123 can be coupled with the first light emitting control line EM1(k), the third node N3 and the fourth node N4 respectively. The first light emitting control sub-circuit 0123 can be configured to control the third node N3 and the fourth node N4 to be connected or disconnected in response to the first light emitting control signal.

[0106] For example, the first light emitting control sub-circuit 0123 can control the third node N3 and the fourth node N4 to be connected when the potential of the first light emitting control signal is the first potential, and can control the third node N3 and the fourth node N4 to be disconnected when the potential of the first light emitting control signal is the second potential.

[0107] The second light emitting control sub-circuit 0124 can be coupled with the second light emitting control line EM2(k), the driving power supply line ELVDD and the input end of the driving circuit 013 respectively. The second light emitting control sub-circuit 0124 can be configured to control the driving power supply line ELVDD and the input end of the driving circuit 013 to be connected or disconnected in response to the second light emitting control signal.

[0108] For example, the second light emitting control sub-circuit 0124 can control the driving power supply line ELVDD and the input end of the driving circuit 013 to be connected when the potential of the second light emitting control signal is the first potential, and can control the driving power supply line ELVDD and the input end of the driving circuit 013 to be disconnected when the potential of the second light emitting control signal is the second potential.

[0109] Of course, in some other embodiments, the control circuit 012 can also not include the second light emitting control sub-circuit 0124. That is, as shown in FIG. 2, the input end of the driving circuit 013 can be directly coupled with the driving power supply line ELVDD.

[0110] Optionally, FIG. 4 is a structure diagram of another pixel according to an embodiment of the present application. FIG. 5 is a structure diagram of another pixel according to an embodiment of the present application. As shown in FIG. 4 and FIG. 5, the pixel circuit 01 can further include a first reset circuit 014 and a second reset circuit 015.

[0111] The first reset circuit 014 can be coupled to the first reset line Reset1(k), the first initial power supply line Vint1, and at least one target node of the third node N3 and the fourth node N4, respectively. The first reset circuit 014 can be configured to control the first initial power supply line Vint1 to be connected or disconnected to the at least one target node in response to a first reset signal provided by the first reset line Reset1(k).

[0112] For example, the first reset circuit 014 can control the first initial power supply line Vint1 to be connected to the at least one target node when the first reset signal provided by the first reset line Reset1(k) has a first potential, so that a first initial power signal provided by the first initial power supply line Vint1 can be transmitted to the at least one target node to reset the at least one target node. In addition, the first reset circuit 014 can control the first initial power supply line Vint1 to be disconnected from the at least one target node when the first reset signal provided by the first reset line Reset1(k) has a second potential.

[0113] Optionally, referring to FIG. 4, the first reset circuit 014 is coupled to the third node N3 in the pixel shown in FIG. 4, that is, the target node is the third node N3 of the third node N3 and the fourth node N4. Referring to FIG. 5, the first reset circuit 014 is coupled to the fourth node N4 in the pixel shown in FIG. 5, that is, the target node is the fourth node N4 of the third node N3 and the fourth node N4. Of course, in some embodiments, the first reset circuit 014 can be coupled to both the third node N3 and the fourth node N4, that is, the target node can include the third node N3 and the fourth node N4.

[0114] The second reset circuit 015 can be coupled to the second reset line Reset2(k), the reference power supply line Vref, and the second node N2, respectively. The second reset circuit 015 can be configured to control the reference power supply line Vref to be connected or disconnected to the second node N2 in response to a second reset signal provided by the second reset line Reset2(k).

[0115] For example, the second reset circuit 015 can control the reference power supply line Vref to be coupled to the second node N2 when the potential of the second reset signal provided by the second reset line Reset2(k) is the first potential, so that the reference power signal provided by the reference power supply line Vref can be transmitted to the second node N2 to reset the second node N2. In addition, the second reset circuit 015 can control the reference power supply line Vref to be decoupled from the second node N2 when the potential of the second reset signal provided by the second reset line Reset2(k) is the second potential.

[0116] Optionally, based on FIG. 5, in the case that the target node is the fourth node N4, in some embodiments, another structure diagram of a pixel circuit can be seen from FIG. 6, which shows that the pixel circuit 01 can further include a third reset circuit 016.

[0117] The third reset circuit 016 can be coupled to the first reset line Reset1(k), the second initial power supply line Vint2 and the third node N3 respectively. The third reset circuit 016 can be configured to control the second initial power supply line Vint2 to be coupled to or decoupled from the third node N3 in response to the first reset signal.

[0118] For example, the third reset circuit 016 can control the second initial power supply line Vint2 to be coupled to the third node N3 when the potential of the first reset signal is the first potential, so that the second initial power signal provided by the second initial power supply line Vint2 can be transmitted to the third node N3 to reset the third node N3. In addition, the third reset circuit 016 can control the second initial power supply line Vint2 to be decoupled from the third node N3 when the potential of the first reset signal is the second potential.

[0119] Of course, in some other embodiments, the pixel circuit 01 can also not include the third reset circuit 016.

[0120] It can be understood that by setting the first reset circuit 014, the second reset circuit 015 and the third reset circuit 016, the corresponding nodes can be reset, so that each frame scanning can be started at the same potential, and the display uniformity of the display panel is ensured to be good.

[0121] Optionally, based on FIG. 4, FIG. 7 shows a structure diagram of a pixel circuit. Based on FIG. 5, FIG. 8 shows another structure diagram of a pixel circuit. In addition, based on FIG. 6, FIG. 9 shows another structure diagram of a pixel circuit.

[0122] As can be seen from FIGS. 7 to 9, the switch circuit 011 can include a switch transistor Tvc.

[0123] The gate of the switch transistor Tvc can be coupled with a switch control line VC(k), the first pole of the switch transistor Tvc can be coupled with a reference power supply line V1, and the second pole of the switch transistor Tvc can be coupled with the first node N1.

[0124] With continuous reference to FIGS. 7-9, it can be seen that the adjusting sub-circuit 0121 can include a first capacitor C1 and a second capacitor C2. The data writing sub-circuit 0122 can include a data writing transistor T1. The first light emitting control sub-circuit 0123 can include a first light emitting control transistor T2. The second light emitting control sub-circuit 0124 can include a second light emitting control transistor T3.

[0125] The first pole plate of the first capacitor C1 can be coupled with the second node N2, and the second pole plate of the first capacitor C1 can be coupled with the third node N3.

[0126] The first pole plate of the second capacitor C2 can be coupled with the first node N1, and the second pole plate of the second capacitor C2 can be coupled with the third node N3.

[0127] That is, in the embodiment of the present application, the first pole plates of the second capacitors C2 in the pixel circuits 01 of the at least two pixels 00 can be connected together, that is, connected to the first node N1. At the same time, the switch transistor Tvc responsible for disconnecting the reference power supply line V1 can be arranged in the edge area A2.

[0128] The gate of the data writing transistor T1 can be coupled with a gate line Gate(k), the first pole of the data writing transistor T1 can be coupled with a data line Dj, and the second pole of the data writing transistor T1 can be coupled with the second node N2.

[0129] The gate of the first light emitting control transistor T2 can be coupled with a first light emitting control line EM1(k), the first pole of the first light emitting control transistor T2 can be coupled with the third node N3, and the second pole of the first light emitting control transistor T2 can be coupled with a fourth node N4.

[0130] The gate of the second light emitting control transistor T3 can be coupled with a second light emitting control line EM2(k), the first pole of the second light emitting control transistor T3 can be coupled with a driving power supply line ELVDD, and the second pole of the second light emitting control transistor T3 can be coupled with an input end of the driving circuit 013.

[0131] With continuous reference to FIGS. 7-9, it can be seen that the first reset circuit 014 can include a first reset transistor T4. The second reset circuit 015 can include a second reset transistor T5.

[0132] The gate of the first reset transistor T4 can be coupled with the first reset line Reset1(k), the first pole of the first reset transistor T4 can be coupled with the first initial power supply line Vint1, and the second pole of the first reset transistor T4 can be coupled with at least one target node.

[0133] It can be understood that for the structure shown in FIG. 4 in which the target node is the third node N3, referring to FIG. 7, the second pole of the first reset transistor T4 can be coupled with the third node N3. For the structures shown in FIG. 5 and FIG. 6 in which the target node is the fourth node N4, referring to FIG. 8 and FIG. 9, the second pole of the first reset transistor T4 can be coupled with the fourth node N4.

[0134] The gate of the second reset transistor T5 can be coupled with the second reset line Reset2(k), the first pole of the second reset transistor T5 can be coupled with the reference power supply line Vref, and the second pole of the second reset transistor T5 can be coupled with the second node N2.

[0135] Continuing to refer to FIG. 9, it can be seen that the third reset circuit 016 can include a third reset transistor T6.

[0136] The gate of the third reset transistor T6 can be coupled with the first reset line Reset1(k), the first pole of the third reset transistor T6 can be coupled with the second initial power supply line Vint2, and the second pole of the third reset transistor T6 can be coupled with the third node N3.

[0137] Continuing to refer to FIG. 7 to FIG. 9, it can be seen that the driving circuit 013 can include a driving transistor T7.

[0138] The gate of the driving transistor T7 can be coupled with the second node N2 as the control terminal of the driving circuit 013, the first pole of the driving transistor T7 can be coupled with the driving power supply line ELVDD as the input terminal of the driving circuit 013, and the second pole of the driving transistor T7 can be coupled with the third node N3 as the output terminal of the driving circuit 013.

[0139] It can be understood that since the pixels shown in FIG. 4 to FIG. 6 all include the second light-emitting control transistor T3, as shown in FIG. 7 to FIG. 9, the first pole of the driving transistor T7 can be coupled with the second pole of the second light-emitting control transistor T3 to indirectly couple with the driving power supply line ELVDD through the second light-emitting control transistor T3. In addition, as described above, in some embodiments, the second light-emitting control transistor T3 can not be included.

[0140] Optionally, based on FIG. 5, FIG. 10 shows another schematic circuit structure diagram of a pixel. As shown in FIG. 10, the switch circuit 011 can include a first switch transistor Tvc1 and a second switch transistor Tvc2. Correspondingly, the switch control line VC(k) can include a first switch control line VC(k)1 and a second switch control line VC(k)2.

[0141] The gate of the first switch transistor Tvc1 and the gate of the second switch transistor Tvc2 can be coupled with the first switch control line VC(k)1 and the second switch control line VC(k)2 respectively, the first pole of the first switch transistor Tvc1 and the first pole of the second switch transistor Tvc2 can be coupled with the reference power supply line V1, and the second pole of the first switch transistor Tvc1 and the second pole of the second switch transistor Tvc2 can be coupled with the first node N1.

[0142] That is, as an optional implementation manner, the switch circuit 011 can include one switch transistor Tvc as shown in FIGS. 7 to 9; as another optional implementation manner, the switch circuit 011 can include a group of parallel switch transistors Tvc as shown in FIG. 10.

[0143] It can be understood that FIGS. 7 to 10 are all schematic circuit diagrams taking the switch circuit 011 located in the edge area A2 as an example. However, as described above, in some embodiments, the switch circuit 011 can also be located in the display area A1. Therefore, taking the structure shown in FIG. 8 as an example, FIG. 11 also schematically shows a schematic circuit structure diagram of a pixel whose switch transistor Tvc included in the switch circuit 011 is located in the display area A1. In addition, taking the structure shown in FIG. 8 as an example, FIG. 12 also schematically shows a schematic circuit structure diagram of a pixel whose first switch transistor Tvc1 and second switch transistor Tvc2 included in the switch circuit 011 are located in the display area A1.

[0144] Optionally, in the embodiments of the present application, the switch control line VC(k) can be shared with the gate line Gate(k), the first reset line Reset1(k) or the second reset line Reset2(k).

[0145] For example, referring to FIG. 10, the first switch control line VC(k)1 is shared with the gate line Gate(k), and the second switch control line VC(k)2 is shared with the second reset line Reset2(k).

[0146] In addition, referring to FIGS. 7 to 12, the reference power supply line V1 can be shared with the driving power supply line ELVDD, the reference power supply line Vref, the first initial power supply line Vint1 or the second initial power supply line Vint2.

[0147] By setting the signal lines in common, the number of signal providing circuits to be set can be reduced, the number of signal lines to be set can be reduced, thereby reducing the frame size of the display panel, and facilitating the design of narrow frame.

[0148] In combination with the drawings, the pixel circuit provided by the embodiments of the present application can be a 7T2C (i.e., 7 transistors and 2 capacitors) structure, except for the switch circuit 011. Of course, in some embodiments, the pixel circuit can also be other structures, such as 9T2C, provided that the 7T2C structure is included.

[0149] Alternatively, as shown in FIGS. 7-12, the transistors in the pixel circuit can all be N-type transistors. In addition, the transistors can be, for example, metal-oxide-semiconductor (MOS) field effect transistors, also known as MOS tubes. The N-type transistor can be referred to as an NMOS tube, and the pixel circuit including the NMOS tube can also be referred to as an NMOS pixel circuit. Correspondingly, the first potential of the effective potential can be a low potential relative to the second potential of the ineffective potential. Of course, in some other embodiments, the transistors in the pixel circuit can also all be N-type transistors, or can include both P-type transistors and N-type transistors.

[0150] Alternatively, the material of the active layer in the P-type transistor can be a P-type transistor of low temperature poly-silicon (LTPS) material. The material of the active layer in the N-type transistor can be an oxide material.

[0151] As can be understood in combination with FIG. 9, there is a first capacitor C1 between the second node N2 and the third node N3, and there is a second capacitor C2 between the third node N3 and the first node N1. When the driving transistor T7 transmits the driving current to the light emitting element 02 to drive the light emitting element 02 to emit light, the potential change on the signal line will be coupled to the second node N2, and due to the voltage division effect of the second capacitor C2, the potential on the third node N3 will not change by the same amount, and thus the gate-source voltage difference Vgs of the driving transistor T7 = VN2-VN3 cannot be maintained, where VN2 refers to the potential on the second node N2, and VN3 refers to the potential on the third node N3. In this way, the driving current changes, causing the display quality of the display panel to deteriorate.

[0152] In the embodiment of the present application, because the switch transistor Tvc is additionally arranged between the second capacitor C2 and the driving power supply line ELVDD, the second capacitor C2 and the driving power supply line ELVDD can be disconnected by the switch transistor Tvc when the light emitting element 02 emits light, that is, the first plate of the second capacitor C2 is in a floating state, the potential change of the second node N2 and the third node N3 is equal, the driving current is kept stable, and the display quality of the display panel is improved.

[0153] In addition, because the switch transistor Tvc and the switch control line VC(k) coupled thereto can be located in the edge area A2 of the substrate 10, and a plurality of pixel circuits can share the same switch transistor Tvc, the structure can be simplified, the PPI of the display panel can be improved, and the narrow frame design of the display panel is facilitated.

[0154] In summary, the embodiment of the present application provides a display panel. The display panel includes a plurality of pixels, and the pixel circuit of each pixel includes a switch circuit, a control circuit and a driving circuit. The switch circuit can control the connection and disconnection of the reference power supply line and the first node under the control of the switch control signal. The control circuit can adjust the potential of the third node based on the reference power supply signal provided by the reference power supply line when the switch circuit controls the reference power supply line and the first node to be connected, and adjust the potential of the second node. In addition, the control circuit can cooperate with the driving circuit to transmit the light emitting driving signal to the light emitting element to drive the light emitting element to emit light. In this way, the switch control signal can be flexibly set, so that the switch circuit can control the disconnection of the reference power supply line and the first node when the light emitting element emits light, so that the potential change of the control end and the output end of the driving circuit is equal, the light emitting driving signal transmitted by the driving circuit is prevented from being offset, and the light emitting element can be reliably driven to emit light. That is, the display effect of the display panel can be ensured to be good.

[0155] In addition, in the embodiment of the present application, because the pixel circuits of at least two pixels share the same switch circuit, the pixel circuit structure can be simplified, the display effect of the display panel can be ensured to be good, and the resolution of the display panel can be high, that is, the resolution of the display panel can be greatly improved.

[0156] The embodiment of the present application also provides a driving method of a pixel circuit in a display panel. The method can be applied to the pixel circuit of the display panel as described in the above embodiment. As shown in FIG. 13, the method includes:

[0157] In step 1301, in the non-light emitting stage, the switch control signal provided by the switch control line has a first potential, the switch circuit controls the reference power supply line to be connected to the first node in response to the switch control signal with the first potential, the control circuit adjusts the potential of the third node based on the reference power signal provided by the reference power supply line, and the potential of the second node is adjusted.

[0158] In step 1302, in the light emitting stage, the switch control signal provided by the switch control line has a second potential, the switch circuit controls the reference power supply line to be disconnected from the first node in response to the switch control signal with the second potential.

[0159] Optionally, taking the pixel circuit structure shown in FIG. 9 and the transistors in the pixel circuit as all NMOS transistors as an example, the driving method of the pixel circuit provided in the embodiment of the present application is described below in combination with the signal timing diagram shown in FIG. 14.

[0160] (1) In the t01 stage in the non-light emitting stage, the first reset signal provided by the first reset line Reset1(k) has a high potential, the second reset signal provided by the second reset line Reset2(k) has a high potential, and the switch control signal provided by the switch control line VC(k) has a high potential; while the first light emitting control signal provided by the first light emitting control line EM1(k) has a low potential, the second light emitting control signal provided by the second light emitting control line EM2(k) has a low potential, and the gate drive signal provided by the gate line Gate(k) has a low potential. Correspondingly, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, and the switch transistor Tvc are all turned on; and the data writing transistor T1, the first light emitting control transistor T2, and the second light emitting control transistor T3 are all turned off. Further, the first initial power supply line Vint1 is connected to the fourth node N4, the reference power supply line Vref is connected to the second node N2, the second initial power supply line Vint2 is connected to the third node N3, and the reference power supply line V1 is connected to the first node N1; and the data line Dj is disconnected from the second node N2, the driving power supply line ELVDD is disconnected from the first electrode of the driving transistor T7, and the third node N3 is disconnected from the fourth node N4.

[0161] On this basis, the first initial power supply signal provided by the first initial power supply line Vint1 can be further transmitted to the fourth node N4 through the turned-on first reset transistor T4 to reset or initialize the fourth node N4; the reference power supply signal provided by the reference power supply line Vref can be transmitted to the second node N2 through the turned-on second reset transistor T5 to reset the second node N2, so that the driving transistor T7 is initially turned on; the second initial power supply signal provided by the second initial power supply line Vint2 can be transmitted to the third node N3 through the turned-on third reset transistor T6 to reset the third node N3; and the reference power supply signal provided by the reference power supply line V1 can be transmitted to the first node N1 through the turned-on switch transistor Tvc. Correspondingly, the t01 stage can also be referred to as an initialization stage.

[0162] (2) In the t02 stage in the non-emitting phase, the potential of the second reset signal provided by the second reset line Reset2(k), the potential of the second emission control signal provided by the second emission control line EM2(k), and the potential of the switch control signal provided by the switch control line VC(k) can all be high potentials; while the potential of the first emission control signal provided by the first emission control line EM1(k), the potential of the first reset signal provided by the first reset line Reset1(k), and the potential of the gate drive signal provided by the gate line Gate(k) can all be low potentials. Correspondingly, the second emission control transistor T3, the second reset transistor T5, and the switch transistor Tvc can all be turned on; and the data write transistor T1, the first emission control transistor T2, the first reset transistor T4, and the third reset transistor T6 can all be turned off. In turn, the driving power supply line ELVDD and the first electrode of the driving transistor T7 can be connected, the reference power supply line Vref and the second node N2 can be connected, and the reference power supply line V1 and the first node N1 can be connected; and the data line Dj and the second node N2 can be disconnected, the third node N3 and the fourth node N4 can be disconnected, the first initial power supply line Vint1 and the fourth node N4 can be disconnected, and the second initial power supply line Vint2 and the third node N3 can be disconnected. In addition, under the storage action of the first capacitor C1, the potential of the second node N2 can remain the potential of the t01 stage, so that the driving transistor T7 remains turned on.

[0163] On this basis, the driving power signal provided by the driving power supply line ELVDD can be further transmitted to the driving transistor T7 through the turned-on second light emitting control transistor T3, and then transmitted to the second node N2 through the turned-on driving transistor T7, so that the threshold voltage Vth of the driving transistor T7 can be written into the second node N2, and the driving current transmitted to the light emitting element 02 by the driving transistor T7 can be irrelevant to the threshold voltage Vth, and the compensation of the threshold voltage Vth can be realized; and the reference power signal provided by the reference power supply line Vref can be continuously transmitted to the second node N2 through the turned-on second reset transistor T5, and the reference power signal provided by the reference power supply line V1 can be transmitted to the first node N1 through the turned-on switch transistor Tvc. Correspondingly, the t02 stage can also be referred to as a Vth compensation stage.

[0164] (3) In the t03 stage of the non-light emitting stage, the potential of the gate drive signal provided by the gate line Gate(k) and the potential of the switch control signal provided by the switch control line VC(k) can be high potentials; and the potential of the first light emitting control signal provided by the first light emitting control line EM1(k), the potential of the second reset signal provided by the second reset line Reset2(k), the potential of the second light emitting control signal provided by the second light emitting control line EM2(k), and the potential of the first reset signal provided by the first reset line Reset1(k) can be low potentials. Correspondingly, the data write transistor T1 and the switch transistor Tvc can be turned on; and the first light emitting control transistor T2, the second light emitting control transistor T3, the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 can be turned off. Further, the data line Dj and the second node N2 can be connected, and the reference power supply line V1 and the first node N1 can be connected; and the third node N3 and the fourth node N4 can be disconnected, the driving power supply line ELVDD and the first electrode of the driving transistor T7 can be disconnected, the first initial power supply line Vint1 and the fourth node N4 can be disconnected, the reference power supply line Vref and the second node N2 can be disconnected, and the second initial power supply line Vint2 and the third node N3 can be disconnected. In addition, under the storage action of the first capacitor C1, the potential of the second node N2 can remain the potential of the t02 stage, so that the driving transistor T7 remains turned on.

[0165] On this basis, the data signal provided by the data line Dj can be further transmitted to the second node N2 through the turned-on data write transistor T1, and the reference power signal provided by the reference power supply line V1 can be transmitted to the first node N1 through the turned-on switch transistor Tvc. Correspondingly, the t03 stage can also be referred to as a signal write stage.

[0166] (4) In the light emitting stage, the potential of the first light emitting control signal provided by the first light emitting control line EM1(k) and the potential of the second light emitting control signal provided by the second light emitting control line EM2(k) can both be high potentials; and the potential of the second reset signal provided by the second reset line Reset2(k), the potential of the first reset signal provided by the first reset line Reset1(k), the potential of the gate driving signal provided by the gate line Gate(k), and the potential of the switch control signal provided by the switch control line VC(k) can all be low potentials. Correspondingly, the first light emitting control transistor T2 and the second light emitting control transistor T3 can both be turned on; and the data writing transistor T1, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, and the switch transistor Tvc can all be turned off. Further, the driving power supply line ELVDD and the first electrode of the driving transistor T7 can be connected, and the third node N3 and the fourth node N4 can be connected; and the data line Dj and the second node N2 can be disconnected, the first initial power supply line Vint1 and the fourth node N4 can be disconnected, the reference power supply line Vref and the second node N2 can be disconnected, the second initial power supply line Vint2 and the third node N3 can be disconnected, and the reference power supply line V1 and the first node N1 can be disconnected. In addition, under the coupling effect of the first capacitor C1, the potential of the second node N2 can be raised, so that the driving transistor T7 is fully turned on.

[0167] On this basis, the driving power supply signal provided by the driving power supply line ELVDD can be transmitted to the first electrode of the driving transistor T7 through the turned-on second light emitting control transistor T3, so that the driving transistor T7 can transmit a light emitting driving signal to the third node N3 based on the driving power supply signal and the potential of the second node N2, and the light emitting driving signal transmitted to the third node N3 can be transmitted to the fourth node N4 through the turned-on first light emitting control transistor T2, that is, to the first electrode of the light emitting element 02. Thus, the light emitting element 02 is driven to emit light, where the light emitting element 02 can emit light based on the light emitting driving signal transmitted to the fourth node N4 and the pull-down power supply signal provided by the pull-down power supply line ELVSS.

[0168] It can be understood that, since the driving method of the pixel circuit has basically the same technical effects as the display panel described above, for the purpose of brevity, the technical effects of the driving method will not be described again here.

[0169] The application also provides a display device. As shown in FIG. 15, the display device comprises a power supply assembly 100 and a display panel 000 as described in the above embodiments.

[0170] The power supply assembly 100 is coupled to the display panel 000 and configured to supply power to the display panel 000.

[0171] Optionally, the display device can be an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, or the like. The OLED display technology has been widely recognized by the market due to its high resolution and high contrast, and the like.

[0172] Optionally, the display device can be a mobile phone, a tablet computer, a television, a display, or any product or component having a display function.

[0173] It can be understood that the display device has substantially the same technical effects as the display panel described above, and therefore the technical effects of the display device will not be described herein for the purpose of brevity.

[0174] It can be understood that the terms used in the embodiments of the present application are only used to explain the embodiments, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meaning understood by a person skilled in the art in the field of the present application.

[0175] As used in the patent application specification and claims of the present application, "first", "second", or "third" and similar words do not indicate any order, number, or importance, but are only used to distinguish different components.

[0176] When we say that an element is "coupled" or "coupled" to another element, it can be directly coupled or coupled to other elements, or there can be intermediate elements. In addition, "coupled" or "coupled" used herein can include wireless coupling or wireless coupling.

[0177] Similarly, "one" or "a" and similar words do not indicate a quantity limit, but indicate the presence of at least one.

[0178] "Include" or "contain" and similar words mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects.

[0179] "Up", "down", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0180] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, and the like made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, the display panel comprising: A substrate and a plurality of pixels located on one side of the substrate, the pixel comprising: a pixel circuit and a light emitting element, the pixel circuit comprising: a switch circuit coupled with a switch control line, a reference power supply line and a first node respectively, and configured to control the reference power supply line and the first node in response to a switch control signal provided by the switch control line; a control circuit coupled with a gate line, a data line, a first light emitting control line, the first node, a second node, a third node and a fourth node respectively, and configured to adjust a potential of the third node based on a reference power signal provided by the reference power supply line when the reference power supply line and the first node are turned on, and to adjust a potential of the second node, to control the data line and the second node in response to a gate drive signal provided by the gate line, and to control the third node and the fourth node in response to a first light emitting control signal provided by the first light emitting control line; the fourth node is coupled with a first electrode of the light emitting element, and a second electrode of the light emitting element is coupled with a pull-down power supply line; a drive circuit having a control end coupled with the second node, an input end coupled with a drive power supply line, and an output end coupled with the third node, and configured to transmit a light emitting drive signal to the third node based on a drive power signal provided by the drive power supply line and the potential of the second node; wherein the pixel circuits of at least two pixels share the same switch circuit.

2. The display panel of claim 1, wherein, The plurality of pixels are arranged in an array; the pixel circuits of at least two pixels in at least one row of pixels share the same switch circuit.

3. The display panel of claim 2, wherein, In one row of pixels, the pixel circuits of a part of pixels and the pixel circuits of another part of pixels share different switch circuits respectively, and the different switch circuits are located on both sides of the one row of pixels in a pixel row direction.

4. The display panel of claim 3, wherein, In one row of pixels, the number of the part of pixels and the number of the another part of pixels sharing different switch circuits are the same.

5. The display panel according to any one of claims 1 to 4, wherein, The substrate has a display area and an edge area at least partially surrounding the display area; The switch circuit shared by the pixel circuits of the at least two pixels is located in the edge area, or in the display area.

6. The display panel of claim 5, wherein, The display panel further comprises: a gate drive circuit located on one side of the substrate and in the edge area, the gate drive circuit is coupled with the gate line and configured to provide the gate drive signal to the gate line; The switch circuit shared by the pixel circuits of the at least two pixels is located in the edge area, and is located on a side of the gate drive circuit close to the display area, or on a side of the gate drive circuit away from the display area.

7. The display panel according to any one of claims 1 to 6, wherein, The switch circuit comprises: a switch transistor; a gate of the switch transistor is coupled with the switch control line, a first electrode of the switch transistor is coupled with the reference power supply line, and a second electrode of the switch transistor is coupled with the first node.

8. The display panel according to any one of claims 1 to 6, wherein, The switch circuit comprises: a first switch transistor and a second switch transistor; the switch control line comprises: a first switch control line and a second switch control line; The gate of the first switch transistor and the gate of the second switch transistor are coupled with the first switch control line and the second switch control line respectively, the first pole of the first switch transistor and the first pole of the second switch transistor are coupled with the reference power supply line, and the second pole of the first switch transistor and the second pole of the second switch transistor are coupled with the first node.

9. The display panel according to any one of claims 1 to 8, wherein The control circuit is further coupled between the driving power supply line and the input end of the driving circuit, and is further coupled with a second light-emitting control line and used for controlling the driving power supply line and the input end of the driving circuit to be turned on or turned off in response to a second light-emitting control signal provided by the second light-emitting control line. The control circuit comprises: An adjusting sub-circuit coupled with the first node, the second node and the third node respectively and used for adjusting the potential of the third node based on the reference power supply signal when the reference power supply line and the first node are turned on, and adjusting the potential of the second node; A data writing sub-circuit coupled with the gate line, the data line and the second node respectively and used for controlling the data line and the second node to be turned on or turned off in response to the gate driving signal; A first light-emitting control sub-circuit coupled with the first light-emitting control line, the third node and the fourth node respectively and used for controlling the third node and the fourth node to be turned on or turned off in response to the first light-emitting control signal; A second light-emitting control sub-circuit coupled with the second light-emitting control line, the driving power supply line and the input end of the driving circuit respectively and used for controlling the driving power supply line and the input end of the driving circuit to be turned on or turned off in response to the second light-emitting control signal.

10. The display panel of claim 9, wherein, The adjusting sub-circuit comprises a first capacitor and a second capacitor, the data writing sub-circuit comprises a data writing transistor, the first light-emitting control sub-circuit comprises a first light-emitting control transistor, and the second light-emitting control sub-circuit comprises a second light-emitting control transistor; The first pole plate of the first capacitor is coupled with the second node, and the second pole plate of the first capacitor is coupled with the third node; The first pole plate of the second capacitor is coupled with the first node, and the second pole plate of the second capacitor is coupled with the third node; The gate of the data writing transistor is coupled with the gate line, the first pole of the data writing transistor is coupled with the data line, and the second pole of the data writing transistor is coupled with the second node; The gate of the first light-emitting control transistor is coupled with the first light-emitting control line, the first pole of the first light-emitting control transistor is coupled with the third node, and the second pole of the first light-emitting control transistor is coupled with the fourth node; The gate of the second light-emitting control transistor is coupled with the second light-emitting control line, the first pole of the second light-emitting control transistor is coupled with the driving power supply line, and the second pole of the second light-emitting control transistor is coupled with the input end of the driving circuit.

11. The display panel according to any one of claims 1 to 10, wherein, The pixel circuit further comprises: A first reset circuit is coupled to the first reset line, the first initial power line, and at least one target node of the third node and the fourth node, and is configured to control the first initial power line and the at least one target node in response to a first reset signal provided by the first reset line. A second reset circuit is coupled to the second reset line, the reference power line, and the second node, and is configured to control the reference power line and the second node in response to a second reset signal provided by the second reset line.

12. The display panel of claim 11, wherein, The first reset circuit includes a first reset transistor, and the second reset circuit includes a second reset transistor. The gate of the first reset transistor is coupled to the first reset line, the first electrode of the first reset transistor is coupled to the first initial power line, and the second electrode of the first reset transistor is coupled to the at least one target node. The gate of the second reset transistor is coupled to the second reset line, the first electrode of the second reset transistor is coupled to the reference power line, and the second electrode of the second reset transistor is coupled to the second node.

13. The display panel of claim 11 or 12, wherein, In a case where the target node is the fourth node, the pixel circuit further includes: A third reset circuit is coupled to the first reset line, a second initial power line, and the third node, and is configured to control the second initial power line and the third node in response to the first reset signal.

14. The display panel of claim 13, wherein, The third reset circuit includes a third reset transistor. The gate of the third reset transistor is coupled to the first reset line, the first electrode of the third reset transistor is coupled to the second initial power line, and the second electrode of the third reset transistor is coupled to the third node.

15. The display panel of any of claims 11 to 14, wherein, The switch control line is shared by the gate line, the first reset line, or the second reset line.

16. The display panel of any of claims 11 to 15, wherein, The reference power line is shared by the driving power line, the reference power line, the first initial power line, or the second initial power line.

17. The display panel of any of claims 1 to 16, wherein, The driving circuit includes a driving transistor. The gate of the driving transistor is coupled to the second node as a control terminal of the driving circuit, the first electrode of the driving transistor is coupled to the driving power line as an input terminal of the driving circuit, and the second electrode of the driving transistor is coupled to the third node as an output terminal of the driving circuit.

18. The display panel of any of claims 1 to 17, wherein, The pixel circuit includes N-type transistors.

19. A driving method of a pixel circuit in a display panel, applied to the pixel circuit of the display panel as claimed in any one of claims 1 to 18, and the method comprises: In a non-emitting stage, a switch control signal provided by a switch control line has a first potential, a switch circuit controls the reference power line and a first node to be conductive in response to the switch control signal with the first potential, and a control circuit adjusts the potential of the third node based on a reference power signal provided by the reference power line and adjusts the potential of the second node. In an emitting stage, a switch control signal provided by a switch control line has a second potential, and a switch circuit controls the reference power line and the first node to be decoupled in response to the switch control signal with the second potential.

20. A display device comprising: A power supply assembly, and a display panel as claimed in any one of claims 1 to 18. The power supply assembly is coupled to the display panel and configured to supply power to the display panel.

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