Floating-point processor

Abstract

The invention relates to a processor comprising: an integer operation processing unit (ALU), a floating-point operation processing unit (FPU), a register bank (RGBK), an external data bus (DTB), a data path connecting the register bank to the floating-point operation processing unit, to the integer operation processing unit, and to the external data bus, and a processing chain configured to at least partially simultaneously process integer operation instructions and floating-point operation instructions, wherein the processing chain comprises common stages for processing an integer operation instruction and a floating-point operation instruction, and at least one additional execution stage for executing a floating-point operation.

Description

[0001] DESCRIPTION

[0002] TITLE: Floating-Point Processor

[0003] technical field

[0004] The present invention relates to the field of processors and in particular microprocessors, especially microprocessors for embedded systems adapted to space applications.

[0005] State of the art

[0006] There are three types of processor architectures for embedded space systems: microcontrollers, signal processing units (SPUs), and general-purpose processors. Microcontrollers are small processors that control command and control operations using actuators and sensors, such as managing a satellite's solar panels. Microcontrollers do not incorporate floating-point operators and operate only at frequencies of a few tens of megahertz.

[0007] Digital signal processors (DSPs) are specialized for high-performance computing. DSPs can perform fixed-point or floating-point operations. To ensure high speed (low latency) and fast results, arithmetic operations are executed in a single clock cycle. The operating frequency of this type of processor is several hundred MHz. These processors can be used, for example, in star trackers. Such sensors are mounted on satellites to determine their position based on the location of stars. This positioning function must be performed in real time and requires significant computing power to process and interpret images.

[0008] Finally, general-purpose processors, particularly those used in personal computers and mobile phones, are capable of delivering high computing power by utilizing spatial and temporal parallelism. The operating frequency of these processors can reach several gigahertz.

[0009] Regardless of their architecture, processors can use two types of instruction sets: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). RISC instructions consist exclusively of instructions for simple, fixed-size operations. These instructions are therefore easy to decode and quick to execute, but result in a large memory footprint. In CISC instructions, the instructions are variable in size, from 1 to 5 bytes, and are executed in one or more clock cycles depending on their complexity. Thus, they are optimized in terms of memory footprint.

[0010] Processors capable of performing floating-point operations typically include a processor for integer operations and a coprocessor for floating-point operations. The combination of a processor and a coprocessor allows for the simultaneous execution of integer and floating-point operations. This type of architecture has two register banks and two separate data paths.

[0011] However, applications such as space applications require processors hardened to withstand critical radiation environments. Indeed, the behavior of a circuit can be altered when it is traversed by energetic particles. The energy of these particles can modify the values ​​stored in registers. To address this problem, architectures have been proposed that implement three sets of redundant registers and use majority voting, resulting in a significant increase in the number of registers. However, in embedded applications, it is also desirable to limit the number of registers to avoid increasing the static and dynamic power consumption of the processor. In fact, the power consumption of embedded systems, particularly in the space sector, is critical because they mostly operate on batteries recharged by solar panels.

[0012] These various constraints necessitate minimizing the number of registers and memory cells. However, embedded software in space applications requires significant floating-point processing power, particularly double-precision 64-bit. Indeed, the single-precision (32-bit) format is often avoided due to concerns about overflow during program execution. Conversely, a 32-bit size for integers is preferred for all integer calculations, such as data addressing.

[0013] It is therefore desirable to propose a high-performance processor architecture for performing double-precision floating-point operations that is both energy-efficient, compact in terms of silicon area, and has an instruction set that allows for the design of programs with a small memory footprint. Summary

[0014] Embodiments relate to a processor comprising: an integer processing unit, a floating-point processing unit, a register bank, an external data bus, a data path connecting the register bank to the floating-point processing unit, the integer processing unit, and the external data bus, and a processing chain configured to process at least partially simultaneously integer operation instructions and floating-point operation instructions, the processing chain comprising common stages for processing an integer operation instruction and a floating-point operation instruction, and at least one additional execution stage for executing a floating-point operation.

[0015] According to one embodiment, the processor includes a program memory access bus separate from the external data bus.

[0016] According to one embodiment, the processor includes a set of CISC-type instructions and is configured to transform CISC instructions into RISC instructions before executing them.

[0017] According to one embodiment, the register bank comprises only 32 32-bit registers that can be used as 16 64-bit registers.

[0018] According to one embodiment, the integer operation processing unit is configured to process 32-bit operands.

[0019] According to one embodiment, the floating-point operation processing unit is configured to process 64-bit operands.

[0020] According to one embodiment, the processor is configured to manage data dependencies in the data path using internal registers.

[0021] According to one embodiment, the processing chain includes: an instruction acquisition stage, an instruction decoding stage, an instruction operand selection stage, a first execution stage of an instruction operation, including writing the result of the operation into a register of the register bank, and two additional execution stages dedicated to executing a floating-point operation, between the selection stage and the first execution stage.

[0022] In one embodiment, the decoding, selection, and execution stages are separated by internal registers. Brief description of the figures

[0023] The present invention will be better understood with the aid of the following description of exemplary embodiments with reference to the accompanying figures, in which identical reference signs correspond to structurally and / or functionally identical or similar elements.

[0024] [Fig 1] Figure 1 schematically represents the architecture of a processor, according to one embodiment,

[0025] [Fig 2] Figure 2 represents a simple instruction processing chain, implemented in the processor, according to one embodiment,

[0026] [Fig 3] Figure 3 represents a floating-point instruction processing chain, implemented in the processor, according to one embodiment,

[0027] [Fig 4] Figure 4 illustrates a case of processor processing a sequence of one floating-point instruction followed by two integer instructions, according to one embodiment,

[0028] [Fig 5] Figures 5A, 5B, 50 illustrate various examples of processor processing of series of three instructions.

[0029] Detailed description

[0030] Figure 1 illustrates the architecture of a PRC processor, and in particular the architecture of its data path, according to one embodiment. The PRC processor's data path includes, among other things, an RGBK register bank, an ALU (arithmetic logic unit), an FPU (floating-point processing unit), an IDEC (instruction decoder), an IR (instruction register), and a PC (instruction pointer register). The RGBK register bank comprises 32-bit registers that can be paired to form 16 64-bit registers. The ALU is configured to perform arithmetic and logic operations with one or two input operands and one output operand.The ALU unit receives as input one or two operands of 32 bits each from the register bank RGBK, and provides a 32-bit output data which is transmitted by an internal data bus DBI1 to an input of the register bank RGBK or to an external data bus DTB giving access to a data memory space connected to the processor PRC and addressed by the external address bus ADB.

[0031] The FPU is configured to perform floating-point operations. For this purpose, the FPU is connected to the RGBK register bank via two 64-bit data buses (4 x 32 bits), and to the DTB data bus and the RGBK register bank via two data buses: the DBI1 bus and an internal 32-bit DBI2 data bus. The IDEC decoder determines, from the instruction in the IR register, the commands to be executed by the ALU or FPU, and the register numbers to be selected in the RGBK register bank to execute the instruction. The DTB data bus can be connected to the internal DBI1 and DBI2 buses, for example, via multiplexers / demultiplexers, to select which of the DBI1 and DBI2 buses to connect to the DTB bus. The PC register is connected to an external 24-bit program address APB bus providing access to a program memory space connected to the PRC processor.The instruction register (IR) is connected to an external 32-bit instruction bus (PGB) to receive an instruction to be executed, located at the address stored in the PC register. The FPU, for example, conforms to the IEEE 754 standard for floating-point arithmetic.

[0032] Thus, the processor features a Harvard-type architecture, possessing a program memory access bus (PGB / APB) separate from the data memory access bus (DTB / ADB).

[0033] The PRC processor includes a single data path connecting the RGBK register bank, the ALU and FPU units, and the external DTB data bus. In one embodiment, the number of registers in the RGBK register bank is limited to 32 32-bit registers. This register bank size is compatible with all C code compilers, such as the CompCert certified compiler, which is used for coding critical embedded applications, such as those in the space sector. This is because this compiler performs few performance optimizations and therefore uses very few registers. Consequently, a larger number of registers may be unnecessary from the compiler's perspective.

[0034] In one embodiment, the PRC processor is of a hybrid type in that it includes a CISC instruction set, with the IDEC decoder configured to decode and transform the CISC instructions into RISC instructions. As a result, the PRC processor can quickly execute instructions on the single data path while simultaneously accessing all processor resources. This minimizes the memory footprint of programs while maintaining good performance.

[0035] In one embodiment, the data path is configured to manage the interactions of the PRC processor with external memory. The PRC processor's data path is further configured to distribute the processing of each instruction across several successive stages of a processing pipeline. Thus, the execution of a new instruction can be initiated as soon as the first stage is available, without waiting for the execution of the previous instruction to be fully completed.

[0036] Because the PRO processor incorporates a single data path, the processing chain can implement multiple stages to handle both integer instructions using the ALU and double-precision floating-point instructions using the FPU. Some stages of the processing chain are used exclusively for floating-point instructions. In one embodiment, the processing chain comprises three execution stages, with only one of these three stages used to process an integer instruction.

[0037] According to one exemplary embodiment, the processing chain comprises four stages corresponding to four processing steps of one clock cycle each, and two additional operation execution stages corresponding to two successive processing steps of one clock cycle each, specifically configured to perform a floating-point operation.

[0038] It is therefore possible to maintain a degree of parallelism between the processing of integer and floating-point instructions, while reducing the number of registers. Furthermore, data dependencies are entirely managed by the data path, thus avoiding the need for the compiler to insert "nop" (or "no operation") statements. This results in a smaller executable code size.

[0039] Figures 2 and 3 represent steps in an example processing chain. Figure 2 shows the steps executed by the stages of the processing chain during the execution of an entire instruction involving the ALU. These steps include ACQ loading the instruction from the IR register and updating the program pointer PC, DEC decoding the instruction, SEL selecting and reading the operands from the registers in the RGBK register bank, and finally EXC executing the entire operation corresponding to the instruction, including writing the result of the operation to a register in the RGBK register bank. The ACQ, DEC, SEL, and EXC steps are executed sequentially during cycles C1 to C4, respectively.

[0040] Figure 3 illustrates the steps executed by the different stages of the processing chain during the execution of a floating-point instruction, thus involving the FPU. These steps include the ACQ, DEC, and SEL steps executed to process an integer instruction, and three EXC1, EXC2, and EXC3 steps for executing the floating-point operation corresponding to the instruction. The third and final EXC3 step includes writing the result of the operation to a register in the RGBK register bank. The ACQ, DEC, SEL, EXC1, EXC2, and EXC3 steps are executed sequentially, during cycles C1 through C6, respectively.

[0041] The processing chains shown in Figures 2 and 3 include internal registers PR1, PR2, PR3, and PR4 (Figure 1) that implement the ACQ, DEC, SEL, EXC / EXC1, EXC2, and EXC3 steps, respectively, during cycles C1 through C6. The instruction loading ACQ cycle C1 is performed at the input of the instruction register IR. The instruction decoding DEC cycle C2 is performed by the instruction decoder IDEC. The result of the DEC decoding (the operation to be executed and the register numbers containing the operands) is stored in the internal registers PR1. The operand selection and SEL cycle C3 is performed in the register bank RGBK. The result of the SEL selection (the operation to be executed and the operand values) is stored in the internal registers PR2. The EXC / EXC1 execution cycle C4 is executed by the AU unit or a first stage of the FPU unit. The EXC2 and EXC3 execution cycles C5, C6 are performed successively in the FPU unit.Intermediate results from the EXC1 and EXC2 execution steps of an instruction by the FPU unit are successively stored in the internal registers PR3 and PR4 in the FPU unit.

[0042] It should be noted that simple floating-point operations like addition and multiplication can be executed in six clock cycles. However, some more complex instructions like division or square root are broken down into several simple floating-point operations, and therefore require more than six clock cycles to process.

[0043] Figure 4 illustrates an optimal case of a three-instruction sequence consisting of a floating-point arithmetic instruction followed by two integer arithmetic instructions. By splitting the processing of each instruction into multiple steps, the processing of the first integer arithmetic instruction can begin as soon as the ACQ step of the floating-point arithmetic instruction is completed. Similarly, the processing of the second integer arithmetic instruction can begin as soon as the ACQ step of the first integer arithmetic instruction is completed.Because the processing of the floating-point instruction involves three execution steps, EXC1, EXC2, and EXC3, the processing of the first integer instruction completes (at the end of step EXC) simultaneously with the second execution step, EXC2, of the floating-point instruction, and the processing of the second integer instruction completes simultaneously with the third execution step, EXC3. The three instructions in the sequence are therefore processed in parallel by the PRC processor in six cycles, C1-C6. Figure 5A illustrates an example of the PRC processor processing a sequence of one floating-point multiplication instruction followed by two integer addition instructions, corresponding to the optimal case shown in Figure 4.This sequence can be written in assembler as follows: fmul r0, r1, r2 add r3, r4, r5 add r4, r3, r6.

[0044] The first instruction is a floating-point multiplication "fmul" of the contents of register r1 (32 bits) by the contents of register r2 (32 bits), with register r0 (64 bits) receiving the result of the multiplication. The second instruction is an integer addition "add" of the contents of register r4 (32 bits) with the contents of register r5 (32 bits), with register r3 (32 bits) receiving the result of the addition. The third instruction is an integer addition "add" of the contents of register r3 (32 bits) with the contents of register r6 (32 bits), with register r4 (32 bits) receiving the result of the addition. In this example, there is no register access conflict, particularly with register r3, since the SEL (Selective Access List) of a register can be performed simultaneously with the EXC (Extract, Extract) of the previous operation using that same register.Thus, this sequence of instructions can be processed by the PRC processor in six C1-C8 cycles instead of 14 cycles if no parallelism was implemented.

[0045] Figure 5B illustrates an example of the PRC processor processing a sequence of a floating-point multiplication instruction "fmul", followed by two integer addition instructions "add". This example does not correspond to the optimal case illustrated in Figure 4, because the instruction following the floating-point instruction uses a register (r0) that is also used by the latter. This sequence can be written in assembly language as follows: fmul r0, r1, r2 add r3, r0, r4 add r5, r3, r6

[0046] The first instruction is a floating-point multiplication, "fmul," of the contents of register r1 (32 bits) by the contents of register r2 (32 bits), with register rO (64 bits) receiving the result of the multiplication. The second instruction is an integer addition, "add," of the contents of register rO (32 bits) with the contents of register r4 (32 bits), with register r3 (32 bits) receiving the result of the addition. The third instruction is an integer addition, "add," of the contents of register r3 (32 bits) with the contents of register r6 (32 bits), with register r5 (32 bits) receiving the result of the addition.Since access to register rO is locked by the execution of the first "fmul" instruction until the beginning of EXC3 (cycle C6), the SEQ sequencer waits for two cycles to elapse before beginning processing the second instruction in cycle C4. The SEL step for selecting register rO can only be performed starting from EXC3 of the "fmul" instruction (cycle C6). In contrast, using register r3 in the two addition instructions does not pose a problem because it can be selected (SEL step) during an EXC execution step in which it is used. Therefore, this instruction sequence can be processed by the PRC processor in eight cycles C1-C8 instead of 14 cycles if no parallelism were implemented.

[0047] Figure 5C illustrates an example of the PRC processor processing a sequence of three floating-point instructions, comprising a multiplication "fmul" followed by two additions "fadd". This sequence can be written in assembly language as follows: fmul r0, r1, r2 fadd r3, r0, r4 fadd r5, r3, r6

[0048] The first instruction is a floating-point multiplication, "fmul", of the contents of register r1 (32 bits) by the contents of register r2 (32 bits), with register rO (64 bits) receiving the result of the multiplication. The second instruction is a floating-point addition, "fadd", of the contents of register rO (32 bits) with the contents of register r4 (32 bits), with register r3 (64 bits) receiving the result of the addition. The third instruction is a floating-point addition, "fadd", of the contents of register r3 (32 bits) with the contents of register r6 (32 bits), with register r5 (64 bits) receiving the result of the addition. Again, access to register rO is locked by the execution of the first instruction until the beginning of stage EXC3 (cycle C6) of the execution of the "fmul" instruction.The SEQ sequencer therefore waits for two cycles to elapse before beginning processing the second "fadd" instruction at cycle C4, as the SEL step for selecting register r0 can only be performed starting from step EXC3 (cycle C6) of the execution of the second "fadd" instruction. Similarly, access to register r3 is locked by the execution of the second "fadd" instruction until the beginning of step EXC3 (cycle C9) of the execution of the "fadd" instruction. Consequently, the SEQ sequencer waits for two cycles to elapse before beginning processing the third "fadd" instruction at cycle C7, as the SEL step for selecting register r3 can only be performed starting from step EXC3 (cycle C9) of the preceding "fadd" instruction. Thus, this sequence of instructions can be executed in 12 C1-C12 cycles, instead of 18 if no parallelism was implemented.It will be readily apparent to those skilled in the art that the present invention is susceptible to various embodiments and applications. In particular, the invention is not limited to a Harvard-style processor. Indeed, the data access bus need not be separate from the program instruction access bus to benefit from the advantages offered by the described processor architecture. Specifically, the processing chain described above and the implementation of a single data path can be implemented in a processor with a single data and program instruction access bus.

[0049] Nor is it necessary for the processor's instruction set to be CISC or RISC. Indeed, the processor's IDEC instruction decoder can be adapted to either of these two types of instruction set, bearing in mind that the choice of instruction set type influences the memory footprint of the programs that can be executed by the processor.

[0050] Furthermore, the internal and external bus sizes shown in Figure 1 are provided as examples. The processor architecture described above can be easily adapted to any other data, program, and address bus sizes.

[0051] Furthermore, the processing chain may be designed to include stages of a different nature and number than those previously described. For example, the processing chain may include five stages common to both integer and floating-point operations, and two additional stages dedicated to executing floating-point operations. The common stages may include a stage for loading the instruction to be executed, a stage for decoding the instruction, a stage for executing the instruction, a stage for transferring data between a register and memory, and a stage for storing the execution result in a register. In other embodiments, some of the stages listed above are grouped into a single stage.

Claims

DEMANDS 1. Processor comprising: an integer processing unit (ALU), a floating-point processing unit (FPU), a register bank (RGBK), an external data bus (DTB), a data path linking the register bank to the floating-point processing unit, the integer processing unit, and the external data bus, and a processing chain configured to process at least partially concurrently integer operation instructions and floating-point operation instructions, the processing chain comprising common stages for processing an integer operation instruction and a floating-point operation instruction, and at least one additional execution stage for executing a floating-point operation.

2. Processor according to claim 1, comprising a program memory access bus (APB, PGB) separate from the external data bus (DTB).

3. Processor according to claim 1 or 2, wherein the processor (PRC) comprises a set of instructions of type CISC and is configured to transform the CISC instructions into RISC instructions before executing them.

4. Processor according to any one of claims 1 to 3, wherein the register bank (RGBK) comprises only 32 32-bit registers that can be exploited as 16 64-bit registers.

5. Processor according to any one of claims 1 to 4, wherein the integer operations processing unit (ALU) is configured to process 32-bit operands.

6. Processor according to any one of claims 1 to 5, wherein the floating-point processing unit (FPU) is configured to process 64-bit operands.

7. A processor according to any one of claims 1 to 6, configured to manage data dependencies in the data path using internal registers (PR1-PR4).

8. A processor according to any one of claims 1 to 7, wherein the processing chain comprises: an instruction acquisition (ACQ) stage, an instruction decoding (DEC) stage, an instruction operand selection (SEL) stage, a first execution stage (EXC, EXC3) of an operation of the instruction, including writing the result of the operation to a register in the register bank (RGBK), and two additional execution stages (EXC1, EXC2) dedicated to executing a floating-point operation, between the selection stage and the first execution stage.

9. Processor according to claim 8, in which the decoding (DEC), selection (SEL) and execution (EXC, EXC1, ECX2, EXC3) stages are separated by internal registers (PR1-PR4).

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