Facilitating efficient time and frequency tracking using synchronization signal block

Abstract

A method comprising receiving, from a network device, a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

Description

FACILITATING EFFICIENT TIME AND FREQUENCY TRACKING USING SYNCHRONIZATION SIGNAL BLOCKTECHNICAL FIELD

[0001] The example and non-limiting embodiments relate to communications, more specifically, facilitating time and frequency tracking using synchronization signal block.BACKGROUND

[0002] In 3rdGeneration Partnership Project (3GPP) development, particularly for physical layer design in 6G compared to 5G, more efficient time and frequency tracking is in need.SUMMARY

[0003] The following summary is intended to be illustrative, but not limit the scope of the claims.

[0004] In accordance with some example embodiments, a method may include receiving, from a network device, a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0005] In accordance with some other example embodiments, a method may include providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0006] In accordance with certain example embodiments, an apparatus may include at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to receive a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determine at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and perform channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0007] In accordance with other certain example embodiments, an apparatus may include at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to provide, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi colocation source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmit, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0008] In accordance with various example embodiments, an apparatus may include means for receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0009] In accordance with other various example embodiments, an apparatus may include means for providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0010] In accordance with further example embodiments, a non-transitory computer readable medium comprising program instructions stored thereon for performing at least the following: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0011] In accordance with further example embodiments, a non-transitory computer readable medium comprising program instructions stored thereon for performing at least the following: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non- consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0012] In accordance with further example embodiments, a computer program comprising instructions stored thereon for performing at least the following: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0013] In accordance with further example embodiments, a computer program comprising instructions stored thereon for performing at least the following: providing,to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi colocation source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The foregoing aspects and features are explained in the following description. For proper understanding of the present disclosure, reference should be made to the accompanying drawings, wherein:

[0015] FIG. 1 illustrates Table 1;

[0016] FIG. 2 illustrates an example of synchronization signal block;

[0017] FIG. 3 illustrates an example of synchronization block slot;

[0018] FIG. 4 illustrates an example plot of PDSCH throughout;

[0019] FIG. 5 illustrates an example of synchronization slot / block structure;

[0020] FIG. 6 illustrates an example of synchronization block allocation;

[0021] FIG. 7 illustrates an example of synchronization block allocation;

[0022] FIG. 8 illustrates an exemplary embodiment performed at a UE;

[0023] FIG. 9 illustrates an example method;

[0024] FIG. 10 illustrates an example method;

[0025] FIG. 11 illustrates an example of a wireless communication network in which the example embodiments may be practiced.DETAILED DESCRIPTION

[0026] Abbreviations that may be found in the specification and / or the drawings are defined at the end of the detailed description section.

[0027] When more than one drawing reference numeral, word, or acronym is usedmay be interpreted as “or”, “and”, or “both”. And, as used in the follows, “at least one of the following: ” and “at least one of ” and similarwording, where the list of two or more elements are joined by “and” or “or,” mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements.

[0028] In 5G (NR), synchronization signal and physical broadcast channel (PBCH) block is transmitted periodically with default periodicity of 20 milliseconds (ms). Beamforming is supported for the synchronization signal block (SSB) transmissions and hence there can be a burst of SSBs transmitted with different transmit beams. A full SSB burst is confined within a 5 ms half-frame. The maximum number of SSBs in the burst, as shown in FIG. 1, particularly Table 1, depends on the carrier frequency range and subcarrier spacing.

[0029] FIG. 2 illustrates an example of SSB in 5G. The SSB has a length of four symbols in time domain, namely symbols #0 to #3, and 20 resource blocks (RBs) in frequency domain. The SSB comprises synchronization signals (SS) and physical broadcast channel (PBCH) signals. Furthermore, the synchronization signals include primary synchronization signals (PSS), which uses less than or up to 12 RBs in the center of the given 20 RBs in symbol #0, and secondary synchronization signals (SSS), which is allocated substantially to the center 12 RBs of the 20 RBs of symbol #2 in frequency domain. The rest of the RBs on each end of the 20 RBs in symbol #2 are allocated to PBCH, and some guard bands are allocated between PBCH and SSS. PBCH and SSS in symbol #2 may be multiplexed in frequency domain. Symbols #1 and #3 are allocated for PBCH, substantially occupying the 20 RBs. In this disclosure, symbol #m, symbol slot #m, and symbol m ( =0. 1, 2, 3, 4...) are exchangeable.

[0030] Turning to FIG. 3, an example of synchronization block slot is depicted to show that all SSBs are confined within a 5 ms half-frame, and the SSBs are transmitted in various patterns based on subcarrier spacing (SCS), frequency range, and other parameters listed in Table 1. Taking SCS 15 kHz as an example, at a low frequency range, such as 0-7 GHz, there may be 2 slots, slots 0 and 1, in the 5 ms half-frame, contain SSBs, and each of slots 0 and 1 carries 2 SSBs. Each slot consists of 14 symbols. The first SSB in slot 0 occupies symbols 2 to 5 out of 14 symbols, and the second SSB in slot 0 occupies symbols 8 to 11. For SCS larger than 60 kHz, the slot duration is less than 250 microseconds (us), one non-synchronization block slot isreserved every 1 ms.

[0031] From SSBs, a user equipment (UE) may determine time and / or frequency synchronization in order to receive broadcast signaling and perform initial access. For acquiring and tracking accurate and precise time and / or frequency synchronization, a separate periodic tracking reference signal (TRS) is configured for the UE in connected mode. In addition, UE may be informed the presence of TRS also in idle and / or inactive mode. In NR, the TRS is a specific configuration of a non-zero power channel state information reference signal (NZP CSI-RS) resources compared to a single reference signal (RS). TRS consists of two symbols, which are two NZP CSI-RS resources, separated by 4 symbols. In frequency domain, the bandwidth is minimum of 52 RBs or a bandwidth part (BWP). Periodic TRS is a pre-requisite for the reception of NZP CSI-RS for channel state information (CSI) measurements, CSI-RS for beam measurement, physical downlink control channel (PDCCH) and physical downlink shared channel (PDSCH) reception, and for dedicated uplink (UL) transmissions. Based on the TRS, the UE estimates Doppler shift, Doppler spread, average latency and delay spread of a radio channel, etc.

[0032] Transmission of UE specific periodic TRS resources imposes a high reference signal resource overhead into a radio system. Furthermore, moving towards envisioned 6G system demanding more energy efficient compared with previous radio systems, transmission of periodical reference signals and channel transmissions need to be minimized. Thus, one change could be made is removing periodic transmission of TRS resources. This cannot be supported in NR, because SSB in its current form cannot provide the needed characteristics / functionality for the purposes that TRS provides. For example, to enable the estimation of different quasi-collocation (QCL) parameters, for example, QCL-type-A and QCL-type-C, the bandwidth of TRS resources in NR is associated with minimum of BWP size in terms of PRBs or 52 PRBs. However, it is shown in FIG. 4, an example plot of PDSCH throughout, that the bandwidth of TRS to estimate the time and frequency parameters does not have a significant impact on PDSCH throughput. In other words, TRS with bandwidth of 24 PRBs can provide feasible estimates.

[0033] Synchronization block structure may be defined by splitting the synchronization block into different parts in time domain, wherein the parts of thesynchronization block may be separated by a specific number of symbols in time domain. The part of the synchronization block is defined as synchronization part. In addition, the synchronization block may be interleaved with another synchronization block or other synchronization blocks, which means at least one synchronization part of the synchronization block may be next to or neighboring to one synchronization part of the other synchronization block(s). If one or more part(s) is allocated for reference signals, this results in having inter-distance in time domain between reference signals of a certain synchronization block(s), providing the channel tracking properties. In one example, a synchronization block may have inter-part distance similar or equivalent to a TRS configuration, particularly TRS symbol distance based on the TRS configuration, or the synchronization block may provide TRS resources to meet TRS requirements for providing accurate time and / or frequency synchronization.

[0034] FIG. 5 illustrates an example of synchronization slot / block structure. One slot includes 14 symbols indexed in the sequence from #0 to #13, and the symbols are assigned 24 RBs in frequency domain. Since the slot comprises synchronization signals, the slot may also be called synchronization slot. Within the slot, there are two synchronization blocks, synchronization block #0 and synchronization block #1. Each synchronization block contains 4 symbols. Synchronization block #0, the first synchronization block with index #0 in the slot, comprises 4 symbols with 2 consecutive symbols with symbol indices #4 and #5, and another 2 consecutive symbols with indices #8 and #9. Yet, symbols #5 and #8 are non-consecutive, though sequentially next to each other, based on their logical symbol indices #1 and #2 in synchronization block #0. Similarly, synchronization block #1 comprises 2 contiguous symbols with symbol indices #6 and #7, and another 2 contiguous symbols #10 and #11. Yet, symbols #7 and #10 are non-contiguous, though sequentially adjacent to each other, as identified by their logical symbol indices #1 and #2 in synchronization block #1. Symbol with symbol index #x, also called symbol with index x, symbol #x or symbol x, means a symbol with symbol index x of a synchronization slot. In the present disclosure, “consecutive” and “contiguous” are exchangeable, meaning adjacent or next to each other; and, “non-consecutive” and “non-contiguous” are exchangeable. Symbol x, when used for at least part of asynchronization block, may be defined as a synchronization part of the synchronization block, and there may be a logical symbol index corresponding to the symbol index x of the synchronization block. Thus, synchronization part index may be identical to logical symbol index or identical to symbol index. Meanwhile, the synchronization block may have a synchronization block index.

[0035] Regarding synchronization block #0 in FIG. 5, each one of the symbols of the synchronization block may be assigned a logical symbol index. In other words, logical symbol indices #0, #1, #2, and #3 may be assigned to or correspond to symbols with symbol indices #4, #5, #8 and #9, respectively. The first symbol #4 or logical symbol #0 of synchronization block #0, may carry PBCH and demodulation reference signal (DMRS). Given 24 RBs of each symbol in frequency domain, synchronization block #0 may have the resources equally divided in frequency domain for PBCH and DMRS, meaning 12 RBs allocated to PBCH and another 12 RBs to DMRS. Each PBCH RB is allocated next to a DMRS RB. The second symbol of synchronization block #0, symbol 5, also known as logical symbol 1, may include 8 RBs, divided into 2 sets of 4 RBs located on each end of the 24 RBs, allocated to PBCH and DMRS. And substantially the rest RBs, located in the center of the 24 RBs, are allocated to the PSS, as shown in the figure, or SSS.

[0036] Symbol 8, which is 4 symbols away from symbol 4 and 2 logical symbols away from logical symbol 0, with logical symbol index 2 of synchronization block #0, may be allocated to PBCH and DMRS in the same way as symbol 4, logical symbol 0. Logical symbols 0 and 2 are 4 symbols apart from each other, which creates a periodicity or inter-distance of 4 symbols, if the resource of these two symbols are used for same type of signaling, for example, TRS. This suggests that the resource elements (REs) allocated for DMRS or PBCH in logical symbols 0 and 2, which are symbols 4 and 8, may be used for carrying TRS or a different RS. Consequently, the two TRSs within one synchronization block are 4 symbols apart. In one example, if the same TRS carried in logical symbol 0 is carried in symbol 2, the TRS in logical symbol 2 may be considered repeat of the TRS in symbol 0. Similarly, the REs in logical symbols 0 and 2 of synchronization block #1, which are symbols 6 and 10, may be allocated for RS or TRS, too, with 4 symbols away from each other. In one example, the TRS may be transmitted and / or receivedperiodically, with periodicity of y symbols, in which y may be an integer larger than one. Symbol 9, with logical symbol index 3, may be allocated for PBCH and DMRS, and SSS or PSS in the similar manner as for symbol 5.

[0037] In one example embodiment, one or more guard band, meaning resource elements (REs) with no transmission, may be used in the at least one synchronization part of a synchronization block, and a size of the one or more guard band is based on at least one synchronization signal in the synchronization block. In other words, the amount of guard band is dependent on the considered synchronization signal including synchronization signal type. The at least one synchronization signal may be at least one of: PSS or SSS. The size of the one or more guard band and / or the amount of guard band, in response to the at least one synchronization signal being the PSS, is larger than the size of the one or more guard band, in response to the at least one synchronization signal being the SSS. This allows simpler filter to be used for PSS detection compared to SSS detection, if the PSS detection is performed. Referring to FIG. 5 again, in symbols 5 and 9, which are logical symbols 1 and 3 or also called synchronization parts 1 and 3, guard band(s) may be allocated between PBCH and DMRS, and PSS or SSS. The size and / or amount of the guard bands in symbol 5 may be larger than that in symbol 9, if PSS is allocated to symbol 5 and SSS to symbol 9. PBCH and DMRS, and PSS or SSS may be multiplexed in frequency domain.

[0038] In another example embodiment, if resource allocation applied to synchronization block #1 is the same way as applied to synchronization block #0, PBCH and DMRS may be allocated and / or carried in symbols 6 and 10, corresponding to logical symbols 0 and 2 of synchronization block #1. This again creates a periodicity or inter-distance of 4 symbols for DMRS in the first and the third logical symbols, in which the resource for DMRS may be used for TRS or other reference signals or synchronization signals. Following this resource allocation pattern, logical symbols 0 and 2 of certain synchronization block may be used for TRS. In that case, the UE may be allocated with resource in two periodic non- consecutive synchronization parts of a synchronization block for TRS transmission and / or receiving, the periodicity or inter-distance is four symbols long in time domain. Four symbols is an example and the inter-distance can also be some otherinteger number of symbols long, or measured in unit of time or else.

[0039] In a further example embodiment, a synchronization block may be divided into symbols in time domain. Each symbol in a synchronization block may be named as a synchronization part. One synchronization block may include multiple consecutive synchronization parts, or non-consecutive synchronization parts which may be separated by a specific number of symbols in time domain. The separate synchronization parts of one synchronization block may be interleaved with another synchronization block. The inter-distance in time domain between the synchronization parts, if used for RSs, of the synchronization block, providing channel tracking properties. The inter-part distance of a synchronization block may be similar or equivalent to the current TRS configuration.

[0040] In another example embodiment, the separate time domain synchronization parts of the synchronization block may be transmitted in the same slot.

[0041] In FIG. 5, synchronization block #0 comprises four non-consecutive synchronization parts, each referring to a symbol, as symbol #5 and symbol #8 are separated by 2 symbols, symbols #6 and #7 belonged to a different synchronization block #1. The synchronization block #0 interleaves with synchronization block #1; in particular, symbols 5 and 8 of synchronization block #0 are interleaved by symbols 6 and 7 of synchronization block #1.

[0042] In an additional example embodiment, PSS resource may be separated from the synchronization block or the main synchronization block. PSS may be transmitted with different periodicity compared to transmission and / or reception of the combined SSS and PBCH / PBCH DMRS resources. Hence, PSS may not be within the main synchronization block.

[0043] In one example embodiment, one synchronization block comprises 4 synchronization parts, each part occupying one symbol. Synchronization parts 0, 1, 2 and 3 correspond to logical symbols 0, 1, 2 and 3, respectively. In time domain signal order, the synchronization block may comprise PSS in synchronization part 0, PBCH and DMRS in synchronization part 1, SSS in synchronization part 2, and PBCH and DMRS in synchronization part 4. Again, the synchronization part n, also known as the logical symbol n, or logical symbol #n, means the symbol with logical symbol index n or #n of the synchronization block.

[0044] In another example embodiment, a synchronization block may comprise of N, N=2, 3, 4..., separate synchronization parts; each part may be separated from its next part by a specific same time domain separation, for example, expressed or counted in number of symbols.

[0045] In further example embodiment, a synchronization block may comprise N, N-2, 3, 4..., separate synchronization parts; each part separated by specific time domain separation, expressed or counted in symbols, wherein the time domain separation between the first and the second synchronization parts, and the time domain separation between the Mh and the (' / V+ / jth synchronization parts may be different, for example, counted as different number of symbols or unit of time or else. In another example, within a synchronization block, the first symbol and the second symbol may be separated by 2 symbols, the second and the third symbols may be separated by 3 symbols, and the third and the fourth symbols may be separated by 4 symbols. Again, symbol may be named as synchronization part.

[0046] In an additional example embodiment, a synchronization block may comprise multiple synchronization parts, among which there may be at least two non- consecutive synchronization parts. The at least two non-consecutive synchronization parts are a number of symbols apart in time domain, in which the number of symbols may be a fixed number, or a non-fixed number meaning a varied number. When the at least two non-consecutive synchronization parts are a non-fixed number apart in time domain, the time distance between two of them may be varied.

[0047] In further example embodiment, some or all of the separate synchronization parts of the synchronization block may be transmitted and / or received on the consecutive symbols.

[0048] In another example embodiment, the separate synchronization parts of the synchronization block may be separated by at least one of: fixed, predefined, preconfigured, or specified number of symbols transmitted in the same slot.

[0049] In an example embodiment, separate synchronization parts of a synchronization block may have configurable time domain separation, wherein the separation is expressed in symbol or symbols.• In one example, a first separation mode, in time domain, may be applied to a first frequency range;• In another example, a second separation mode, in time domain, may be applied to a second frequency range. The number of symbols separation between non-consecutive synchronization parts of the second separation mode different from that of the separation between non-consecutive parts of the first separation mode.

[0050] FIG. 6 illustrates an example of synchronization block allocation. The synchronization block comprises resources for PSS or SSS, PBCH and DMRS. The slot includes symbols 0 to 13, in total of 14 slots in time domain and 24 RBs in frequency domain. Among the 14 symbols, there are 3 synchronization blocks, synchronization blocks #0, #1, and #2, and each synchronization block includes 3 synchronization parts, also known as symbols. Synchronization block #0 comprises synchronization parts 2, 6, and 10; synchronization block #1 comprises synchronization parts 3, 7, and 11; and, synchronization block #2 comprises synchronization parts 4, 8, and 12. Besides the synchronization part index or the symbol index of slot, each synchronization part or symbol in a synchronization block has a corresponding logical symbol index regarding the particular synchronization block based on the allocation of the symbol within the synchronization block.

[0051] Taking synchronization block #0 as an example, in the event that synchronization part index follows symbol index, synchronization part 2, which is symbol 2, may be assigned a logical symbol index 0 of synchronization block #0, also known as synchronization block 0. Synchronization part 6, the second symbol in synchronization block #0, is given logical symbol index 1 or #1. Similarly, synchronization part 10 of synchronization block #0, the third symbol in the block, is logical symbol 2 of the block. In addition, regarding synchronization block #0, synchronization parts 2, 6 and 10, which are logical symbols 0, 1 and 2, are allocated as resources for PSS or SSS, PBCH and DMRS, and PBCH and DMRS, respectively. Each synchronization part is 4 symbols away from its sequentially adjacent synchronization part of the same synchronization slot. Logical symbols 1 and 2 are 4 symbols apart and each of them contain resources for PBCH and DMRS. In this figure, as for synchronization parts 6 or 10 in frequency domain, 24 RBs are divided into 24 one RBs, half of them are allocated for PBCH and another half are allocated for DMRS. Each PBCH resource occupies 1 RB, and each DMRS resourcetakes 1 RB. Further, each PBCH resource is allocated next to a DMRS resource. In another example DMRS is multiplexed with PBCH in each RB, e.g. that every fourth resource element (RE) is DMRS. If the resource allocated for DMRS in the figure is allocated to TRS instead, the TRS may be transmitted and / or received periodically, one in every 4 symbols, in the second and the third synchronization parts of the synchronization block. Then the periodicity of TRS is the same as for the PBCH. In another example, TRS may be transmitted and / or received periodically, with a periodicity of an integer number of symbols in a synchronization block or a synchronization slot.

[0052] An additional example of synchronization block allocation is shown in FIG. 7. The synchronization block may comprise a first part and a second part, where the first and the second parts may be separate in time domain with predefined or known time separation. The first part includes logical symbols 0, 1, 2, and 3, and the second part includes logical symbol 4. Each logical symbol may be a synchronization part. In this example, the synchronization part index may be identical to the logical symbol index. The second part of the block may comprise at least one repeat signal of a signal allocated in the first part. In the first part of the synchronization block, synchronization part 0, also known as logical symbol 0, is allocated for PSS, synchronization parts 1 and 3 may be allocated for PBCH and DMRS, and synchronization part 2 for PBCH and DMRS and a first SSS. Synchronization part 4 in the second part of the synchronization block may be allocated to transmission / reception of a second SSS, which may be a repeated SSS of the first SSS carried in symbol 2 of the first part, with a predefined or preconfigured time period apart from the SSS in synchronization part 2. The time period may be counted as a number of symbols, or unit of time, or else. In one example, the resources for SSS in synchronization parts 2 and 4 may be used for TRS for tracking. In another example, the resource allocated for DMRS in synchronization parts 1 and 3, may be instead used for TRS.

[0053] FIG. 8 depicts an exemplary embodiment performed at a UE. At 810, UE is configured or indicated that synchronization block #x is QCL source for PDCCH reception, in which #x is the index number of the synchronization block. The synchronization block may be used for at least one of: time tracking, frequencytracking, or channel parameter estimation including at least one of: delay spread, average delay, Doppler shift, or Doppler spread, etc. At 820, the UE determines slot(s) of the synchronization block #x, meaning the slot(s) that includes synchronization block #x. In the present disclosure, synchronization block #x and synchronization block x are exchangeable. The UE further determines synchronization part(s), also called symbol(s), that has been or is allocated for PBCH and / or DMRS, which are used for the estimation and periodicity of synchronization block #x. When the resource allocated for DMRS is used for TRS, the UE may further determine periodicity of synchronization block #x. The UE, at 830, performs estimation of the at least one of: delay spread, average delay, Doppler shift, or Doppler spread based, at least partially, on PBCH and / or DMRS(TRS) symbols of the synchronization block #x. At 840, the UE receives PDCCH for which the synchronization block #x is indicated as a QCL source.

[0054] Turning to FIG. 9, which is a flowchart of example method, which may be performed at the UE. The example method may include: receiving, from a network device, a first reference signal in a first synchronization part of a first synchronization block, 910, wherein the first synchronization block comprises at least two non- consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block, 920; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block, 930.

[0055] Turning to FIG. 10, which is a flowchart of example method, which may be performed at, for example, a NW device or NW node. The example method may include: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, 1010, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block, 1020.

[0056] The synchronization block structure disclosed herein allows determiningaccurate and precise time and frequency domain channel characteristics. Further, it eliminates or at least alleviates use of dedicated and periodic TRS. Additionally, it reduces system overhead.

[0057] Reference is made to FIG. 11, which illustrates an example of a wireless communication network according to certain embodiment. Network (NW) element or access device 1102 is adapted for communication over a wireless link 1104 with apparatus, such as a mobile device, a mobile terminal, UE 1105. The access device 1102 may be an access point, an access node, a base station, gNB or an eNB, etc. similar to the NW or NW element depicted in FIGs.l to 3 and described above. UE 1105 may be a UE as illustrated in FIGs.8 to 9 and described above. Access device 1102 may comprise a frequency selective repeater, of any wireless network such as 6G, 5G NR, LTE, LTE-A, GSM, GERAN, WCDMA, CDMA, Wireless LAN, and the like. Access device 1102 may be a UE, which may perform operations like an access device. It is commonly found that one or more than one UE are under the control of device such as access device 1102; or, a UE is under the control of more than one network node. For simplicity, one UE 1105 and one NW element 1102 are shown in FIG. 11.

[0058] UE 1105 includes processing means such as at least one data processor, DP 1106, storing means such as at least one computer-readable memory, MEM 1108, for storing data 1110, at least one computer program, PROG 1111, or other set of executable instructions, communication means such as a transmitter, TX 1112, and a receiver, RX 1114, for bidirectional wireless communications with NW element 1102 via at least antenna 1116.

[0059] NW element 1102 also includes processing means such as at least one data processor, DP 1120, storing means such as at least one computer-readable memory, MEM 1122, for storing data 1124 and at least one computer program, PROG 1126, or other set of executable instructions. NW element 1102 may also include communication means such as a transmitter, TX 1128, and a receiver, RX 1130, for bidirectional wireless communications with one or more of UEs, such as UE 1105 and / or other similar UEs. Both the UE and the NW element may have many antennas, such as an array of antennas configured for multiple input multiple output (MIMO) communications, or multiple antennas for multiple radio access technologies. Other configurations of these devices, for example, may be provided.

[0060] The at least one of PROG 1126 in NW element 1102 includes a set of program instructions which, when executed by the associated DP 1120, enable the device to operate in accordance with the example embodiments of the present disclosure, as detailed above. UE 1105 also stores software 1111 in its MEM 1108 to implement certain example embodiments of this disclosure. Thus, the example embodiments of this disclosure may be implemented at least in part by computer software stored on MEMs 1108 and 1122, which is executed by the DP 1106 of the UE 1105, and / or by the DP 1120 of NW element 1102, or by hardware, or by a combination of stored software and hardware and / or firmware. Electronic devices implementing these embodiments of the disclosure may be one or more components of same such as the previously described stored software, hardware, firmware and DP, or a system on a chip, SoC, or an application specific integrated circuit, ASIC.

[0061] Data processors 1120 and 1106 may comprise, for example, at least one of a microprocessor, application-specific integrated chip, ASIC, field-programmable gate array, FPGA, and a microcontroller. Data processors 1120 and 1106 may comprise at least one, and in some embodiments more than one, processing core. Memory 1122 and 1108 may comprise, for example, at least one of magnetic, optical and holographic or other kind or kinds of memory. At least part of memory 1122 and 1108 may be comprised in data processors 1120 and 1106, respectively. At least part of memory 1122 and 1108 may be comprised externally to data processor 1120 and 1106. The various embodiments of UE 1105 can include, but are not limited to, personal portable digital devices having wireless communication capabilities, including but not limited to smart devices, mobile devices, wireless handsets, cellular telephones, navigation devices, sensor devices, actuator devices, laptop / palmtop / tablet computers, digital cameras and music devices, and Internet appliances. The various embodiments of NW element or access device 1102 can include but are not limited to communication devices having wireless communication and control capabilities, including but not limited to gNB-type devices that are tailored to control the devices within the subnetwork, UE-type devices that have the control functionalities to manage the devices within the subnetwork.

[0062] Various embodiments of the computer readable MEMs 1108 and 1122 include any data storage technology type which is suitable to the local technical environment,which includes but not limited to semiconductor based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory, removable memory, disc memory, flash memory, DRAM, SRAM, EEPROM and the like. Various embodiments of the DPs 1120 and 1106 include but are not limited to general purpose computers, special purpose computers, microprocessors, digital signal processors, DSPs, and multi-core processors.

[0063] The memory and the computer program instructions may be configured, with the processor for the particular device, to cause a hardware apparatus such as user equipment and or NW element to perform any of the processes described in FIGs 1 to 11. Therefore, in certain embodiments, a non-transitory computer-readable medium may be encoded with computer instructions that, when executed in hardware, perform a process such as one of the processes described herein. Alternatively, certain embodiments may be performed entirely in hardware.

[0064] In certain embodiments, an apparatus may include circuitry configured to perform any of the processes or functions illustrated in FIGs 1 through 11. For example, circuitry may be hardware-only circuit implementations, such as analog and / or digital circuitry. In another example, circuitry may be a combination of hardware circuits and software, and at least one memory that work together to cause an apparatus to perform various processes or functions. In yet another example, circuitry may be hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of a microprocessor(s), that include software, such as firmware for operation. Software in circuitry may not be present when it is not needed for the operation of the hardware.

[0065] According to a first embodiment, a method may comprise receiving, from a network device, a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block may comprise at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block. The first synchronization block may be quasi co-location source for physical downlink control channel reception.

[0066] The first reference signal may comprise a tracking reference signal. The first synchronization part may comprise at least one symbol. The first index of the first synchronization part may comprise at least one of: a symbol index, or a logical symbol index. The symbol index may correspond to the logical symbol index, and both may be reference index of the first synchronization part. The first synchronization block may comprise multiple synchronization parts, including the at least two non- consecutive synchronization parts. The at least two non-consecutive synchronization parts may be a number of symbols apart in time domain. The number of symbols may include at least one of: a fixed number of symbols, or a non-fixed number of symbols.

[0067] The method may further comprise receiving a second reference signal in a second synchronization part of the first synchronization block, wherein the at least two non-consecutive synchronization parts may comprise the first synchronization part and the second synchronization part. The second reference signal may comprise a TRS. This TRS may be a repeat of the TRS, which is the first RS, received in the first synchronization part. The first synchronization part and the second synchronization part may be four symbols apart in time domain. The method may further comprise receiving a second synchronization block, wherein at least part of the first synchronization block may interleave with at least part of the second synchronization block.

[0068] The method may further comprise receiving at least one of: configuration or indication, indicating that the first synchronization block is quasi co-location source for physical downlink control channel reception. The method may further comprise receiving, in at least one synchronization part of the first synchronization block, at least one of: at least one physical broadcast channel signal or at least one synchronization signal, wherein the at least one of: at least one physical broadcast channel signal or at least one synchronization signal is multiplexed with the first reference signal in frequency domain.

[0069] One or more guard band may be used in the at least one synchronization part of the first synchronization block and a size of the one or more guard band may be based on the at least one synchronization signal. The at least one synchronization signal may comprise at least one of: a primary synchronization signal or a secondary synchronization signal. The size of the one or more guard band, in response to the atleast one synchronization signal being the primary synchronization signal, may be larger than the size of the one or more guard band, in response to the at least one synchronization signal being the secondary synchronization signal. The channel estimation may comprise at least one of: delay spread, average delay, Doppler shift, or Doppler spread. In response to that each of two of the at least two non-consecutive synchronization parts, allocated for secondary synchronization signals, being apart from each other with a fixed number of symbols, the secondary synchronization signals in a first of the two of the at least two non-consecutive synchronization parts may be repeated in a second of the two of the at least two non-consecutive synchronization parts.

[0070] The method may further comprise receiving another synchronization block. The first synchronization block may comprise a first separation mode for multiple synchronization parts in the first synchronization block, and the other synchronization block may comprise a second separation mode for multiple synchronization parts in the other synchronization block. The first separation mode may be used in a first frequency range and the second separation mode may be used in a second frequency range.

[0071] According to a second embodiment, a method may comprise providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, may be quasi co-location source for physical downlink control channel reception, wherein the first synchronization block may comprise at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block. The first reference signal may comprise a tracking reference signal. The first synchronization part may comprise at least one symbol. The first index of the first synchronization part may comprise at least one of: a symbol index, or a logical symbol index. The symbol index may correspond to the logical symbol index, and both may be reference index of the first synchronization part. The first synchronization block may comprise multiple synchronization parts, including the at least two non-consecutive synchronization parts. The at least two non-consecutive synchronization parts may be a number of symbols apart in time domain. The numberof symbols may include at least one of: a fixed number of symbols, or a non-fixed number of symbols.

[0072] The method may further comprise transmitting, to the user equipment, a second reference signal in a second synchronization part of the first synchronization block, wherein the at least two non-consecutive synchronization parts may comprise the first synchronization part and the second synchronization part. The first synchronization part and the second synchronization part may be four symbols apart in time domain. The second reference signal may comprise a TRS. This TRS may be a repeat of the TRS, which is the first RS, received in the first synchronization part.

[0073] The method may further comprise transmitting a second synchronization block, wherein at least part of the first synchronization block may interleave with at least part of the second synchronization block. The method may further comprise transmitting, in at least one synchronization part of the first synchronization block, at least one of: at least one physical broadcast channel signal or at least one synchronization signal. The at least one of: at least one physical broadcast channel signal or at least one synchronization signal may be multiplexed with the first reference signal in frequency domain.

[0074] One or more guard band may be used in the at least one synchronization part of the first synchronization block and a size of the one or more guard band may be based on the at least one synchronization signal. The at least one synchronization signal may comprise at least one of: a primary synchronization signal or a secondary synchronization signal. The size of the one or more guard band, in response to the at least one synchronization signal being the primary synchronization signal, may be larger than the size of the one or more guard band, in response to the at least one synchronization signal being the secondary synchronization signal. The channel estimation may comprise at least one of: delay spread, average delay, Doppler shift, or Doppler spread. In response to that each of two of the at least two non-consecutive synchronization parts, allocated for secondary synchronization signals, being apart from each other with a fixed number of symbols, the secondary synchronization signals in a first of the two of the at least two non-consecutive synchronization parts may be repeated in a second of the two of the at least two non-consecutive synchronization parts.

[0075] The method may further comprise receiving another synchronization block, wherein the first synchronization block may comprise a first separation mode for multiple synchronization parts in the first synchronization block, and the other synchronization block may comprise a second separation mode for multiple synchronization parts in the other synchronization block, and wherein the first separation mode may be used in a first frequency range and the second separation mode may be used in a second frequency range.

[0076] According to a third and fourth embodiment, an apparatus may comprise at least one processor and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform the method according to any of the first and second embodiment, and any of their variants.

[0077] According to a fifth and sixth embodiment, an apparatus may comprise means for performing the method according to any of the first and second embodiment, and any of their variants.

[0078] According to a seventh and eighth embodiment, a non-transitory computer readable medium may comprise program instructions stored thereon for performing the method according to any of the first and second embodiment, and any of their variants.

[0079] According to an ninth and tenth embodiment, a non-transitory computer readable medium may comprise program instructions that, when executed by an apparatus, cause the apparatus to at least perform according to any of the first and second embodiment, and any of their variants.

[0080] According to a eleventh and twelfth embodiment, a computer program may comprise instructions stored thereon for performing a method according to any of the first and second embodiment, and any of their variants.

[0081] According to a thirteenth and fourteenth embodiment, a computer program may comprise instructions which, when executed by an apparatus, cause the apparatus to perform a method according to any of the first and second embodiment, and any of their variants.

[0082] According to a fifteenth embodiment, an apparatus may comprise at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive a first reference signal in a first synchronization part of a first synchronization block, wherein the firstsynchronization block comprises at least two non-consecutive synchronization parts; determine at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and perform channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0083] According to a sixteenth embodiment, an apparatus may comprise at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: provide, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmit, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0084] According to a seventeenth embodiment, an apparatus may comprise means for: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0085] According to an eighteenth embodiment, an apparatus may comprise means for: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non- consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0086] According to a nineteenth embodiment, a computer program may comprise instructions stored thereon for performing at least the following: receiving a firstreference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0087] According to a twentieth embodiment, a non-transitory computer readable medium may comprise program instructions that, when executed by an apparatus, cause the apparatus to perform at least the following: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0088] According to a twenty-first embodiment, a non-transitory computer readable medium may comprise program instructions stored thereon for performing at least the following: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

[0089] According to a twenty-second embodiment, a computer program may comprise instructions stored thereon for performing at least the following: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi colocation source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronizationblock.

[0090] According to a twenty-third embodiment, a non-transitory computer readable medium may comprise program instructions stored thereon for performing at least the following: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non- consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

[0091] The foregoing description is illustrative, which means various alternatives and modifications may be performed by one skilled in the art. Features from various embodiments described above may be selectively combined into a new embodiment. The description is intended to embrace all such alternatives, modifications, and variances which fall within the scope of the appended claims.

[0092] The features, structures, or characteristics of certain embodiments described throughout this specification may be combined in any suitable manner in one or more embodiments. For example, the usage of the phrases “an example embodiment”, “one example embodiment”, “another example embodiment”, “a further example embodiment”, “some example embodiment”, “an additional example embodiment”, or similar language, throughout this specification refers to the fact that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present disclosure. Thus, appearance of the phrases “an example embodiment”, “one example embodiment”, “another example embodiment”, “a further example embodiment”, “some example embodiment”, “an additional example embodiment”, or similar language, throughout this specification does not necessarily limit to the same group of embodiments, and the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0093] One with ordinary skill in the art will readily understand that certain embodiments discussed above may be practiced with steps in a different order, and / or with hardware elements in configurations which are different than thosewhich are disclosed. Therefore, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the disclosure. Reference should be made to the appended claims in order to determine the metes and bounds of the disclosure.

[0094] Partial Glossary

[0095] 3GPP 3rdGeneration Partnership Project

[0096] 5G 5thgeneration

[0097] 6G 6thgeneration

[0098] AP access point

[0099] ASIC application specific integrated circuit

[0100] BS base station

[0101] BWP bandwidth part

[0102] CSI channel state information

[0103] CSI-RS channel state information reference signal

[0104] DMRS demodulation reference signal

[0105] DP data processor

[0106] DSP digital signal processor

[0107] eNB evolved node B

[0108] gNB next generation eNB

[0109] FPGA field-programmable gate array

[0110] MIMO multiple input multiple output

[0111] NR new radio

[0112] NW network

[0113] NZP CSI-RS non-zero power channel state information reference signal

[0114] PBCH physical broadcast channel

[0115] PDCCH physical downlink control channel

[0116] PDSCH physical downlink shared channel

[0117] PSS primary synchronization signal

[0118] scs subcarrier spacing

[0119] ss synchronization signals

[0120] sss secondary synchronization signal

[0121] RE resource element

[0122] RB resource block

[0123] RS reference signal

[0124] TRS tracking reference signal

[0125] QCL quasi-collocation

[0126] SoC system on a chip

[0127] SSB synchronization signal block

[0128] UE user equipment

[0129] UL uplink

Claims

WE CLAIM:

1. An apparatus comprising: at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determine at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and perform channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

2. The apparatus of claim 1, wherein the first reference signal comprises a tracking reference signal.

3. The apparatus of claim 1 or 2, wherein the first synchronization part comprises at least one symbol.

4. The apparatus of any one of claims 1 to 3, wherein the first index of the first synchronization part comprises at least one of: a symbol index, or a logical symbol index.

5. The apparatus of claim 4, wherein the symbol index corresponds to the logical symbol index, and both are reference index of the first synchronization part.

6. The apparatus of any one of claims 1 to 5, wherein the first synchronization block comprises multiple synchronization parts, including the at least two non- consecutive synchronization parts.

7. The apparatus of any one of claims 1 to 6, wherein the at least two non- consecutive synchronization parts are a number of symbols apart in time domain.

8. The apparatus of claim 7, wherein the number of symbols includes at least one of: a fixed number of symbols, or a non-fixed number of symbols.

9. The apparatus of any one of claims 1 to 8, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive a second reference signal in a second synchronization part of the first synchronization block, wherein the at least two non-consecutive synchronization parts comprise the first synchronization part and the second synchronization part.

10. The apparatus of claim 9, wherein the first synchronization part and the second synchronization part are four symbols apart in time domain.

11. The apparatus of any one of claims 1 to 10, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive a second synchronization block; wherein at least part of the first synchronization block interleaves with at least part of the second synchronization block.

12. The apparatus of any one of claims 1 to 11, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive at least one of: configuration or indication, indicating that the first synchronization block is quasi co-location source for physical downlink control channel reception.

13. The apparatus of any one of claims 1 to 12, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive, in at least one synchronization part of the first synchronization block, at least one of: at least one physical broadcast channel signal or at least one synchronization signal, wherein the at least one of: at least one physical broadcast channel signal or at least one synchronization signal is multiplexed with the first reference signal in frequency domain.

14. The apparatus of claim 13, wherein one or more guard band is used in the at least one synchronization part of the first synchronization block and a size of the one or more guard band is based on the at least one synchronization signal, and wherein the at least one synchronization signal comprises at least one of: a primary synchronization signal or a secondary synchronization signal.

15. The apparatus of claim 14, wherein the size of the one or more guard band, in response to the at least one synchronization signal being the primary synchronization signal, is larger than the size of the one or more guard band, in response to the at least one synchronization signal being the secondary synchronization signal.

16. The apparatus of any one of claims 1 to 15, wherein the channel estimation comprises at least one of: delay spread, average delay,Doppler shift, orDoppler spread.

17. The apparatus of any one of claims 1 to 16, wherein in response to that each of two of the at least two non-consecutive synchronization parts, allocated for secondary synchronization signals, are apart from each other with a fixednumber of symbols, the secondary synchronization signals in a first of the two of the at least two non-consecutive synchronization parts is repeated in a second of the two of the at least two non-consecutive synchronization parts.

18. The apparatus of any one of claims 1 to 17, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive another synchronization block, wherein the first synchronization block comprises a first separation mode for multiple synchronization parts in the first synchronization block, and the other synchronization block comprises a second separation mode for multiple synchronization parts in the other synchronization block, and wherein the first separation mode is used in a first frequency range and the second separation mode is used in a second frequency range.

19. An apparatus comprising: at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: provide, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmit, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

20. The apparatus of claim 19, wherein the first reference signal comprises a tracking reference signal.

21. The apparatus of claim 19 or 20, wherein the first synchronization part comprises at least one symbol.

22. The apparatus of any one of claims 19 to 21, wherein the first index of the first synchronization part comprises at least one of: a symbol index, or a logical symbol index.

23. apparatus of claim 22, wherein the symbol index corresponds to the logical symbol index, and both are reference index of the first synchronization part.

24. The apparatus of any one of claims 19 to 23, wherein the first synchronization block comprises multiple synchronization parts, including the at least two non- consecutive synchronization parts.

25. The apparatus of any one of claims 19 to 24, wherein the at least two non- consecutive synchronization parts are a number of symbols apart in time domain.

26. The apparatus of claim 25, wherein the number of symbols includes at least one of: a fixed number of symbols, or a non-fixed number of symbols.

27. The apparatus of any one of claims 19 to 26, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit, to the user equipment, a second reference signal in a second synchronization part of the first synchronization block, wherein the at least two non-consecutive synchronization parts comprise the first synchronization part and the second synchronization part.

28. The apparatus of claim 27, wherein the first synchronization part and the secondsynchronization part are four symbols apart in time domain.

29. The apparatus of any one of claims 19 to 28, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit a second synchronization block; wherein at least part of the first synchronization block interleaves with at least part of the second synchronization block.

30. The apparatus of any one of claims 19 to 29, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit, in at least one synchronization part of the first synchronization block, at least one of: at least one physical broadcast channel signal or at least one synchronization signal, wherein the at least one of: at least one physical broadcast channel signal or at least one synchronization signal is multiplexed with the first reference signal in frequency domain.

31. The apparatus of claim 30, wherein one or more guard band is used in the at least one synchronization part of the first synchronization block and a size of the one or more guard band is based on the at least one synchronization signal, and wherein the at least one synchronization signal comprises at least one of: a primary synchronization signal or a secondary synchronization signal.

32. The apparatus of claim 31, wherein the size of the one or more guard band, in response to the at least one synchronization signal being the primary synchronization signal, is larger than the size of the one or more guard band, in response to the at least one synchronization signal being the secondary synchronization signal.

33. The apparatus of any one of claims 19 to 32, wherein the channel estimation comprises at least one of:delay spread, average delay, Doppler shift, or Doppler spread.

34. The apparatus of any one of claims 19 to 33, wherein in response to that each of two of the at least two non-consecutive synchronization parts, allocated for secondary synchronization signals, are apart from each other with a fixed number of symbols, the secondary synchronization signals in a first of the two of the at least two non-consecutive synchronization parts is repeated in a second of the two of the at least two non-consecutive synchronization parts.

35. The apparatus of any one of claims 19 to 34, wherein the at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive another synchronization block, wherein the first synchronization block comprises a first separation mode for multiple synchronization parts in the first synchronization block, and the other synchronization block comprises a second separation mode for multiple synchronization parts in the other synchronization block, and wherein the first separation mode is used in a first frequency range and the second separation mode is used in a second frequency range.

36. A method comprising: receiving, from a network device, a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of:the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

37. A method comprising: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; and transmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

38. An apparatus comprising means for: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

39. An apparatus comprising means for: providing, to a user equipment, at least one of: configuration or indication, indicating that a first synchronization block, with a first index of the first synchronization block, is quasi co-location source for physical downlink control channel reception, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; andtransmitting, to the user equipment, a first reference signal in a first synchronization part, with a first index of the first synchronization part, of the first synchronization block.

40. A computer program comprising instructions stored thereon for performing at least the following: receiving a first reference signal in a first synchronization part of a first synchronization block, wherein the first synchronization block comprises at least two non-consecutive synchronization parts; determining at least one of: a first index of the first synchronization part, or a first index of the first synchronization block; and performing channel estimation based, at least partially, on at least one of: the received first reference signal, the first index of the first synchronization part, or the first index of the first synchronization block.

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