Method for manufacturing semiconductor wafer, and semiconductor wafer

Abstract

[Problem] To reduce the width of a scribe lane in individual directions provided in a lattice shape on a semiconductor wafer. [Solution] This method for manufacturing a semiconductor wafer includes forming a plurality of semiconductor chips in a matrix shape within a chip region included in each of a plurality of shot regions provided to a wafer body, and forming a test circuit within a test region provided along an end side of the chip region. The plurality of shot regions are arranged on the wafer body so that the arrangements of the plurality of semiconductor chips in the matrix directions are aligned between the plurality of shot regions.

Description

Semiconductor wafer manufacturing method and semiconductor wafer

[0001] The present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor wafer.

[0002] In the manufacture of semiconductor chips, the semiconductor chips are formed in chip regions defined by division lines (also called scribe lanes) arranged in a grid pattern on the surface of a wafer. After the semiconductor chips are formed in the chip regions, the wafer is divided along the scribe lanes to separate the semiconductor chips.

[0003] On the other hand, as the size of semiconductor chips decreases, there is a demand for dividing wafers with narrower scribe lanes.

[0004] For example, Patent Document 1 below discloses forming accessory patterns only in scribe lanes, among scribe lanes arranged in a grid pattern on the surface of a semiconductor wafer, that extend in a direction in which the semiconductor wafer cannot be cleaved. The accessory patterns include alignment marks for positioning used in the exposure process of semiconductor chips, or test patterns for inspecting semiconductor chips. The semiconductor wafer disclosed in Patent Document 1 can further reduce the width of scribe lanes in which accessory patterns are not formed, that extend in a direction in which the semiconductor wafer can be cleaved.

[0005] JP 2016-134427 A

[0006] However, in the semiconductor wafer disclosed in Patent Document 1, it is difficult to reduce the width of the scribe lane in which the accessory pattern is formed, which extends in a direction in which the semiconductor wafer cannot be cleaved.

[0007] Therefore, the present invention has been made in consideration of the above problems, and an object of the present invention is to provide a new and improved method for manufacturing a semiconductor wafer, and a semiconductor wafer, which are capable of reducing the width of scribe lanes arranged in a grid pattern in each direction.

[0008] In order to solve the above problem, according to one aspect of the present invention, a method for manufacturing a semiconductor wafer is provided, which includes forming a plurality of semiconductor chips in a matrix in a chip area included in each of a plurality of shot areas provided on a wafer body, and forming a test circuit in a test area provided along an edge of the chip area, and the plurality of shot areas are arranged on the wafer body so that the matrix direction arrangement of the plurality of semiconductor chips is aligned between the plurality of shot areas.

[0009] In addition, in order to solve the above-mentioned problems, according to another aspect of the present invention, a semiconductor wafer is provided which includes a wafer body having a plurality of shot areas each including a chip area in which a plurality of semiconductor chips are arranged in a matrix, and a test area including a test circuit and arranged along an edge of the chip area, and the plurality of shot areas are arranged on the wafer body so that the matrix direction arrangement of the plurality of semiconductor chips is aligned between the plurality of shot areas.

[0010] As described above, according to the present invention, it is possible to reduce the width of the scribe lanes in each direction that are provided in a grid pattern on a semiconductor wafer.

[0011] It is a plan view showing the overall configuration of a semiconductor wafer according to an embodiment of the present invention. It is a plan view showing the configuration of a shot area provided on the semiconductor wafer. It is a plan view showing the overall configuration of a semiconductor wafer on which the shot area shown in Figure 2 is formed. It is a schematic view showing the transfer of semiconductor chips from the semiconductor wafer shown in Figure 3 to an alignment substrate.

[0012] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant explanations will be omitted.

[0013] 1. Semiconductor Wafer First, a semiconductor wafer according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a plan view showing the overall configuration of a semiconductor wafer 10 according to this embodiment. Figure 2 is a plan view showing the configuration of a shot region 100 provided on the semiconductor wafer 10.

[0014] 1, a plurality of shot areas 100 are arranged in a matrix on the surface of a semiconductor wafer 10 according to this embodiment. In each of the shot areas 100, a plurality of semiconductor chips 111 are formed and arranged in a matrix, as shown in FIG.

[0015] The semiconductor wafer 10 is a thin plate-shaped substrate made of a semiconductor such as silicon (Si). The semiconductor wafer 10 may be a disk-shaped substrate thinly sliced ​​from a cylindrical ingot, or may be a substrate further cut into a rectangular plate from the disk-shaped substrate. The semiconductor wafer 10 may be, for example, a silicon (Si) wafer, a silicon carbide (SiC) wafer, or a compound semiconductor (GaN, InP, GaAs, GaP, etc.) wafer. The semiconductor wafer 10 may also be a sapphire wafer or a quartz wafer with a semiconductor layer stacked on its surface.

[0016] The semiconductor wafer 10 has a linear portion (orientation flat) 11 provided on its outer edge, which serves as a mark for aligning the orientation of the semiconductor wafer 10 in the manufacturing process of the semiconductor chip 111. However, instead of the linear portion 11, a notch may be provided on the outer edge of the semiconductor wafer 10, which serves as a mark for orientation alignment.

[0017] The shot region 100 is an area that is patterned by one exposure in each of the multiple exposure processes included in the manufacturing process of the semiconductor chip 111. The exposure process is a process for forming a pattern on the surface of the semiconductor wafer 10, and in the exposure process, multiple exposures are repeatedly performed on the surface of the semiconductor wafer 10 to form a large number of semiconductor chips 111 on the surface of the semiconductor wafer 10. The area in which a pattern is formed by one exposure at this time is the shot region 100.

[0018] For example, in the exposure process, exposure using a mask may be performed on each of the shot areas 100 while repeatedly moving and stopping a stage to which the semiconductor wafer 10 is fixed. As a result, the same pattern corresponding to the mask is formed in each of the shot areas 100, and the circuit of the semiconductor chip 111 is formed in each of the shot areas 100 based on the formed pattern. Therefore, in each of the shot areas 100, the circuits of the multiple semiconductor chips 111 are each formed with the same pattern.

[0019] The shot area 100 may be located inside the outer edge of the semiconductor wafer 10 so as not to protrude from the semiconductor wafer 10 as shown in FIG. 1, or conversely, it may be located with a portion of it protruding so as not to leave any blank space on the semiconductor wafer 10.

[0020] More specifically, as shown in FIG. 2, the shot area 100 includes a chip area 110 and a test area 120 provided along the edge of the chip area 110 .

[0021] The chip region 110 is a region where a plurality of semiconductor chips 111 are formed in a matrix. The semiconductor chips 111 may be, for example, integrated circuit (IC) chips that include electronic circuits in which semiconductor elements formed on the semiconductor wafer 10 are connected by fine wiring.

[0022] The test area 120 is an area where alignment marks and test circuits are formed.

[0023] The alignment marks are provided for aligning the patterning in the multiple exposure processes. By aligning the mask in each of the multiple exposure processes based on the alignment marks, the patterns in the multiple exposure processes are overlaid with high precision. The alignment marks may be, for example, cross marks, diffraction grating marks, or Fresnel zone plates.

[0024] The test circuit is a circuit provided for quality inspection of the semiconductor chip 111. The test circuit may include, for example, a partial circuit for evaluating the performance and characteristics of the semiconductor chip 111. The test circuit may also include patterns such as wiring and contacts for evaluating the manufacturing process of the semiconductor chip 111, and may also include an electronic circuit for evaluating the performance and characteristics of the semiconductor elements included in the semiconductor chip 111.

[0025] The test area 120 including the alignment marks and the test circuit is provided, for example, along an edge of the rectangular chip area 110. In the example shown in Fig. 2, the test area 120 is provided along the left edge of the chip area 110 as viewed from the front of Fig. 2. However, the test area 120 may be provided along the right, upper, or lower edge of the chip area 110 as viewed from the front of Fig. 2, or may be provided along multiple edges of the chip area 110.

[0026] The alignment marks included in the test area 120 are used to align the exposure to the shot area 100, so it is sufficient that the alignment marks are provided for each shot area 100, not for each semiconductor chip 111. Furthermore, the test circuit included in the test area 120 is used to detect the effects of exposure variations for each shot area 100, or in-plane variations within the semiconductor wafer 10, etc.

[0027] In the semiconductor wafer 10 according to this embodiment, a test region 120 in which alignment marks and test circuits are formed and a chip region 110 in which semiconductor chips 111 are formed are provided as separate regions. As a result, only the semiconductor chips 111 are formed in the chip region 110, and therefore it is possible to narrow the width of the scribe lanes between the semiconductor chips 111 to the width required for dividing the semiconductor wafer 10, regardless of the extension direction.

[0028] For example, when dividing the semiconductor wafer 10 by dry etching, it is possible to divide the semiconductor wafer 10 and separate the semiconductor chips 111 by etching scribe lanes having a width of 0.5 μm to 10 μm provided between the semiconductor chips 111. In such a case, the semiconductor wafer 10 according to this embodiment allows the width of the scribe lanes between the semiconductor chips 111 to be narrowed to approximately 0.5 μm to 10 μm.

[0029] As described above, the semiconductor wafer 10 according to this embodiment can narrow the width of the scribe lanes between the semiconductor chips 111 formed on the surface, regardless of the extension direction. As a result, the semiconductor wafer 10 according to this embodiment can reduce the width of the scribe lanes in each direction that are provided in a grid pattern on the surface.

[0030] 2. Transfer of Semiconductor Chips Next, the transfer of the semiconductor chips 111 formed on the semiconductor wafer 10 to the alignment substrate will be described with reference to Figures 3 and 4. Figure 3 is a plan view showing the overall configuration of the semiconductor wafer 10 on which the shot regions 100 shown in Figure 2 are formed. Figure 4 is a schematic diagram showing the transfer of the semiconductor chips 111 from the semiconductor wafer 10 shown in Figure 3 to the alignment substrate 20. The alignment substrate 20 is a substrate for aligning the semiconductor chips 111 at a desired arrangement pitch by transferring the semiconductor chips 111 formed on the semiconductor wafer 10.

[0031] In the semiconductor wafer 10 according to this embodiment, shot areas 100 including test areas 120 and chip areas 110 shown in FIG. 2 are arranged in a matrix on the surface of the semiconductor wafer 10. Each of the multiple shot areas 100 has the same pattern because it is formed in an exposure process using the same mask. Therefore, as shown in FIG. 3, the semiconductor wafer 10 can connect the chip areas 110 and the test areas 120 between the multiple shot areas 100.

[0032] Specifically, the test area 120 extending in the vertical direction on the left side of the shot area 100 is connected between the multiple shot areas 100, thereby extending in the vertical direction from the upper end to the lower end of the semiconductor wafer 10. Furthermore, the chip areas 110 are connected so that the arrangement pitch of the semiconductor chips 111 between the chip areas 110 matches the arrangement pitch of the semiconductor chips 111 within the chip area 110, thereby allowing the arrangement of the semiconductor chips 111 to be continuous between the multiple shot areas 100.

[0033] 4, in the product area CA where a plurality of chip areas 110 are successively arranged in the vertical direction, the semiconductor chips 111 are arranged at the same arrangement pitch without any gaps. Therefore, it is possible to transfer the semiconductor chips 111 formed in the product area CA collectively from the semiconductor wafer 10 to the alignment substrate 20.

[0034] For example, if the desired arrangement pitch of the semiconductor chips 111 on the alignment substrate 20 is the same as the arrangement pitch of the semiconductor chips 111 formed in the chip area 110, it is possible to transfer the semiconductor chips 111 formed in the product area CA all at once to the alignment substrate 20. In such a case, since the semiconductor chips 111 formed in the product area CA are arranged at the same arrangement pitch as the desired arrangement pitch on the alignment substrate 20, the transferred semiconductor chips 111 are aligned on the alignment substrate 20 at the desired arrangement pitch.

[0035] Furthermore, when the desired arrangement pitch of the semiconductor chips 111 on the alignment substrate 20 is an integer multiple of the arrangement pitch of the semiconductor chips 111 formed in the chip area 110, it is possible to transfer the semiconductor chips 111 formed in the product area CA to the alignment substrate 20 all at once while thinning them out. That is, the semiconductor chips 111 present in the product area CA can be thinned out to an arrangement pitch corresponding to the integer multiple and then transferred to the alignment substrate 20. In such a case, the semiconductor chips 111 formed in the product area CA are thinned out by the number corresponding to the integer multiple and transferred, so that the transferred semiconductor chips 111 are aligned on the alignment substrate 20 at the desired arrangement pitch.

[0036] Therefore, in the semiconductor wafer 10 according to this embodiment, the semiconductor chips 111 present in the product area CA can be transferred collectively onto the alignment substrate 20 .

[0037] The plurality of semiconductor chips 111 transferred to the alignment substrate 20 are further transferred to, for example, a display substrate of a micro LED (Light Emitting Diode) display. Specifically, it is important that the LED driving ICs in the micro LED display are mounted on the display substrate in an arrangement that matches the arrangement pitch of the LED pixels. Therefore, the alignment substrate 20 aligns the plurality of LED driving ICs at the arrangement pitch of the LED pixels, making it possible to mount the LED driving ICs collectively on the display substrate of the micro LED display.

[0038] Although the preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to these examples. It is clear that a person skilled in the art to which the present invention pertains can conceive of various modifications and alterations within the scope of the technical ideas set forth in the claims, and it is understood that these also naturally fall within the technical scope of the present invention.

[0039] 10...semiconductor wafer, 20...alignment substrate, 100...shot area, 110...chip area, 120...test area, 111...semiconductor chip, CA...product area

Claims

1. A method for manufacturing a semiconductor wafer, comprising: forming a plurality of semiconductor chips in a matrix in a chip area included in each of a plurality of shot areas provided on a wafer body; and forming a test circuit in a test area provided along the edge of the chip area; wherein the plurality of shot areas are arranged on the wafer body so that the matrix direction arrangement of the plurality of semiconductor chips is consistent between the plurality of shot areas.

2. The method for manufacturing a semiconductor wafer according to claim 1, wherein the semiconductor chip and the test circuit are formed in a manufacturing process including multiple exposure steps.

3. The method for manufacturing a semiconductor wafer according to claim 2, wherein in each of the multiple exposure steps, exposure is performed on the multiple shot areas using the same mask.

4. The method for manufacturing a semiconductor wafer according to claim 2, wherein an alignment mark is further formed in the test area, and the alignment mark is used for aligning exposure in each of the multiple exposure steps.

5. The method for manufacturing a semiconductor wafer according to claim 2, wherein the shot area is an area where patterning is performed in one exposure.

6. A method for manufacturing a semiconductor wafer according to any one of claims 1 to 5, wherein the plurality of shot areas are further arranged on the wafer body so that the test areas are connected to each other in the extension direction of the test areas between the plurality of shot areas.

7. The method for manufacturing a semiconductor wafer according to claim 6, wherein the plurality of semiconductor chips provided in the plurality of chip regions are diced into individual chips and then transferred collectively to an alignment substrate.

8. The method for manufacturing a semiconductor wafer according to claim 7, wherein the arrangement pitch of the plurality of semiconductor chips on the alignment substrate is an integral multiple of 1 or more of the arrangement pitch of the plurality of semiconductor chips on the wafer body.

9. A semiconductor wafer comprising: a wafer body provided with a plurality of shot areas, each of which includes a chip area in which a plurality of semiconductor chips are arranged in a matrix, and a test area including a test circuit and arranged along an edge of the chip area; wherein the plurality of shot areas are arranged on the wafer body such that the arrangement of the plurality of semiconductor chips in the matrix direction is aligned between the plurality of shot areas.

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