Bus system, bus control device, and bus control method

Abstract

A bus system according to the present disclosure comprises: a first controller that has controller authority during an initial state; and one or more second controllers that are connected to the first controller via a bus. When having handed over the controller authority to a specific second controller from among the one or more second controllers, the first controller transmits an interrupt signal to the bus, and determines, on the basis of a response to the interrupt signal, whether the second controller having the controller authority is present on the bus.

Description

BUS SYSTEM, BUS CONTROL DEVICE, AND BUS CONTROL METHOD

[0001] The present disclosure relates to a bus system, a bus control device, and a bus control method.

[0002] In recent years, the traditional I 2 As a serial interface to replace Inter-Integrated Circuit (registered trademark), 3 Improved Inter Integrated Circuit (IIC) (registered trademark) has been developed. 3 C is I 2 While maintaining compatibility with C, it is designed to be fast and easy to set up.

[0003] "Specification for I3C", MIPI Alliance Inc (US), 11 June 2021, Version 1.1.1

[0004] I 3 In the C bus system, the protocol does not work unless there is at least one controller on the bus. 3 Since the pull-up control of C is usually the responsibility of the controller, if there is no controller on the bus, the bus level will become unstable if a high level is expected from the pull-up resistor. Therefore, if a device in the controller role leaves the bus, 3 It cannot function as a C-bus system and the controller is 3 It is necessary to restore the C bus and restart the system.

[0005] Also, I 3 In a multiple controller system, if a secondary controller leaves the bus while the controller authority is still transferred, the system will stop. Even if the secondary controller is allowed to join the bus again, it will join as a target, so this is not a recovery measure. For this reason, in the past, it was not possible to freely move the secondary controller to the I / O 3 It was not possible to insert or remove it from the C bus.

[0006] Therefore, the present disclosure 3It is an object of the present invention to provide a bus system, a bus control device and a bus control method that allow the controller to be freely inserted and removed in the bus system.

[0007] The bus system of the present disclosure includes a first controller that has controller authority in an initial state, and one or more second controllers that are connected to the first controller via a bus, and when the first controller delegates the controller authority to a specific second controller among the one or more second controllers, it sends an interrupt signal to the bus and determines whether or not the second controller with the controller authority is present on the bus based on the response to the interrupt signal.

[0008] FIG. 1 is a schematic diagram illustrating a configuration of a bus system applicable to an embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating a schematic description of delegation of controller authority in a bus system applicable to an embodiment of the present disclosure. FIG. 3 is a schematic diagram illustrating a schematic description of holding and releasing of controller authority in a bus system applicable to an embodiment of the present disclosure. FIG. 4 is a block diagram illustrating a configuration of an example of a primary / secondary controller applicable to an embodiment. FIG. 5 is a flowchart illustrating an example of a process for delegating controller authority between controllers applicable to an embodiment. FIG. 6 is a timing chart illustrating an example of a process for delegating controller authority between controllers applicable to an embodiment. FIG. 7 is a timing chart illustrating an example of a process for delegating controller authority between controllers applicable to an embodiment. FIG. 8 is a schematic diagram illustrating a configuration of a bus system according to an existing technology. FIG. 9 is a schematic diagram illustrating a configuration of an example of a bus system according to an embodiment of the present disclosure. FIG. 10 is a schematic diagram illustrating a state in which a secondary controller having control authority has left the bus according to an embodiment. FIG. 11 is a schematic diagram illustrating a state in which a secondary controller having control authority has left the bus according to an embodiment. FIG. 12 is a flowchart illustrating an example of a process according to an embodiment. FIG. 1 is a schematic diagram for explaining a determination process using a data signal SDA and a clock signal SCL according to an embodiment. FIG. 2 is a functional block diagram of an example for explaining a function for executing autonomous acquisition of a controller role according to an embodiment. FIG. 3 is a sequence diagram for explaining a process in which a primary controller autonomously acquires controller authority according to an embodiment. FIG. 4 is a sequence diagram for explaining a process in which a primary controller autonomously acquires controller authority according to an embodiment. FIG. 5 is a sequence diagram for explaining a role selection process in which a secondary controller rejoins the bus according to an embodiment. FIG. 6 is a sequence diagram for explaining a role selection process in which a secondary controller rejoins the bus according to an embodiment.1 is a sequence diagram illustrating a role selection process when a secondary controller rejoins the bus according to an embodiment; FIG. 2 is a schematic diagram illustrating an example configuration for keeping the bus in either a normal high state or a weak high state according to an embodiment; FIG. 3 is a schematic diagram illustrating deep sleep according to an embodiment; FIG. 4 is a schematic diagram illustrating a power-off state according to an embodiment;

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and redundant description will be omitted.

[0010] Hereinafter, embodiments of the present disclosure will be described in the following order: 1. Technology applicable to embodiments of the present disclosure 1-1. Bus system applicable to embodiments 1-2. Configuration applicable to embodiments 2. Existing technology 3. Embodiments of the present disclosure 3-1. Overview of embodiments 3-2. Processing according to embodiments 3-3. Specific examples of processing according to embodiments 3-4. Control when a controller leaves the bus according to embodiments

[0011] (1. Techniques Applicable to Embodiments of the Present Disclosure) The present disclosure relates to control of a bus system. 3 A bus system according to Improved Inter Integrated Circuit (IIC) (registered trademark) may be applied. Hereinafter, a bus system according to an embodiment of the present disclosure will be referred to as an IIC. 3 In the following, the bus system will be described as being related to I 3 The bus system related to C is "I 3 It is sometimes called the C bus.

[0012] (1-1. Bus System Applicable to the Embodiments) FIG. 1 is a schematic diagram illustrating the configuration of a bus system applicable to the embodiments of the present disclosure. In the example of section (a) of FIG. 1, a bus system 1 applicable to the embodiments includes, for example, I 3One primary controller 10 and multiple secondary controllers 30, 30, and 30 are connected to a C bus 20. The bus 20 includes a signal line 20a for transmitting a data signal SDA and a signal line 20b for transmitting a clock signal SCL.

[0013] When there is no need to particularly distinguish between the secondary controllers 30, 30, and 30, they will be represented in the following description by the secondary controller 30. Furthermore, because a common configuration can be applied to the primary controller 10 and the secondary controller 30, when there is no need to particularly distinguish between them, the primary controller 10 and the secondary controller 30 may be simply referred to as "controllers" in the following description.

[0014] The primary controller 10 and the secondary controller 30 can each assume either a controller role or a target role as their role on the bus 20. The controller role is assigned to a device of the primary controller 10 or the secondary controller 30 that has controller authority, and is a role that transmits a clock signal SCL onto the bus 20 and enables transmission of a data signal SDA on the bus 20. The target role is assigned to a device of the primary controller 10 or the secondary controller 30 that does not have controller authority, and transmits a data signal SDA via the bus 20 in response to the clock signal SCL transmitted onto the bus 20.

[0015] The primary controller 10 is a device that has controller authority and is assigned the controller role in the initial state. The primary controller 10 plays a leading role in initializing the bus 20 and in data communication on the bus 20. The secondary controller 30 is usually assigned the target role, and is assigned the controller role by, for example, being delegated controller authority from the primary controller 10. Only one device assigned the controller role can exist on the bus 20. On the other hand, multiple devices assigned the target role can exist on the bus 20.

[0016] 1, the primary controller 10 and the secondary controllers 30 to 30 connected to the bus 20 can delegate controller authority among themselves. For example, the primary controller 10 may delegate controller authority to the secondary controller 30. The secondary controller 30, to which the controller authority has been delegated, may then delegate the controller authority to the secondary controller 30 or 30, or may return the controller authority to the primary controller 10.

[0017] FIG. 2 is a schematic diagram for explaining the delegation of controller authority in a bus system applicable to an embodiment of the present disclosure.

[0018] In FIG. 2, section (a) shows an example of a case where the secondary controller 30 requests the primary controller 10 to transfer controller authority. In response to the authority request from the secondary controller 30, the primary controller 10 either transfers the controller authority or rejects the authority request. Section (b) shows an example of a case where the primary controller 10 transfers controller authority to a specific secondary controller 30. The primary controller 10 confirms with the specific secondary controller 30 whether or not the controller authority can be transferred. When the primary controller 10 receives a response from the specific secondary controller 30 indicating that the controller authority can be transferred, the primary controller 10 transfers the controller authority to the specific secondary controller 30.

[0019] FIG. 3 is a schematic diagram for explaining in outline the retention and release of controller authority in a bus system applicable to an embodiment of the present disclosure.

[0020] 3, section (a) shows an example in which the secondary controller 30 to which the controller authority has been delegated retains the controller authority until a request is made. Section (b) shows an example in which the secondary controller 30 to which the controller authority has been delegated returns the controller authority to the primary controller 10 after completing a specified task. Section (c) shows an example in which the secondary controller 30 to which the controller authority has been delegated delegates the controller authority to another secondary controller 30 at any timing. The timing at which the secondary controller 30 delegates the controller authority to another secondary controller 30 may be, for example, when a task that the secondary controller 30 does not support is being executed.

[0021] (1-2. Configurations Applicable to the Embodiments) Next, configurations applicable to the embodiments of the present disclosure will be described.

[0022] 4 is a block diagram showing an example of the configuration of a primary / secondary controller 11 applicable to the embodiment. Note that the primary controller 10 and the secondary controller 30 can be realized with the same configuration, and therefore in FIG. 4 they are collectively shown as the primary / secondary controller 11.

[0023] 4, the primary / secondary controller 11 includes a target control unit 100, a controller control unit 110, a register 120, and a role change control unit 130. The target control unit 100, the controller control unit 110, the register 120, and the role change control unit 130 are connected to each other via an internal bus 140a so that they can communicate with each other.

[0024] Registers 120 include a role change register 121 and a role monitor register 122. Primary controller 10 may further include buffers 150 and 151. Buffers 150 and 151 may be configured outside primary controller 10.

[0025] The target control unit 100 includes a target control state machine 101 and a register / table 102. The register / table 102 stores its own dynamic address (DA) and static address (SA) on the bus 20, as well as synchronization data and other data. The primary / secondary controller 11 sets these dynamic addresses and static addresses, for example, in accordance with its connection to the bus 20. The synchronization data is used to pass data that the primary / secondary controller 11 had when operating in the controller role to the target role, enabling continuous operation.

[0026] The controller control unit 110 includes a controller control state machine 111 , a register / table 112 , a peripheral 113 , a microprocessor 114 , and a memory 115 .

[0027] The register / table 112 stores its own dynamic address (DA) and static address (SA) on the bus 20, a device address table (DAT), a group address table (GAAT), synchronization data, and data therefor. The dynamic address, static address, and synchronization data are the same as those stored in the register / table 102. The device address table stores the addresses on the bus 20 of each device connected to the bus 20 to which the primary / secondary controller 11 is connected. The group address table stores the addresses of each device group connected to the bus 20.

[0028] In the controller control unit 110, the microprocessor 114 is communicatively connected to the memory 115 and the register / table 112 (and the controller control state machine 111) via an internal bus 140b. The internal bus 140b is communicatively connected to the internal bus 140a. The peripheral 113 is communicatively connected to the internal bus 140b via an internal bus 140c.

[0029] 4, buffer 150 is a buffer for data signal SDA. In buffer 150, terminal Y outputs data signal SDA input to primary controller 10 as input data signal ISDA. Input data signal ISDA is passed to target control unit 100 and controller control unit 110, respectively.

[0030] In the buffer 150, an output data signal OSDA, which is a data signal output from the target control unit 100 or the controller control unit 110, is input to a terminal A. At this time, one of the output data signals OSDA output from the target control unit 100 or the controller control unit 110 is selected by a selector 160 in accordance with a control signal AXRSIG output from the controller control unit 110, and input to a terminal A of the buffer 150. The output data signal OSDA is output from the buffer 150 to, for example, a signal line 20a of the bus 20.

[0031] In the buffer 150, a terminal XOEN outputs an output enable signal XSDAOEN for switching input / output between the target control unit 100 and the controller control unit 110. The output enable signal XSDAOEN is a signal included in the bit string of the data signal SDA. The buffer 150 extracts and outputs the output enable signal XSDAOEN from the data signal SDA. The output enable signal XSDAOEN is passed to either the target control unit 100 or the controller control unit by a selection made by a selector 161 in response to the above-mentioned control signal AXRSIG output from the controller control unit 110.

[0032] 4, buffer 151 is a buffer for clock signal SCL. In buffer 151, terminal Y outputs clock signal SCL input to primary controller 10 as input clock signal ISCL. The input clock signal SCL is passed to target control unit 100. In buffer 151, terminal A inputs output clock signal OSCL, which is clock signal SCL output from controller control unit 110. The output clock signal OSCL is output from buffer 151 to signal line 20b of bus 20, for example.

[0033] The role change control unit 130 changes the state of the target control state machine 101 in the target control unit 100 and the state of the controller control state machine 111 in the controller control unit 110 based on the role information written in the register 120, more specifically, the role change register 121. The role change control unit 130 may change the state of the target control state machine 101 and the state of the controller control state machine 111 exclusively.

[0034] For example, the role change control unit 130 controls the target control state machine 101 to either the target role or disabled based on the role change information. Also, for example, the role change control unit 130 changes the controller control state machine 111 to either the controller role or disabled based on the role change information. The role change control unit 130 writes the current role of the primary / secondary controller 11 to the role monitor register 122.

[0035] The target control unit 100 and the controller control unit 110 perform a handshake by sending a request regarding the controller role from the controller control unit 110 to the target control unit 100, CTROLEREQ, and a response to the request, CTROLEREQW, CTROLEACK, and by sending a request regarding the target role from the controller control unit 110 to the target control unit 100, CTROLEREQ, and a response to the request, CTROLEREQW, TCROLEACK.

[0036] The memory 115 is a storage medium including, for example, a RAM (Random Access Memory) area and a ROM (Read Only Memory) area, and programs such as firmware (FW) are stored in the ROM area in advance. The microprocessor 114 controls the overall operation of this primary / secondary controller 11 in accordance with the firmware stored in the ROM area of ​​the memory 115, using the RAM area of ​​the memory 115 as work memory.

[0037] 5 is a flowchart showing an example of a process for transferring controller authority between controllers, which is applicable to an embodiment. In the flowchart of FIG. 5, the primary controller 10 or secondary controller 30 assigned the target role is called the "target," and the device currently executing the controller function is called the "active controller." For example, the primary controller 10 or secondary controller 30 that currently has controller authority is the active controller.

[0038] In delegating controller authority, two cases are possible: the target requests the active controller to assume the controller role (Case #1), and the active controller voluntarily grants the controller role to the device performing the target role (Case #2).

[0039] In case #1, in step S100, the target requests the active controller to assume the controller role, and the process proceeds to step S101.

[0040] On the other hand, in case #2, in step S120, the active controller issues a command GETSTATUS to the target on the bus 20 to check the status. In the next step S121, the active controller determines whether or not an error has occurred based on the response from the target on the bus 20 to the command GETSTATUS. If the active controller determines that an error has occurred (step S121, "No"), it shifts the process to step S122. On the other hand, if the active controller determines that no error has occurred (step S121, "Yes"), it shifts the process to step S101.

[0041] In step S101, the active controller that has received the controller role request in step S100 or that has detected an error in the response to the command GETSTATUS from the target in step S121 determines whether to disable interrupts. If the active controller determines not to disable interrupts (step S101, "No"), it proceeds to step S103.

[0042] If the active controller determines that the interrupt should be disabled (step S101, "Yes"), it proceeds to step S102, issues a command DISEC to the target, and disables the target event. The target event may include, for example, a hot join, an in-band interrupt (IBI), or a controller role request.

[0043] That is, in the case of the controller role, the active controller automatically issues the command DISEC in response to the response ACK to the controller role request in step S100, and disables the interrupt by the target (interrupt disable #1). This interrupt disable #1 disables target events in the target. Furthermore, the processing after the interrupt disable #1 processing is software (SW) processing.

[0044] In step S103, the active controller determines whether the current state is an appropriate activity state based on the required role switching time. If the active controller determines that the current state is an appropriate activity state (step S103, "Yes"), the active controller proceeds to step S105.

[0045] On the other hand, if the active controller determines that the activity state is not appropriate (step S103, "No"), it proceeds to step S104, issues command ENTASx to the target, and sets the active state. The active state is a waiting time for switching roles, and may be selected from a number of values, such as 1 μsec, 100 μsec, 2 msec, and 50 msec. After the active state is set in step S104, the process proceeds to step S105.

[0046] In step S105, the active controller determines whether the target supports the command GETSTATUS format 2. If the active controller determines that the target does not support the command (step S105, "No"), the process proceeds to step S112.

[0047] On the other hand, if the active controller determines that the target supports format 2 of the command GETSTATUS (step S105, "Yes"), it moves the process to step S106.

[0048] In step S106, the active controller determines whether the target is in a resynchronized deep sleep state (having synchronized data). If the active controller determines that the target is in a resynchronized deep sleep state ("Yes" in step S106), the active controller proceeds to step S108.

[0049] On the other hand, if the active controller determines that the target is not in a resynchronized deep sleep state ("No" in step S106), it shifts the process to step S107. In step S107, the active controller extracts an address from the device address table (DAT) stored in the register / table 112, issues a command DEFTGTS for data synchronization, and broadcasts it to the bus 20. After the process of step S107, the process shifts to step S108.

[0050] In step S108, the active controller determines whether the target address is an address of an active group. If the active controller determines that the address is not an address of an active group (step S108, "No"), the active controller proceeds to step S110.

[0051] On the other hand, if the active controller determines that the group address is valid ("Yes" in step S108), it proceeds to step S109. In step S109, the active controller extracts the address from the group address table (GAAT) stored in the register / table 112, issues a command DEFTGRPA to synchronize data with the address group, and broadcasts it to the bus 20. After the processing of step S109, the processing proceeds to step S110.

[0052] In step S110, the active controller determines whether the target is currently performing a processing operation. If the active controller determines that the target is not currently performing a processing operation (step S110, "No"), the active controller proceeds to step S112.

[0053] On the other hand, if the active controller determines that the target is currently processing ("Yes" in step S110), it proceeds to step S111 and polls the target for its status using the command GETSTATUS until the target's processing operation is completed. When the active controller detects through polling that the target's processing operation has been completed, it proceeds to step S112.

[0054] In step S112, the active controller issues a command GETACCCR to the target. The command GETACCCR is a command used by the active controller to transfer the controller role to the target (secondary controller) in response to a controller role request.

[0055] The active controller initiates the controller role transfer process by issuing this command GETACCCR. In response to the command GETACCCR sent from the active controller, the target (secondary controller) changes its status to the controller role by driving SDA low and oscillating SCL. Meanwhile, the active controller that sent the command GETACCCR completes the transfer of the controller role when the device that has newly acquired the controller role drives the data signal SDA low and then drives SCL low. If the target (secondary controller) does not drive SDA low, the active controller drives SDA low to test the new active controller whose target status has changed. In response to the data signal SDA driven low, the new active controller drives the clock signal SCL low. In response to this low-state clock signal SCL, the active controller that issued the command GETACCCR activates the target role.

[0056] As shown in steps S107, S109, and S111, the active controller performs resynchronization with the target when delegating controller authority. By performing resynchronization, the device having controller authority (active controller) and the device to which the controller authority is delegated (target) have the same information. In this state, the active controller issues the command GETACCCR to switch roles. Furthermore, the processes of steps S107, S109, and S111, including the process of issuing the command GETACCCR in step S112, are interrupt processes (interrupt #2) that can be automatically or manually executed.

[0057] 6A and 6B are timing charts showing an example of a process for transferring controller authority between controllers, which is applicable to the embodiment.

[0058] 6A and 6B, the passage of time is indicated toward the right. The signals, from top to bottom, are a data signal SDA, a data signal SDA due to the new active controller role, a data signal SDA due to the active controller role of the delegation source, a clock signal SCL due to the new active controller role, a clock signal SCL due to the active controller role of the delegation source, and a clock signal SCL.

[0059] 6A and 6B, "H" and "L" indicate the high and low thresholds of each signal, respectively. Also, as shown in the upper left of each of FIGS. 6A and 6B, the solid lines indicate the active drive state, the dotted lines indicate the open-drain pull-up state, and the dashed lines indicate the high-impedance (Hi-Z) non-driven state.

[0060] 6A shows a first example of processing when transferring controller authority between controllers. The active controller from which the controller is being transferred controls the data signal SDA and the clock signal SCL after transferring the command GETACCCR issued in step S112 of the flowchart in FIG. 5, for example. The issuance of the command GETACCCR is stopped by the command STOP. Meanwhile, the new active controller sets both the clock signal SCL and the data signal SDA to Hi-Z.

[0061] At time t1, the active controller that has delegated control the clock signal SCL to a high state (step S1), which causes the clock signal SCL to be set to a high state in the new active controller (step S1').

[0062] Time t1 to command STOP setup time t SU_STOPAt time t2 after the lapse of time, the active controller from which the data signal SDA is transferred controls the data signal SDA to a high state by actual driving or by a pull-up resistor of the open drain (step S2). As a result, the data signal SDA is set to a high state in the new active controller (step S2'). At this time, if the active controller from which the data signal SDA is transferred controls the data signal SDA to a high state by actual driving, after the data signal SDA transitions to a high state, the active controller from which the data signal SDA is transferred may control the high state by a pull-up resistor of the open drain.

[0063] When the data signal SDA is controlled to a high state by a pull-up resistor, it smoothly transitions from a low state to a high state as shown by the diagonal dotted or dashed line in the figure.

[0064] The new active controller detects that the data signal SDA is in a high state (time t3), and the clock signal turnaround time t SCO At time t4 after the lapse of time, the new active controller controls the data signal SDA to a high state by enabling the pull-up resistor of the open drain (step S3a). At the same time, the new active controller controls the clock signal SCL to a high state by actually driving it (step S3b).

[0065] The active controller of the delegation source releases the clock signal SCL to Hi-Z at time t5, which is the delay time tCRHPOverlap after time t2 (step S4a). Also, at time t5, the active controller of the delegation source disables the pull-up resistor of the open drain of the data signal SDA and releases the data signal SDA to Hi-Z (step S4b).

[0066] The new active controller detects that the data signal SDA is in a high state from time t3 to time t NEWCRLock At time t6 after the time t, the data signal SDA is actually driven to the low state and the command START is generated (step S5). NEWCRLock is the time interval during which the new active controller is not actually driving the data signal SDA to a low state.

[0067] From time t6 to a predetermined time t CAS At time t7 after the lapse of time, the clock signal SCL is driven to the low state, generating the first falling edge of the clock signal SCL (step S6). After this falling edge of the clock signal SCL, the new active controller controls the clock signal SCL by driving it to the high state and the low state (C1, C2, ... in the figure). Meanwhile, the new active controller drives the data signal SDA in open-drain mode for the address arbitration phase (A6, A5, ... in the figure).

[0068] As described above, from time t3 to time t6, the controller authority is transferred from the original active controller to the new active controller (controller role handover).

[0069] If the new active controller does not send a START command within the handoff period after the controller authority is transferred, the original active controller or another target drives the data signal SDA to a low state. If the new active controller controls the clock signal SCL and no problems occur in subsequent transfers, the controller authority transfer is considered successful.

[0070] 6B shows a second example of processing when transferring controller authority between controllers. Note that in FIG. 6B, the processing before time t6 is the same as the processing in FIG. 6A, and therefore a description thereof will be omitted here.

[0071] 6B, the controller or other target after delegating the controller authority drives the data signal SDA to a low state at time t. In this example, the data signal SDA is driven to a low state at time t (step S8), and the data signal SDA is set to a low state in the active controller that delegated the controller authority (step S8'). The new active controller continues to drive the data signal SDA to a low state for a predetermined time t from time t. CAS At time t8 after the lapse of time, the clock signal SCL is driven to a low state (step S9).

[0072] The new active controller actually drives and controls the clock signal SCL to a high state and a low state after the falling edge of the clock signal SCL at time t. Meanwhile, the new active controller drives the data signal SDA in an open-drain mode for the address arbitration phase.

[0073] (2. Existing Technology) Next, existing technology related to the embodiments of the present disclosure will be described.

[0074] 7 is a schematic diagram showing the configuration of a bus system according to the existing technology. The bus system 1000 shown in FIG. 7 is similar to the bus system 1 shown in section (a) of FIG. 1, and is configured to include, for example, an I 3 A primary controller 10, a secondary controller 30, and a target 40 are connected to a bus 20, which is a C bus. The target 40 may be a secondary controller 30 assigned a target role, or may be a device whose role is fixed to the target role. Although not shown, the bus 20 includes a signal line 20a that transmits a data signal SDA and a signal line 20b that transmits a clock signal SCL.

[0075] I 3 In the C bus system, the protocol does not work unless there is at least one controller on the bus 20. 3 Since the pull-up control of I is usually the responsibility of the controller, if there is no controller on the bus 20, the level of the bus 20 becomes unstable when a high level is expected by the pull-up resistor. Therefore, if a device in the controller role leaves the bus, I 3 The C bus system cannot function, and the controller must be returned to the bus 20 to restart the system.

[0076] Also, I 3In a multiple controller system, for example, if the secondary controller 30 leaves the bus 20 while the controller authority is still transferred, the system will stop. Even if the secondary controller 30 is allowed to rejoin the bus 20, it will rejoin as a target, and this is not a recovery measure. For this reason, in the bus system 1000 according to the existing technology, the secondary controller 30 cannot be freely inserted or removed from the bus 20.

[0077] (3. Embodiments of the Present Disclosure) Next, embodiments of the present disclosure will be described.

[0078] (3-1. Overview of the embodiment) First, an overview of the embodiment of the present disclosure will be described. Fig. 8 is a schematic diagram showing an example configuration of a bus system according to the embodiment of the present disclosure.

[0079] 8, the bus system 1 according to the embodiment of the present disclosure is similar to the bus system 1000 shown in FIG. 3 A primary controller 10, a secondary controller 30, and a target 40 are connected to a bus 20, which is a C bus. The target 40 may be a secondary controller 30 assigned a target role, or may be a device whose role is fixed to the target role. Although not shown, the bus 20 includes a signal line 20a that transmits a data signal SDA and a signal line 20b that transmits a clock signal SCL.

[0080] As already explained, the primary controller 10 can delegate the controller authority to the secondary controller 30. After the controller authority is delegated, the role of the primary controller 10 is changed to the target role.

[0081] It is assumed that the secondary controller 30, whose controller authority has been delegated and whose role has been changed to the controller role, leaves the bus 20 and then rejoins the bus 20. In the bus system 1 according to the embodiment, when rejoining the bus 20, the secondary controller 30 checks whether or not a controller is present on the bus 20 by driving the data signal SDA low and detecting the clock signal SCL low. Depending on the result of this check, the secondary controller 30 rejoins the bus in an appropriate role.

[0082] Meanwhile, the primary controller 10 checks whether there is a device with controller authority on the bus 20 by performing error detection for an IBI (In-Band Interrupt). If an error such as a timeout error occurs in the IBI, the primary controller 10 determines that there is no device with controller authority on the bus 20 and autonomously acquires the controller role.

[0083] In the embodiment of the present disclosure, with the above-mentioned configuration, I 3 The secondary controller 30 can be freely inserted into and removed from the bus 20 that conforms to the C standard.

[0084] 9A to 9C are schematic diagrams illustrating a state in which a secondary controller 30 having control authority is disconnected from the bus 20 according to an embodiment.

[0085] FIG. 9A shows the state where the secondary controller 30 is removed from the bus 20. 3 As shown in section (a) of FIG. 9A, the bus system 1 3 A primary controller 10, a secondary controller 30, and a target 40 are connected to a bus 20 conforming to the C standard, and as shown in section (b), the primary controller 10 delegates control authority to the secondary controller 30.

[0086] 9A, when the secondary controller 30 to which the controller authority has been delegated is physically removed from the bus 20, there will be no devices with control authority on the bus 20. The secondary controller 30 that was removed from the bus 20 can rejoin the bus 20 by being physically connected to the bus 20 again.

[0087] FIG. 9B shows that the power supply to the secondary controller 30 is turned off. 3 9B and FIG. 9C (described later), the configuration of the bus system 1 and the transfer of controller authority from the primary controller 10 to the secondary controller 30 shown in sections (a) and (b) are the same as those in the example of FIG. 9A, and therefore will not be described here.

[0088] In this case, as shown in section (c) of FIG. 9B, when the power supply of the secondary controller 30 to which the control authority has been delegated is turned off, there will be no device on the bus 20 that has the control authority.

[0089] FIG. 9C shows the state where the secondary controller 30 enters a deep sleep state. 3 The deep sleep state is a state in which, for example, in a device including the secondary controller 30, only the detection unit that detects signals transmitted to the bus 20 is in an operating state, and the other parts are in an inoperating state, and power is supplied only to the parts that are in an operating state.

[0090] In this case, as shown in section (c) of Figure 9C, when the secondary controller 30 to which controller authority has been delegated is put into a deep sleep state, the secondary controller 30 exists on the bus 20 but does not function as a device with controller authority.

[0091] (3-2. Processing According to the Embodiment) Next, the processing according to the embodiment will be described in more detail. Fig. 10 is a flowchart showing an example of the processing according to the embodiment. Each step in the flowchart shown in Fig. 10 is executed by, for example, the microprocessor 114 of the primary controller 10 based on firmware stored in the memory 115.

[0092] In step S200, the primary controller 10 executes boot processing. In the boot processing, hardware settings are performed so that the device can be powered on and operational. In the next step S201, the primary controller 10 executes normal operations as a device in the controller role.

[0093] In the next step S202, the primary controller 10 determines whether or not to perform a role change. For example, when the primary controller 10 and the secondary controller 30 are both participating in the bus 20, and controller authority is to be transferred from a device including the primary controller 10 to a device including the secondary controller 30, the primary controller 10 may determine that a role change will occur.

[0094] If the primary controller 10 determines not to perform a role change (step S202, "No"), the process proceeds to step S210, and after the process of step S210 in which the primary controller 10 performs the operation as a controller in the controller role, the process returns to step S202.

[0095] On the other hand, if the primary controller 10 determines that a role change should be performed ("Yes" in step S202), the process proceeds to step S203. The primary controller 10 transfers controller authority to the secondary controller 30 according to the process described using the flowchart in Fig. 5, for example, and sets its own role as the target role. In step S203, the primary controller 10 performs the operation as the target.

[0096] In the next step S204, the primary controller 10 transmits the IBI to the bus 20. A specific example will be described later, but the primary controller 10 transmits the IBI a predetermined number of times at predetermined time intervals, and then transmits the IBI again in the same manner after a predetermined time has elapsed. The IBI transmission in step S204 is thus performed periodically.

[0097] In the next step S205, the primary controller 10 determines whether the response to the IBI transmission in step S204 has timed out with respect to the time set as the activity state. The time set as the activity state may be, for example, the value set in step S104 in the flowchart of FIG. 5 (1 μsec, 100 μsec, 2 msec, 50 msec, etc.).

[0098] If the primary controller 10 determines that the response to the IBI transmission in step S204 has timed out ("Yes" in step S205), the primary controller 10 returns the process to step S203. On the other hand, if the primary controller 10 determines that the response to the IBI transmission in step S204 has timed out ("Yes" in step S205), the primary controller 10 shifts the process to step S206.

[0099] In step S206, the primary controller 10 determines whether or not a device with controller authority exists on the bus 20. The primary controller 10 makes this determination by driving the data signal SDA to the low state and detecting the low state of the clock signal SCL. If an ACK is returned from the bus 20, the primary controller 10 determines that a controller exists, and if a NACK is returned from the bus 20, the primary controller 10 determines that a controller does not exist. This also applies to the determination in step S208, which will be described later.

[0100] If the primary controller 10 determines that a device with controller authority exists on the bus 20 (step S206, "Yes"), the process returns to step S203. On the other hand, if the primary controller 10 determines in step S206 that a device with controller authority does not exist on the bus 20, the process proceeds to step S207.

[0101] The processing of steps S205 and S206 will be described in more detail with reference to Fig. 11. Fig. 11 is a schematic diagram for explaining the determination processing using the data signal SDA and the clock signal SCL according to the embodiment. In Fig. 11, section (a) shows an example of the data signal SDA and the clock signal SCL when a device having controller authority is present on the bus 20.

[0102] The data signal SDA is driven from a high state to a low state. The secondary controller 30, to which the controller authority has been delegated, oscillates the clock signal SCL in response to the low state of the data signal SDA, driving it as a clock that alternates between a low state and a high state. If the low state of this clock signal SCL is detected within the time specified by the activity state from the time the data signal SDA was driven to the low state, it can be determined that a device with controller authority exists on the bus 20 (step S205, "No"). Then, the process returns to step S203, and the primary controller 10 continues the target operation.

[0103] To the secondary controller 30 to which the controller authority has been delegated, for example, a 7-bit target address of the secondary controller 30 is transferred in the data signal SDA in response to the falling edge of the clock signal SCL to the low state. By detecting this target address, the primary controller 10 can determine that a device with controller authority exists on the bus 20 even if a timeout has occurred for the activity state (step S206, "Yes").

[0104] 11, section (b) shows an example of the data signal SDA and clock signal SCL when a device with controller authority exists on the bus 20. If no device with controller authority exists on the bus 20, the clock does not oscillate and the clock signal SCL remains high. Therefore, even if the data signal SDA is driven low, no data is transferred. If the low state of the clock signal SCL is not detected within the time specified by the activity state from the time the data signal SDA is driven low (step S205, "No"), it can be determined that no device with controller authority exists on the bus 20 (step S206, "No").

[0105] Returning to the flowchart of Fig. 10, in step S207, the primary controller 10 autonomously acquires the controller role. That is, in step S207, the determination processes in steps S205 and S206 determine that no device with controller authority exists on the bus 20. Therefore, the primary controller 10 takes the initiative in acquiring the controller role and recovering the controller authority.

[0106] FIG. 12 is a functional block diagram illustrating an example of a function for executing autonomous acquisition of the controller role according to an embodiment.

[0107] In Fig. 12, role change register 121 and role monitor register 122 correspond to role change register 121 and role monitor register 122 in Fig. 4. Also, although omitted in Fig. 4, initial role register 123 is included in register 120 and stores the role in the initial state of the controller. For example, if the controller is the primary controller 10, initial role register 123 stores information indicating the controller role.

[0108] The role change control FSM (Finite State Machine) 170 may correspond to the role change control unit 130 in Fig. 4. The controller bus control FSM 171 and the target bus control FSM 172 may correspond to the controller control state machine 111 and the target control state machine 101 in Fig. 4, respectively. The role change control FSM 170, the controller bus control FSM 171, and the target bus control FSM 172 each have a function of changing the operation of the circuit by transitioning their own state based on the state of the bus 20. Furthermore, the controller / target switch (SW) 173 may be a function configured by the microprocessor 114 according to firmware, for example.

[0109] Role information of either the controller role or the target role is written to the role change register 121 from a higher-level system via an APB (ARM Peripheral Bus), for example. Alternatively, the role information to be written to the role change register 121 may be generated by a hardware sequencer. The role change control FSM 170 controls the controller / target SW 173, the controller bus control FSM 171, and the target bus control FSM 172 based on the role information written to the role change register 121.

[0110] For example, when role information indicating the controller role is written in the role change register 121, the role change control FSM 170 controls the controller bus control FSM 171 to be enabled and the target bus control FSM 172 to be disabled. At the same time, the role change control FSM 170 controls the controller / target SW 173 to select the controller bus control FSM 171.

[0111] The controller control unit 110 generates and outputs a data signal SDA in accordance with the control of the controller bus control FSM 171. The data signal SDA output from the controller control unit 110 is written to, for example, the buffer 150 in accordance with the selection of the controller / target SW 173.

[0112] On the other hand, the clock signal SCL input to the controller via the bus 20 is read from the buffer 151 in accordance with the selection of the controller / target SW 173, and input to the controller control unit 110. The controller control unit 110 detects the state (high state or low state) of the clock signal SCL in accordance with the control of the controller bus control FSM 171.

[0113] In this way, the role change control FSM 170 controls the controller bus control FSM 171, the target bus control FSM 172, and the controller / target SW 173 based on the role information written in the role change register 121, thereby enabling the controller to independently recover controller authority.

[0114] 10 , in step S208, the primary controller 10 again determines whether or not there is another device with controller authority on the bus 20. The determination process in step S208 is similar to the determination process in step S206 described above, and therefore will not be described here. By performing the determination again in step S208, it is possible to avoid a situation in which two devices with controller authority are present on the bus 20 at the same time.

[0115] If the primary controller 10 determines that there is no other device with controller authority on the bus 20 (step S208, "No"), it proceeds to step S210 and performs operations as a controller in accordance with the controller role it voluntarily acquired in step S207. After the processing of step S210, the processing returns to step S202.

[0116] On the other hand, if the primary controller 10 determines that another device with controller privileges exists on the bus 20 ("Yes" in step S208), it proceeds to step S209. In step S209, the primary controller 10 relinquishes the controller role that it voluntarily acquired in step S207. This causes the role of the primary controller 10 to return to the target role. After the processing of step S209, the processing returns to step S203.

[0117] (3-3. Specific Example of Processing According to the Embodiment) Next, the processing when the controller leaves and rejoins the bus 20 according to the embodiment will be described in more detail with reference to FIGS. 13A to 14C and the flowchart of FIG. 10 mentioned above.

[0118] 13A to 14C, the primary controller 10 has been assigned the target role after the controller authority has been delegated, and the secondary controller 30 has been assigned the controller role after the controller authority has been acquired.

[0119] 13A to 14C, for example, as shown in FIG. 9A, the bus system 1 3 A primary controller 10, a secondary controller 30, and a target 40 are connected to a bus 20 conforming to the C standard, and as shown in section (b), the primary controller 10 delegates control authority to the secondary controller 30. Furthermore, as shown in section (c) of FIG. 9A, the secondary controller 30 to which the control authority has been delegated leaves the bus 20, and then connects to the bus 20 and rejoins the bus 20.

[0120] 13A and 13B are sequence diagrams illustrating a process in which the primary controller 10 independently acquires controller authority according to an embodiment.

[0121] 13A shows a first example of a process in which the primary controller 10 independently acquires controller authority according to an embodiment. In FIG. 13A, the primary controller 10 periodically transmits an IBI (FIG. 10, step S204). In this example, the primary controller 10 transmits the IBI multiple times (five times in this example) at 10 μsec intervals, then waits a 10 msec interval, and again transmits the IBI five times at 10 μsec intervals. The primary controller 10 repeatedly transmits the IBI multiple times and waits for an interval.

[0122] Hereinafter, unless otherwise specified, an IBI transmitted multiple times consecutively at a predetermined time interval is referred to as an IBI transmission set. In the following example, an IBI transmission set is an IBI transmitted five times at 10 μsec intervals.

[0123] If an ACK is returned at least once out of five IBI transmissions made in the IBI transmission set, the primary controller 10 determines that a device with controller authority exists on the bus 20 (FIG. 10, steps S205 and S206). On the other hand, if the ACK replies to all five IBI transmissions made in the IBI transmission set time out, the primary controller 10 determines that no device with controller authority exists on the bus 20 (FIG. 10, step S206). In this case, the primary controller 10 executes the process of step S207 in FIG. 10 and autonomously acquires the controller role.

[0124] In the example of Figure 13A, an ACK is returned at least once out of the five IBI transmissions in the first and second IBI transmission sets in the figure, and the primary controller 10 determines that a device with controller authority exists on the bus 20.

[0125] During the 10 msec interval following the second IBI transmission set transmission, the secondary controller 30 leaves the bus 20 (step S300), and then rejoins the bus 20 (step S301). In this case, during the third IBI transmission set transmission, the rejoining secondary controller 30 can return an ACK in response to the IBI transmission. The secondary controller 30 rejoins the bus 20 as a controller with controller authority, just as it did before it left.

[0126] On the other hand, the primary controller 10 determines that there is another device with controller authority on the bus 20 (FIG. 10, step S206, "Yes"), and continues to operate as a target (step S203).

[0127] 13B shows a second example of a process in which the primary controller 10 independently acquires controller authority according to an embodiment. In FIG. 13B, the process up to step S300 in which the secondary controller 30 leaves the bus 20 is the same as in FIG. 13A, and therefore a description thereof will be omitted.

[0128] 13B, the secondary controller 30 rejoins the bus 20 after the third IBI transmission set (step S302). In this case, an ACK for the third IBI transmission set is not returned to the primary controller 10. The primary controller 10 determines that no controller exists on the bus 20 (FIG. 10, step S206, "No"), autonomously acquires the controller role (FIG. 10, step S207), and recovers controller privileges (step S303).

[0129] On the other hand, since a controller (primary controller 10) with controller authority exists on the bus 20, the role of the secondary controller 30 is changed from the controller role to the target role, and the secondary controller 30 rejoins the bus 20 as a target.

[0130] 14A to 14C are sequence diagrams illustrating the role selection process when the secondary controller 30 rejoins the bus 20 according to an embodiment.

[0131] FIG. 14A is a sequence diagram illustrating a first example of a role selection process when a secondary controller 30 rejoins the bus 20 according to an embodiment.

[0132] 14A, the secondary controller 30 leaves the bus 20 in step S310 during the interval between transmissions by the IBI transmission set, and rejoins the bus 20 in step S311. When the secondary controller 30 rejoins the bus 20, it drives the data signal SDA to the low state. Meanwhile, the primary controller 10, operating as the target, holds the clock signal SCL to the high state (step S312). Since the clock signal SCL remains high, the secondary controller 30 rejoins the bus 20 as the controller.

[0133] After the interval ends, the primary controller 10 performs transmission using the IBI transmission set. Because the secondary controller 30 exists as a controller on the bus 20, the primary controller 10 receives one or more ACKs in response to the transmission using the IBI transmission set. Because the ACK in response to the IBI transmission has not timed out for the time set as the activity state (FIG. 10, step S205, "No"), the primary controller 10 continues to operate as a target.

[0134] The secondary controller 30 drives the data signal SDA to a low state, as in step S312. Meanwhile, the primary controller 10, operating as the target, maintains the clock signal SCL to a high state (step S313). That is, step S313 rechecks whether or not there is a controller on the bus 20 (corresponding to the check in step S206 in FIG. 10). If this check reveals an error in the role change of the secondary controller 30, it is corrected to the correct role. In this example, because the clock signal SCL sent by the primary controller 10 remains high, the secondary controller 30 is the correct controller (step S314; corresponding to the check in step S208 in FIG. 10).

[0135] The secondary controller 30 notifies the primary controller 10 that it has the controller authority by broadcasting on the bus 20 (step S315).

[0136] FIG. 14B is a sequence diagram illustrating a second example of the role selection process when the secondary controller 30 rejoins the bus 20 according to the embodiment.

[0137] In FIG. 14B, the secondary controller 30 leaves the bus 20 in step S320 during the interval between transmissions by the IBI transmission set, and does not rejoin the bus 20 until the next transmission by the IBI transmission set.

[0138] When the secondary controller 30 rejoins the bus 20, whether the secondary controller 30 rejoins as a target or as a controller is determined by the primary controller 10 at the time of rejoining. In the example of Fig. 14B, the primary controller 10 determines that there is no controller on the bus 20 (Fig. 10, step S206, "No") because the ACK in response to the IBI transmission times out relative to the time set as the activity state (Fig. 10, step S205, "Yes"). Therefore, the primary controller 10 voluntarily acquires the controller role and regains controller authority (step S321).

[0139] In the example of FIG. 14B , after the primary controller 10 voluntarily recovers controller privileges in step S321, the secondary controller 30 rejoins the bus 20 (step S322). The secondary controller 30 that rejoins the bus 20 drives the data signal SDA low. Meanwhile, the primary controller 10 that voluntarily recovered controller privileges drives the clock signal SCL low (step S323). The secondary controller 30 checks whether a controller exists on the bus 20 based on the data signal SDA and the clock signal SCL. As a result of the check, the secondary controller 30 determines that a controller exists on the bus 20 and rejoins the bus 20 as a target.

[0140] After rejoining the bus 20, the secondary controller 30 drives the data signal SDA low, and the primary controller 10 drives the clock signal SCL low (step S324). The secondary controller 30 rechecks the presence or absence of a controller on the bus 20 based on the data signal SDA and the clock signal SCL (step S324). If this check reveals a role change error on the secondary controller 30, it is corrected to the correct role. In this example, the clock signal SCL sent by the primary controller 10 is low, so the secondary controller 30 is the correct target.

[0141] The primary controller 10 notifies the secondary controller 30 that it has controller authority by broadcasting on the bus 20 using the dynamic address (DA) and static address (SA) (step S325).

[0142] FIG. 14C is a sequence diagram illustrating a third example of a role selection process when the secondary controller 30 rejoins the bus 20 according to an embodiment.

[0143] 14C, the secondary controller 30 leaves the bus 20 in step S320 during the interval between transmissions by the IBI transmission set (step S330), and rejoins the bus 20 during the next transmission by the IBI transmission set (step S331). The secondary controller 30 that has rejoined the bus 20 drives the data signal SDA low, and the primary controller 10 maintains the clock signal SCL high (step S332). Because the clock signal SCL remains high, the secondary controller 30 rejoins the bus 20 as the controller.

[0144] On the other hand, the primary controller 10 determines that there is no controller on the bus 20 (FIG. 10, step S206, "No") because the ACK for the IBI transmission has timed out relative to the time set as the activity state (FIG. 10, step S205, "Yes"), so the primary controller 10 voluntarily acquires the controller role (FIG. 10, step S207) and regains controller authority (step S333).

[0145] That is, in the example of FIG. 14C, when the primary controller 10 independently recovers the controller authority in step S333, there will be two controllers on the bus 20.

[0146] Furthermore, the primary controller 10, which has voluntarily regained the controller authority, drives the clock signal SCL to the low state (step S334). The secondary controller 30 checks the presence or absence of a controller on the bus 20 based on the data signal SDA and the clock signal SCL. As a result of the check, the secondary controller 30 determines that a controller is present on the bus 20, drives the clock signal SCL to the low state, and changes the role to the target role (step S335).

[0147] The primary controller 10 notifies the secondary controller 30 that it has controller authority by broadcasting on the bus 20 using the dynamic address (DA) and static address (SA) (step S336).

[0148] In this way, the bus system 1 according to the embodiment determines the roles of the primary controller 10 and the secondary controller 30 depending on the timing at which the secondary controller 30, which has left the bus 20, rejoins the bus 20. Therefore, the bus system 1 according to the embodiment allows the secondary controller 30 to be freely inserted and removed from the bus 20.

[0149] (Example of a Case Where the Primary Controller is Inserted into or Removed from the Bus 20) In the above description, the secondary controller 30 is inserted into or removed from the bus 20, but this is not limited to this example. In other words, the above-described processing can also be applied to a case where the primary controller 10 is inserted into or removed from the bus 20.

[0150] For example, when the primary controller 10 has controller authority, a specific secondary controller 30 connected to the bus 20 may detect that the primary controller 10 has left the bus 20. After detecting that the primary controller 10 has left the bus 20, the specific secondary controller 30 may autonomously acquire controller authority. Furthermore, when the specific secondary controller 30 is functioning as a target, it may perform a weak pull-up to hold the bus 20 in a high state when the primary controller 10 has left the bus 20. Furthermore, the specific secondary controller 30 may detect a target reset pattern to transition the target (e.g., the primary controller 10) to a deep sleep state or to wake up from the deep sleep state.

[0151] (3-4. Control when the controller leaves the bus according to the embodiment) Next, control when the controller leaves the bus 20 according to the embodiment will be described.

[0152] (Bus pull-up control) I 3 In a bus 20 conforming to IEEE 802.11b / g, the primary controller 10 must maintain the bus 20 in a high state when the controller is removed from the bus 20, regardless of whether the primary controller 10 is in the controller role or the target role. In this embodiment, when the primary controller 10 maintains the bus 20 in a high state, it can select either a normal high state or a high state that is weaker than the normal high state.

[0153] FIG. 15 is a schematic diagram illustrating an example configuration for holding the bus 20 in either a normal high state or a weak high state according to an embodiment.

[0154] 15 , one primary controller 10, one secondary controller 30, and multiple targets 40 are connected to a bus 20. In the bus 20, a signal line 20a that transmits a data signal SDA is connected to a power supply line (not shown) via a pull-up resistor 200. In addition, in the bus 20, a signal line 20b that transmits a clock signal SCL is connected to the power supply line (not shown) via pull-up resistors 201 and 202.

[0155] The pull-up resistors 200, 201, and 202 are controlled to be turned on or off by switches 211, 212, and 213, respectively. The pull-up resistors 200, 201, and 202 are enabled when turned on, and disabled (cut off) when turned off. The switches 211 and 212 are directly controlled by the primary controller 10. On the other hand, the switch 213 is controlled by an OR circuit 210 based on the logical sum of the control of the primary controller 10 and the control of the secondary controller 30.

[0156] Of pull-up resistors 201 and 202 connected to signal line 20a for data signal SDA, pull-up resistor 201 has a higher resistance than pull-up resistor 202. In the example shown in the figure, pull-up resistor 201 has a resistance of 100 kΩ, while pull-up resistor 202 has a resistance of 1 kΩ. When pull-up resistor 201 is OFF and pull-up resistor 202 is ON, signal line 20a is pulled up normally; when pull-up resistor 201 is ON and pull-up resistor 202 is OFF, signal line 20a is pulled up weaker than normal via the larger resistance value of pull-up resistor 201.

[0157] The pull-up by the pull-up resistor 202 may be performed by selecting either open drain or push-pull. For example, in the case of open drain, the pull-up resistor 202 may be turned on, and in the case of push-pull, the pull-up resistor 202 may be turned off.

[0158] On the other hand, the pull-up resistor 200 connected to the signal line 20b of the clock signal SCL has a high resistance (100 kΩ in the illustrated example), and the signal line 20b is pulled up weakly compared to a normal pull-up.

[0159] Normally (for example, in the controller role), the primary controller 10 pulls up the signal line 20a of the data signal SDA using the pull-up resistor 202. In the target role, the primary controller 10 turns off the pull-up resistor 202 and turns on the pull-up resistor 201 to weakly pull up the data signal SDA. The primary controller 10 also weakly pulls up the signal line 20b of the clock signal SCL.

[0160] The pull-up resistors 200 , 201 , and 202 may be implemented as always ON without any control, or may be implemented under the control of the primary controller 10 .

[0161] (Variations of Bus Detachment) In the above-mentioned Figures 9A to 9C, three examples have been described as examples of the secondary controller 30 detachment from the bus 20: an example in which the secondary controller 30 detachment from the bus 20 is caused by removing the secondary controller 30 from the bus 20 (Figure 9A); an example in which the secondary controller 30 detachment from the bus 20 is caused by turning off the power of the secondary controller 30 connected to the bus 20 (Figure 9B); and an example in which the secondary controller 30 connected to the bus 20 is detachment from the bus 20 by putting the secondary controller 30 connected to the bus 20 into a deep sleep state (Figure 9C).

[0162] Of these, the power-off example in Fig. 9B and the deep sleep example in Fig. 9C each relate to power control of the secondary controller 30. Here, these power-off examples and deep sleep examples will be described in more detail.

[0163] Fig. 16A is a schematic diagram illustrating deep sleep according to an embodiment. In Fig. 16A, the left side schematically shows the secondary controller 30 in a deep sleep state. The deep sleep state of the secondary controller 30 is, for example, a state in which power from the power supply circuit 60 is supplied only to the detection unit 180 that detects signals from the bus 20, and not to other parts. The secondary controller 30 in the deep sleep state is present on the bus 20.

[0164] When the secondary controller 30 is a device in the controller role, the detection unit 180 in the secondary controller 30 in the deep sleep state detects, for example, a hot-join (HJ) request, a controller-roll request (CRR), or an IBI sent from the target 40 via the bus 20. When the detection unit 180 detects any of these, it controls the power supply circuit 60 to supply power to parts of the secondary controller 30 other than the detection unit 180, as shown on the right side of FIG. 16A , thereby waking up the secondary controller 30 and making it active. The secondary controller 30 that has been woken up from deep sleep responds as a device in the controller role.

[0165] 16B is a schematic diagram illustrating a power-off state according to an embodiment. When the secondary controller 30 is completely powered off, the power supply circuit 60 also stops operating, and power is not supplied to the various components, including the detection unit 180. A completely powered-off secondary controller 30 is treated the same as a removable controller (not present on the bus 20).

[0166] In Figures 16A and 16B, the control during deep sleep and complete power off is explained using the secondary controller 30 as an example, but this is not limited to this example, and similar control can also be applied to the primary controller 10.

[0167] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0168] The present technology can also be configured as follows. (1) A bus system including a first controller having controller authority in an initial state, and one or more second controllers connected to the first controller via a bus, wherein the first controller, when delegating the controller authority to a specific second controller among the one or more second controllers, transmits an interrupt signal to the bus and determines whether the second controller having the controller authority is present on the bus based on a response to the interrupt signal. (2) The bus system according to (1), wherein the first controller independently acquires the controller authority when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus. (3) The bus system according to (2), wherein the first controller independently acquires the controller authority using a value stored in a register of the first controller. (4) The bus system according to (2) or (3), wherein the first controller drives the bus to a low state when the specific second controller to which the controller authority has been delegated is present on the bus, and drives the bus to a high state when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus. (5) The bus system according to (4), wherein the first controller drives the bus to the high state, which is weaker than when the second controller with the controller authority is not present on the bus, when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus. (6) The bus system according to any one of (2) to (4), wherein the first controller transmits the interrupt signal to the bus after autonomously acquiring the controller authority, and re-determines whether the specific second controller to which the controller authority has been delegated is present on the bus in response to the interrupt signal.(7) The bus system according to (6), wherein the first controller relinquishes the controller authority that it has independently acquired when the re-determination determines that the second controller with the controller authority is present on the bus. (8) The bus system according to any one of (1) to (7), wherein the first controller transmits the interrupt signal a predetermined number of times within a predetermined period, and determines that the specific second controller to which the controller authority has been delegated is present on the bus when there is a response to at least one of the predetermined number of interrupt signals. (9) The bus system according to any one of (1) to (8), wherein the first controller wakes up the specific second controller from the deep sleep state using at least one of hot join, the interrupt signal, and a controller role request when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus because it is in a deep sleep state. (10) The bus is an I / O bus. 3The bus system according to any one of (1) to (9), which is a bus conforming to the C (Improved Inter Integrated Circuit) (registered trademark) standard. (11) A bus control device comprising: a control unit that controls a role of its own device to either a controller or a target; and a determination unit that determines whether or not another bus control device with controller authority exists on the bus based on a response to an interrupt signal transmitted to the bus, wherein the control unit transmits the interrupt signal and performs the determination by the determination unit when the control unit transfers the controller authority that it has in an initial state to the other bus control device connected via the bus. (12) The bus control device according to (11), wherein the control unit independently acquires the controller authority when the determination determines that the other bus control device with controller authority does not exist on the bus. (13) The bus control device according to (12), further comprising a register, wherein the control unit independently acquires the controller authority using a value stored in the register. (14) The bus control device according to (12) or (13), wherein the control unit drives the bus to a low state when the other bus control device with the controller authority is present on the bus, and drives the bus to a high state when the determination determines that the bus control device with the controller authority is not present on the bus. (15) The bus control device according to (14), wherein the control unit drives the bus to the high state, which is weaker than when the other bus control device has the controller authority and is not present on the bus, when the determination determines that the other bus control device with the controller authority is not present on the bus. (16) The bus control device according to any one of (12) to (15), wherein the control unit transmits the interrupt signal to the bus after autonomously acquiring the controller authority, and re-determines whether the other bus control device with the controller authority is present on the bus in response to the interrupt signal.(17) The bus control device according to (16), wherein the control unit abandons the independently acquired controller authority when the re-determination determines that the other bus control device with the controller authority exists on the bus. (18) The bus control device according to any one of (11) to (17), wherein the control unit transmits the interrupt signal a predetermined number of times within a predetermined period, and determines that the other bus control device with the controller authority exists on the bus when there is a response to at least one of the predetermined number of interrupt signals. (19) The bus is an I. 31. The bus control device according to any one of (11) to (18), wherein the bus is a bus conforming to the C (Improved Inter Integrated Circuit) (registered trademark) standard. (20) The bus control device according to any one of (11) to (19), wherein the control unit, when it is determined that the other bus control device having the controller authority is not present on the bus because it is in a deep sleep state, wakes the other bus control device from the deep sleep state using at least one of hot join, the interrupt signal, and a controller role request. (21) A bus control device comprising: a control unit that controls the role of its own device to either a controller or a target; and a determination unit that determines whether the other bus control device having controller authority is present on the bus based on an interrupt signal transmitted from the other bus control device connected via the bus, wherein the determination unit determines that the other bus control device has left the bus when the controller authority has been delegated from the other bus control device and the interrupt signal has not been detected within a predetermined time. (22) The bus control device according to (21), wherein the other bus control device has the controller authority in an initial state. (23) The bus control device according to (21), wherein the control unit independently acquires the controller authority when the determination determines that the other bus control device does not exist on the bus. (24) The bus control device according to any one of (21) to (23), wherein the control unit controls the role of its own device to the target and drives the bus to a high state when the determination determines that the other bus control device does not exist on the bus. (25) The bus control device according to (24), wherein the control unit drives the bus to a high state that is weaker than when the control unit has the controller authority and the other bus control device does not exist on the bus.(26) The bus control device according to any one of (21) to (25), wherein the control unit transitions the other bus control device determined to have left the bus to a deep sleep state, and recovers the other bus control device in the deep sleep state from the deep sleep state. (27) A bus control method comprising: a transmitting step of transmitting an interrupt signal to the bus when a first controller having controller authority in an initial state delegates the controller authority to a specific second controller among one or more second controllers connected to the first controller via a bus; and a determining step of determining whether the second controller having controller authority is present on the bus based on a response to the interrupt signal.

[0169] 1,1000 bus system 10 primary controller 20 bus 20a, 20b signal line 30, 301, 302, 303 secondary controller 40 target 60 power supply circuit 100 target control unit 110 controller control unit 114 microprocessor 115 memory 120 register 121 role change register 122 role monitor register 123 initial role register 130 role change control unit 170 role change control FSM 171 controller bus control FSM 172 target bus control FSM 173 controller / target SW 180 detection unit 200, 201, 202 pull-up resistor 211, 212, 213 switch

Claims

1. A bus system comprising: a first controller having controller authority in an initial state; and one or more second controllers connected to the first controller via a bus, wherein the first controller, when delegating the controller authority to a specific second controller among the one or more second controllers, sends an interrupt signal to the bus, and determines whether or not the second controller having the controller authority is present on the bus based on a response to the interrupt signal.

2. The bus system according to claim 1, wherein the first controller independently acquires the controller authority when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus.

3. The bus system according to claim 2, wherein the first controller autonomously acquires the controller authority using a value stored in a register of the first controller.

4. The bus system of claim 2, wherein the first controller drives the bus to a low state when the specific second controller to which the controller authority has been delegated is present on the bus, and drives the bus to a high state when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus.

5. The bus system of claim 4, wherein, when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus, the first controller drives the bus to the high state that is weaker than when the second controller with the controller authority is not present on the bus.

6. The bus system according to claim 2, wherein after said first controller independently acquires said controller authority, said first controller transmits said interrupt signal to said bus, and in response to said interrupt signal, re-determines whether or not said specific second controller to which said controller authority has been delegated is present on said bus.

7. The bus system according to claim 6, wherein the first controller abandons the controller authority that it has independently acquired when the re-evaluation determines that the second controller having the controller authority is present on the bus.

8. The bus system according to claim 1, wherein the first controller transmits the interrupt signal a predetermined number of times within a predetermined period, and when there is a response to at least one of the predetermined number of interrupt signals, determines that the specific second controller to which the controller authority has been delegated is present on the bus.

9. The bus system of claim 1, wherein, when the determination determines that the specific second controller to which the controller authority has been delegated is not present on the bus because it is in a deep sleep state, the first controller wakes up the specific second controller from the deep sleep state using at least one of a hot join, the interrupt signal, and a controller role request.

10. The bus is 3 2. The bus system according to claim 1, wherein the bus system is a bus conforming to the Improved Inter Integrated Circuit (C) (registered trademark) standard.

11. A bus control device comprising: a control unit that controls the role of the device itself to either a controller or a target; and a determination unit that determines whether or not there is another bus control device with controller authority on the bus based on a response to an interrupt signal sent to the bus, wherein the control unit sends the interrupt signal and the determination is made by the determination unit when the control unit delegates the controller authority that it has in the initial state to the other bus control device connected via the bus.

12. The bus control device according to claim 11, wherein the control unit independently acquires the controller authority when the determination determines that no other bus control device having the controller authority exists on the bus.

13. The bus control device according to claim 12, further comprising a register, wherein the control unit performs the autonomous acquisition of the controller authority using a value stored in the register.

14. The bus control device according to claim 12, wherein the control unit drives the bus to a low state when the other bus control device having the controller authority is present on the bus, and drives the bus to a high state when the determination determines that the bus control device having the controller authority is not present on the bus.

15. The bus control device according to claim 14, wherein, when the determination determines that the other bus control device having the controller authority does not exist on the bus, the control unit drives the bus to the high state that is weaker than when the other bus control device has the controller authority and does not exist on the bus.

16. The bus control device according to claim 12, wherein the control unit, after independently acquiring the controller authority, transmits the interrupt signal to the bus, and, depending on a response to the interrupt signal, re-determines whether or not another bus control device having the controller authority exists on the bus.

17. The bus control device according to claim 16, wherein the control unit abandons the controller authority that it has independently acquired when the re-determination determines that another bus control device having the controller authority exists on the bus.

18. The bus control device according to claim 11, wherein the control unit transmits the interrupt signal a predetermined number of times within a predetermined period, and when there is a response to at least one of the predetermined number of interrupt signals, determines that the other bus control device with the controller authority is present on the bus.

19. The bus is 3 12. The bus control device according to claim 11, wherein the bus conforms to the C (Improved Inter Integrated Circuit) (registered trademark) standard.

20. A bus control method comprising: a transmission step of transmitting an interrupt signal to the bus when a first controller having controller authority in an initial state delegates the controller authority to a specific second controller among one or more second controllers connected to the first controller via a bus; and a determination step of determining whether or not the second controller having the controller authority is present on the bus based on a response to the interrupt signal.

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