Method for manufacturing back gate wiring

Abstract

The present invention proposes a method for forming back gate wiring, wherein a recess process is used based on an Xtacking technique in which a semiconductor structure is inverted and used, thereby reducing the process complexity and cost and thus simplifying the process. The semiconductor structure comprises: gate electrodes or sacrificial layers formed to extend in the horizontal direction and stacked to be spaced apart from each other in the vertical direction, and vertical channel structures formed to extend in the vertical direction through the gate electrodes or the sacrificial layers.

Description

Back gate wiring manufacturing method

[0001] The following examples describe a method for manufacturing a back gate wiring in a three-dimensional flash memory having a structure including a back gate.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is required to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a memory cell string has been proposed.

[0004] In relation to such 3D flash memory, ensuring cell characteristics and reliability, which deteriorate with vertical scaling, are emerging as key issues. To address this, a structure that includes a back gate within the internal space of the vertical channel pattern has been proposed.

[0005] However, there is currently no clear proposal regarding the process for manufacturing the back gate wiring that connects the back gates.

[0006] Accordingly, the process for manufacturing the back gate wiring is described through the examples below.

[0007]

[0008] One embodiment proposes a method for forming a back gate wiring based on an Xtacking technique that uses a semiconductor structure upside down to simplify the process for manufacturing a three-dimensional memory having a structure including a back gate.

[0009] At this time, one embodiment proposes a method of forming a common source together with a back gate wiring.

[0010] In particular, one embodiment proposes a method for preventing short circuits between a common source and a back gate wiring.

[0011] Additionally, one embodiment proposes a method of implementing the back gate wiring in various forms.

[0012] Other embodiments propose a back gate wiring manufacturing method using a recess process based on an Xtacking technique that uses a semiconductor structure upside down to achieve a technical goal that can be applied regardless of scaling for improved integration while reducing process complexity and cost and promoting process simplification.

[0013] At this time, one embodiment proposes a back gate wiring manufacturing method that prevents vertical channel patterns from being recessed together in the recess process.

[0014] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0015] According to one embodiment, a method for manufacturing a back gate wiring may include preparing a semiconductor structure including gate electrodes that are formed to extend in a horizontal direction and are stacked while being spaced apart from each other in a vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the gate electrodes, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed to contact an outer wall of the vertical channel pattern, and a back gate that is formed to extend in the vertical direction in an inner space of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the gate electrodes; sequentially forming a common source and a separation insulating layer on one surface of the semiconductor structure; etching a region corresponding to a back gate of each of the vertical channel structures in the separation insulating layer and the common source to form holes; forming a separation insulating film on an inner wall of each of the holes; and forming a back gate wiring inside a space formed by the separation insulating film in each of the holes and on one surface of the separation insulating layer.

[0016] According to another embodiment, a method for manufacturing a back gate wiring includes: preparing a semiconductor structure including sacrificial layers that are formed to extend in a horizontal direction and are stacked while being spaced apart from each other in a vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the sacrificial layers, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed in contact with an outer wall of the vertical channel pattern, and a back gate formed to extend in the vertical direction in an inner space of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to gate electrodes to be formed in spaces from which the sacrificial layers are removed; sequentially forming a common source and a separation insulating layer on one surface of the semiconductor structure; etching a region corresponding to the back gate of each of the vertical channel structures in the separation insulating layer and the common source to form holes; forming a separation insulating film on an inner wall of each of the holes; forming a back gate wiring inside a space formed by the separation insulating film in each of the holes and on one surface of the separation insulating layer; And it may include a step of removing the sacrificial layers and forming the gate electrodes in the spaces from which the sacrificial layers have been removed.

[0017] According to one aspect, the step of forming the back gate wiring may include: forming a vertical portion of the back gate wiring inside a space formed by the separation insulating film in each of the holes; and forming a horizontal portion of the back gate wiring on one surface of the separation insulating layer.

[0018] According to another aspect, the step of forming the horizontal portion of the back gate wiring may include one of the steps of forming the horizontal portion of the back gate wiring in a plate shape; or the step of forming the horizontal portion of the back gate wiring in a line shape.

[0019] According to one embodiment, a method for manufacturing a back gate wiring may include preparing a semiconductor structure including gate electrodes that are formed to extend in a horizontal direction and are stacked while being spaced apart from each other in a vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the gate electrodes, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed to contact an outer sidewall of the vertical channel pattern, and a back gate that is formed to extend in the vertical direction in an inner space of the vertical channel pattern; recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one surface of the semiconductor structure; sequentially forming a common source and a separation insulating layer so as to contact the exposed side surface of each of the vertical channel structures; and forming a back gate wiring on the vertical channel structures so as to contact the back gate of each of the vertical channel structures.

[0020] According to another embodiment, a method for manufacturing a back gate wiring may include preparing a semiconductor structure including sacrificial layers that are formed to extend in a horizontal direction and are stacked while being spaced apart from each other in a vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the sacrificial layers, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed to contact an outer sidewall of the vertical channel pattern, and a back gate that extends in the vertical direction in an inner space of the vertical channel pattern; recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one surface of the semiconductor structure; sequentially forming a common source and a separation insulating layer so as to contact the exposed side surface of each of the vertical channel structures; forming a back gate wiring on the vertical channel structures so as to contact the back gate of each of the vertical channel structures; and removing the sacrificial layers to form gate electrodes in spaces where the sacrificial layers are removed.

[0021] According to one aspect, the preparing step may be characterized as a step of preparing the semiconductor structure in which a capping film is formed in an area corresponding to the back gate among the exposed ends of each of the vertical channel structures.

[0022] According to another aspect, the capping film may be formed of a material or composition different from that of the common source, in order to prevent an area corresponding to the back gate among the exposed ends of each of the vertical channel structures from being recessed together when a portion of the common source is recessed in the step of sequentially forming the common source and the separation insulating layer.

[0023] One embodiment proposes a method for forming a back gate wiring based on an Xtacking technique that uses a semiconductor structure upside down, thereby achieving a technical effect of promoting process simplification in manufacturing a three-dimensional memory having a structure including a back gate.

[0024] At this time, one embodiment may propose a method of forming a common source together with the back gate wiring.

[0025] In particular, one embodiment may propose a method for preventing short circuits between a common source and a back gate wiring.

[0026] Additionally, one embodiment may propose a method of implementing the back gate wiring in various forms.

[0027] One embodiment proposes a back gate wiring manufacturing method using a recess process based on an Xtacking technique that uses a semiconductor structure upside down, thereby achieving a technological effect that can be applied regardless of scaling for improving integration while reducing process complexity and cost and thus simplifying the process.

[0028] At this time, one embodiment can propose a back gate wiring manufacturing method that prevents vertical channel patterns from being recessed together in the recess process.

[0029] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0030]

[0031] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0032] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0033] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0034] FIG. 4 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to one embodiment.

[0035] FIGS. 5A to 5G are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the back gate wiring manufacturing method illustrated in FIG. 4.

[0036] FIGS. 6A to 6G are plan views illustrating the structure of a three-dimensional flash memory in which each of the horizontal portion of the back gate wiring and the common source is formed in a plate shape to explain the method for manufacturing the back gate wiring illustrated in FIG. 4.

[0037] FIGS. 7 and 8 are plan views illustrating the structure of a three-dimensional flash memory in which a common source is formed in a line shape to explain the back gate wiring manufacturing method illustrated in FIG. 4.

[0038] FIGS. 9 and 10 are plan views illustrating the structure of a three-dimensional flash memory in which the horizontal portion of the back gate wiring is formed in a line shape to explain the back gate wiring manufacturing method illustrated in FIG. 4.

[0039] FIG. 11 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to another embodiment.

[0040] FIG. 12 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0041] Fig. 13 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of Fig. 12.

[0042] FIG. 14 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to one embodiment.

[0043] FIGS. 15a to 15g are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the back gate wiring manufacturing method illustrated in FIG. 14.

[0044] FIGS. 16A to 16E are cross-sectional views illustrating the structure of a three-dimensional flash memory when a capping film is included to explain the back gate wiring manufacturing method illustrated in FIG. 14.

[0045] FIGS. 17a to 17g are plan views illustrating the structure of a three-dimensional flash memory in which each of the back gate wiring and the common source is formed in a plate shape to explain the method for manufacturing the back gate wiring illustrated in FIG. 14.

[0046] FIGS. 18 and 19 are plan views illustrating the structure of a three-dimensional flash memory in which a common source is formed in a line shape to explain the back gate wiring manufacturing method illustrated in FIG. 14.

[0047] FIGS. 20 and 21 are plan views illustrating the structure of a three-dimensional flash memory in which the back gate wiring is formed in a line shape to explain the back gate wiring manufacturing method illustrated in FIG. 14.

[0048] FIG. 22 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to another embodiment.

[0049] FIG. 23 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0051] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0052] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0053] Hereinafter, with reference to the drawings, a three-dimensional flash memory and a manufacturing method thereof that improve channel current characteristics by increasing the area through which channel current flows while simultaneously increasing the channel current value itself are described in detail.

[0054]

[0055] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0056] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a common source (CS), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source (CS) and the bit lines (BL0, BL1, BL2).

[0057] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0058] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be connected in common to a common source (CS) provided between the bit lines (BL0, BL1, BL2) and a common source (CS).

[0059] At this time, the common source (CS) may be implemented in a plate shape so as to be shared by the cell strings (CSTR) constituting the array, but is not limited thereto and may be implemented in a line shape so as to be shared only by the cell strings (CSTR) included in the same row or column. When the common source (CS) is implemented in a line shape, a plurality of common sources (CS) may be provided, and the plurality of common sources (CS) may be two-dimensionally arranged while extending in the first direction (D1) and spaced apart from each other along the second direction (D2). The same electrical voltage may be applied to the plurality of common sources (CS), but is not limited thereto and each of the plurality of common sources (CS) may be electrically independently controlled so as to be applied with different voltages.

[0060] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source (CS), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) disposed between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

[0061] For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0062] A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from a common source (CS). That is, the memory cell transistors (MCT) may be connected in series between a first string select transistor (SST1) and a ground select transistor (GST) along a third direction (D3). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source (CS). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT). The dummy cell transistors (DMC) may be omitted depending on the implementation.

[0063] According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECT) may be provided. A common source (CS) can be commonly connected to the sources of the erase control transistors (ECT).

[0064] Here, the dummy word line (DWL) can also be omitted, as can the dummy cell transistors (DMC).

[0065] The gate electrodes of the memory cell transistors (MCT) provided at substantially the same distance from the common source (CS) may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source (CS), the gate electrodes provided in different rows or columns may be independently controlled.

[0066] The ground selection lines (GSL0, GSL1, GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) may extend along the first direction (D1), be spaced apart from each other in the second direction (D2) and be arranged two-dimensionally. However, the present invention is not limited thereto and each of the ground selection lines (GSL0, GSL1, GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) may be implemented in a plate form and thus may be shared by the cell strings (CSTR) constituting the array.

[0067] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from a common source (CS) can be electrically isolated from each other.

[0068] Additionally, erase control transistors (ECT) of different cell strings (CSTR) may be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate gate-induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to bit lines (BL0, BL1, BL2) and / or a common source (CS) during an erase operation of the memory cell array, and gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0069] In addition, although the drawing omits the back gates (BG) that are respectively connected to the cell strings (CSTR) in the array of the three-dimensional flash memory, each of the back gates (BG) may be electrically connected to the memory cell transistors (MCT) within each of the strings (CSTR). That is, the back gates (BG) may be provided corresponding to the cell strings (CSTR). A detailed description thereof will be provided below.

[0070]

[0071] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment, and FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, which corresponds to a cross-section taken along line A-A' of FIG. 2.

[0072] Referring to the drawings, the laminated structure (ST) can be formed to extend in the first direction (D1) and the second direction (D2). In the drawings, the laminated structure (ST) is illustrated as one, but is not limited thereto, and a plurality of laminated structures (ST) may be provided and arranged two-dimensionally while being spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0073] The stacked structure (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)). The stacked structure (ST) may have a substantially flat upper surface. Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0074] Although omitted in the drawing, the stacked structure (ST) may exist in a state of being arranged on the substrate (SUB) prior to the formation of the common source (CS) and the back gate wiring (BGW). That is, the stacked structure (ST) may be manufactured by alternately stacking gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) may be removed during the formation of the common source (CS) and the back gate wiring (BGW), so that the substrate (SUB) may not be included as a result.

[0075] The substrate (SUB) used in the manufacturing process of the stacked structure (ST) may be a semiconductor substrate such as a substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0076] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3) and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked in a direction from bottom to top.

[0077] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0078] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0079] Although not shown, the end of the stacked structure (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structure (ST) may have a length in the first direction (D1) that decreases from the bottom toward the top. The third gate electrode (EL3) may have the shortest length in the first direction (D1) and may have the longest distance from the bottom along the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and may have the shortest distance from the bottom along the third direction (D3). By means of the step structure, the thickness of the stacked structure (ST) can decrease as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0080] However, without being limited or restricted thereto, the end of the laminated structure (ST) may have a step structure along the second direction (D2).

[0081] Each of the interlayer insulating layers (ILDs) may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than the other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating layers (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0082] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) may be stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0083] A plurality of channel holes (CH) penetrating a portion of a stacked structure (ST) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may extend in a third direction (D3) while being connected to a common source (CS). The vertical channel structures (VS) may be connected to the common source (CS) by having a lower surface of each of a portion of the vertical channel structures (VS) come into contact with an upper surface of the common source (CS).

[0084] The rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as illustrated in FIG. 2, 15 vertical channel structures (VS) may penetrate the stacked structure (ST) forming 6 columns and 5 rows. However, the number of vertical channel structures (VS) forming the array is not limited thereto.

[0085] As vertical channel structures (VS) are formed in a plate shape, the array is formed in a horizontal plane of multiple rows and columns of gate electrodes (EL1, EL2, EL3), so that the three-dimensional flash memory can have a structure in which the integration of memory cell strings is improved.

[0086] In particular, memory directivity can be improved as the common source (CS) and its wiring are located at the bottom of the stacked structure (ST), unlike the conventional structure in which the CS and its wiring are included inside the stacked structure (ST).

[0087] At this time, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on a horizontal plane and to be misaligned with each other. For example, the vertical channel structures (VS) included in a first column may be arranged in the first row, the third row, and the third row, and the vertical channel structures (VS) included in a second column may be arranged in the second row and the fourth row, such that the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string can be further improved compared to the case where the vertical channel structures (VS) included in a pair of adjacent columns are arranged side by side in the same row on a horizontal plane.

[0088] Each of the vertical channel structures (VS) may be formed to extend from the bottom to the top in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0089] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a back gate (BG), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with an open bottom, and the back gate (BG) may have a shape that fills the inner space of the vertical channel pattern (VCP).

[0090] The data storage pattern (DSP) can cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the vertical channel pattern (VCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. Accordingly, the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) can form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2) together with the regions corresponding to the second gate electrodes (EL2) of the vertical channel pattern (VCP). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0091] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by a voltage applied through the second gate electrodes (EL2), or by maintaining the state of electrons (e.g., the polarization state of charges). For example, an ONO (tunnel oxide-nitride-blocking oxide) layer or a ferroelectric layer can be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent a binary data value or a multi-valued data value by a change in the trapped charge or hole, or can represent a binary data value or a multi-valued data value by a change in the state of charges.

[0092] Although the above data storage pattern (DSP) is described as being vertically connected and extended, it is not limited to this and may be segmented into multiple pieces and formed only in the portion corresponding to the second gate electrodes (EL), thereby forming memory cells together with the regions corresponding to the second gate electrodes (EL2) among the vertical channel pattern (VCP).

[0093] A vertical channel pattern (VCP) is a component that supplies electrons or holes to transfer charges to a data storage pattern (DSP). The vertical channel pattern (VCP) may be formed to extend in a vertical direction (e.g., a third direction (D3)) while covering an inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage. More specifically, the vertical channel pattern (VCP) may perform a memory operation in response to a voltage applied by a bit line (BL), a common source (CS), a back gate (BG), and gate electrodes (EL1, EL2, EL3). For this purpose, the vertical channel pattern (VCP) may be formed of, for example, single-crystalline silicon or polycrystalline silicon.

[0094] The upper surface of the vertical channel pattern (VCP) may be positioned at a higher level than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the vertical channel pattern (VCP) may be positioned between the upper surface and the lower surface of the third gate electrode (EL3). The lower surface of the vertical channel pattern (VCP) may be coplanar with the upper surface of the common source (CS) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD).

[0095] The back gate (BG) may be formed to be in contact with the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP). For example, the back gate (BG) may be formed to extend vertically (e.g., in the third direction (D3)) within the inner space of the vertical channel pattern (VCP).

[0096] Here, the back gate (BG) can be formed to apply a voltage for a memory operation to the vertical channel pattern (VCP). To this end, the back gate (BG) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). In addition to the described metal materials, the back gate (BG) can include at least one of all metal materials that can be formed by ALD.

[0097] In addition, a back gate insulating film (BG-INS) may be formed and extended in a vertical direction (e.g., a third direction (D3)) between the back gate (BG) and the vertical channel pattern (VCP). Accordingly, the back gate insulating film (BG-INS) may prevent the back gate (BG) from directly contacting the vertical channel pattern (VCP). The back gate insulating film (BG-INS), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide. However, the back gate insulating film (BG-INS) may be omitted depending on the implementation example.

[0098] Referring back to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0099] The back gates (BG) included in each of the vertical channel structures (VS) may be electrically connected to each other by a back gate wiring (BGW). Accordingly, the back gate wiring (BGW), like the back gate (BG), may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0100] Although the drawing illustrates that the back gate wiring (BGW) is implemented in the form of a plate to connect the back gates (BG) of each of the vertical channel structures (VS) constituting the array, it may be implemented in the form of a line, without being limited thereto. In this case, the back gate wiring (BGW) may be implemented to connect the back gates (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). Furthermore, the back gate wiring (BGW) may be shared not only by the vertical channel structures (VS) included in the same row or column, but also by the vertical channel structures (VS) included in adjacent rows or columns, thereby connecting the back gates (BG) included in each of the vertical channel structures (VS) included in the same row or column and the vertical channel structures (VS) included in adjacent rows or columns to each other. A detailed description thereof will be provided below.

[0101] At this time, the back gate wiring (BGW) may include a horizontal portion (BGW-H) and a vertical portion (BGW-V). The horizontal portion (BGW-H) of the back gate wiring (BGW) is a portion that is positioned below the common source (CS) and extends in a horizontal direction (e.g., the first direction (D1) and the second direction (D2)), and the vertical portion (BGW-V) of the back gate wiring (BGW) may be a portion formed in the inner space of the etched holes (BG-H) corresponding to the back gate (BG) of each of the vertical channel structures (VS) in the separation insulating layer (S-INS-L) and the common source (CS) described below.

[0102] The reason why the back gate wiring (BGW) is configured to include a horizontal portion (BGW-H) and a vertical portion (BGW-V) is due to the manufacturing process of the back gate wiring (BGW) described below.

[0103] The common source (CS) is a component corresponding to the common source (CS) of FIG. 1, and can be electrically connected to the vertical channel structures (VS) via a vertical channel pattern (VCP). Similarly, the common source (CS) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) so as to enable voltage application to the vertical channel structures (VS).

[0104] Although the drawing illustrates that the common source (CS) is implemented in a plate shape to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) constituting the array, it is not limited thereto and may be implemented in a line shape. In this case, the common source (CS) may be implemented to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). Furthermore, the common source (CS) is shared not only by the vertical channel structures (VS) included in the same row or column, but also by the vertical channel structures (VS) included in adjacent rows or columns, thereby connecting the vertical channel patterns (VCPs) included in each of the vertical channel structures (VS) included in the same row or column and the vertical channel structures (VS) included in adjacent rows or columns to each other. A detailed description thereof will be provided below.

[0105] A separating insulating layer (S-INS-L) may be interposed between the common source (CS) and the horizontal portion (BGW-H) of the back gate wiring (BGW). Therefore, a short circuit between the horizontal portion (BGW-H) of the back gate wiring (BGW) and the common source (CS) due to the horizontal portion (BGW-H) of the back gate wiring (BGW) directly contacting one surface of the common source (CS) can be prevented by the separating insulating layer (S-INS-L).

[0106] In addition, in the etched holes (BG-H) corresponding to the back gate (BG) of each of the vertical channel structures (VS) in the isolation insulating layer (S-INS-L) and the common source (CS), an isolation insulating film (S-INS) may be interposed between the vertical portion (BGW-V) of the back gate wiring (BGW) and the inner wall of the holes (BG-H) of the common source (CS). That is, the isolation insulating film (S-INS) may be formed to surround the outer wall of the vertical portion (BGW-V) of the back gate wiring (BGW) within each of the holes (BG-H). Accordingly, a short circuit between the common source (CS) and the vertical portion (BGW-V) of the back gate wiring (BGW) due to the vertical portion (BGW-V) of the back gate wiring (BGW) directly contacting the common source (CS) within each of the holes (BG-H) can be prevented.

[0107] A capping layer (CAP) may be provided on an upper surface of a vertical channel pattern (VCP). The capping layer (CAP) may be connected to an upper portion of the vertical channel pattern (VCP). A side wall of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). An upper surface of the capping layer (CAP) may be substantially coplanar with an upper surface of a stacked structure (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILD). A lower surface of the capping layer (CAP) may be located at a level lower than an upper surface of a third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap the third gate electrode (EL3) in a horizontal direction.

[0108] The capping layer (CAP) may be formed of a material having a lower contact resistance than the contact resistance that the vertical channel pattern (VCP) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP) may reduce the contact resistance between the bit line (BL) and the vertical channel pattern (VCP), which will be described later. However, depending on the implementation example, the capping layer (CAP) may be omitted.

[0109] A capping insulating film (CAP-INS) may be provided on the stacked structure (ST) and the vertical channel structures (VS). The capping insulating film (CAP-INS) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD) and an upper surface of the capping layer (CAP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0110] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0111] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a vertical channel pattern (VCP) included in the vertical channel structures (VS).

[0112] A three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes gate electrodes (EL1, EL2, EL3) to which voltages for memory operation are applied, a bit line (BL), a common source (CS), a vertical channel pattern (VCP), a data storage pattern (DSP), and a back gate (BG), and a back gate wiring (BGW), according to an implementation example.

[0113] In addition, the 3D flash memory may be a 3D flash memory based on hybrid bonding, in which two structures having the structure illustrated in FIG. 3 are prepared and then bonded facing each other with respect to a bit line (BL). However, the 3D flash memory may also be a 3D flash memory based on hybrid bonding, in which two structures are bonded facing each other with respect to a back gate wiring (BGW), without being limited thereto.

[0114] Below, a method for manufacturing a back gate wiring (BGW) in a three-dimensional flash memory of the described structure is described.

[0115]

[0116] FIG. 4 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to one embodiment, and FIGS. 5A to 5G are cross-sectional views illustrating the structure of a three-dimensional flash memory in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 4, and FIGS. 6A to 6G are plan views illustrating the structure of a three-dimensional flash memory in a case where each of a horizontal portion of a back gate wiring and a common source are formed in a plate shape in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 4, and FIGS. 7 to 8 are plan views illustrating the structure of a three-dimensional flash memory in a case where a common source is formed in a line shape in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 4, and FIGS. 9 to 10 are plan views illustrating the structure of a three-dimensional flash memory in a case where a horizontal portion of a back gate wiring is formed in a line shape in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 4.

[0117] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 3, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0118] In addition, a method for manufacturing a back gate wiring based on a semiconductor structure (SEMI-STR) before a capping insulating film (CAP-INS), a bit line contact plug (BLPG), and bit lines (BL) are created is described through FIGS. 5a to 5g below.

[0119] In step (S410), the manufacturing system can prepare a semiconductor structure (SEMI-STR) as shown in FIG. 5a and FIG. 6a.

[0120] Here, the semiconductor structure (SEMI-STR) may include gate electrodes (EL1, EL2, EL3) that are formed to extend in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and are stacked while being spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and vertical channel structures (VS) that are formed to extend in a vertical direction (e.g., a third direction (D3)) through the gate electrodes (EL1, EL2, EL3). Each of the vertical channel structures (VS) may include a vertical channel pattern (VCP) that is formed to extend in a vertical direction (e.g., a third direction (D3)) as described above, a data storage pattern (DSP) that is formed in contact with an outer wall of the vertical channel pattern (VCP), and a back gate (BG) that is formed to extend in a vertical direction (e.g., a third direction (D3)) in an inner space of the vertical channel pattern (VCP).

[0121] The semiconductor structure (SEMI-STR) is prepared through the existing manufacturing process of each of the gate electrodes (EL1, EL2, EL3), interlayer insulating layers (ILD), and vertical channel structures (VS), and a detailed description thereof will be omitted.

[0122] In step (S420), the manufacturing system can sequentially form a common source (CS) and a separation insulating layer (S-INS-L) on one side of a semiconductor structure (SEMI-STR).

[0123] In more detail, the manufacturing system can form a common source (CS) on the upper surface of the flipped semiconductor structure (SEMI-STR) as shown in FIGS. 5b and 6b after flipping the semiconductor structure (SEMI-STR) through the Xtacking process, and can form a separation insulating layer (S-INS-L) on the upper surface of the common source (CS) as shown in FIGS. 5c and 6c. As described above, in the process of manufacturing a 3D flash memory based on hybrid bonding, a back gate wiring manufacturing method is performed. In step (S420), another semiconductor structure (SEMI-STR) is already bonded to the lower surface (the opposite side of the one side on which the common source (CS) and the isolation insulating layer (S-INS-L) are sequentially formed) of the semiconductor structure (SEMI-STR) prepared (if all upper structures such as bit lines (BLs) have been completely manufactured for each of the semiconductor structures (SEMI-STR)) or may be bonded after steps (S430 to S450) described below (if upper structures such as bit lines (BLs) have not been completely manufactured for each of the semiconductor structures (SEMI-STR).

[0124] Before the common source (CS) is formed, a CMP process may be performed on the upper surface of the semiconductor structure (SEMI-STR) on which the common source (CS) is to be formed. Conventional deposition processes such as ALD and CVD may be used in the process of forming each of the common source (CS) and the isolation insulating layer (S-INS-L).

[0125] The isolation insulating layer (S-INS-L) is a component interposed between the back gate wiring (BGW) (more precisely, the horizontal portion (BGW-H) of the back gate wiring (BGW)) and the common source (CS), which will be described later, and can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) (more precisely, the horizontal portion (BGW-H) of the back gate wiring (BGW)) directly contacting one surface of the common source (CS). Accordingly, the step (S420) may include a step of forming the isolation insulating layer (S-INS-L) on one surface of the common source (CS) in order to prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) (more precisely, the horizontal portion (BGW-H) of the back gate wiring (BGW)) directly contacting one surface of the common source (CS).

[0126] Although the common source (CS) is illustrated as being formed in a plate shape in FIG. 6b, it is not limited thereto and may be formed in a line shape as illustrated in FIG. 7 or FIG. 8. That is, in step (S420), the manufacturing system may form the common source (CS) in a plate shape or a line shape.

[0127] When the common source (CS) is formed in a line shape, the common source (CS) can be configured to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the common source (CS) can be formed corresponding to each of the columns in the array of vertical channel structures (VS) as illustrated in FIG. 7, thereby connecting the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same column.

[0128] However, without being limited thereto, when the common source (CS) is formed in a line shape, the common source (CS) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to the space between columns in an array of vertical channel structures (VS) as illustrated in FIG. 8, thereby connecting vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0129] In step (S430), the manufacturing system can form holes (BG-H) by etching an area corresponding to the back gate (BG) of each of the vertical channel structures (VS) in the isolation insulating layer (S-INS-L) and the common source (CS), as illustrated in FIGS. 5d and 6d. The holes (BG-H) can be etched using a dry or wet etching method.

[0130] At this time, the etching area on the horizontal plane of each hole (BG-H) can be variously adjusted so as to satisfy the conditions of being greater than or equal to the horizontal plane area of ​​the back gate (BG) and the conditions of the common source (CS) being in contact with the vertical channel pattern (VCP) of each of the vertical channel structures (VS).

[0131] In step (S440), the manufacturing system can form a separation insulating film (S-INS) on the inner wall of each of the holes (BG-H) as shown in FIG. 5e and FIG. 6e.

[0132] The isolation insulating film (S-INS) is a component interposed between the back gate wiring (BGW) (more precisely, the vertical portion (BGW-V) of the back gate wiring (BGW)) and the common source (CS) (more precisely, the sidewall of the common source (CS) exposed through the holes (BG-H)), which can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) (more precisely, the vertical portion (BGW-V) of the back gate wiring (BGW)) directly contacting the common source (CS) (more precisely, the sidewall of the common source (CS) exposed through the holes (BG-H)) within each of the holes (BG-H). Accordingly, step (S440) may be a step of forming a separation insulating film (S-INS) on the inner sidewall of each of the holes (BG-H) to prevent a short circuit between the back gate wiring (BGW) (more precisely, the vertical portion (BGW-V) of the back gate wiring (BGW)) and the common source (CS) due to direct contact between the back gate wiring (BGW) (more precisely, the sidewall of the common source (CS) exposed through the holes (BG-H)).

[0133] The thickness of the isolation insulating film (S-INS) can be variously adjusted to satisfy the condition that the common source (CS) contacts the vertical channel pattern (VCP) of each of the vertical channel structures (VS) by considering the etching area on the horizontal plane of each of the holes (BG-H).

[0134] Here, step (S440) can be performed by forming a separation insulating film (S-INS) on one side of the separation insulating layer (S-IN-L) and the inner wall and bottom surface of each of the holes (BG-H), and then removing the separation insulating film (S-INS) formed on one side of the separation insulating layer (S-IN-L) and the bottom surface of each of the holes (BG-H) to leave the separation insulating film (S-INS) only on the inner wall of each of the holes (BG-H).

[0135] In step (S450), the manufacturing system can form a back gate wiring (BGW) on one side of a space formed by a separation insulating film (S-ONS) and a separation insulating layer (S-INS-L) in each of the holes (BG-H).

[0136] More specifically, the manufacturing system can form a vertical portion (BGW-V) of a back gate wiring (BGW) inside a space formed by a separating insulating film (S-INS) in each of the holes (BG-H) as illustrated in FIGS. 5f and 6f, and then form a horizontal portion (BGW-H) of the back gate wiring (BGW) on one surface of a separating insulating layer (S-INS-L) as illustrated in FIGS. 5g and 6g.

[0137] At this time, the manufacturing system can form the horizontal portion (BGW-H) of the back gate wiring (BGW) on one side of the separating insulating layer (S-INS-L) so that the horizontal portion (BGW-H) of the back gate wiring (BGW) is in contact with the vertical portion (BGW-V) of the back gate wiring (BGW) formed immediately before.

[0138] The horizontal plane area of ​​the vertical portion (BGW-V) of the back gate wiring (BGW) can be variously adjusted so as to satisfy the condition that it is less than or equal to the horizontal plane area of ​​the back gate (BG).

[0139] Although FIG. 6g illustrates that the horizontal portion (BGW-H) of the back gate wiring (BGW) is formed in a plate shape, it is not limited thereto and may be formed in a line shape as illustrated in FIG. 9 or FIG. 10. That is, in step (S450), the manufacturing system can form the horizontal portion (BGW-H) of the back gate wiring (BGW) in a plate shape or a line shape.

[0140] When the horizontal portion (BGW-H) of the back gate wiring (BGW) is formed in a line shape, the horizontal portion (BGW-H) of the back gate wiring (BGW) can be configured to connect the back gates (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the horizontal portion (BGW-H) of the back gate wiring (BGW) can be formed corresponding to each of the columns in the array of the vertical channel structures (VS), as illustrated in FIG. 9, thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in the same column.

[0141] However, without being limited thereto, when the horizontal portion (BGW-H) of the back gate wiring (BGW) is formed in a line shape, the horizontal portion (BGW-H) of the back gate wiring (BGW) may be configured to be shared by the vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the horizontal portion (BGW-H) of the back gate wiring (BGW) may be formed corresponding to the space between columns in the array of the vertical channel structures (VS) as illustrated in FIG. 10, thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in the columns adjacent to the left and right.

[0142] In the above drawings, when the common source (CS) and back gate wiring (BGW) are configured in a line shape, they are shown to be formed in a direction orthogonal to the bit lines (BL) on the horizontal plane. However, this is not limited or restricted to this and they may also be formed in a direction parallel to the bit lines (BL) on the horizontal plane. Since this is possible only by rotating the formation direction by 90 degrees, a detailed description thereof will be omitted.

[0143] In addition, although the above back gate wiring (BGW) manufacturing method has been described as using a gate first process based on a semiconductor structure (SEMI-STR) in which gate electrodes (EL1, EL2, EL3) are first formed, it is not limited thereto and may also use a gate replacement process based on a semiconductor structure (SEMI-STR) including sacrificial layers (SAC) corresponding to spaces in which gate electrodes (EL1, EL2, EL3) are to be formed later. A detailed description thereof will be described with reference to FIG. 10.

[0144]

[0145] FIG. 11 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to another embodiment.

[0146] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 3, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0147] In addition, the manufacturing method described below is similar to the manufacturing method described above with reference to FIG. 4, but is characterized by using a gate replacement process based on a semiconductor structure (SEMI-STR) including sacrificial layers (SAC) corresponding to spaces where gate electrodes (EL1, EL2, EL3) will be formed later.

[0148] In step (S1110), the manufacturing system can prepare a semiconductor structure (SEMI-STR).

[0149] Here, the semiconductor structure (SEMI-STR) may include sacrificial layers (SAC) that are formed to extend in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and are stacked while being spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and vertical channel structures (VS) that are formed to extend in a vertical direction (e.g., a third direction (D3)) through the sacrificial layers (SAC). Each of the vertical channel structures (VS) may include a vertical channel pattern (VCP) that is formed to extend in a vertical direction (e.g., a third direction (D3)) as described above, a data storage pattern (DSP) that is formed in contact with an outer wall of the vertical channel pattern (VCP), and a back gate (BG) that is formed to extend in a vertical direction (e.g., a third direction (D3)) in an inner space of the vertical channel pattern (VCP).

[0150] The semiconductor structure (SEMI-STR) is prepared through the existing manufacturing process of each of the gate electrodes (EL1, EL2, EL3), interlayer insulating layers (ILD), and vertical channel structures (VS), and a detailed description thereof will be omitted.

[0151] In step (S1120), the manufacturing system can sequentially form a common source (CS) and a separation insulating layer (S-INS-L) on one side of a semiconductor structure (SEMI-STR).

[0152] In more detail, the manufacturing system can form a common source (CS) on the upper surface of the flipped semiconductor structure (SEMI-STR) after flipping the semiconductor structure (SEMI-STR) through an Xtacking process, and form a separation insulating layer (S-INS-L) on the upper surface of the common source (CS). As described above, in the process of manufacturing a 3D flash memory based on hybrid bonding, a back gate wiring manufacturing method is performed, and in step (S1120), another semiconductor structure (SEMI-STR) is already bonded to the lower surface (the opposite side of the one side on which the common source (CS) and the isolation insulating layer (S-INS-L) are sequentially formed) of the semiconductor structure (SEMI-STR) prepared (if all upper structures such as bit lines (BLs) have been completely manufactured for each of the semiconductor structures (SEMI-STR)) or may be bonded after steps (S1130 to S1160) described below (if upper structures such as bit lines (BLs) have not been completely manufactured for each of the semiconductor structures (SEMI-STR)).

[0153] Before the common source (CS) is formed, a CMP process may be performed on the upper surface of the semiconductor structure (SEMI-STR) on which the common source (CS) is to be formed. Conventional deposition processes such as ALD and CVD may be used in the process of forming each of the common source (CS) and the isolation insulating layer (S-INS-L).

[0154] The isolation insulating layer (S-INS-L) is a component interposed between the back gate wiring (BGW) (more precisely, the horizontal portion (BGW-H) of the back gate wiring (BGW)) and the common source (CS), which will be described later, and can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) (more precisely, the horizontal portion (BGW-H) of the back gate wiring (BGW)) directly contacting one surface of the common source (CS). Accordingly, the step (S1120) may include a step of forming the isolation insulating layer (S-INS-L) on one surface of the common source (CS) in order to prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) (more precisely, the horizontal portion (BGW-H) of the back gate wiring (BGW)) directly contacting one surface of the common source (CS).

[0155] The common source (CS) may be formed not only in a plate shape but also in a line shape. That is, in step (S1120), the manufacturing system may form the common source (CS) in a plate shape or a line shape.

[0156] When the common source (CS) is formed in a line shape, the common source (CS) may be configured to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to each of the columns in the array of the vertical channel structures (VS), thereby connecting the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same column.

[0157] However, without being limited thereto, when the common source (CS) is formed in a line shape, the common source (CS) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to a space between columns in an array of vertical channel structures (VS), thereby connecting vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0158] In step (S1130), the manufacturing system can form holes (BG-H) by etching an area corresponding to the back gate (BG) of each of the vertical channel structures (VS) in the isolation insulating layer (S-INS-L) and the common source (CS). The holes (BG-H) can be etched by a dry or wet etching method.

[0159] At this time, the etching area on the horizontal plane of each hole (BG-H) can be variously adjusted so as to satisfy the conditions of being greater than or equal to the horizontal plane area of ​​the back gate (BG) and the conditions of the common source (CS) being in contact with the vertical channel pattern (VCP) of each of the vertical channel structures (VS).

[0160] In step (S1140), the manufacturing system can form a separation insulating film (S-INS) on the inner wall of each of the holes (BG-H).

[0161] The isolation insulating film (S-INS) is a component interposed between the back gate wiring (BGW) (more precisely, the vertical portion (BGW-V) of the back gate wiring (BGW)) and the common source (CS) (more precisely, the sidewall of the common source (CS) exposed through the holes (BG-H)), which can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) (more precisely, the vertical portion (BGW-V) of the back gate wiring (BGW)) directly contacting the common source (CS) (more precisely, the sidewall of the common source (CS) exposed through the holes (BG-H)) within each of the holes (BG-H). Accordingly, step (S1140) may be a step of forming a separation insulating film (S-INS) on the inner sidewall of each of the holes (BG-H) to prevent a short circuit between the back gate wiring (BGW) (more precisely, the vertical portion (BGW-V) of the back gate wiring (BGW)) and the common source (CS) due to direct contact between the back gate wiring (BGW) (more precisely, the sidewall of the common source (CS) exposed through the holes (BG-H)).

[0162] The thickness of the isolation insulating film (S-INS) can be variously adjusted to satisfy the condition that the common source (CS) contacts the vertical channel pattern (VCP) of each of the vertical channel structures (VS) by considering the etching area on the horizontal plane of each of the holes (BG-H).

[0163] Here, step (S1140) can be performed by forming a separation insulating film (S-INS) on one side of the separation insulating layer (S-IN-L) and the inner wall and bottom surface of each of the holes (BG-H), and then removing the separation insulating film (S-INS) formed on one side of the separation insulating layer (S-IN-L) and the bottom surface of each of the holes (BG-H) to leave the separation insulating film (S-INS) only on the inner wall of each of the holes (BG-H).

[0164] In step (S1150), the manufacturing system can form a back gate wiring (BGW) on one side of a space formed by a separation insulating film (S-ONS) and a separation insulating layer (S-INS-L) in each of the holes (BG-H).

[0165] More specifically, the manufacturing system can form a vertical portion (BGW-V) of a back gate wiring (BGW) inside a space formed by a separating insulating film (S-INS) in each of the holes (BG-H), and then form a horizontal portion (BGW-H) of the back gate wiring (BGW) on one surface of a separating insulating layer (S-INS-L).

[0166] At this time, the manufacturing system can form the horizontal portion (BGW-H) of the back gate wiring (BGW) on one side of the separating insulating layer (S-INS-L) so that the horizontal portion (BGW-H) of the back gate wiring (BGW) is in contact with the vertical portion (BGW-V) of the back gate wiring (BGW) formed immediately before.

[0167] The horizontal plane area of ​​the vertical portion (BGW-V) of the back gate wiring (BGW) can be variously adjusted so as to satisfy the condition that it is less than or equal to the horizontal plane area of ​​the back gate (BG).

[0168] The horizontal portion (BGW-H) of the back gate wiring (BGW) may be formed not only in a plate shape but also in a line shape. That is, in step (S1150), the manufacturing system may form the horizontal portion (BGW-H) of the back gate wiring (BGW) in a plate shape or a line shape.

[0169] When the horizontal portion (BGW-H) of the back gate wiring (BGW) is formed in a line shape, the horizontal portion (BGW-H) of the back gate wiring (BGW) can be configured to connect the back gates (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the horizontal portion (BGW-H) of the back gate wiring (BGW) can be formed corresponding to each of the columns in the array of the vertical channel structures (VS), thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in the same column.

[0170] However, without being limited thereto, when the horizontal portion (BGW-H) of the back gate wiring (BGW) is formed in a line shape, the horizontal portion (BGW-H) of the back gate wiring (BGW) may be configured to be shared by the vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the horizontal portion (BGW-H) of the back gate wiring (BGW) may be formed corresponding to the space between columns in the array of the vertical channel structures (VS), thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in the columns adjacent to the left and right.

[0171] In step (S1160), the manufacturing system can form gate electrodes (EL1, EL2, EL3) in the spaces where the sacrificial layers (SAC) are removed by removing the sacrificial layers (SAC). The removal of the sacrificial layers (SAC) can be performed through a trench or hole formed on one side of the semiconductor structure (SEMI-STR) for a gate replacement process. Since the gate replacement process can be applied in a conventional manner, a detailed description thereof will be omitted.

[0172] As with the manufacturing method described above with reference to FIG. 4, when the common source (CS) and back gate wiring (BGW) are configured in a line shape, they may be formed not only in a direction perpendicular to the bit lines (BL) on the horizontal plane, but also in a direction parallel to the bit lines (BL) on the horizontal plane. Since this only requires a 90-degree rotation in the formation direction, a detailed description thereof will be omitted.

[0173]

[0174] FIG. 12 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment, and FIG. 13 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, which corresponds to a cross-section taken along line A-A' of FIG. 12.

[0175] Referring to the drawings, the laminated structure (ST) can be formed to extend in the first direction (D1) and the second direction (D2). In the drawings, the laminated structure (ST) is illustrated as one, but is not limited thereto, and a plurality of laminated structures (ST) may be provided and arranged two-dimensionally while being spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0176] The stacked structure (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)). The stacked structure (ST) may have a substantially flat upper surface. Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0177] Although omitted in the drawing, the stacked structure (ST) may exist in a state of being arranged on the substrate (SUB) prior to the formation of the common source (CS) and the back gate wiring (BGW). That is, the stacked structure (ST) may be manufactured by alternately stacking gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) may be removed during the formation of the common source (CS) and the back gate wiring (BGW), so that the substrate (SUB) may not be included as a result.

[0178] The substrate (SUB) used in the manufacturing process of the stacked structure (ST) may be a semiconductor substrate such as a substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0179] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3) and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked in a direction from bottom to top.

[0180] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0181] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0182] Although not shown, the end of the stacked structure (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structure (ST) may have a length in the first direction (D1) that decreases from the bottom toward the top. The third gate electrode (EL3) may have the shortest length in the first direction (D1) and may have the longest distance from the bottom along the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and may have the shortest distance from the bottom along the third direction (D3). By means of the step structure, the thickness of the stacked structure (ST) can decrease as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0183] However, without being limited or restricted thereto, the end of the laminated structure (ST) may have a step structure along the second direction (D2).

[0184] Each of the interlayer insulating layers (ILDs) may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than the other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating layers (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0185] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) may be stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0186] A plurality of channel holes (CH) penetrating a portion of a stacked structure (ST) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may extend in a third direction (D3) while being connected to a common source (CS). The vertical channel structures (VS) may be connected to the common source (CS) by having a lower surface of each of a portion of the vertical channel structures (VS) come into contact with an upper surface of the common source (CS).

[0187] The rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as illustrated in FIG. 12, 15 vertical channel structures (VS) may penetrate the stacked structure (ST) forming 6 columns and 5 rows. However, the number of vertical channel structures (VS) forming the array is not limited or restricted thereto.

[0188] As vertical channel structures (VS) are formed in a plate shape, the array is formed in a horizontal plane of multiple rows and columns of gate electrodes (EL1, EL2, EL3), so that the three-dimensional flash memory can have a structure in which the integration of memory cell strings is improved.

[0189] In particular, memory directivity can be improved as the common source (CS) and its wiring are located at the bottom of the stacked structure (ST), unlike the conventional structure in which the CS and its wiring are included inside the stacked structure (ST).

[0190] At this time, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on a horizontal plane and to be misaligned with each other. For example, the vertical channel structures (VS) included in a first column may be arranged in the first row, the third row, and the third row, and the vertical channel structures (VS) included in a second column may be arranged in the second row and the fourth row, such that the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string can be further improved compared to the case where the vertical channel structures (VS) included in a pair of adjacent columns are arranged side by side in the same row on a horizontal plane.

[0191] Each of the vertical channel structures (VS) may be formed to extend from the bottom to the top in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0192] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a back gate (BG), and a capping layer (CAP-L). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with an open bottom, and the back gate (BG) may have a shape that fills the inner space of the vertical channel pattern (VCP).

[0193] The data storage pattern (DSP) can cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the vertical channel pattern (VCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. Accordingly, the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) can form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2) together with the regions corresponding to the second gate electrodes (EL2) of the vertical channel pattern (VCP). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0194] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by a voltage applied through the second gate electrodes (EL2), or by maintaining the state of electrons (e.g., the polarization state of charges). For example, an ONO (tunnel oxide-nitride-blocking oxide) layer or a ferroelectric layer can be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent a binary data value or a multi-valued data value by a change in the trapped charge or hole, or can represent a binary data value or a multi-valued data value by a change in the state of charges.

[0195] Although the above data storage pattern (DSP) is described as being vertically connected and extended, it is not limited to this and may be segmented into multiple pieces and formed only in the portion corresponding to the second gate electrodes (EL), thereby forming memory cells together with the regions corresponding to the second gate electrodes (EL2) among the vertical channel pattern (VCP).

[0196] A vertical channel pattern (VCP) is a component that supplies electrons or holes to transfer charges to a data storage pattern (DSP). The vertical channel pattern (VCP) may be formed to extend in a vertical direction (e.g., a third direction (D3)) while covering an inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage. More specifically, the vertical channel pattern (VCP) may perform a memory operation in response to a voltage applied by a bit line (BL), a common source (CS), a back gate (BG), and gate electrodes (EL1, EL2, EL3). For this purpose, the vertical channel pattern (VCP) may be formed of, for example, single-crystalline silicon or polycrystalline silicon.

[0197] The upper surface of the vertical channel pattern (VCP) may be positioned at a higher level than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the vertical channel pattern (VCP) may be positioned between the upper surface and the lower surface of the third gate electrode (EL3). The lower surface of the vertical channel pattern (VCP) may be coplanar with the upper surface of the common source (CS) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD).

[0198] The back gate (BG) may be formed to be in contact with the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP). For example, the back gate (BG) may be formed to extend vertically (e.g., in the third direction (D3)) within the inner space of the vertical channel pattern (VCP).

[0199] Here, the back gate (BG) can be formed to apply a voltage for a memory operation to the vertical channel pattern (VCP). To this end, the back gate (BG) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). In addition to the described metal materials, the back gate (BG) can include at least one of all metal materials that can be formed by ALD.

[0200] In addition, a back gate insulating film (BG-INS) may be formed and extended in a vertical direction (e.g., a third direction (D3)) between the back gate (BG) and the vertical channel pattern (VCP). Accordingly, the back gate insulating film (BG-INS) may prevent the back gate (BG) from directly contacting the vertical channel pattern (VCP). The back gate insulating film (BG-INS), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide. However, the back gate insulating film (BG-INS) may be omitted depending on the implementation example.

[0201] Referring back to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0202] The back gates (BG) included in each of the vertical channel structures (VS) may be electrically connected to each other by a back gate wiring (BGW). Accordingly, the back gate wiring (BGW), like the back gate (BG), may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0203] Although the drawing illustrates that the back gate wiring (BGW) is implemented in the form of a plate to connect the back gates (BG) of each of the vertical channel structures (VS) constituting the array, it may be implemented in the form of a line, without being limited thereto. In this case, the back gate wiring (BGW) may be implemented to connect the back gates (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). Furthermore, the back gate wiring (BGW) may be shared not only by the vertical channel structures (VS) included in the same row or column, but also by the vertical channel structures (VS) included in adjacent rows or columns, thereby connecting the back gates (BG) included in each of the vertical channel structures (VS) included in the same row or column and the vertical channel structures (VS) included in adjacent rows or columns to each other. A detailed description thereof will be provided below.

[0204] The common source (CS) is a component corresponding to the common source (CS) of FIG. 1, and can be electrically connected to the vertical channel structures (VS) via a vertical channel pattern (VCP). More specifically, the common source (CS) can be formed by a manufacturing method described below so as to be in contact with the lower side of the vertical channel pattern (VCP) of each of the vertical channel structures (VS). However, without being limited thereto, the common source (CS) may also be formed so as to be in contact with the lower side of the data storage pattern (DSP).

[0205] Likewise, the common source (CS) may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) to enable voltage application to the vertical channel structures (VS).

[0206] Although the drawing illustrates that the common source (CS) is implemented in a plate shape to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) constituting the array, it is not limited thereto and may be implemented in a line shape. In this case, the common source (CS) may be implemented to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). Furthermore, the common source (CS) is shared not only by the vertical channel structures (VS) included in the same row or column, but also by the vertical channel structures (VS) included in adjacent rows or columns, thereby connecting the vertical channel patterns (VCPs) included in each of the vertical channel structures (VS) included in the same row or column and the vertical channel structures (VS) included in adjacent rows or columns to each other. A detailed description thereof will be provided below.

[0207] A separating insulating layer (S-INS-L) may be interposed between the common source (CS) and the back gate wiring (BGW). Therefore, a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) directly contacting one surface of the common source (CS) can be prevented by the separating insulating layer (S-INS-L).

[0208] The isolation insulating layer (S-INS-L) can be formed so as to contact the lower side of the back gate insulating film (BG-INS) in each of the vertical channel structures (VS) by forming it by the manufacturing method described below.

[0209] A capping layer (CAP-L) may be provided on an upper surface of a vertical channel pattern (VCP). The capping layer (CAP-L) may be connected to an upper portion of the vertical channel pattern (VCP). A side wall of the capping layer (CAP-L) may be surrounded by a data storage pattern (DSP). An upper surface of the capping layer (CAP-L) may be substantially coplanar with an upper surface of the stacked structure (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILD). A lower surface of the capping layer (CAP-L) may be located at a level lower than an upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP-L) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP-L) may overlap the third gate electrode (EL3) in a horizontal direction.

[0210] The capping layer (CAP-L) may be formed of a material having a lower contact resistance than the contact resistance that the vertical channel pattern (VCP) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP-L) may reduce the contact resistance between the bit line (BL) and the vertical channel pattern (VCP), which will be described later. However, depending on the implementation example, the capping layer (CAP-L) may be omitted.

[0211] A capping insulating film (CAP-INS) may be provided on the stacked structure (ST) and the vertical channel structures (VS). The capping insulating film (CAP-INS) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD) and an upper surface of the capping layer (CAP-L). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP-L) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0212] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0213] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a vertical channel pattern (VCP) included in the vertical channel structures (VS).

[0214] A three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes gate electrodes (EL1, EL2, EL3) to which voltages for memory operation are applied, a bit line (BL), a common source (CS), a vertical channel pattern (VCP), a data storage pattern (DSP), and a back gate (BG), and a back gate wiring (BGW), according to an implementation example.

[0215] In addition, the 3D flash memory may be a 3D flash memory based on hybrid bonding, in which two structures having the structure illustrated in FIG. 13 are prepared and then the two structures are bonded facing each other with respect to a bit line (BL). However, the 3D flash memory may also be a 3D flash memory based on hybrid bonding, in which two structures are bonded facing each other with respect to a back gate wiring (BGW), without being limited thereto.

[0216] Below, a method for manufacturing a back gate wiring (BGW) in a three-dimensional flash memory of the described structure is described.

[0217]

[0218] FIG. 14 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to one embodiment, and FIGS. 15a to 15g are cross-sectional views illustrating a structure of a three-dimensional flash memory in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 14, and FIGS. 16a to 16e are cross-sectional views illustrating a structure of a three-dimensional flash memory when a capping film is included in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 14, and FIGS. 17a to 17g are plan views illustrating a structure of a three-dimensional flash memory when each of the back gate wiring and the common source is formed in a plate shape in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 14, and FIGS. 18 to 19 are plan views illustrating a structure of a three-dimensional flash memory when the common source is formed in a line shape in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 14, and FIGS. 20 to 21 are plan views illustrating a structure of a three-dimensional flash memory when the back gate wiring is formed in a line shape in order to explain the method for manufacturing a back gate wiring illustrated in FIG. 14. This is a floor plan showing the structure of memory.

[0219] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1, 12 and 13, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0220] In addition, the following drawings describe a method for manufacturing a back gate wiring based on a semiconductor structure (SEMI-STR) before a capping insulating film (CAP-INS), a bit line contact plug (BLPG), and bit lines (BL) are created.

[0221] In step (S1410), the manufacturing system can prepare a semiconductor structure (SEMI-STR) as shown in FIG. 15a and FIG. 17a.

[0222] Here, the semiconductor structure (SEMI-STR) may include gate electrodes (EL1, EL2, EL3) that are formed to extend in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and are stacked while being spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and vertical channel structures (VS) that are formed to extend in a vertical direction (e.g., a third direction (D3)) through the gate electrodes (EL1, EL2, EL3). Each of the vertical channel structures (VS) may include a vertical channel pattern (VCP) that is formed to extend in a vertical direction (e.g., a third direction (D3)) as described above, a data storage pattern (DSP) that is formed in contact with an outer wall of the vertical channel pattern (VCP), and a back gate (BG) that is formed to extend in a vertical direction (e.g., a third direction (D3)) in an inner space of the vertical channel pattern (VCP).

[0223] The semiconductor structure (SEMI-STR) is manufactured through a conventional manufacturing process for each of the gate electrodes (EL1, EL2, EL3), interlayer insulating layers (ILD), and vertical channel structures (VS), and then flipped and prepared using the Xtacking technique. A detailed description thereof will be omitted.

[0224] As described above, in the process of manufacturing a 3D flash memory based on hybrid bonding, a back gate wiring manufacturing method is performed. In step (S1410), another semiconductor structure (SEMI-STR) is already bonded to the lower surface of the semiconductor structure (SEMI-STR) prepared (if all upper structures such as bit lines (BLs) have been completely manufactured for each of the semiconductor structures (SEMI-STR)) or may be bonded after steps (S1420 to S1440) described below (if upper structures such as bit lines (BLs) have not been completely manufactured for each of the semiconductor structures (SEMI-STR).

[0225] In step (S1410), when a semiconductor structure (SEMI-STR) is prepared, a CMP process can be performed on one side of the semiconductor structure (SEMI-STR) (the side on which step (S1420) described below is to be performed).

[0226] At this time, when a part of the common source (CS) is recessed in step (S1430) described below, an area corresponding to the back gate (BG) of each of the exposed ends of the vertical channel structures (VS) may be recessed together. Accordingly, in step (S1410), the manufacturing system may prepare a semiconductor structure (SEMI-STR) in which a capping film (CAP) is formed in an area corresponding to the back gate (BG) of each of the exposed ends of the vertical channel structures (VS), as illustrated in FIG. 16A. For example, the capping film (CAP) may be formed of a material or composition different from that of the common source (CS) in order to prevent an area corresponding to the back gate (BG) of each of the exposed ends of the vertical channel structures (VS) from being recessed together when a part of the common source (CS) is recessed in step (S1430).

[0227] In step (S1420), the manufacturing system can recess the semiconductor structure (SEMI-STR) so that one end of each of the vertical channel structures (VS) is exposed on one side of the semiconductor structure (SEMI-STR), as illustrated in FIG. 15b, FIG. 17b, and FIG. 16b.

[0228] Here, one side of the semiconductor structure (SEMI-STR) is recessed so that the lowest one among the interlayer insulating layers (ILDs) included in the semiconductor structure (SEMI-STR) excluding the vertical channel structures (VS) is removed (since the semiconductor structure (SEMI-STR) is prepared by being turned over using the Xtacking technique).

[0229] Additionally, one side of the semiconductor structure (SEMI-STR) may be recessed, and at the same time, an area corresponding to the data storage pattern (DSP) of each of the exposed sides of the vertical channel structures (VS) may be recessed, but is not limited thereto.

[0230] In step (S1430), the manufacturing system can sequentially form a common source (CS) and a separation insulating layer (S-INS-L) to contact the exposed side of each of the vertical channel structures (VS).

[0231] In more detail, the manufacturing system comprises a first step of forming a common source (CS) so as to contact an exposed side surface of a vertical channel pattern (VCP) in each of the vertical channel structures (VS) as illustrated in FIGS. 15c, 17c, and 16c; a second step of recessing a portion of the common source (CS) and a region corresponding to the vertical channel pattern (VCP) so as to expose a back gate insulating film (BG-INS) at an exposed end of each of the vertical channel structures (vs) as illustrated in FIGS. 15d, 17d, and 16d; a third step of forming a separation insulating layer (S-INS-L) on the common source (CS) so as to contact the exposed side surface of the back gate insulating film (BG-INS) in each of the vertical channel structures (VS) as illustrated in FIGS. 15e, 17e, and 16e; and a third step of forming a separation insulating layer (S-INS-L) so as to expose the back gate (BG) of each of the vertical channel structures (VS) as illustrated in FIGS. 15f, 17f. Step (S1430) can be performed through the fourth step of CMP (Chemical mechanical polishing) of a portion of the insulating layer (S-INS-L).

[0232] The first step described corresponds to a case where, in step (S1420), one side of the semiconductor structure (SEMI-STR) is recessed and at the same time, an area corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is recessed. In a case where, in step (S1420), the area corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is not recessed, a step may be performed in which a common source (CS) is formed so as to contact the exposed side of the data storage pattern (DSP) in each of the vertical channel structures (VS). In this case, the second step may be performed in which, in a case where, in the same time as a part of the common source (CS) is recessed, an area corresponding to the data storage pattern (DSP) and an area corresponding to the vertical channel pattern (VCP) are recessed together at the exposed ends of each of the vertical channel structures (vs) so as to expose a back gate insulating film (BG-INS).

[0233] The fourth step described may be performed by CMPing one end of each of the vertical channel structures (VS) together with a portion of the isolation insulating layer (S-INS-L) so that the capping film (CAP) is removed to expose the back gate (BG), as illustrated in FIGS. 16a to 16e, when the capping film (CAP) is included in each of the vertical channel structures (VS).

[0234] In the process of forming each of the common source (CS) and the separation insulating layer (S-INS-L), conventional deposition processes such as ALD and CVD can be used.

[0235] The isolation insulating layer (S-INS-L) is a component interposed between the back gate wiring (BGW) and the common source (CS), which will be described later, and can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) directly contacting one surface of the common source (CS).

[0236] Although the common source (CS) is shown to be formed in a plate shape in FIGS. 15c, 17c, 16c, 15d, 17d, and 16d, it is not limited thereto and may be formed in a line shape as shown in FIGS. 18 to 19. That is, in step (S1430), the manufacturing system can form the common source (CS) in a plate shape or a line shape.

[0237] When the common source (CS) is formed in a line shape, the common source (CS) can be configured to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the common source (CS) can be formed corresponding to each of the columns in the array of the vertical channel structures (VS) as illustrated in FIG. 18, thereby connecting the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same column.

[0238] However, without being limited thereto, when the common source (CS) is formed in a line shape, the common source (CS) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to the space between columns in an array of vertical channel structures (VS) as illustrated in FIG. 19, thereby connecting the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0239] In step (S1440), the manufacturing system can form back gate wiring (BGW) on the vertical channel structures (VS) so as to contact the back gate (BG) of each of the vertical channel structures (VS), as illustrated in FIG. 15g and FIG. 17g.

[0240] Although FIG. 15g and FIG. 17g illustrate that the back gate wiring (BGW) is formed in a plate shape, it is not limited thereto and may be formed in a line shape as illustrated in FIG. 20 or FIG. 21. That is, in step (S1440), the manufacturing system may form the back gate wiring (BGW) in a plate shape or a line shape.

[0241] When the back gate wiring (BGW) is formed in a line shape, the back gate wiring (BGW) can be configured to connect the back gates (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the back gate wiring (BGW) can be formed corresponding to each of the columns in the array of vertical channel structures (VS) as illustrated in FIG. 20, thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in the same column.

[0242] However, without being limited thereto, when the back gate wiring (BGW) is formed in a line shape, the back gate wiring (BGW) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the back gate wiring (BGW) may be formed corresponding to the space between columns in an array of vertical channel structures (VS) as illustrated in FIG. 21, thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0243] In the above drawings, when the common source (CS) and back gate wiring (BGW) are configured in a line shape, they are shown to be formed in a direction orthogonal to the bit lines (BL) on the horizontal plane. However, this is not limited or restricted to this and they may also be formed in a direction parallel to the bit lines (BL) on the horizontal plane. Since this is possible only by rotating the formation direction by 90 degrees, a detailed description thereof will be omitted.

[0244] In addition, although the above back gate wiring (BGW) manufacturing method has been described as using a gate first process based on a semiconductor structure (SEMI-STR) in which gate electrodes (EL1, EL2, EL3) are first formed, it is not limited thereto and may also use a gate replacement process based on a semiconductor structure (SEMI-STR) including sacrificial layers (SAC) corresponding to spaces in which gate electrodes (EL1, EL2, EL3) are to be formed later. A detailed description thereof will be described with reference to FIG. 22.

[0245]

[0246] FIG. 22 is a flow chart illustrating a method for manufacturing a back gate wiring in a three-dimensional flash memory according to another embodiment.

[0247] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1, 12 and 13, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0248] In addition, the manufacturing method described below is similar to the manufacturing method described above with reference to FIG. 14, but is characterized by using a gate replacement process based on a semiconductor structure (SEMI-STR) including sacrificial layers (SAC) corresponding to spaces where gate electrodes (EL1, EL2, EL3) will be formed later.

[0249] In step (S2210), the manufacturing system can prepare a semiconductor structure (SEMI-STR).

[0250] Here, the semiconductor structure (SEMI-STR) may include sacrificial layers (SAC) that are formed to extend in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and are stacked while being spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and vertical channel structures (VS) that are formed to extend in a vertical direction (e.g., a third direction (D3)) through the sacrificial layers (SAC). Each of the vertical channel structures (VS) may include a vertical channel pattern (VCP) that is formed to extend in a vertical direction (e.g., a third direction (D3)) as described above, a data storage pattern (DSP) that is formed in contact with an outer wall of the vertical channel pattern (VCP), and a back gate (BG) that is formed to extend in a vertical direction (e.g., a third direction (D3)) in an inner space of the vertical channel pattern (VCP).

[0251] The semiconductor structure (SEMI-STR) is manufactured through a conventional manufacturing process for each of the gate electrodes (EL1, EL2, EL3), interlayer insulating layers (ILD), and vertical channel structures (VS), and then flipped and prepared using the Xtacking technique. A detailed description thereof will be omitted.

[0252] As described above, in the process of manufacturing a 3D flash memory based on hybrid bonding, a back gate wiring manufacturing method is performed. In step (S2210), another semiconductor structure (SEMI-STR) is already bonded to the lower surface of the semiconductor structure (SEMI-STR) prepared (if all upper structures such as bit lines (BLs) have been completely manufactured for each of the semiconductor structures (SEMI-STR)) or may be bonded after steps (S2220 to S2250) described below (if upper structures such as bit lines (BLs) have not been completely manufactured for each of the semiconductor structures (SEMI-STR)).

[0253] In step (S2210), when a semiconductor structure (SEMI-STR) is prepared, a CMP process can be performed on one side of the semiconductor structure (SEMI-STR) (the side on which step (S2220) described below is to be performed).

[0254] At this time, when a part of the common source (CS) is recessed in step (S2230) described below, an area corresponding to the back gate (BG) of each of the exposed ends of the vertical channel structures (VS) may be recessed together. Accordingly, in step (S2210), the manufacturing system may prepare a semiconductor structure (SEMI-STR) in which a capping film (CAP) is formed in an area corresponding to the back gate (BG) of each of the exposed ends of the vertical channel structures (VS). For example, the capping film (CAP) may be formed of a material or composition different from that of the common source (CS) in order to prevent an area corresponding to the back gate (BG) of each of the exposed ends of the vertical channel structures (VS) from being recessed together when a part of the common source (CS) is recessed in step (S2230).

[0255] In step (S2220), the manufacturing system can recess the semiconductor structure (SEMI-STR) so that one end of each of the vertical channel structures (VS) is exposed on one side of the semiconductor structure (SEMI-STR).

[0256] Here, one side of the semiconductor structure (SEMI-STR) is recessed so that the lowest one among the interlayer insulating layers (ILDs) included in the semiconductor structure (SEMI-STR) excluding the vertical channel structures (VS) is removed (since the semiconductor structure (SEMI-STR) is prepared by being turned over using the Xtacking technique).

[0257] Additionally, one side of the semiconductor structure (SEMI-STR) may be recessed, and at the same time, an area corresponding to the data storage pattern (DSP) of each of the exposed sides of the vertical channel structures (VS) may be recessed, but is not limited thereto.

[0258] In step (S2230), the manufacturing system can sequentially form a common source (CS) and a separation insulating layer (S-INS-L) to contact the exposed side of each of the vertical channel structures (VS).

[0259] In more detail, the manufacturing system can perform step (S2230) through a first step of forming a common source (CS) so as to contact an exposed side surface of a vertical channel pattern (VCP) in each of the vertical channel structures (VS), a second step of recessing a region corresponding to the vertical channel pattern (VCP) and a portion of the common source (CS) so as to expose a back gate insulating film (BG-INS) in an exposed end of each of the vertical channel structures (vs), a third step of forming a separation insulating layer (S-INS-L) on the common source (CS) so as to contact the exposed side surface of the back gate insulating film (BG-INS) in each of the vertical channel structures (VS), and a fourth step of chemical mechanical polishing (CMP) a portion of the separation insulating layer (S-INS-L) so as to expose the back gate (BG) of each of the vertical channel structures (VS).

[0260] The first step described corresponds to a case where, at step (S2220), one side of the semiconductor structure (SEMI-STR) is recessed and at the same time, an area corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is recessed. If, at step (S2220), the area corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is not recessed, a step may be performed in which a common source (CS) is formed so as to contact the exposed side of the data storage pattern (DSP) in each of the vertical channel structures (VS). In this case, the second step may be performed in which, at the same time as a part of the common source (CS) is recessed, an area corresponding to the data storage pattern (DSP) and an area corresponding to the vertical channel pattern (VCP) are recessed together at the exposed ends of each of the vertical channel structures (vs) so as to expose a back gate insulating film (BG-INS).

[0261] The fourth step described may be performed by CMPing one end of each of the vertical channel structures (VS) together with a portion of the isolation insulating layer (S-INS-L) so that the capping film (CAP) is removed to expose the back gate (BG), if the vertical channel structures (VS) each include a capping film (CAP).

[0262] In the process of forming each of the common source (CS) and the separation insulating layer (S-INS-L), conventional deposition processes such as ALD and CVD can be used.

[0263] The isolation insulating layer (S-INS-L) is a component interposed between the back gate wiring (BGW) and the common source (CS), which will be described later, and can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) due to the back gate wiring (BGW) directly contacting one surface of the common source (CS).

[0264] The common source (CS) may be formed not only in a plate shape but also in a line shape. That is, in step (S2230), the manufacturing system may form the common source (CS) in a plate shape or a line shape.

[0265] When the common source (CS) is formed in a line shape, the common source (CS) may be configured to connect the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to each of the columns in the array of the vertical channel structures (VS), thereby connecting the vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in the same column.

[0266] However, without being limited thereto, when the common source (CS) is formed in a line shape, the common source (CS) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to a space between columns in an array of vertical channel structures (VS), thereby connecting vertical channel patterns (VCPs) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0267] In step (S2240), the manufacturing system can form back gate wiring (BGW) on the vertical channel structures (VS) so as to contact the back gate (BG) of each of the vertical channel structures (VS).

[0268] The back gate wiring (BGW) may be formed not only in a plate shape but also in a line shape. That is, in step (S2240), the manufacturing system may form the back gate wiring (BGW) in a plate shape or a line shape.

[0269] When the back gate wiring (BGW) is formed in a line shape, the back gate wiring (BGW) can be configured to connect the back gates (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). For example, the back gate wiring (BGW) can be formed corresponding to each of the columns in the array of the vertical channel structures (VS), thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in the same column.

[0270] However, without being limited thereto, when the back gate wiring (BGW) is formed in a line shape, the back gate wiring (BGW) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the back gate wiring (BGW) may be formed corresponding to a space between columns in an array of vertical channel structures (VS), thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0271] In step (S2250), the manufacturing system can form gate electrodes (EL1, EL2, EL3) in the spaces where the sacrificial layers (SAC) have been removed by removing the sacrificial layers (SAC). The removal of the sacrificial layers (SAC) can be performed through a trench or hole formed on one side of the semiconductor structure (SEMI-STR) for a gate replacement process. Since the gate replacement process can be applied in a conventional manner, a detailed description thereof will be omitted.

[0272] As with the manufacturing method described above with reference to FIG. 14, when the common source (CS) and back gate wiring (BGW) are configured in a line shape, they may be formed not only in a direction perpendicular to the bit lines (BL) on the horizontal plane, but also in a direction parallel to the bit lines (BL) on the horizontal plane. Since this only requires a 90-degree rotation in the formation direction, a detailed description thereof will be omitted.

[0273]

[0274] FIG. 23 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0275] Referring to FIG. 23, an electronic system (2300) including a three-dimensional flash memory according to embodiments may include a main substrate (2301), a controller (2302) mounted on the main substrate (2301), one or more semiconductor packages (2303), and a DRAM (2304).

[0276] The semiconductor package (2303) and DRAM (2304) can be interconnected with the controller (2302) by wiring patterns (2305) provided on the main substrate (2301).

[0277] The main board (2301) may include a connector (2306) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2306) may vary depending on the communication interface between the electronic system (2300) and the external host.

[0278] The electronic system (2300) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (2300) may operate by power supplied from an external host, for example, through a connector (2306). The electronic system (2300) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2302) and a semiconductor package (2303).

[0279] The controller (2302) can write data to the semiconductor package (2303) or read data from the semiconductor package (2303), and can improve the operating speed of the electronic system (2300).

[0280] The DRAM (2304) may be a buffer memory to mitigate the speed difference between the semiconductor package (2303), which is a data storage space, and an external host. The DRAM (2304) included in the electronic system (2300) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (2303). When the electronic system (2300) includes the DRAM (2304), the controller (2302) may further include a DRAM controller for controlling the DRAM (2304) in addition to the NAND controller for controlling the semiconductor package (2303).

[0281] A semiconductor package (2303) may include first and second semiconductor packages (2303a, 2303b) that are spaced apart from each other. The first and second semiconductor packages (2303a, 2303b) may each be a semiconductor package including a plurality of semiconductor chips (2320). Each of the first and second semiconductor packages (2303a, 2303b) may include a package substrate (2310), semiconductor chips (2320) on the package substrate (2310), adhesive layers (2330) disposed on a lower surface of each of the semiconductor chips (2320), connection structures (2340) that electrically connect the semiconductor chips (2320) and the package substrate (2310), and a molding layer (2350) that covers the semiconductor chips (2320) and the connection structures (2340) on the package substrate (2310).

[0282] The package substrate (2310) may be a printed circuit board including package upper pads (2311). Each of the semiconductor chips (2320) may include input / output pads (2321). Each of the semiconductor chips (2320) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 22. More specifically, each of the semiconductor chips (2320) may include a gate stack structure (2322) and memory channel structures (2323). The memory channel structures (2323) may correspond to the vertical channel structures (VS) described above.

[0283] The connection structures (2340) may be, for example, bonding wires that electrically connect the input / output pads (2321) and the package upper pads (2311). Accordingly, in each of the first and second semiconductor packages (2303a, 2303b), the semiconductor chips (2320) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (2311) of the package substrate (2310). According to embodiments, in each of the first and second semiconductor packages (2303a, 2303b), the semiconductor chips (2320) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (2340).

[0284] Unlike the illustration, the controller (2302) and the semiconductor chips (2320) may be included in a single package. The controller (2302) and the semiconductor chips (2320) may be mounted on a separate interposer substrate different from the main substrate (2301), and the controller (2302) and the semiconductor chips (2320) may be connected to each other by wiring provided on the interposer substrate.

[0285]

[0286] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0287] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. A step of preparing a semiconductor structure including gate electrodes that are formed to extend in a horizontal direction and are stacked while being spaced apart from each other in a vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the gate electrodes, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed in contact with an outer wall of the vertical channel pattern, and a back gate that extends in the vertical direction in an inner space of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the gate electrodes; A step of sequentially forming a common source and a separation insulating layer on one surface of the semiconductor structure; A step of forming holes by etching an area corresponding to the back gate of each of the vertical channel structures in the above separation insulating layer and the above common source; A step of forming a separation insulating film on the inner wall of each of the above holes; and A step of forming a back gate wiring on the inside of the space formed by the separation insulating film in each of the above holes and on one side of the separation insulating layer. A method for manufacturing a back gate wiring including:

2. A step of preparing a semiconductor structure including sacrificial layers that are formed to extend in the horizontal direction and are stacked while being spaced apart from each other in the vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the sacrificial layers, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed in contact with an outer wall of the vertical channel pattern, and a back gate that extends in the vertical direction in an inner space of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to gate electrodes to be formed in spaces where the sacrificial layers are removed; A step of sequentially forming a common source and a separation insulating layer on one surface of the semiconductor structure; A step of forming holes by etching an area corresponding to the back gate of each of the vertical channel structures in the above separation insulating layer and the above common source; A step of forming a separation insulating film on the inner wall of each of the above holes; A step of forming a back gate wiring on the inner side of the space formed by the separation insulating film in each of the above holes and on one side of the separation insulating layer; and A step of removing the sacrificial layers and forming the gate electrodes in the spaces where the sacrificial layers are removed. A method for manufacturing a back gate wiring including:

3. In paragraph 1, The step of forming the above back gate wiring is: A step of forming a vertical portion of the back gate wiring inside the space formed by the separation insulating film in each of the holes; and A step of forming a horizontal portion of the back gate wiring on one surface of the above separation insulating layer. A method for manufacturing a back gate wiring, characterized in that it includes:

4. In paragraph 2, The step of forming the above back gate wiring is: A step of forming a vertical portion of the back gate wiring inside the space formed by the separation insulating film in each of the holes; and A step of forming a horizontal portion of the back gate wiring on one surface of the above separation insulating layer. A method for manufacturing a back gate wiring, characterized in that it includes:

5. In either of paragraphs 3 or 4, The step of forming the horizontal portion of the above back gate wiring is: A step of forming a horizontal portion of the above back gate wiring in a plate shape; or A step of forming the horizontal portion of the above back gate wiring in a line shape A method for manufacturing a back gate wiring, characterized in that it comprises one of the steps.

6. A step of preparing a semiconductor structure including gate electrodes that are formed to extend in the horizontal direction and are stacked while being spaced apart from each other in the vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the gate electrodes, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern that is formed in contact with an outer wall of the vertical channel pattern, and a back gate that is formed to extend in the vertical direction in an inner space of the vertical channel pattern; A step of recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one side of the semiconductor structure; A step of sequentially forming a common source and a separation insulating layer so as to contact the exposed side surfaces of each of the above vertical channel structures; and A step of forming a back gate wiring on the vertical channel structures so as to contact the back gate of each of the vertical channel structures. A method for manufacturing a back gate wiring including:

7. A step of preparing a semiconductor structure including sacrificial layers that are formed to extend in the horizontal direction and are stacked while being spaced apart from each other in the vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the sacrificial layers, each of the vertical channel structures including a vertical channel pattern that extends in the vertical direction, a data storage pattern formed in contact with an outer wall of the vertical channel pattern, and a back gate that extends in the vertical direction in an inner space of the vertical channel pattern; A step of recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one side of the semiconductor structure; A step of sequentially forming a common source and a separation insulating layer so as to contact the exposed side surfaces of each of the above vertical channel structures; A step of forming a back gate wiring on the vertical channel structures so as to contact the back gate of each of the vertical channel structures; and A step of removing the sacrificial layers and forming gate electrodes in the spaces where the sacrificial layers have been removed. A method for manufacturing a back gate wiring including:

8. In paragraph 6, The above preparation steps are: A method for manufacturing a back gate wiring, characterized in that it is a step of preparing a semiconductor structure in which a capping film is formed in an area corresponding to the back gate among the exposed ends of each of the vertical channel structures.

9. In paragraph 7, The above preparation steps are: A method for manufacturing a back gate wiring, characterized in that it is a step of preparing a semiconductor structure in which a capping film is formed in an area corresponding to the back gate among the exposed ends of each of the vertical channel structures.

10. In either of paragraphs 8 or 9, The above capping film is, A method for manufacturing a back gate wiring, characterized in that the back gate wiring is formed with a material or composition different from that of the common source, in order to prevent an area corresponding to the back gate among the exposed ends of each of the vertical channel structures from being recessed together when a portion of the common source is recessed in the step of sequentially forming the common source and the separation insulating layer.

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