Temperature-stabilized thin-film resistor

Abstract

Provided herein is a temperature-stabilized thin-film resistor including a substrate; a bottom encapsulation or passivation layer on the substrate; a thin-film resistive layer on the bottom encapsulation or passivation layer; and a top encapsulation or passivation layer on the thin-film resistive layer.

Description

TEMPERATURE-STABILIZED THIN-FILM RESISTORCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application Serial No. 63 / 649,702, filed May 20, 2024, the entire contents of which are incorporated herein by reference.STATEMENT OF FEDERALLY FUNDED RESEARCH

[0002] None.TECHNICAL FIELD

[0003] The present invention relates in general to thin-film resistors, and particularly to temperature-stabilized thin-film resistors.BACKGROUND

[0004] Tantalum nitride (TaN) is often prepared as a thin film. Methods of depositing such films include RF-magnetron-reactive sputtering, direct current (DC) or RF sputtering, selfpropagating high-temperature synthesis (SHS) via “combustion” of tantalum powder in nitrogen, low-pressure metalorganic chemical-vapor deposition (LP-MOCVD), ion beam assisted deposition (IBAD), plasma-enhanced chemical-vapor deposition (PECVD), and by electron-beam evaporation of tantalum in concert with high-energy nitrogen ions.

[0005] Depending on the relative amount of N2, the deposited film can vary from TaN to hexagonal Ta?N as nitrogen decreases during the process of formation. A variety of tantalumnitrogen ratios can be formed in the deposition process. The electrical properties of TaN films vary from those of a metal to those of an insulator depending on the relative nitrogen ratio. A nitrogen-rich TaN film is more resistive.SUMMARY

[0006] As embodied and broadly described herein, an aspect of the present disclosure relates to a temperature-stabilized thin-film resistor comprising: a substrate; a bottom encapsulation or passivation layer on the substrate; a thin-film resistive layer on the bottom encapsulation or passivation layer; and a top encapsulation or passivation layer on the thin-film resistive layer. In one aspect, the substrate is selected from: a silicon substrate, and silicon-germanium-based substrate, a silicon-based integrated passive device substrate, a silicon-based laterally diffusedmetal-oxide-semiconductor substrate; a gallium nitride-based substrate, a glass substrate, a ceramic substrate, or a glass-ceramic composite substrate. In another aspect, the bottom encapsulation or passivation layer comprises a nonconductive inert or refractory material. In another aspect, the top encapsulation or passivation layer comprises a nonconductive inert or refractory material. In another aspect, the bottom, the top, or both the top and bottom encapsulation or passivation layers comprise a nonconductive inert, a refractory material, or combinations thereof. In another aspect, the nonconductive inert or refractory material layer comprises HfN, ZrN, or SiN. In another aspect, the thin film resistive layer comprises TaN, nichrome, or Ta. In another aspect, the bottom encapsulation or passivation layer thickness is from is 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A. In another aspect, the top encapsulation or passivation layer thickness is from 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A. In another aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 500°C. In another aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 600°C. In another aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 700°C. In another aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 800°C. In another aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 900°C. In another aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of l,000°C. In another aspect, the temperature-stabilized thin film resistor has no oxidation damage up a temperature of 1, 100°C. In another aspect, the temperature-stabilized thin-film resistor does not have defects, holes, or cracks. In another aspect, the encapsulation or passivation layer, the thin-film resistive layer, or a top encapsulation or passivation layer are deposited at standard cubic centimeter (seem) flow rates of SiTUHe of 150 to 200 seem; NH3 of 8 to 15 seem; He of 800 to 900 seem; and N2 of 500 to 600 seem). In another aspect, deposition conditions further comprise an RF power of 50 to 75 W and a pressure of 1200 to 1750 mTorr.

[0007] As embodied and broadly described herein, an aspect of the present disclosure relates to a method of making a temperature-stabilized thin-film resistor comprising: providing a substrate; depositing a bottom encapsulation or passivation layer on the substrate; depositing a thin-film resistive layer on the bottom encapsulation or passivation layer; and depositing a topencapsulation or passivation layer on the thin-film resistive layer. In one aspect, the substrate is selected from: a silicon substrate, and silicon-germanium-based substrate, a silicon-based integrated passive device substrate, a silicon-based laterally diffused metal-oxide- semiconductor substrate; a gallium nitride-based substrate, a glass substrate, a ceramic substrate, or a glass-ceramic composite substrate. In another aspect, the bottom or top encapsulation or passivation layers are deposited using an atomic layer deposition (ALD) process, RF-magnetron-reactive sputtering, direct current (DC) or RF sputtering, selfpropagating high-temperature synthesis (SHS) via “combustion” of tantalum powder in nitrogen, low-pressure metalorganic chemical-vapor deposition (LP-MOCVD), ion beam assisted deposition (IBAD), plasma-enhanced chemical-vapor deposition (PECVD), by electron-beam evaporation of tantalum in concert with high-energy nitrogen ions, chemicalvapor deposition (CVD), another commercially available processes, or some combination. In one aspect, the thin-film resistive layer is deposited using an atomic layer deposition (ALD) process, RF-magnetron-reactive sputtering, direct current (DC) or RF sputtering, selfpropagating high-temperature synthesis (SHS) via “combustion” of tantalum powder in nitrogen, low-pressure metalorganic chemical-vapor deposition (LP-MOCVD), ion beam assisted deposition (IBAD), plasma-enhanced chemical-vapor deposition (PECVD), by electron-beam evaporation of tantalum in concert with high-energy nitrogen ions, chemicalvapor deposition (CVD), another commercially available processes, or some combination. In one aspect, the bottom encapsulation or passivation layer thickness is from 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A. In one aspect, the top encapsulation or passivation layer thickness is from 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A. In one aspect, the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 500, 606, 700, 800, 900, 1,000, or 1,100 °C. In one aspect, the temperature-stabilized thin- film resistor does not have defects, holes, or cracks. In one aspect, the encapsulation or passivation layer, the thin-film resistive layer, or a top encapsulation or passivation layer are deposited at standard cubic centimeter (seem) flow rates of SiH4He of 150 to 200 seem; NH3 of 8 to 15 seem; He of 800 to 900 seem; and N2 of 500 to 600 seem). In one aspect, deposition conditions comprise an RF power of 50 to 75 W and a pressure of 1200 to 1750 mTorr.

[0008] As embodied and broadly described herein, an aspect of the present disclosure relates to a method of making a temperature-stabilized thin-film resistor comprising: depositing a thin film of a refractory material, then depositing a TaN thin film; patterning the TaN thin film using a photoresist pattern and etching using an Argon Ion milling process; covering the patterned TaN thin film with a top layer of the refractory thin film; patterning a photoresist on the top refractory thin film for contact vias; and etching to form contact vias with end point detection to prevent over etching past the TaN thin film. In one aspect, the method further comprises the step of forming the contact vias to make electrical connections to the temperature-stabilized thin-film resistor. In another aspect, the method further comprises the step of wired bonding or depositing a metal thin film to make electrical connections to the temperature-stabilized thin-film resistor.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the features and advantages of the present disclosure, reference is now made to the detailed description of the disclosure along with the accompanying figures and in which:

[0010] FIG. 1 shows a cross section of an encapsulation or passivation protected TaN thin-film resistor.

[0011] FIG. 2A shows a cross section of an encapsulation or passivation protected TaN thin- film resistor stack.

[0012] FIG. 2B shows holes and cracks in a top SiN layer of an encapsulation or passivation- protected TaN thin-film resistor stack.

[0013] FIG. 3A shows a cross section for an encapsulation or passivation protected TaN thin- film resistor stack.

[0014] FIG. 3B shows an encapsulation or passivation protected TaN thin-film resistor stack with no defects in a top SiN layer.

[0015] FIG. 4 shows a flowchart for a method embodiment of the present invention.

[0016] FIG. 5 shows another flowchart for a method embodiment of the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0017] While the making and using of various embodiments of the present disclosure are discussed in detail below, it should be appreciated that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the disclosure and do not delimit the scope of the invention.

[0018] To facilitate the understanding of this disclosure, a number of terms are defined below. Terms defined herein have meanings as commonly understood by a person of ordinary skill in the areas relevant to the present disclosure. Terms such as “a”, “an”, and “the” are not intended to refer to only a singular entity but include the general class of which a specific example may be used for illustration. The terminology herein is used to describe specific embodiments of the invention, but their usage does not delimit the invention, except as outlined in the claims.

[0019] In the specification, reference may be made to the spatial relationships between various components and to the spatial orientation of various aspects of components as the devices are depicted in the attached drawings. However, as will be recognized by those skilled in the art after a complete reading of the present application, the devices, members, apparatuses, etc. described herein may be positioned in any desired orientation. Thus, the use of terms such as “above,” “below,” “upper,” “lower,” or other like terms to describe a spatial relationship between various components or to describe the spatial orientation of aspects of such components should be understood to describe a relative relationship between the components or a spatial orientation of aspects of such components, respectively, as the device described herein may be oriented in any desired direction.

[0020] Prevention of oxidation of a thin-film resistive layer material requires the encapsulation or passivation of a thin-film resistive layer using a nonconductive inert or refractory material that prevents the exposure of the resistive layer material to oxygen while heated. Several refractory thin film materials can be used, such as silicon nitride (SiN), hafnium nitride (HfN), or zirconium nitride (ZrN). The refractory thin films can make excellent materials to encapsulate or passivate a thin-film resistive layer. In general, refractory thin films are accomplished by depositing a thin film of the refractory material, then depositing the thin-film resistive layer. The thin-film resistive layer is then patterned using a photoresist pattern and then etched using a milling process such as an argon-ion milling process. The patterned thin- film resistive layer is then covered with a top layer of the refractory thin film. The top refractory layer is then patterned using photoresist with contact vias opened using a milling process such as an argon-ion milling process with end-point detection to prevent over etching past the thin-film resistive layer. Electrical connection to the thin-film resistive layer can be made using standard wired bonding or metal thin-film processes. In optimizing the thickness of the encapsulation or passivation layers, reduced defects such as holes and cracks that reduce the effectiveness of the encapsulation or passivation layers have been seen in preliminary data.

[0021] FIG. 1 shows a cross section of an encapsulation or passivation protected TaN thin-film resistor. As used herein, an encapsulation layer and a passivation layer both serve as protective coatings, but with different primary purposes. An encapsulation layer is generally used to isolate the device from the external environment, while a passivation layer is generally used for improving the electrical and chemical properties of the semiconductor surface. In the embodiment of FIG. 1, a thin-film resistor 100 that includes a TaN resistive layer 101; two electrical contact and contact adhesion layers are depicted, a contact pad with adhesive layer 102 and a resistor contact with adhesion layer 105; encapsulation or passivation layers 103, one on each side of the TaN thin-film resistive layer 101, and a substrate 104. The thin-film resistive layer 101 generally includes, e.g., the nickel -chromium alloy nichrome, tantalum nitride (TaN), or tantalum (Ta) metal. Each thin-film resistive layer material has a unique oxidation potential that determines its application environment and use. The encapsulation or passivation layers 103 generally include, e.g., silicon nitride (SiN), hafnium nitride (HfN), or zirconium nitride (ZrN). In this embodiment, the encapsulation or passivation layers 103 are deposited via plasma enhanced chemical vapor deposition (PECVD), which when heated above 500 °C, release presumed hydrogen in the encapsulation or passivation layers 103, and cause defects such as holes or cracks.

[0022] FIG. 2A shows an embodiment of the present invention, a thin-film resistor 200, which includes thin-film resistive layer 205, SiN encapsulation or passivation layers 204 and 206, and substrate 207, which can be ceramic, e.g., a ceramic wafer. The top encapsulation or passivation layer 204 shown in FIG. 2B is a photograph that shows multiple holes 208 and cracks 209. The thin-film resistive material of layer 205 can be selected from, e.g., TaN, the nickel-chromium alloy nichrome, or tantalum (Ta).

[0023] FIG. 3A shows a cross-section of an embodiment of the present invention, a thin-film resistor 300, which includes, the top encapsulation or passivation layer 304, the encapsulated or passivated resistive layer 305, the bottom encapsulation or passivation layer 306, and the substrate 307. The encapsulation or passivation layers 304 and 306 can include, e.g., HfN, ZrN, or SiN. The thin-film resistive material of resistive layer 305 can be selected from, e.g., TaN, nichrome, or tantalum, FIG. 3B the top encapsulation or passivation layer 304 with no defects. The encapsulated or passivated layers 304 and 306 can vary in thickness from 50, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, or 20,000 A as long as they are dense and defect-free. Thinner layers can be created by use of, e.g., an atomic layer deposition (ALD) process. Thethicker layers can easily be produced by RF sputtering; PECVD, CVD, or other commercially available processes. A non-limiting example embodiment of the present invention was created using a plasma-therm PECVD tool, where the deposition conditions include a lid temperature of 200° C and an electrode temperature of 300° C. The skilled artisan will recognize that the lid temperature may vary depending on the material used from the thickness of the encapsulation / passivation layer identified as element 103, can vary 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15%. The deposition conditions also include these deposition gases at standard cubic centimeter (seem) flow rates of SiEUEle at 150 to 200 seem (e.g., 200 seem); NH3 at 8 to 15 seem (e.g., 12 seem); He at 800 to 900 seem (e.g., 840 seem); and N2 at 500 to 600 seem (e.g., 550 seem). The deposition conditions further include RF power of 50 to 75 W (e.g., 65 W) and a pressure of 1200 to 1750 mTorr (e.g., 1500 mTorr). These conditions resulted in a deposition rate for the SiN layer of 220 ± 10 A / min.

[0024] FIG. 4 shows a flowchart of a method 400, for making a temperature-stabilized thin- film resistor, e.g, temperature-stabilized thin film resistor 300. Method 400 includes block 405, depositing a thin film of a refractory material, then depositing a TaN thin film. Method 400 also includes block 410, patterning the TaN thin film using a photoresist pattern and etching using an Argon Ion milling process, and block 415, covering the patterned TaN thin film with a top layer of the refractory thin film. In addition, method 400 includes block 420, patterning a photoresist on the top refractory thin film for contact vias, and block 425, etching to form contact vias with end point detection to prevent over etching past the TaN thin film.

[0025] TaN thin films can be fabricated by using reactive RF (13.56MHz) magnetron sputtering deposition technique on a Denton Vacuum Discovery- 18 Deposition System with a 3 -inch-diameter tantalum target of a purity of 99.95%. Amorphous glass and wafers have been used as substrates. The substrates were cleaned prior to the deposition in a sequence of acetone, distilled water, and ethanol in an ultrasonic bath for 15, 5, and 15 minutes, respectively. For each deposition, 2-3 pieces of glass substrates and 6-8 pieces of other types of substrates were mounted on a copper substrate stage at a distance of 8-14 cm from the target surface. During deposition, the substrate stage was rotated at 9 RPM to obtain homogeneous film quality and thickness. The system was first pumped to 8xl0'7torr in about 5 hours. Then a mixture of pure N2 gas of purity 99.9995% was induced in the deposition chamber by using mass flow controllers. The total processing ambient gas pressure was kept at 5.0 mtorr for all the films, in an N2 partial pressure. The rf power was kept at 200 W, corresponding to a power density of 4.3 W / cm2on the target surface. Each film was deposited for up to 60 minutes. The deposited TaN material did not undergo any post annealing process. As-deposited TaN films weremeasured by using various characterization techniques including scanning electron microscope (SEM), and a four-probe method to measure the sheet resistance. TaN films grown on glass substrates with a deposition rate of about 8 nm / min, with a 1.0 % partial pressure of N2 had a thickness ranging from 50A to 10,000A. In general, a TaN resistor will have a sheet resistance of about 50 Q / sq.

[0026] TaN will oxidize above 50°C in ambient air. This has been reported by Cabrera-Mott et. al. Oxidation of TaN films at 250-350 °C follows a quartic time law with an oxidation activation energy of 1.45 eV. Long-term exposure of a TaN material 125 °C to 175 °C in air causes further oxidation and resistance changes with an activation energy of about 1.25 eV. A TaN resistor will oxidize when exposed to heat in air or when it is heated while it has direct intimate contact with a surface or substrate that allows the transfer or release of oxygen over temperature cycling. Most TaN thin-film resistors range between 50 A and 200 A in thickness, where modest oxidation can dramatically change the resistance of the TaN thin-film resistor.

[0027] In embodiments of the present invention the substrate, such as substrate 307, may be selected from: a silicon substrate, and silicon-germanium-based substrate, a silicon-based integrated passive device substrate, a silicon-based laterally diffused metal-oxide- semiconductor substrate; a gallium nitride-based substrate, a glass substrate, a ceramic substrate, or a glass-ceramic composite substrate.

[0028] FIG. 5 shows a flowchart of another method 500 for making a temperature-stabilized thin-film resistor, e.g., the temperature-stabilized thin-film resistor 300. The method 500 includes block 505, providing a substrate, and block 510, depositing a bottom encapsulation or passivation layer on the substrate, Method 400 also includes block 515, depositing a thin-film resistive layer on the bottom encapsulation or passivation layer, and block 520, depositing a top encapsulation or passivation layer on the thin-film resistive layer.

[0029] It is contemplated that any aspects of the disclosure discussed in this specification can be implemented with respect to any method, kit, reagent, or composition of the disclosure, and vice versa. Furthermore, compositions of the disclosure can be used to achieve methods of the disclosure.

[0030] It will be understood that particular aspects described herein are shown by way of illustration and not as limitations of the disclosure. The principal features of this disclosure can be employed in various aspects without departing from the scope of the disclosure. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Suchequivalents are considered to be within the scope of this disclosure and are covered by the claims.

[0031] All publications and patent applications mentioned in the specification are indicative of the level of skill of those skilled in the art to which this disclosure pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

[0032] The use of the word “a” or “an” when used in conjunction with the term “comprising” in the claims and / or the specification may mean “one,” but it is also consistent with the meaning of “one or more,” “at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and / or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and / or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

[0033] As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “includes” and “include”) or “containing” (and any form of containing, such as “contains” and “contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In aspects of any of the compositions and methods provided herein, “comprising” may be replaced with “consisting essentially of’ or “consisting of’. As used herein, the phrase “consisting essentially of’ requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention. As used herein, the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method / process step or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), propertie(s), method / process steps or limitation(s)) only.

[0034] The term “or combinations thereof’ as used herein refers to all permutations and combinations of the listed items preceding the term. For example, “A, B, C, or combinations thereof’ is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of oneor more item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CAB ABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.

[0035] As used herein, words of approximation such as, without limitation, “about”, "substantial" or "substantially" refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present. The extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skilled in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature. In general, but subject to the preceding discussion, a numerical value herein that is modified by a word of approximation such as “about” may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.

[0036] Additionally, the section headings herein are provided for consistency with the suggestions under 37 CFR 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the disclosure(s) set out in any claims that may issue from this disclosure. Specifically, and by way of example, although the headings refer to a “Field of Invention,” such claims should not be limited by the language under this heading to describe the so-called technical field. Further, a description of technology in the “Background” section is not to be construed as an admission that technology is prior art to any disclosure(s) in this disclosure. Neither is the “Summary” to be considered a characterization of the disclosure(s) set forth in issued claims. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure but should not be constrained by the headings set forth herein.

[0037] All of the compositions and / or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the compositions and methods of this disclosure have been described in terms of preferred aspects, it will be apparent to those of skill in the art that variations may be applied to the compositions and / or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the disclosure. All such similarsubstitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the disclosure as defined by the appended claims.

[0038] To aid the Patent Office, and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims to invoke paragraph 6 of 35 U.S.C. § 112, U.S.C. § 112 paragraph (f), or equivalent, as it exists on the date of filing hereof unless the words “means for” or “step for” are explicitly used in the particular claim.

[0039] For each of the claims, each dependent claim can depend both from the independent claim and from each of the prior dependent claims for each and every claim so long as the prior claim provides a proper antecedent basis for a claim term or element.

Claims

What is claimed is:

1. A temperature-stabilized thin-film resistor comprising: a substrate; a bottom encapsulation or passivation layer on the substrate; a thin-film resistive layer on the bottom encapsulation or passivation layer; and a top encapsulation or passivation layer on the thin-film resistive layer.

2. The temperature-stabilized thin-film resistor of claim 1, wherein the substrate is selected from: a silicon substrate, and silicon-germanium-based substrate, a silicon-based integrated passive device substrate, a silicon-based laterally diffused metal -oxide- semiconductor substrate; a gallium nitride-based substrate, a glass substrate, a ceramic substrate, or a glass-ceramic composite substrate.

3. The temperature-stabilized thin-film resistor of claim 1, wherein the bottom, the top, or both the top and bottom encapsulation or passivation layers comprise a nonconductive inert, a refractory material, or combinations thereof.

4. The temperature-stabilized thin-film resistor of claim 3, wherein the nonconductive inert or refractory material layer comprises HfN, ZrN, or SiN.

5. The temperature-stabilized thin-film resistor of claim 1, wherein the thin-film resistive layer comprises TaN, nichrome, or Ta.

6. The temperature-stabilized thin-film resistor of claim 1, wherein the bottom encapsulation or passivation layer thickness is from 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A.

7. The temperature-stabilized thin-film resistor of claim 1, wherein the top encapsulation or passivation layer thickness is from is 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A.

8. The temperature-stabilized thin-film resistor of claim 1, wherein the temperature- stabilized thin-film resistor has no oxidation damage up a temperature of 500, 606, 700,800, 900, 1,000, or 1,100 °C.

9. The temperature-stabilized thin-film resistor of claim 1, wherein the temperature- stabilized thin-film resistor does not have defects, holes, or cracks.

10. The temperature-stabilized thin-film resistor of claim 1, wherein the bottom encapsulation or passivation layer, the thin-film resistive layer, or a top encapsulation or passivation layer are deposited at standard cubic centimeter (seem) flow rates of SikkHe of 150 to 200 seem; NH3 of 8 to 15 seem; He of 800 to 900 seem; and N2 of 500 to 600 seem).

11. The temperature-stabilized thin-film resistor of claim 1, wherein deposition conditions further comprise an RF power of 50 to 75 W and a pressure of 1200 to 1750 mTorr.

12. A method of making a temperature-stabilized thin-film resistor comprising: providing a substrate; depositing a bottom encapsulation or passivation layer on the substrate; depositing a thin-film resistive layer on the bottom encapsulation or passivation layer; and depositing a top encapsulation or passivation layer on the thin-film resistive layer.

13. The method of claim 12, wherein the substrate is selected from: a silicon substrate, and silicon-germanium-based substrate, a silicon-based integrated passive device substrate, a silicon-based laterally diffused metal -oxide-semiconductor substrate; a gallium nitridebased substrate, a glass substrate, a ceramic substrate, or a glass-ceramic composite substrate.

14. The method of claim 12, wherein the bottom or top encapsulation or passivation layers are deposited using an atomic layer deposition (ALD) process, RF-magnetron- reactive sputtering, direct current (DC) or RF sputtering, self-propagating high-temperature synthesis (SHS) via “combustion” of tantalum powder in nitrogen, low-pressure metalorganic chemical-vapor deposition (LP-MOCVD), ion beam assisted deposition (IBAD), plasma-enhanced chemical-vapor deposition (PECVD), by electron-beam evaporation of tantalum in concert with high-energy nitrogen ions, chemical-vapor deposition (CVD), another commercially available processes, or some combination.

15. The method of claim 12, wherein the thin-film resistive layer is deposited using anatomic layer deposition (ALD) process, RF-magnetron-reactive sputtering, direct current (DC) or RF sputtering, self-propagating high-temperature synthesis (SHS) via “combustion” of tantalum powder in nitrogen, low-pressure metalorganic chemical-vapor deposition (LP-MOCVD), ion beam assisted deposition (IB AD), plasma-enhanced chemical-vapor deposition (PECVD), by electron-beam evaporation of tantalum in concert with high-energy nitrogen ions, chemical-vapor deposition (CVD), another commercially available processes, or some combination.

16. The method of claim 12, wherein the bottom encapsulation or passivation layer thickness is from 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A.

17. The method of claim 12, wherein the top encapsulation or passivation layer thickness is from 50 A, 75, 100, 200, 250, 300, 400, 500, 600, 700, 750, 800, 900, 1,000, 2,000, 2,500, 3,000, 4,000, 5,000, 6,000, 7,000, 7,500, 8,000, 9,000, 10,000, 11,000, 12,000, 12,500, 13,000, 14,000, 15,000, 16,000, 17,000, 17,500, 18,000, 19,000, to 20,000 A.

18. The method of claim 12, wherein the temperature-stabilized thin-film resistor has no oxidation damage up a temperature of 500, 606, 700, 800, 900, 1,000, or 1,100 °C.

19. The method of claim 12, wherein the temperature-stabilized thin-film resistor does not have defects, holes, or cracks.

20. The method of claim 12, wherein the encapsulation or passivation layer, the thin- film resistive layer, or a top encapsulation or passivation layer are deposited at standard cubic centimeter (seem) flow rates of SiFUHe of 150 to 200 seem; NH3 of 8 to 15 seem; He of 800 to 900 seem; and N2 of 500 to 600 seem).

21. The method of claim 12, wherein deposition conditions comprise an RF power of 50 to 75 W and a pressure of 1200 to 1750 mTorr.

22. A method of making a temperature-stabilized thin-film resistor comprising: depositing a thin film of a refractory material, then depositing a TaN thin film; patterning the TaN thin film using a photoresist pattern and etching using an Argon Ion milling process;covering the patterned TaN thin film with a top layer of the refractory thin film; patterning a photoresist on the top refractory thin film for contact vias; and etching to form contact vias with end point detection to prevent over etching past theTaN thin film.

23. The method of claim 22, further comprising the step of forming the contact vias to make electrical connections to the temperature-stabilized thin-film resistor.

24. The method of claim 22, further comprising the step of wired bonding or depositing a metal thin film to make electrical connections to the temperature-stabilized thin-film resistor.

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