Shift register unit and driving method therefor, and gate driver on array circuit and display apparatus

Abstract

A shift register unit and a driving method therefor, and a gate driver on array circuit and a display apparatus. In the shift register unit, in response to the potentials of a first node (Q) and a second node (QB), a second output circuit (03) can control a first power supply terminal (VGH) or a reference clock terminal (CKC) to output a signal to a redundant output terminal (GD); and the second output circuit (03) comprises a capacitor (C1) coupled between the second node (QB) and the redundant output terminal (GD), and under the coupling effect of the capacitor (C1), the second output circuit (03) can adjust the potential of the first node (Q) on the basis of the potential of the redundant output terminal (GD). Therefore, it can be ensured that the potential of the first node (Q) remains stable, such that a third output circuit (04) reliably outputs a signal to a scan output terminal (G‹N›) in response to the potential of the first node (Q) and the potential of the second node (QB), thereby reliably driving pixels to emit light and accordingly ensuring a better display effect of a display panel.

Description

Shift register unit and its driving method, gate driving circuit, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit and its driving method, gate driving circuit, and display device. Background Technology

[0002] Currently, gate driver circuits can be integrated onto the display panel using gate driver on array (GOA) technology, which facilitates narrow bezel designs for display devices. Correspondingly, the gate driver circuit is also called a GOA circuit.

[0003] In related technologies, a GOA circuit typically includes multiple cascaded GOA units, each of which includes an input circuit and an output circuit. The input circuit is coupled to the input clock terminal, the input signal terminal, and the driving node, respectively, and is used to control the on / off state of the input signal terminal and the driving node in response to the clock signal provided by the input clock terminal, thereby controlling the potential of the driving node. The output circuit is coupled to the driving node, the output power supply terminal, the output clock terminal, and the output signal terminal, respectively, and is used to control the on / off state of either the output power supply terminal or the output clock terminal and the output signal terminal based on the potential of the driving node, so as to output a gate drive signal to the pixels in the display panel via the output signal terminal, thereby driving the pixels to emit light and driving the display panel to display an image.

[0004] However, due to factors such as leakage, the potential of the driving node cannot remain stable, which in turn causes the output circuit to fail to reliably output signals, thus failing to reliably drive the pixels to emit light, resulting in poor display effect of the display panel.

[0005] Summary of the Invention

[0006] A shift register unit and its driving method, a light-emitting driving circuit, and a display device are provided. The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] The input circuit is coupled to a first clock terminal, a second clock terminal, a first input terminal, a first node, and a second node, respectively, and is used to control the potential of the first node and the potential of the second node based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, and the first input signal provided by the first input terminal.

[0009] A first output circuit is coupled to the first node, the second node, the second clock terminal, the first power supply terminal, and the shift output terminal, respectively, and is used to control the on / off state of the second clock terminal and the shift output terminal in response to the potential of the first node, and to control the on / off state of the first power supply terminal and the shift output terminal in response to the potential of the second node; wherein, the shift output terminal is used to be coupled to the first input terminal of another cascaded shift register unit;

[0010] The second output circuit is coupled to the first control node, the second node, the first power supply terminal, the reference clock terminal, and the redundant output terminal, respectively. It is used to control the switching between the first power supply terminal and the redundant output terminal in response to the potential of the first control node, and to control the switching between the reference clock terminal and the redundant output terminal in response to the potential of the second node. It also includes a first capacitor coupled between the second node and the redundant output terminal. The first control node is either the first node itself or coupled to the shift output terminal.

[0011] The third output circuit is coupled to the second control node, the second node, the third clock terminal, the second power supply terminal, and the scan output terminal, respectively, and is used to control the on / off state of the third clock terminal and the scan output terminal in response to the potential of the second control node, and to control the on / off state of the second power supply terminal and the scan output terminal in response to the potential of the second node; wherein, the scan output terminal is used to be coupled to a pixel in the display panel, and the second control node is the first node or coupled to the shift output terminal.

[0012] Optionally, the reference clock terminal is shared with the first clock terminal;

[0013] Alternatively, the reference clock terminal may be shared with the second clock terminal.

[0014] Alternatively, the reference clock terminal is independent of both the first clock terminal and the second clock terminal, and the transition edge of the reference clock signal provided by the reference clock terminal from the second potential to the first potential is located after the transition edge of the second clock signal provided by the second clock terminal from the second potential to the first potential.

[0015] Optionally, the first node includes: a first sub-node and a second sub-node; the input circuit is coupled to the first sub-node, the first output circuit is coupled to the second sub-node, the first control node is either the first sub-node or the second sub-node, and the second control node is either the first sub-node or the second sub-node; the shift register unit further includes:

[0016] A first control circuit is coupled to a third power supply terminal, the first sub-node, and the second sub-node, respectively, and is used to control the on / off state of the first sub-node and the second sub-node in response to a third power supply signal provided by the third power supply terminal.

[0017] Optionally, the first control circuit includes: a first transistor;

[0018] The gate of the first transistor is coupled to the third power supply terminal, the first electrode of the first transistor is coupled to the first sub-node, and the second electrode of the first transistor is coupled to the second sub-node.

[0019] Optionally, the second node includes a third child node and a fourth child node; the input circuit and the first output circuit are both coupled to the third child node, and the second output circuit and the third output circuit are both coupled to the fourth child node; the shift register unit further includes:

[0020] The second control circuit is coupled to the third power supply terminal, the third sub-node, and the fourth sub-node respectively, and is used to control the on / off state of the third sub-node and the fourth sub-node in response to the third power supply signal provided by the third power supply terminal.

[0021] Optionally, the second control circuit includes: a second transistor;

[0022] The gate of the second transistor is coupled to the third power supply terminal, the first terminal of the second transistor is coupled to the third sub-node, and the second terminal of the second transistor is coupled to the fourth sub-node.

[0023] Optionally, the second control circuit includes two second transistors connected in series;

[0024] The gates of both second transistors are coupled to the third power supply terminal, the first terminals of the two second transistors are coupled to the third sub-node and the fourth sub-node respectively, and the second terminals of the two second transistors are coupled to the series node; the shift register unit further includes:

[0025] The leakage protection circuit is coupled to the fourth sub-node, the fourth power supply terminal and the series node respectively, and is used to control the on / off state of the fourth power supply terminal and the series node in response to the potential of the fourth sub-node.

[0026] Optionally, the leakage protection circuit includes: a third transistor;

[0027] The gate of the third transistor is coupled to the fourth sub-node, the first terminal of the third transistor is coupled to the fourth power supply terminal, and the second terminal of the third transistor is coupled to the series node.

[0028] Optionally, the second control circuit is also coupled to the first node and is also used to control the on / off state of the third sub-node and the fourth sub-node in response to the third power signal and the potential of the first node.

[0029] Optionally, the second control circuit includes two second transistors connected in series;

[0030] The gates of the two second transistors are respectively coupled to the third power supply terminal and the first node, the first terminals of the two second transistors are respectively coupled to the third sub-node and the fourth sub-node, and the second terminals of the two second transistors are coupled together.

[0031] Optionally, any one of the first control node and the second control node includes: a first control sub-node and a second control sub-node; the first control sub-node is the first node or coupled to the shift output terminal; when either control node is the second control node, the third output circuit is coupled to the second control sub-node; when either control node is both the first control node and the second control node, both the second output circuit and the third output circuit are coupled to the second control sub-node; the shift register unit further includes:

[0032] The third control circuit is coupled to the third power supply terminal, the first control sub-node, and the second control sub-node respectively, and is used to control the on / off state of the first control sub-node and the second control sub-node in response to the third power supply signal provided by the third power supply terminal.

[0033] Optionally, the third control circuit includes: a fourth transistor;

[0034] The gate of the fourth transistor is coupled to the third power supply terminal, the first terminal of the fourth transistor is coupled to the first control sub-node, and the second terminal of the fourth transistor is coupled to the second control sub-node.

[0035] Optionally, the second node includes a third child node and a fifth child node; the input circuit, the first output circuit, and the third output circuit are all coupled to the third child node, and the second output circuit is coupled to the fifth child node; the shift register unit further includes:

[0036] The fourth control circuit is coupled to the third power supply terminal, the third sub-node, and the fifth sub-node respectively, and is used to control the on / off state of the third sub-node and the fifth sub-node in response to the third power supply signal provided by the third power supply terminal, and to control the on / off state of the third sub-node and the fifth sub-node in response to the potential of the fifth sub-node.

[0037] Optionally, the fourth control circuit includes a fifth transistor and a sixth transistor;

[0038] The gate of the fifth transistor is coupled to the third power supply terminal, the first terminal of the fifth transistor is coupled to the third sub-node, and the second terminal of the fifth transistor is coupled to the fifth sub-node;

[0039] The gate and second terminal of the sixth transistor are both coupled to the fifth sub-node, and the first terminal of the sixth transistor is coupled to the third sub-node.

[0040] Optionally, the input circuit includes:

[0041] The first input sub-circuit is coupled to the first clock terminal, the first input terminal, the first node, the second node, the second clock terminal, and the first power supply terminal, respectively, and is used to control the on / off state of the first input terminal and the first node in response to the first clock signal, and to control the on / off state of the first power supply terminal and the first node in response to the potential of the second node and the second clock signal, so as to control the potential of the first node.

[0042] The second input sub-circuit is coupled to the input control terminal, the second input terminal, the first node, and the second node, respectively, and is used to control the on / off state of the second input terminal and the second node in response to the input control signal provided by the input control terminal, and to control the on / off state of the input control terminal and the second node in response to the potential of the first node, so as to control the potential of the second node; wherein the input control terminal and the second input terminal are respectively the first power supply terminal and the second clock terminal; or, the input control terminal and the second input terminal are respectively the first clock terminal and the third power supply terminal.

[0043] Optionally, the first input sub-circuit includes a seventh transistor, an eighth transistor, and a ninth transistor; the second input sub-circuit includes a tenth transistor and an eleventh transistor.

[0044] The gate of the seventh transistor is coupled to the first clock terminal, the first terminal of the seventh transistor is coupled to the first input terminal, and the second terminal of the seventh transistor is coupled to the first node.

[0045] The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the first power supply terminal, and the second terminal of the eighth transistor is coupled to the first terminal of the ninth transistor.

[0046] The gate of the ninth transistor is coupled to the second clock terminal, and the second terminal of the ninth transistor is coupled to the first node;

[0047] The gate of the tenth transistor is coupled to the input control terminal, the first terminal of the tenth transistor is coupled to the second input terminal, and the second terminal of the tenth transistor is coupled to the second node;

[0048] The gate of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the input control terminal, and the second electrode of the eleventh transistor is coupled to the second node.

[0049] Optionally, when the input control terminal and the second input terminal are respectively the first power supply terminal and the second clock terminal, the second input sub-circuit further includes a second capacitor coupled between the second input terminal and the input control terminal, and the shift register unit further includes:

[0050] The fifth control circuit is coupled to the first node, the input control terminal and the second input sub-circuit respectively, and is used to control the on / off state of the input control terminal and the second input sub-circuit in response to the potential of the first node.

[0051] Optionally, the fifth control circuit includes: a twelfth transistor;

[0052] The gate of the twelfth transistor is coupled to the first node, the first terminal of the twelfth transistor is coupled to the input control terminal, and the second terminal of the twelfth transistor is coupled to the second input sub-circuit.

[0053] Optionally, the second node includes a third sub-node and a sixth sub-node; the first input sub-circuit, the second input sub-circuit, the first output circuit, and the third output circuit are all coupled to the third sub-node, and the fourth control circuit included in the shift register unit is coupled to the sixth sub-node; the input circuit further includes:

[0054] The third input sub-circuit is coupled to the input control terminal, the second input terminal, the first node, and the sixth sub-node, respectively, and is used to control the on / off state of the second input terminal and the sixth sub-node in response to the input control signal, and to control the on / off state of the input control terminal and the sixth sub-node in response to the potential of the first node.

[0055] Optionally, the third input sub-circuit includes: a thirteenth transistor and a fourteenth transistor;

[0056] The gate of the thirteenth transistor is coupled to the input control terminal, the first terminal of the thirteenth transistor is coupled to the second input terminal, and the second terminal of the thirteenth transistor is coupled to the second node;

[0057] The gate of the fourteenth transistor is coupled to the first node, the first terminal of the fourteenth transistor is coupled to the input control terminal, and the second terminal of the fourteenth transistor is coupled to the second node.

[0058] Optionally, the first output circuit includes: a fifteenth transistor, a sixteenth transistor, and a third capacitor; the second output circuit includes: a seventeenth transistor, an eighteenth transistor, and a third capacitor; and the third output circuit includes: a nineteenth transistor and a twentieth transistor.

[0059] The gate of the fifteenth transistor is coupled to the first node, the first terminal of the fifteenth transistor is coupled to the second clock terminal, and the second terminal of the fifteenth transistor is coupled to the shift output terminal.

[0060] The gate of the sixteenth transistor is coupled to the second node, the first terminal of the sixteenth transistor is coupled to the first power supply terminal, and the second terminal of the sixteenth transistor is coupled to the shift output terminal.

[0061] The third capacitor is coupled between the first node and the shift output terminal;

[0062] The gate of the seventeenth transistor is coupled to the first control node, the first terminal of the seventeenth transistor is coupled to the first power supply terminal, and the second terminal of the seventeenth transistor is coupled to the redundant output terminal.

[0063] The gate of the eighteenth transistor is coupled to the second node, the first terminal of the eighteenth transistor is coupled to the reference clock terminal, and the second terminal of the eighteenth transistor is coupled to the redundant output terminal.

[0064] The gate of the nineteenth transistor is coupled to the second control node, the first terminal of the nineteenth transistor is coupled to the third clock terminal, and the second terminal of the nineteenth transistor is coupled to the scan output terminal.

[0065] The gate of the twentieth transistor is coupled to the second node, the first terminal of the twentieth transistor is coupled to the second power supply terminal, and the second terminal of the twentieth transistor is coupled to the scan output terminal.

[0066] Optionally, the shift register unit includes P-type transistors, and the scan output terminal is used to couple to the N-type transistor in the pixel via a gate line.

[0067] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect, the method comprising:

[0068] In the first stage, the input circuit controls the potential of the first node to the first potential and the potential of the second node to the second potential based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, and the first input signal provided by the first input terminal. The first output circuit responds to the potential of the first node by controlling the second clock terminal to conduct with the shift output terminal. The second output circuit responds to the potential of the first control node by controlling the first power supply terminal to conduct with the redundant output terminal. The third output circuit responds to the potential of the second control node by controlling the third clock terminal to conduct with the scan output terminal.

[0069] In the second stage, the input circuit controls the potential of the first node to the second potential and the potential of the second node to the first potential based on the first clock signal, the second clock signal, and the first input signal. The first output circuit responds to the potential of the second node by controlling the first power supply terminal to be connected to the shift output terminal. The second output circuit responds to the potential of the second node by controlling the reference clock terminal to be connected to the redundant output terminal and adjusts the potential of the second node based on the potential of the redundant output terminal through coupling. The third output circuit responds to the potential of the second node by controlling the second power supply terminal to be connected to the scan output terminal.

[0070] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: at least two cascaded shift register units as described in the preceding aspect.

[0071] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in yet another aspect above, the display panel comprising a plurality of pixels;

[0072] The gate driving circuit is coupled to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure;

[0075] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0076] Figure 3 is a schematic diagram of the structure of another shift register unit provided in an embodiment of this disclosure;

[0077] Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0078] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0079] Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0080] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0081] Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0082] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0083] Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0084] Figure 11 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0085] Figure 12 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0086] Figure 13 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure;

[0087] Figure 14 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0088] Figure 15 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0089] Figure 16 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0090] Figure 17 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0091] Figure 18 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0092] Figure 19 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0093] Figure 20 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0094] Figure 21 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0095] Figure 22 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0096] Figure 23 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0097] Figure 24 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0098] Figure 25 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0099] Figure 26 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0100] Figure 27 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0101] Figure 28 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0102] Figure 29 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0103] Figure 30 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0104] Figure 31 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0105] Figure 32 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0106] Figure 33 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0107] Figure 34 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0108] Figure 35 is a schematic flowchart of a driving method for a shift register unit provided in an embodiment of this disclosure;

[0109] Figure 36 is a signal timing diagram of a shift register unit provided in an embodiment of this disclosure;

[0110] Figure 37 is a signal timing simulation diagram of a shift register unit based on Figure 36;

[0111] Figure 38 is a signal timing diagram of another shift register unit based on the structure shown in Figure 13;

[0112] Figure 39 is a signal timing diagram of another shift register unit based on the structure shown in Figure 14;

[0113] Figure 40 is a signal timing diagram of another shift register unit based on the structure shown in Figure 15;

[0114] Figure 41 is a signal timing simulation diagram of another shift register unit based on the structure shown in Figure 13;

[0115] Figure 42 is a signal timing simulation diagram of another shift register unit based on the structure shown in Figure 15;

[0116] Figure 43 is a signal timing diagram of another shift register unit based on the structure shown in Figure 19;

[0117] Figure 44 is a signal timing diagram of another shift register unit based on the structure shown in Figure 21;

[0118] Figure 45 is a signal timing diagram of another shift register unit based on the structure shown in Figure 23;

[0119] Figure 46 is a signal timing simulation diagram of another shift register unit based on the structure shown in Figure 23;

[0120] Figure 47 is a schematic diagram of a gate driving circuit provided in an embodiment of this disclosure;

[0121] Figure 48 is a schematic diagram of another gate driving circuit provided in an embodiment of this disclosure;

[0122] Figure 49 is a schematic diagram of another gate driving circuit provided in an embodiment of this disclosure;

[0123] Figure 50 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0124] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0125] It is understood that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include either P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high; an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. Also, multiple signals in various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two states and do not represent that the first potential or the second potential has a specific value throughout the text.

[0126] In the display field, especially in displays using organic light-emitting diodes (OLEDs), the development of low-temperature polycrystalline oxide (LTPO+) is becoming increasingly urgent. Specifically, considering narrow bezel designs, LTPS materials are often used to fabricate the GOA (Gateway Assembly) circuit, while oxide materials are often used to fabricate the pixel circuits within the pixels. It's understood that this refers to the fabrication of transistors within the circuitry. LTPS transistors are typically P-type transistors, while oxide transistors are typically N-type transistors. Therefore, it is crucial to ensure that the P-type transistors in the GOA circuit output a high-potential positive shift voltage to the N-type transistors in the pixel, and equally important to maintain a stable low-potential signal waveform from the P-type transistors in the GOA circuit to the pixel for reliable noise reduction.

[0127] Optionally, the light-emitting device can be selected according to actual needs, and is not limited to the OLED described above. For example, in some embodiments, the light-emitting device can also be a quantum dot light-emitting diode (QLED) or a micro light-emitting diode (Micro LED), etc. The embodiments of this disclosure do not limit the structure of the light-emitting device.

[0128] Based on this, the present disclosure provides a shift register unit that can stably output signals to pixels. As shown in FIG1, the shift register unit includes: an input circuit 01, a first output circuit 02, a second output circuit 03, and a third output circuit 04.

[0129] The input circuit 01 is coupled to the first clock terminal CKA, the second clock terminal CKB, the first input terminal IN1, the first node Q, and the second node QB. The input circuit 01 is used to control the potential of the first node Q and the potential of the second node QB based on the first clock signal provided by the first clock terminal CKA, the second clock signal provided by the second clock terminal CKB, and the first input signal provided by the first input terminal IN1.

[0130] For example, input circuit 01 can control the potential of the first node Q to be the first potential and the potential of the second node QB to be the second potential when the potential of the first clock signal provided by the first clock terminal CKA is the first potential, the potential of the second clock signal provided by the second clock terminal CKB is the second potential, and the potential of the first input signal provided by the first input terminal IN1 is the first potential. Also, input circuit 01 can control the potential of the first node Q to be the second potential and the potential of the second node QB to be the first potential when the potential of the first clock signal provided by the first clock terminal CKA is the first potential, the potential of the second clock signal provided by the second clock terminal CKB is the second potential, and the potential of the first input signal provided by the first input terminal IN1 is the second potential. That is, during the same time period, input circuit 01 can control the potential of the first node Q and the potential of the second node QB to be different.

[0131] Optionally, in this embodiment of the disclosure, the first potential can be an effective potential, the second potential can be an ineffective potential, and the first potential can be a lower potential relative to the second potential; that is, the first potential of the effective potential can be a lower potential, and the second potential of the ineffective potential can be a higher potential. Of course, in some other embodiments, the first potential can also be a higher potential relative to the second potential.

[0132] The first output circuit 02 is connected to the first node Q, the second node QB, the second clock terminal CKB, the first power supply terminal VGH, and the shift output terminal CR, respectively. <n>Coupling. The first output circuit 02 is used to control the second clock terminal CKB and the shift output terminal CR in response to the potential of the first node Q. <n>The switching on and off of the circuit, in response to the potential of the second node QB, controls the connection between the first power supply terminal VGH and the shift output terminal CR. <n>The on / off state.

[0133] Among them, the shift output terminal CR <n>The first input terminal IN1 is used to couple with another cascaded shift register unit to drive the other cascaded shift register unit. However, referring to Figure 1, for the first-stage shift register unit, since there are no cascaded shift register units, its first input terminal IN1 can be coupled to a separate enable signal terminal STV to receive the enable signal provided by STV and operate under the drive of that enable signal. Correspondingly, the first output circuit 02 can also be called a cascaded output circuit.

[0134] Understandable, <n>This refers to the Nth level shift register unit, where N can be an integer greater than or equal to 1 and less than or equal to the total number of shift register levels. The following embodiments will not be described in detail again.

[0135] Optionally, in some embodiments, the cascaded shift register unit can refer to the next cascaded shift register unit of the current stage; that is, it can be an adjacent Nth stage shift register unit and an (N+1)th stage shift register unit connected through the shift output terminal CR. <n>Cascaded with each other. In other embodiments, the other cascaded shift register unit can refer to the next two cascaded shift register units of the current shift register unit; that is, it can be the Nth shift register unit and the (N+2)th shift register unit connected through the shift output terminal CR. <n>Cascaded with each other. In some other embodiments, the cascaded shift register unit can refer to the next three cascaded shift register units of the current shift register unit; that is, it can be the Nth shift register unit and the (N+3)th shift register unit connected through the shift output terminal CR. <n>Cascading. In some embodiments, the cascaded shift register unit may refer to the next four stages or other stages cascaded from the current stage shift register unit. In embodiments of this disclosure, the current stage shift register unit is processed via the shift output terminal CR. <n>The number of stages in the cascaded shift register unit is not limited.

[0136] For example, the first output circuit 02 can control the second clock terminal CKB and the shift output terminal CR when the potential of the first node Q is the first potential. <n>The circuit is turned on, allowing the second clock signal provided by the second clock terminal CKB to be transmitted to the shift output terminal CR. <n>Furthermore, the first output circuit 02 can control the second clock terminal CKB and the shift output terminal CR when the potential of the first node Q is the second potential. <n>Disconnect the coupling. Furthermore, the first output circuit 02 can control the first power supply terminal VGH and the shift output terminal CR when the potential of the second node QB is the first potential. <n>The circuit is turned on, allowing the first power signal provided by the first power supply terminal VGH to be transmitted to the shift output terminal CR. <n>Furthermore, the first output circuit 02 can control the first power supply terminal VGH and the shift output terminal CR when the potential of the second node QB is the second potential. <n>Disconnect the coupling. That is, the first output circuit 02 can respond to the potential of the first node Q and the potential of the second node QB, and output via the shift terminal CR. <n>The second clock signal or the first power signal is output to the first input terminal IN1 of the next cascaded shift register unit to realize cascaded driving.

[0137] The second output circuit 03 is coupled to the first control node N1, the second node QB, the first power supply terminal VGH, the reference clock terminal CKC, and the dummy output terminal GD. The second output circuit 03 controls the switching between the first power supply terminal VGH and the dummy output terminal GD in response to the potential of the first control node N1, and controls the switching between the reference clock terminal CKC and the dummy output terminal GD in response to the potential of the second node QB. It also includes a first capacitor C1 coupled between the second node QB and the dummy output terminal GD. Accordingly, the second output circuit 03 can adjust the potential of the second node QB based on the potential of the dummy output terminal GD through the coupling effect of the first capacitor C1. That is, the second output circuit 03 can adjust the potential of the second node QB based on the potential of the dummy output terminal GD through coupling.

[0138] Wherein, the first control node N1 is the first node Q or coupled to the shift output terminal CR <n>.

[0139] That is, in one embodiment, as shown in FIG1, the second output circuit 03 can be coupled to the first node Q. Accordingly, the second output circuit 03 can be used to control the on / off state of the first power supply terminal VGH and the redundant output terminal GD in response to the potential of the first node Q.

[0140] Alternatively, in another embodiment, as shown in FIG2, the second output circuit 03 can be connected to the shift output terminal CR. <n>Coupled accordingly, the second output circuit 03 can be used in response to the shift output terminal CR <n>The voltage level controls the switching between the first power supply terminal VGH and the redundant output terminal GD. Furthermore, as the name suggests, the redundant output terminal GD is an output terminal that is not coupled to any structure. Correspondingly, the second output circuit 03 can also be called a dummy output circuit.

[0141] For example, the second output circuit 03 can control the first power supply terminal VGH to conduct with the redundant output terminal GD when the potential of the first control node N1 is at the first potential, so that the first power supply signal provided by the first power supply terminal VGH is transmitted to the redundant output terminal GD; and the second output circuit 03 can control the first power supply terminal VGH to decouple from the redundant output terminal GD when the potential of the first control node N1 is at the second potential. Furthermore, the second output circuit 03 can control the reference clock terminal CKC to conduct with the redundant output terminal GD when the potential of the second node QB is at the first potential, so that the reference clock signal provided by the reference clock terminal CKC is transmitted to the redundant output terminal GD; and the second output circuit 03 can control the reference clock terminal CKC to decouple from the redundant output terminal GD when the potential of the second node QB is at the second potential. Furthermore, the second output circuit 03 can also adjust the potential of the second node QB based on the potential of the redundant output terminal GD, so that when the first potential control reference clock signal of the second node QB is transmitted to the redundant output terminal GD in response to the transmission of the reference clock signal, the potential of the second node QB is further reliably pulled down based on the low potential reference clock signal.

[0142] The third output circuit 04 is connected to the second control node N2, the second node QB, the third clock terminal GCK, the second power supply terminal VGL1, and the scan output terminal G. <n>Coupled. The third output circuit 04 is used to control the third clock terminal GCK and the scan output terminal G in response to the potential of the second control node N2. <n>The switching on and off of the signal, and in response to the potential of the second node QB, controls the connection between the second power supply terminal VGL1 and the scan output terminal G. <n>The on / off state.

[0143] Among them, the scan output terminal G <n>Used to couple with pixels in a display panel to drive the pixels to emit light. For example, the scan output terminal G <n>The third output circuit 04 can be coupled to the pixel circuit within the pixel via a gate line and used to output a gate drive signal to the pixel circuit, thereby causing the pixel circuit to drive the light-emitting element in the pixel to emit light. Correspondingly, the third output circuit 04 can also be called a scan output circuit. Optionally, the display panel can generally include multiple rows and columns of pixels arranged in an array. Multiple cascaded shift register units can be coupled one-to-one with the multiple rows of pixels via gate lines, thereby scanning the pixels row by row.

[0144] Furthermore, the second control node N2 is either the first node Q or coupled to the shift output terminal CR. <n>.

[0145] That is, similar to the first control node N1, in one embodiment, as shown in Figure 1, the third output circuit 04 can be coupled to the first node Q. Accordingly, the third output circuit 04 can be used to control the third clock terminal GCK and the scan output terminal G in response to the potential of the first node Q. <n>The on / off state.

[0146] Alternatively, in another embodiment, as shown in FIG2, the third output circuit 04 can be connected to the shift output terminal CR. <n>Coupled accordingly, the third output circuit 04 can be used in response to the shift output terminal CR. <n>The potential controls the third clock terminal GCK and the scan output terminal G. <n>The on / off state.

[0147] For example, the third output circuit 04 can control the third clock terminal GCK and the scan output terminal G when the potential of the second control node N2 is the first potential. <n>When the circuit is turned on, the third clock signal provided by the third clock terminal GCK is transmitted to the scan output terminal G. <n>Furthermore, the third output circuit 04 can control the third clock terminal GCK and the scan output terminal G when the potential of the second control node N2 is the second potential. <n>Disconnect the coupling. Furthermore, the third output circuit 04 can control the second power supply terminal VGL1 and the scan output terminal G when the potential of the second node QB is the first potential. <n>The circuit is turned on, allowing the second power signal provided by the second power supply terminal VGL1 to be transmitted to the scan output terminal G. <n>Furthermore, the third output circuit 04 can control the second power supply terminal VGL1 and the scan output terminal G when the potential of the second node QB is the second potential. <n>Disconnect the coupling.

[0148] Optionally, the potential of the first power signal provided by the first power supply terminal VGH can be a high potential; the potential of the second power signal provided by the second power supply terminal VGL1 can be a low potential. Furthermore, for the shift register unit including a P-type transistor, the first output circuit 02 responds to the first potential of the second node QB, and outputs data via the shift output terminal CR. <n>The output of a high-level first power supply signal to the first input terminal IN1 of the next-level shift register unit can be considered as noise reduction; while the first output circuit O2 responds to the first potential of the first node Q, and outputs a high-level signal via the shift output terminal CR. <n>Outputting the second clock signal from the first input IN1 of the next-level shift register unit can be considered as cascading drive. For the N-type transistor in the pixel, the third output circuit 04 responds to the first potential of the second node QB and outputs the signal via the scan output terminal G. <n>Outputting a low-potential second power signal to the pixel can be considered as noise reduction; while the third output circuit 04 responds to the first potential of the second control node N2 (e.g., the first node Q), and outputs a signal via the scan output terminal G. <n>Outputting a third clock signal to the pixel can be considered as performing scan driving. Therefore, in this embodiment of the disclosure, the first node Q can also be called a pull-up node, and the second node QB can also be called a pull-down node.

[0149] It is understandable that in some embodiments without a second output circuit 03, the potential of the second node QB may not be stably maintained at the first potential due to various factors, i.e., insufficient low voltage. Therefore, the third output circuit 04 cannot reliably control the second power supply terminal VGL1 and the scan output terminal G. <n>The circuit is turned on, thus preventing the reliable transmission of the low-potential second power supply signal to the scan output terminal G. <n>To the scan output terminal G <n>Noise is removed from coupled signal lines (e.g., gate lines).

[0150] In this embodiment, a second output circuit 03 is also provided, and this second output circuit 03 can reliably pull down the potential of the second node QB when the potential of the second node QB is low. Therefore, it can be ensured that the third output circuit 04 responds to a lower potential of the second node QB and reliably controls the second power supply terminal VGL1 and the scan output terminal G. <n>The circuit is turned on, allowing the low-potential second power supply signal to be reliably transmitted to the scan output terminal G. <n>To the scan output terminal G <n>The coupled gate lines are adequately noise-damped. Similarly, the first output circuit 02, based on the reliable pull-down of the second node QB by the second output circuit 03, can also ensure that the first output circuit 02 responds to a lower potential of the second node QB, reliably controlling the first power supply terminal VGH and the shift output terminal CR. <n>The circuit is turned on, allowing the first power signal to be reliably transmitted to the shift output terminal CR. <n>.

[0151] It is understandable that, taking the second control node N2 as an example, the second control node N2 is set to be coupled to the shift output terminal CR. <n>Based on this, since the potential of the first node Q is the first potential, the potential of the second node QB is generally the second potential. Therefore, when the first output circuit O2 responds to the first potential of the first node Q, it controls the second clock terminal CKB and the shift output terminal CR. <n>The circuit is turned on, allowing the second clock signal to be transmitted to the shift output terminal CR. <n>At that time, the second output circuit 04 can respond to the second potential of the second node QB and control the second power supply terminal VGL1 and the scan output terminal G. <n>Disconnect the coupling. At this time, if the potential of the second clock signal is also the second potential, the second output circuit 04 can still respond to the shift output terminal CR. <n>The second potential controls the third clock terminal GCK and the scan output terminal G. <n>Disconnect the coupling so that the scan output terminal G <n>It is in a floating state. That is, the shift output terminal CR... <n>The potential of the first node and the potential of the second node QB can be the same as the second potential for a relatively long time. Therefore, the second control node N2 is coupled to the shift output terminal CR. <n>Compared to setting the second control node N2 as the first node N1, it is possible to add a scan output terminal G. <n>The time spent floating. Based on this, in some embodiments, a second control node N2 is coupled to the shift output terminal CR. <n>Based on this, the second output circuit 03 can be omitted.

[0152] Optionally, in some embodiments, the first control node N1 and the second control node N2 can be the same, that is, they can be the same node. For example, referring to Figure 1, the first control node N1 and the second control node N2 can both be the first node Q; or referring to Figure 2, the first control node N1 and the second control node N2 can both be the shift output terminal CR. <n>Alternatively, in some embodiments, the first control node N1 and the second control node N2 may be different. For example, referring to Figure 3, the first control node N1 may be the first node Q, while the second control node N2 may be the shift output terminal CR. <n>This disclosure does not limit the scope of the embodiments.

[0153] In summary, this disclosure provides a shift register unit. In this shift register unit, the input circuit can control the potentials of a first node and a second node. A first output circuit can respond to the potentials of the first and second nodes by controlling a second clock terminal or a first power supply terminal to output a signal to the shift output terminal. A second output circuit can respond to the potentials of the first and second nodes by controlling a first power supply terminal or a reference clock terminal to output a signal to a redundant output terminal. The second output circuit includes a capacitor coupled between the second node and the redundant output terminal. Accordingly, the second output circuit can adjust the potential of the first node based on the potential of the redundant output terminal under the coupling effect of the capacitor. A third output circuit can respond to the potentials of the first and second nodes by controlling a third clock terminal or a second power supply terminal to output a signal to the scan output terminal. Thus, by flexibly setting the reference clock signal provided by the reference clock terminal, the second output circuit can maintain a stable potential of the first node, thereby enabling the third output circuit to reliably output signals, such as gate drive signals, to the scan output terminal, thereby reliably driving pixel emission and ensuring a better display effect on the display panel.

[0154] Alternatively, in one implementation, referring to Figure 1, the reference clock terminal CKC can be shared with the first clock terminal CKA. This allows the second output circuit 03 to further pull down the potential of the second node QB based on the low potential of the first clock signal through coupling, thereby ensuring that the third output circuit 04 reliably controls the second power supply terminal VGL1 and the scan output terminal G. <n>To enable the scanning output terminal G to conduct. <n>Reliable noise reduction for coupled gate lines.

[0155] Alternatively, in another optional implementation, referring to Figure 2, the reference clock terminal CKC can be shared with the second clock terminal CKB. This allows the second output circuit 03 to further pull down the potential of the second node QB based on the low potential of the second clock signal through coupling, thereby ensuring that the third output circuit 04 reliably controls the second power supply terminal VGL1 and the scan output terminal G. <n>To enable the scanning output terminal G to conduct. <n>Reliable noise reduction for coupled gate lines.

[0156] Alternatively, in another optional implementation, referring to Figure 3, the reference clock terminal CKC, the first clock terminal CKA, and the second clock terminal CKB can all be independent of each other, and the transition edge of the reference clock signal provided by the reference clock terminal CKC from the second potential to the first potential can be located after the transition edge of the second clock signal provided by the second clock terminal CKB from the second potential to the first potential.

[0157] In this configuration, with the second potential being high and the first potential being low, the transition edge from the second potential to the first potential can be a falling edge. That is, the falling edge of the reference clock signal can occur after the falling edge of the second clock signal. This prevents the second clock signal provided by the second clock terminal CKB from transitioning from high to low before the second output circuit 03 reliably controls the reference clock terminal CKC and the redundant output terminal GD to conduct, and before reliably pulls down the potential of the second node QB based on the reference clock signal through coupling, thus avoiding the problem of poor potential stability of the second node QB. This also avoids the problem of poor coupling effect of the second node QB potential due to the delay of the falling edge of the second clock signal. In other words, it further ensures that the potential of the second node QB remains stable and is reliably pulled down to a lower potential by the second output circuit 03 through coupling, allowing the third output circuit 04 to reliably control the second power supply terminal VGL1 and the scan output terminal GD. <n>Turn on, enabling the scanning output terminal G <n>Sufficient noise reduction for coupled gate lines.

[0158] Optionally, Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 4, the first node Q may include: a first child node Q1 and a second child node Q2.

[0159] The input circuit 01 can be coupled to the first child node Q1. That is, the input circuit 01 can control the potential of the first child node Q1 in the first node Q. The first output circuit 02 can be coupled to the second child node Q2. That is, the first output circuit 02 can respond to the potential of the second child node Q2 in the first node Q, controlling the second clock terminal CKB and the shift output terminal CR. <n>The first control node N1 can be either the first child node Q1 or the second child node Q2. That is, the second output circuit 03 can respond to the potential of the first child node Q1 or the second child node Q2 in the first node Q to control the on / off state of the first power supply terminal VGH and the redundant output terminal GD. The second control node N2 can be either the first child node Q1 or the second child node Q2. That is, the third output circuit 04 can respond to the potential of the first child node Q1 or the second child node Q2 in the first node Q to control the on / off state of the third clock terminal GCK and the scan output terminal GD. <n>The on / off state of the shift register unit. For example, in the shift register unit shown in Figure 4, the first control node N1 and the second control node N2 are both the second child node Q2 in the first node Q.

[0160] Based on this, referring to Figure 4, it can be seen that the shift register unit may also include: a first control circuit 05.

[0161] The first control circuit 05 can be coupled to the third power supply terminal VGL2, the first sub-node Q1, and the second sub-node Q2, respectively. The first control circuit 05 can be used to control the on / off state of the first sub-node Q1 and the second sub-node Q2 in response to the third power supply signal provided by the third power supply terminal VGL2.

[0162] For example, the first control circuit 05 can control the first sub-node Q1 and the second sub-node Q2 to conduct when the potential of the third power signal provided by the third power supply terminal VGL2 is the first potential.

[0163] Optionally, the potential of the third power signal provided by the third power supply terminal VGL2 can be a low potential. Furthermore, in some embodiments, the third power supply terminal VGL2 can be shared with the second power supply terminal VGL1. This simplifies wiring and saves costs.

[0164] Understandably, by setting the first control circuit 05, the input circuit can be isolated from each output circuit to prevent interference between the input and output circuits. For example, it can prevent the bootstrap effect of the capacitors set in the output circuit from being affected, so that both the input and output circuits can maintain stable output.

[0165] Optionally, Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 5, the second node QB may include a third child node QB1 and a fourth child node QB2.

[0166] Both the input circuit 01 and the first output circuit 02 can be coupled to the third child node QB1. That is, the input circuit 01 can control the potential of the third child node QB1 in the second node QB, and the first output circuit 02 can respond to the potential of the third child node QB1 in the second node QB, controlling the first power supply terminal VGH and the shift output terminal CR. <n>The second output circuit 03 and the third output circuit 04 can both be coupled to the fourth child node QB2. That is, the second output circuit 03 can respond to the potential of the fourth child node QB2 in the second node QB to control the on / off state of the reference clock terminal CKC and the redundant output terminal GD; the third output circuit 04 can respond to the potential of the fourth child node QB2 in the second node QB to control the on / off state of the second power supply terminal VGL1 and the scan output terminal GD. <n>The on / off state of the circuit. Of course, in some other embodiments, the input circuit 01, the first output circuit 02 and the second output circuit 03 may all be coupled to the third child node QB1, and only the third output circuit 04 may be coupled to the fourth child node QB2.

[0167] Based on this, referring to Figure 5, it can be seen that the shift register unit may also include: a second control circuit 06.

[0168] The second control circuit 06 can be coupled to the third power supply terminal VGL2, the third sub-node QB1, and the fourth sub-node QB2, respectively. The second control circuit 06 can be used to control the on / off state of the third sub-node QB1 and the fourth sub-node QB2 in response to the third power supply signal provided by the third power supply terminal VGL2.

[0169] For example, the first control circuit 05 can control the third sub-node QB1 and the fourth sub-node QB2 to conduct when the potential of the third power signal provided by the third power supply terminal VGL2 is the first potential.

[0170] It is understandable that, similar to the first control circuit 05, the second control circuit 06 can also achieve the same isolation effect. For example, the second control circuit 06 can effectively isolate the first output circuit 02 from the third output circuit 04.

[0171] Optionally, Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 6, any one of the first control node N1 and the second control node N2 may include: a first control sub-node N11 and a second control sub-node N12.

[0172] The first control sub-node N11 can be the first node Q or coupled to the shift output terminal CR. <n>Furthermore, when either control node is the second control node N2, the third output circuit 04 can be coupled to the second control sub-node N12. When either control node is the first control node N1 and the second control node N2, both the second output circuit 03 and the third output circuit 04 can be coupled to the second control sub-node N12. It is understood that, based on the division of the first node Q into the first sub-node Q1 and the second sub-node Q2, the first node Q here can refer to either the first sub-node Q1 or the second sub-node Q2.

[0173] For example, in the shift register unit shown in Figure 6, the first control node N1 and the second control node N2 both include a first control sub-node N11 and a second control sub-node N12, and the first control sub-node N11 is the second sub-node Q2 in the first node Q. The second output circuit 03 and the third output circuit 04 are both coupled to the second control sub-node N12.

[0174] For example, in the shift register unit shown in Figure 7, only the second control node N2 includes the first control sub-node N11 and the second control sub-node N12, and the first control sub-node N11 and the first control node N1 are both the second sub-node Q2 in the first node Q, and the third output circuit 04 is coupled to the second control sub-node N12.

[0175] Optionally, in Figures 6 and 7, the second control sub-node N12 is also identified as node Q3, which can be considered as another sub-node included in the first node Q.

[0176] Based on this, referring to Figures 6 and 7, it can be seen that the shift register unit may also include: a third control circuit 07.

[0177] The third control circuit 07 can be coupled to the third power supply terminal VGL2, the first control sub-node N11 and the second control sub-node N12 respectively, and can be used to control the on / off state of the first control sub-node N11 and the second control sub-node N12 in response to the third power supply signal provided by the third power supply terminal VGL2.

[0178] For example, the third control circuit 07 can control the first control sub-node N11 and the second control sub-node N12 to conduct when the potential of the third power signal provided by the third power supply terminal VGL2 is the first potential.

[0179] It is understandable that, similar to the second control circuit 06, the third control circuit 07 can also achieve the same isolation effect. For example, the third control circuit 07 can effectively isolate the first output circuit 02 from the third output circuit 04.

[0180] That is, in one implementation, as shown in Figure 6, the third control circuit 07 can be coupled between the second child node Q2 and the second output circuit 03 and the third output circuit 04. Alternatively, in another implementation, as shown in Figure 7, the third control circuit 07 can be coupled between the second child node Q2 and the third output circuit 04. It is understood that, compared to the structure in Figure 6, by setting the third control circuit 07 to be coupled between the second child node Q2 and the third output circuit 04, the potential of the second child node Q2 can be prevented from being too low, thus reducing the negative bias temperature stress (NBTS) of the transistor in the second output circuit 03 coupled to the second child node Q2.

[0181] Of course, similar to the third control circuit 07, in one implementation, the second control circuit 06 can be coupled between the third child node QB1 and the second output circuit 03 and the third output circuit 04, as shown in Figures 5 to 7. Alternatively, in another implementation, the second control circuit 06 can be coupled between the third child node QB1 and the third output circuit 04.

[0182] Optionally, Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 9, the second node QB may include a third child node QB1 and a fifth child node QB3.

[0183] The input circuit 01, the first output circuit 02, and the third output circuit 04 can all be coupled to the third child node QB1. That is, as described above, the input circuit 01 can control the potential of the third child node QB1 in the second node QB; the first output circuit 02 can respond to the potential of the third child node QB1 in the second node QB, controlling the first power supply terminal VGH and the shift output terminal CR. <n>The on / off state of the circuit; and the third output circuit 04 can respond to the potential of the third child node QB1 in the second node QB, controlling the connection between the second power supply terminal VGL1 and the scan output terminal G. <n>The second output circuit 03 can be coupled to the fifth child node QB3. That is, the second output circuit 03 can control the on / off state of the reference clock terminal CKC and the redundant output terminal GD in response to the potential of the fifth child node QB3 in the second node QB.

[0184] Based on this, referring to Figure 8, it can be seen that the shift register unit may also include: a fourth control circuit 08.

[0185] The fourth control circuit 08 can be coupled to the third power supply terminal VGL2, the third sub-node QB1, and the fifth sub-node QB3, respectively. The fourth control circuit 08 can be used to control the on / off state of the third sub-node QB1 and the fifth sub-node QB3 in response to the third power supply signal provided by the third power supply terminal VGL2, and to control the on / off state of the third sub-node QB1 and the fifth sub-node QB3 in response to the potential of the fifth sub-node QB3.

[0186] For example, the fourth control circuit 08 can control the third sub-node QB1 and the fifth sub-node QB3 to conduct when the potential of the third power signal provided by the third power supply terminal VGL2 is at the first potential. Furthermore, the fourth control circuit 08 can control the third sub-node QB1 and the fifth sub-node QB3 to conduct when the potential of the fifth sub-node QB3 is at the first potential, and can control the third sub-node QB1 and the fifth sub-node QB3 to disconnect when the potential of the fifth sub-node QB3 is at the second potential.

[0187] It is understandable that, similar to the second control circuit 06, the fourth control circuit 08 can also achieve the same isolation effect. For example, the fourth control circuit 08 can effectively isolate the input circuit 01 from the third output circuit 04.

[0188] Optionally, based on the second node QB including a fourth sub-node QB2, as shown in Figure 8, the third output circuit 04 can be coupled to the fourth sub-node QB2 in the second node QB, and the fourth control circuit 08 can also be coupled to the fourth sub-node QB2. It can control the on / off state of the fourth sub-node QB2 and the fifth sub-node QB3 according to the potential of the fifth sub-node QB3, rather than controlling the on / off state of the third sub-node QB1 and the fifth sub-node QB3.

[0189] Optionally, Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. As shown in Figure 9, the input circuit 01 may include: a first input sub-circuit 011 and a second input sub-circuit 012.

[0190] The first input sub-circuit 011 can be coupled to the first clock terminal CKA, the first input terminal IN1, the first node Q, the second node QB, the second clock terminal CKB, and the first power supply terminal VGH, respectively. The first input sub-circuit 011 can be used to control the on / off state of the first input terminal IN1 and the first node Q in response to the first clock signal, and to control the on / off state of the first power supply terminal VGH and the first node Q in response to the potential of the second node QB and the second clock signal, thereby controlling the potential of the first node Q.

[0191] For example, the first input sub-circuit 011 can control the first input terminal IN1 to be connected to the first node Q when the potential of the first clock signal is a first potential, so that the first input signal provided by the first input terminal IN1 is transmitted to the first node Q; and the first input sub-circuit 011 can control the first input terminal IN1 to be disconnected from the first node Q when the potential of the first clock signal is a second potential. Furthermore, the first input sub-circuit 011 can control the first power supply terminal VGH to be connected to the first node Q when the potential of the second node QB and the potential of the second clock signal are both the first potential, so that the first power supply signal provided by the first power supply terminal VGH is transmitted to the first node Q; and the first input sub-circuit 011 can control the first power supply terminal VGH to be disconnected from the first node Q when the potential of the second node QB and / or the potential of the second clock signal is the second potential.

[0192] The second input sub-circuit 012 can be coupled to the input control terminal Con, the second input terminal IN2, the first node Q, and the second node QB, respectively. The second input sub-circuit 012 can be used to control the on / off state of the second input terminal IN2 and the second node QB in response to the input control signal provided by the input control terminal Con, and to control the on / off state of the input control terminal Con and the second node QB in response to the potential of the first node Q, so as to control the potential of the second node QB.

[0193] For example, the second input sub-circuit 012 can control the second input terminal IN2 to conduct with the second node QB when the potential of the input control signal provided by the input control terminal Con is a first potential, so that the second input signal provided by the second input terminal IN2 is transmitted to the second node QB; and the second input sub-circuit 012 can control the second input terminal IN2 to decouple from the second node QB when the potential of the input control signal provided by the input control terminal Con is a second potential. Furthermore, the second input sub-circuit 012 can control the input control terminal Con to conduct with the second node QB when the potential of the first node Q is a first potential, so that the input control signal provided by the input control terminal Con is transmitted to the second node QB; and the second input sub-circuit 012 can control the input control terminal Con to decouple from the second node QB when the potential of the first node Q is a second potential.

[0194] Understandably, based on the division of the first node Q into the first child node Q1 and the second child node Q2, and the division of the second node QB into the third child node QB1, the fourth child node QB2, and the fifth child node QB3, the first input sub-circuit 011 and the second input circuit 012 can both be coupled to the first child node Q1 and the third child node QB1. That is, the first input sub-circuit 011 can respond to the first clock signal to control the on / off state of the first input terminal IN1 with the first child node Q1 in the first node Q, and respond to the potential of the third child node QB1 in the second node QB and the second clock signal to control the on / off state of the first power supply terminal VGH with the first child node Q1 in the first node Q. Furthermore, the second input sub-circuit 012 can respond to the input control signal provided by the input control terminal Con to control the on / off state of the second input terminal IN2 with the third child node QB1 in the second node QB, and respond to the potential of the first child node Q1 in the first node Q to control the on / off state of the input control terminal Con with the third child node QB1 in the second node QB.

[0195] Optionally, as an alternative implementation: as shown in Figure 9, the input control terminal Con and the second input terminal IN2 can be the first clock terminal CKA and the third power supply terminal VGL2, respectively. That is, the second input sub-circuit 012 can be used to control the on / off state of the third power supply terminal VGL2 and the third child node QB1 in the second node QB in response to the first clock signal provided by the first clock terminal CKA, and to control the on / off state of the first clock terminal CKA and the third child node QB1 in the second node QB in response to the potential of the first child node Q1 in the first node Q.

[0196] Alternatively, as an alternative implementation: as shown in Figure 10, the input control terminal Con and the second input terminal IN2 can be the first power supply terminal VGH and the second clock terminal CKB, respectively. That is, the second input sub-circuit 012 can be used to control the on / off state of the second clock terminal CKB and the third sub-node QB1 in the second node QB in response to the first power supply signal provided by the first power supply terminal VGH, and to control the on / off state of the first power supply terminal VGH and the third sub-node QB1 in the second node QB in response to the potential of the first sub-node Q1 in the first node Q.

[0197] Optionally, when the input control terminal Con and the second input terminal IN2 are the first power supply terminal VGH and the second clock terminal CKB, respectively, the second input sub-circuit 012 may further include a second capacitor C2 coupled between the second input terminal IN2 and the input control terminal Con. Accordingly, the second input sub-circuit 012 can adjust the input control signal based on the second input signal provided by the second input terminal IN2 under the coupling effect of the second capacitor C2. That is, the second input sub-circuit 012 can adjust the input control signal based on the second input signal provided by the second input terminal IN2 through coupling. Furthermore, referring to Figure 10, the shift register unit may further include a fifth control circuit 09.

[0198] The fifth control circuit 09 can be coupled to the first node Q, the input control terminal Con, and the second input sub-circuit 012, respectively. The fifth control circuit 09 can be used to control the on / off state of the input control terminal Con and the second input sub-circuit 012 in response to the potential of the first node Q.

[0199] For example, when the potential of the first node Q is the first potential, the fifth control circuit 09 can control the input control terminal Con (i.e., the first power supply terminal VGH) to conduct with the second input sub-circuit 012, so that the input control signal provided by the input control terminal Con (i.e., the first power supply signal provided by the first power supply terminal VGH) is transmitted to the second input sub-circuit 012; and the fifth control circuit 09 can control the input control terminal Con to disconnect from the second input sub-circuit 012 when the potential of the first node Q is the second potential.

[0200] As can be understood, as mentioned earlier, based on the division of the first node Q into the first child node Q1 and the second child node Q2, the fifth control circuit 09 can be coupled to the first child node Q1. That is, the fifth control circuit 05 can respond to the potential of the first child node Q1 in the first node Q and control the on / off state of the input control terminal Con and the second input sub-circuit 012.

[0201] It is also understandable that the second input sub-circuit 012 is directly coupled to the first power supply terminal VGH and is used to control the on / off state of the first power supply terminal VGH and the second node QB in response to the potential of the first node Q. That is, the fifth control circuit 05 can be used to control the on / off state of the first power supply terminal VGH and the second input sub-circuit 012, so that the second input sub-circuit 012 further responds to the first power signal provided by the first power supply terminal VGH and controls the on / off state of the second input terminal IN2 and the second node QB.

[0202] Optionally, based on Figure 9, Figure 11 shows a schematic diagram of another shift register unit provided in an embodiment of the present disclosure. Based on Figure 10, Figure 12 shows a schematic diagram of another shift register unit provided in an embodiment of the present disclosure. As shown in Figures 11 and 12, the second node QB may include: a third child node QB1 and a sixth child node QB4.

[0203] Specifically, the first input sub-circuit 011, the second input sub-circuit 012, the first output circuit 02, and the third output circuit 04 can all be coupled to the third sub-node QB1. That is, as described above, the first input sub-circuit 011 can respond to the potential of the third sub-node QB1 in the second node QB to control the potential of the first sub-node Q1 in the first node Q; the second input sub-circuit 012 can control the potential of the third sub-node QB1 in the second node QB; and the first output circuit 02 can respond to the potential of the third sub-node QB1 in the second node QB to control the connection between the first power supply terminal VGH and the shift output terminal CR. <n>The on / off state of the third output circuit 04 can respond to the potential of the third child node QB1 in the second node QB, controlling the connection between the second power supply terminal VGL1 and the scan output terminal G. <n>The fourth control circuit 08 can be coupled to the sixth child node QB4. That is, the fourth control circuit 08 can respond to the third power signal provided by the third power supply terminal VGL2 to control the on / off state of the sixth child node QB4 and the fifth child node QB3 in the second node QB.

[0204] Based on this, referring to Figures 11 and 12, it can be seen that the input circuit 01 may also include: a third input sub-circuit 013.

[0205] The third input sub-circuit 013 can be coupled to the input control terminal Con, the second input terminal IN2, the first node Q, and the sixth sub-node QB4, respectively. The third input sub-circuit 013 can be used to control the on / off state of the second input terminal IN2 and the sixth sub-node QB4 in response to an input control signal, and to control the on / off state of the input control terminal Con and the sixth sub-node QB4 in response to the potential of the first node Q. That is, the third input sub-circuit 013 and the second input sub-circuit 012 can be input sub-circuits with the same function.

[0206] For example, the third input sub-circuit 013 can control the second input terminal IN2 to conduct with the sixth sub-node QB4 when the potential of the input control signal is the first potential, so that the second input signal provided by the second input terminal IN2 is transmitted to the sixth sub-node QB4; and the third input sub-circuit 013 can control the second input terminal IN2 to decouple from the sixth sub-node QB4 when the potential of the input control signal is the second potential. Furthermore, the third input sub-circuit 013 can control the input control terminal Con to conduct with the sixth sub-node QB4 when the potential of the first node Q is the first potential, so that the input control signal provided by the input control terminal Con is transmitted to the sixth sub-node QB4; and the third input sub-circuit 013 can control the input control terminal Con to decouple from the sixth sub-node QB4 when the potential of the first node Q is the second potential.

[0207] It is understandable that, based on the division of the first node Q into the first child node Q1 and the second child node Q2, the third input sub-circuit 013 can be coupled to the first child node Q1 in the first node Q. That is, the third input sub-circuit 013 can respond to the potential of the first child node Q1 in the first node Q and control the on / off state of the input control terminal Con and the sixth child node QB4.

[0208] Optionally, in conjunction with the embodiments described above, Figures 13 to 34 schematically illustrate the circuit structure diagrams of the shift register unit under different embodiments.

[0209] Optionally, as can be seen from Figures 13 to 34, the first control circuit 05 may include: a first transistor T1.

[0210] The gate of the first transistor T1 can be coupled to the third power supply terminal VGL2, the first terminal of the first transistor T1 can be coupled to the first sub-node Q1, and the second terminal of the first transistor T1 can be coupled to the second sub-node Q2.

[0211] Optionally, as can be seen from Figures 16 to 33, as an optional implementation, the second control circuit 06 may include a second transistor T2.

[0212] The gate of the second transistor T2 can be coupled to the third power supply terminal VGL2, the first terminal of the second transistor T2 can be coupled to the third sub-node QB1, and the second terminal of the second transistor T2 can be coupled to the fourth sub-node QB2.

[0213] Alternatively, as can be seen from Figure 26, as another optional implementation, the second control circuit 06 may include two second transistors T2-1 and T2-2 connected in series.

[0214] The gates of the two second transistors T2-1 and T2-2 can both be coupled to the third power supply terminal VGL2. The first terminals of the two second transistors T2-1 and T2-2 can be coupled to the third sub-node QB1 and the fourth sub-node QB2, respectively. The second terminals of the two second transistors T2-1 and T2-2 can both be coupled to the series node P0. Accordingly, referring to Figure 26, it can be seen that the shift register unit may also include: a leakage protection circuit 10.

[0215] The leakage protection circuit 10 can be coupled to the fourth sub-node QB2, the fourth power supply terminal VGL3, and the series node P0, respectively. The leakage protection circuit 10 can be used to control the switching on and off of the fourth power supply terminal VGL3 and the series node P0 in response to the potential of the fourth sub-node QB2.

[0216] For example, the leakage protection circuit 10 can control the fourth power supply terminal VGL3 to conduct with the series node P0 when the potential of the fourth sub-node QB2 is the first potential, so that the fourth power supply signal provided by the fourth power supply terminal VGL3 is transmitted to the series node P0; and the leakage protection circuit 10 can control the fourth power supply terminal VGL3 to disconnect from the series node P0 when the potential of the fourth sub-node QB2 is the second potential.

[0217] Optionally, as can be seen from Figure 27, the leakage protection circuit 10 may include a third transistor T3.

[0218] The gate of the third transistor T3 can be coupled to the fourth sub-node QB2, the first terminal of the third transistor T3 can be coupled to the fourth power supply terminal VGL3, and the second terminal of the third transistor T3 can be coupled to the series node P0.

[0219] It is understandable that the potential of the fourth power signal provided by the fourth power supply terminal VGL3 can be low, and the potential of the fourth power signal provided by the fourth power supply terminal VGL3 can be less than or equal to that of the third power supply terminal VGL2. In this way, the leakage path from the fourth child node QB2 to the third child node QB1 can be prevented, which is more conducive to low-frequency driving.

[0220] Optionally, referring to Figure 28, as another optional implementation, the second control circuit 06 can also be coupled to the first node Q, and can also be used to control the on / off state of the third sub-node QB1 and the fourth sub-node QB2 in response to the third power supply signal and the potential of the first node Q. Here, the first node Q can refer to any one of the sub-nodes Q1, Q2, and Q3 included in the first node Q. In this way, the purpose of preventing leakage current can still be achieved, and the leakage current prevention circuit 10 can be omitted.

[0221] That is, based on this, referring to Figure 28, it can be seen that the second control circuit 06 may include two second transistors T2-1 and T2-2 connected in series.

[0222] Furthermore, the gates of the two second transistors T2-1 and T2-2 can be coupled to the third power supply terminal VGL2 and the first node Q, respectively. The first terminals of the two second transistors T2 can be coupled to the third sub-node QB1 and the fourth sub-node QB2, respectively. The second terminals of the two second transistors T2-1 and T2-2 are coupled.

[0223] Of course, in some other embodiments, other transistors with gates coupled to the third power supply terminal VGL2 (e.g., the first transistor T1) can also be designed in the same way as the structure of the second control circuit 06, such as setting the first transistor T1 to include two transistors connected in series to achieve leakage protection.

[0224] Optionally, referring to Figures 17 to 33, it can be seen that the third control circuit 07 may include a fourth transistor T4.

[0225] The gate of the fourth transistor T4 can be coupled to the third power supply terminal VGL2, the first terminal of the fourth transistor T4 can be coupled to the first control sub-node N11, and the second terminal of the fourth transistor T4 can be coupled to the second control sub-node N12.

[0226] Optionally, referring further to Figures 20 to 28 and Figure 33, it can be seen that the fourth control circuit 08 may include a fifth transistor T5 and a sixth transistor T6.

[0227] Specifically, the gate of the fifth transistor T5 can be coupled to the third power supply terminal VGL2, the first terminal of the fifth transistor T5 can be coupled to the third sub-node QB1, and the second terminal of the fifth transistor T5 can be coupled to the fifth sub-node QB3.

[0228] The gate and second terminal of the sixth transistor T6 can both be coupled to the fifth sub-node QB3, and the first terminal of the sixth transistor T6 can be coupled to the third sub-node QB1.

[0229] Optionally, referring further to Figures 13 to 34, the first input sub-circuit 011 may include: a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The second input sub-circuit 012 may include: a tenth transistor T10 and an eleventh transistor T11.

[0230] Among them, the gate of the seventh transistor T7 can be coupled to the first clock terminal CKA, the first terminal of the seventh transistor T7 can be coupled to the first input terminal IN1, and the second terminal of the seventh transistor T7 can be coupled to the first node Q.

[0231] The gate of the eighth transistor T8 can be coupled to the second node QB, the first terminal of the eighth transistor T8 can be coupled to the first power supply terminal VGH, and the second terminal of the eighth transistor T8 can be coupled to the first terminal of the ninth transistor T9.

[0232] The gate of the ninth transistor T9 can be coupled to the second clock terminal CKB, and the second terminal of the ninth transistor T9 can be coupled to the first node Q.

[0233] The gate of the tenth transistor T10 can be coupled to the input control terminal Con, the first terminal of the tenth transistor T10 can be coupled to the second input terminal IN2, and the second terminal of the tenth transistor T10 can be coupled to the second node QB.

[0234] The gate of the eleventh transistor T11 can be coupled to the first node Q, the first terminal of the eleventh transistor T11 can be coupled to the input control terminal Con, and the second terminal of the eleventh transistor T11 can be coupled to the second node QB.

[0235] Optionally, referring further to Figures 13 to 21, 29 to 32, and 34, it can be seen that the fifth control circuit 09 may include: the twelfth transistor T12.

[0236] The gate of the twelfth transistor T12 can be coupled to the first node Q, the first terminal of the twelfth transistor T12 can be coupled to the input control terminal Con, and the second terminal of the twelfth transistor T12 can be coupled to the second input sub-circuit 012.

[0237] Optionally, referring to Figures 21, 23 to 28, and 33, it can be seen that the third input sub-circuit 013 may include: a thirteenth transistor T13 and a fourteenth transistor T14.

[0238] Specifically, the gate of the thirteenth transistor T13 can be coupled to the input control terminal Con, the first terminal of the thirteenth transistor T13 can be coupled to the second input terminal IN2, and the second terminal of the thirteenth transistor T13 can be coupled to the second node QB.

[0239] The gate of the fourteenth transistor T14 can be coupled to the first node Q, the first terminal of the fourteenth transistor T14 can be coupled to the input control terminal Con, and the second terminal of the fourteenth transistor T14 can be coupled to the second node QB.

[0240] Optionally, referring further to Figures 13 to 33, it can be seen that the first output circuit 02 may include: a fifteenth transistor T15, a sixteenth transistor T16, and a third capacitor C3. Correspondingly, it can be seen that the first output circuit 02, under the coupling effect of the third capacitor C3, can output based on the shift output terminal CR. <n>The potential of the first node Q is adjusted by the potential of the first output circuit 02. That is, the first output circuit 02 can also be used to adjust the potential of the shift output terminal CR through coupling. <n>The potential of the first node Q is adjusted by the potential of the transistor. The second output circuit 03 may include: the seventeenth transistor T17 and the eighteenth transistor T18. The third output circuit 04 may include: the nineteenth transistor T19 and the twentieth transistor T20.

[0241] Specifically, the gate of the fifteenth transistor T15 can be coupled to the first node Q, the first terminal of the fifteenth transistor T15 can be coupled to the second clock terminal CKB, and the second terminal of the fifteenth transistor T15 can be coupled to the shift output terminal CR. <n>Coupled.

[0242] The gate of the sixteenth transistor T16 can be coupled to the second node QB, the first terminal of the sixteenth transistor T16 can be coupled to the first power supply terminal VGH, and the second terminal of the sixteenth transistor T16 can be coupled to the shift output terminal CR. <n>Coupled.

[0243] The third capacitor C3 can be coupled to the first node Q and the shift output terminal CR. <n>between.

[0244] The gate of the seventeenth transistor T17 can be coupled to the first control node N1, the first terminal of the seventeenth transistor T17 can be coupled to the first power supply terminal VGH, and the second terminal of the seventeenth transistor T17 can be coupled to the redundant output terminal GD.

[0245] The gate of the eighteenth transistor T18 can be coupled to the second node QB, the first terminal of the eighteenth transistor T18 can be coupled to the reference clock terminal CKC, and the second terminal of the eighteenth transistor T18 can be coupled to the redundant output terminal GD.

[0246] The gate of the nineteenth transistor T19 can be coupled to the second control node N2, the first terminal of the nineteenth transistor T19 can be coupled to the third clock terminal GCK, and the second terminal of the nineteenth transistor T19 can be coupled to the scan output terminal G. <n>Coupled.

[0247] The gate of the twentieth transistor T20 can be coupled to the second node QB, the first terminal of the twentieth transistor T20 can be coupled to the second power supply terminal VGL1, and the second terminal of the twentieth transistor T20 can be coupled to the scan output terminal G. <n>Coupled.

[0248] It is understood that in Figures 13 to 21, 29 to 32, and 34, the input control terminal Con of the shift register unit is always the first power supply terminal VGH, and the coupled second input terminal IN2 is always the second clock terminal CKB. In Figures 22 to 28, and 33, the input control terminal Con of the shift register unit is always the first clock terminal CKA, and the coupled second input terminal IN2 is always the third power supply terminal VGL2.

[0249] Optionally, in some embodiments, as can be seen from Figures 22 to 28 and Figure 33, based on the fact that the input control terminal Con coupled to the shift register unit is the first clock terminal CKA and the second input terminal IN2 coupled to the shift register unit is the third power supply terminal VGL2, the third output circuit 04 may further include a circuit connected to the shift output terminal G. <n>And the fourth capacitor C4 between the second node QB. Correspondingly, it can be seen that the third output circuit 04 can also, under the coupling effect of this fourth capacitor C4, achieve output based on the shifted output terminal CR. <n>The potential of the first node Q is adjusted by the potential of the first node.

[0250] That is, the shift register unit provided in this disclosure may include at least the following embodiments (it is understood that the device structure of each circuit mentioned in the following embodiments is shown in the corresponding drawings, and will not be described in detail here):

[0251] Example 1: Referring to Figure 13, the shift register unit includes: an input circuit 01, a first output circuit 02, a second output circuit 03, and a third output circuit 04. The input circuit 01 may include a first input sub-circuit 011 and a second input sub-circuit 012. The input control terminal Con and the second input terminal IN2 coupled to the second input sub-circuit 012 are respectively the first power supply terminal VGH and the second clock terminal CKB. Correspondingly, the shift register unit also includes a fifth control circuit 09. Furthermore, the first node Q is divided into a first sub-node Q1 and a second sub-node Q2. Correspondingly, the shift register unit also includes a first control circuit 05. The reference clock terminal CKC can be shared with the first clock terminal CKA. This simplifies wiring and saves costs.

[0252] Example 2: Referring to Figure 14, compared to the structure shown in Figure 13, the shared reference clock terminal CKC with the first clock terminal CKA is replaced with a shared terminal CKB with the second clock terminal. This simplifies wiring and saves costs.

[0253] Example 3: Referring to Figure 15, compared to the structure shown in Figure 13, the shared reference clock terminal CKC with the first clock terminal CKA / second clock terminal CKB is replaced with independent reference clock terminals CKA and CKB. Furthermore, as mentioned earlier, the falling edge of the reference clock signal provided by the independent reference clock terminal CKC occurs after the falling edge of the second clock signal provided by the second clock terminal CKB. This further ensures better potential stability of the second node QB.

[0254] Example 4: Referring to Figure 16, relative to any of the structures shown in Figures 13 to 15, the second node QB is divided into a third sub-node QB1 and a fourth sub-node QB2. Correspondingly, a shift register unit including a second control circuit 06 is also provided. Thus, as described above, a better isolation effect can be achieved, preventing interference with the bootstrap effect of the capacitor.

[0255] Example 5: Referring to Figure 17, compared to the structure shown in Figure 16, both the first control node N1 and the second control node N2 include a first control sub-node N11 and a second control sub-node N12. Correspondingly, a shift register unit is also provided, including a third control circuit 07 coupled between the first control sub-node N11 and the second output circuit 03 and the third output circuit 04. This provides better isolation and prevents interference with the capacitor's bootstrap effect.

[0256] Example 6: Referring to Figure 18, compared to the structure shown in Figure 17, only the second control node N2 is divided into a first control sub-node N11 and a second control sub-node N12. Correspondingly, the shift register unit includes a third control circuit 07 coupled between the first control sub-node N11 and the third output circuit 04. That is, the position of the third control circuit 07 is changed compared to Figure 17. In this way, the NBTS of the seventeenth transistor T17 included in the second output circuit 03 can be reduced.

[0257] Example 7: Referring to Figure 19, compared to the structure shown in Figure 18, the reference clock terminal CKC and the second clock terminal CKB2 are shared. Here, the second clock terminal CKB2 can refer to the second clock terminal CKB2 coupled to the shift register unit coupled to the even-numbered row pixels. That is, in some embodiments, for the shift register unit coupled to the odd-numbered row pixels, the corresponding coupled clock terminals may include: a first clock terminal CKA, a second clock terminal CKB, and third clock terminals GCK1 and GCK3; for the shift register unit coupled to the even-numbered row pixels, the corresponding coupled clock terminals may include: a first clock terminal CKA2, a second clock terminal CKB2, and third clock terminals GCK2 and GCK4. In other words, dual clocks can be used to drive the shift register unit coupled to the odd-numbered row pixels and the shift register unit coupled to the even-numbered row pixels respectively.

[0258] Example 8: Referring to Figure 20, compared to the structure shown in Figure 18, in addition to dividing the second node QB into a third sub-node QB1 and a fourth sub-node QB2, the second node QB is further divided into a fifth sub-node QB3. Correspondingly, a shift register unit including a fourth control circuit 08 is also provided. This achieves better isolation and prevents interference with the capacitor's bootstrap effect.

[0259] Example 9: Referring to Figure 21, compared to the structure shown in Figure 20, in addition to dividing the second node QB into third sub-nodes QB1, fourth sub-nodes QB2, and fifth sub-nodes QB3, the second node QB is further divided into a sixth sub-node QB4. Correspondingly, the input circuit 01 in the shift register unit is also configured to include a third input sub-circuit 013. This ensures independent and reliable control of the second output circuit 03.

[0260] Example 10: Referring to Figure 22, compared to the structure shown in Figure 20, the input control terminal Con coupled to the second input sub-circuit 012 is replaced by the first power supply terminal VGH with the first clock terminal CKA. Correspondingly, the second input terminal IN2 coupled to the second input sub-circuit 012 is replaced by the second clock terminal CKB with the third power supply terminal VGL2, and the fifth control circuit 09 is omitted. In this way, the structure can be simplified and costs can be saved.

[0261] Example 11: Referring to Figure 23, compared to the structure shown in Figure 22, in addition to dividing the second node QB into third child node QB1, fourth child node QB2, and fifth child node QB3, the second node QB is further divided into a sixth child node QB4. Correspondingly, the input circuit 01 in the shift register unit is also configured to include a third input sub-circuit 013. That is, similar to the change in Figure 21 compared to Figure 20.

[0262] Example 12: Referring to Figure 24, compared to the structure shown in Figure 23, the first control sub-node N11, which includes the first control node N1 and the second control node N2, is replaced by the first sub-node Q1 instead of the second sub-node Q2. That is, the second output circuit 03 is coupled to the first sub-node Q1, and the third output circuit 04 is coupled to the first sub-node Q1 through the third control circuit 07. In this way, the nineteenth transistor T19 will not be connected in series with the fifteenth transistor T15 and the seventeenth transistor T17, thereby avoiding mutual interference between the nineteenth transistor T19 and the fifteenth transistor T15.

[0263] Example 13: Referring to Figure 25, compared to the structure shown in Figure 24, the coupling of the second output circuit 03 to the first sub-node Q1 is replaced by coupling to the second sub-node Q2. This also avoids mutual interference between the nineteenth transistor T19 and the fifteenth transistor T15.

[0264] Example 14: Referring to Figures 26 and 27, compared to the structure shown in Figure 24, the second control circuit 06 includes two second transistors T2-1 and T2-2 connected in series, instead of a single second transistor T2, and the gates of both second transistors T2-1 and T2-2 are coupled to the same third power supply terminal VGL2. Correspondingly, the shift register unit also includes a leakage protection circuit 10. Thus, as described above, the leakage path from the fourth sub-node QB2 to the third sub-node QB1 can be blocked, achieving a better leakage protection effect and facilitating low-frequency driving.

[0265] Example 15: Referring to Figure 28, compared to the structure shown in Figure 27, the second control circuit 06 includes two second transistors T2-1 and T2-2 connected in series. One second transistor T2-1 is coupled to the third power supply terminal VGL2, and the other second transistor T2-2 is coupled to nodes Q1, Q2, or Q3 of the first node Q. Accordingly, the leakage protection circuit 10 can be omitted. This not only provides better leakage protection but also simplifies the structure and saves costs.

[0266] Example 16: Referring to Figure 29, relative to any of the structures shown in Figures 13 to 15, both the first control node N1 and the second control node N2 are replaced by the second child node Q2 in the first node Q with the shift output terminal CR. <n>That is, both the second output circuit 03 and the third output circuit 04 are configured to be connected to the shift output terminal CR. <n>Coupled. This allows for the addition of a scan output terminal G. <n>The time spent in a floating state.

[0267] Example 17: Referring to Figure 30, relative to the structure shown in Figure 16, both the second output circuit 03 and the third output circuit 04 are connected to the shift output terminal CR. <n>Coupled.

[0268] Example 18: Referring to Figure 31, relative to the structure shown in Figure 17, both the second output circuit 03 and the third output circuit 04 are connected to the shift output terminal CR through the third control circuit 07. <n>Coupled.

[0269] Example 19: Referring to Figure 32, relative to the structure shown in Figure 18, the second output circuit 03 and the shift output terminal CR are configured. <n>Coupled, and the third output circuit 04 is set to be connected to the shift output terminal CR through the third control circuit 07. <n>Coupled.

[0270] Example 20: Referring to Figure 33, relative to the structure shown in Figure 24, a third output circuit 04 is configured to connect to the shift output terminal CR via a third control circuit 07. <n>Coupled.

[0271] Example 21: Referring to Figure 34, compared to the structure shown in Figure 13, the second output circuit 03 is omitted, and a third output circuit 04 and a shift output terminal CR are provided. <n>Coupled.

[0272] It is understood that the embodiments described above in conjunction with Figures 13 to 34 are merely illustrative. Various modifications of the circuit based on any of the structures shown in Figures 1 to 12 should be included, and will not be elaborated upon here. For example, in Figures 22 to 33, the second clock terminal CKB coupled to the eighteenth transistor T18 can be replaced with the first clock terminal CKA.

[0273] Optionally, the transistors included in the shift register unit can all be P-type transistors, and the scan output terminal G <n>It can be used to couple to N-type transistors in pixels via gate lines. That is, as described above, the shift register unit provided in this embodiment can be an LTPS structure circuit, and the pixel circuit can be an oxide structure circuit. This shift register unit can be applied in an LTPO+ architecture. Furthermore, this LTPS structure shift register unit can achieve low-level secondary bootstrapping through a dummy output section, causing the scan output section to output to the scan output terminal G. <n>It reliably outputs low-potential signals, achieving sufficient noise reduction.

[0274] In summary, this disclosure provides a shift register unit. In this shift register unit, the input circuit can control the potentials of a first node and a second node. A first output circuit can respond to the potentials of the first and second nodes by controlling a second clock terminal or a first power supply terminal to output a signal to the shift output terminal. A second output circuit can respond to the potentials of the first and second nodes by controlling a first power supply terminal or a reference clock terminal to output a signal to the redundant output terminal. The second output circuit includes a capacitor coupled between the second node and the redundant output terminal, and correspondingly, the second output circuit can operate under the coupling effect of this capacitor. A third output circuit can respond to the potentials of the first and second nodes by controlling a third clock terminal or a second power supply terminal to output a signal to the scan output terminal. Thus, by flexibly setting the reference clock signal provided by the reference clock terminal, the second output circuit can maintain a stable potential of the first node, thereby enabling the third output circuit to reliably output a signal, such as a gate drive signal, to the scan output terminal, thereby reliably driving pixel emission and ensuring a better display effect on the display panel.

[0275] This disclosure also provides a method for driving a shift register unit, which can be used to drive a shift register unit as described in the above embodiments. As shown in FIG35, the method includes:

[0276] Step 3501, First stage: The input circuit controls the potential of the first node to the first potential and the potential of the second node to the second potential based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, and the first input signal provided by the first input terminal. The first output circuit responds to the potential of the first node by controlling the second clock terminal to conduct with the shift output terminal. The second output circuit responds to the potential of the first control node by controlling the first power supply terminal to conduct with the redundant output terminal. The third output circuit responds to the potential of the second control node by controlling the third clock terminal to conduct with the scan output terminal.

[0277] Step 3502, Second Stage: Based on the first clock signal, the second clock signal, and the first input signal, the input circuit controls the potential of the first node to the second potential and controls the potential of the second node to the first potential. The first output circuit responds to the potential of the second node by controlling the first power supply terminal and the shift output terminal to conduct. The second output circuit responds to the potential of the second node by controlling the reference clock terminal and the redundant output terminal to conduct, and adjusts the potential of the second node based on the potential of the redundant output terminal through coupling. The third output circuit responds to the potential of the second node by controlling the second power supply terminal and the scan output terminal to conduct.

[0278] Optionally, referring to Figure 34, taking the setting of coupling the gate of the nineteenth transistor T19 with the second child node Q2 as an example, and referring to Figure 36, the working process of the shift register unit is briefly described as follows:

[0279] In stage t01, the potentials of the enable signal provided by the enable signal terminal STV, the first clock signal provided by the first clock terminal CKA, and the third clock signal provided by the third clock terminal GCK are all low, while the potential of the second clock signal provided by the second clock terminal CKB is high. Accordingly, this enables the seventh transistor T7 to turn on and the ninth transistor T9 to turn off. This allows the low-potential enable signal to be transmitted to the first child node Q1 via the enabled seventh transistor T7. Furthermore, since the potential of the third power signal provided by the third power supply terminal VGL2 is low, the first transistor T1 can be turned on, allowing the low-potential enable signal transmitted to the first child node Q1 to be transmitted to the second child node Q2 via the enabled first transistor T1.

[0280] That is, in stage t01, the potentials of the first child node Q1 and the second child node Q2 can both be set to low potentials. Based on this, the eleventh transistor T11 and the twelfth transistor T12 can both be turned on, allowing the high-potential first power signal provided by the first power supply terminal VGH to be transmitted via the turned-on eleventh transistor T11 and twelfth transistor T12 to the gate of the tenth transistor T10 and the second node QB, respectively, thereby turning off the eighth transistor T8 and the tenth transistor T10. That is, in stage t01, the potential of the second node QB can also be set to low potentials.

[0281] With the potentials of the first child node Q1 and the second child node Q2 both low, and the potential of the second node QB high, the sixteenth transistor T16 and the twentieth transistor T20 can be turned off, while the fifteenth transistor T15 and the nineteenth transistor T19 can be turned on. This allows the high-potential second clock signal provided by the second clock terminal CKB to be transmitted to the shift output terminal CR via the turned-on fifteenth transistor T15. <n>And the low-potential third clock signal provided by the third clock terminal GCK is transmitted to the scan output terminal G via the turned-on nineteenth transistor T19. <n>That is, in this stage t01, the shift register unit can be shifted via the shift output terminal CR. <n>and scan output terminal G <n>The second clock signal is output at a high level and the third clock signal is output at a low level.

[0282] During stages t02 to t03, the potentials of the enable signal provided by the enable signal terminal STV and the first clock signal provided by the first clock terminal CKA are both high. The potential of the second clock signal provided by the second clock terminal CKB is first low and then high, and the potential of the third clock signal provided by the third clock terminal GCK is first high and then low. Furthermore, due to the coupling effect of the capacitor, the potentials of the second child node Q2 and the second node QB can be maintained at the low and high potentials of stage t01, respectively. That is, during stages t02 to t03, the sixteenth transistor T16 and the twentieth transistor T20 can both remain off, and the fifteenth transistor T15 and the nineteenth transistor T19 can both remain on. Correspondingly, this allows the shift register unit to first pass through the shift output terminal CR... <n>and scan output terminal G <n>The second clock signal, which is at a low level, and the third clock signal, which is at a high level, are output respectively, and then the output is shifted to the CR terminal. <n>and scan output terminal G <n>The second clock signal is output at a high level and the third clock signal is output at a low level.

[0283] In stage t04, the potential of the first clock signal provided by the first clock terminal CKA becomes low, while the potential of the turn-on signal provided by the turn-on signal terminal STV and the potential of the second clock signal provided by the second clock terminal CKB are both high, and the potential of the third clock signal provided by the third clock terminal GCK is low. Accordingly, the seventh transistor T7 can be turned on again, and the ninth transistor T9 can be turned off. This allows the high-potential turn-on signal to be transmitted to the first child node Q1 via the turned-on seventh transistor T7, and then to the second child node Q2 via the turned-on first transistor T1. That is, in stage t04, the potentials of both the first child node Q1 and the second child node Q2 can be set to high. Based on this, the eleventh transistor T11 and the twelfth transistor T12 can both be turned off, and the tenth transistor T10 remains off in response to the high-potential second clock signal. That is, in stage t04, the potential of the second node QB can remain high. With the potentials of the first child node Q1, the second child node Q2, and the second node QB all high, the sixteenth transistor T16 and the twentieth transistor T20 can be turned off, as can the fifteenth transistor T15 and the nineteenth transistor T19, thereby turning off the shift output terminal CR. <n>and scan output terminal G <n>Under the coupling effect of the capacitor, they remain at the high potential and low potential of the previous stage t03, respectively.

[0284] In stage t05, the potential of the second clock signal provided by the second clock terminal CKB becomes low, while the potentials of the first clock signal provided by the first clock terminal CKA, the turn-on signal provided by the turn-on signal terminal STV, and the third clock signal provided by the third clock terminal GCK are all high. Accordingly, the ninth transistor T9 and the tenth transistor T10 are both turned on, and the seventh transistor T7 is turned off. This allows the low-potential second clock signal to be transmitted to the second node QB via the turned-on tenth transistor T10. Based on this, the eighth transistor T8 is turned on. With both the eighth transistor T8 and the ninth transistor T9 turned on, the high-potential first power signal provided by the first power terminal VGH is further transmitted sequentially via the turned-on eighth transistor T8 and ninth transistor T9 to the first child node Q1, and then via the turned-on first transistor T1 to the second child node Q2. That is, in stage t05, the potentials of the first child node Q1 and the second child node Q2 can both be set to high, and the potential of the second node QB can be set to low.

[0285] With the potentials of the first child node Q1 and the second child node Q2 both high, and the potential of the second node QB low, the sixteenth transistor T16 and the twentieth transistor T20 can be turned on, while the fifteenth transistor T15 and the nineteenth transistor T19 can be turned off. This allows the first power signal provided by the first power supply terminal VGH to be transmitted to the shift output terminal CR via the turned-on sixteenth transistor T16. <n>And cause the low-potential second power supply signal provided by the second power supply terminal VGL1 to be transmitted to the scan output terminal G via the turned-on twentieth transistor T20. <n>That is, in this stage t05, the shift register unit can be shifted via the shift output terminal CR. <n>and scan output terminal G <n>It outputs a high-level first power supply signal and a low-level second power supply signal respectively.

[0286] It is understandable that the potential of the second power supply signal, which is generally low, is approximately -5 volts (V), and the potential of the third power supply signal, which is also low, is approximately -8V. Therefore, referring to the signal simulation diagram shown in Figure 37, it can be seen that after stage t05, the potential of the second node QB remains around -5V, while the potential of the output terminal G after scanning... <n>The output low-potential second power supply signal also remains at approximately -5V. This causes the gate-source voltage difference Vgs - threshold voltage Vth of the twentieth transistor T20 to be greater than 0, meaning the twentieth transistor T20 is in a floating state and cannot scan the output terminal G. <n>The coupled gate lines are adequately noise-damped. That is, during stage t04, the low voltage at the second node QB will be insufficient to maintain the scan output G. <n>The state of outputting a low-potential signal.

[0287] In this embodiment of the present disclosure, taking the structure shown in FIG13 as an example, that is, taking the shift register unit as including a second output circuit 03, and the reference clock terminal CKC coupled to the second output circuit 03 being shared with the first clock terminal CKA, FIG38 shows the corresponding signal timing diagram. Referring to FIG38, the working process of the shift register unit in one embodiment of the present disclosure is briefly described as follows:

[0288] In stage t01, the potentials of the enable signal provided by the enable signal terminal STV, the first clock signal provided by the first clock terminal CKA, and the third clock signal provided by the third clock terminal GCK are all low, while the potential of the second clock signal provided by the second clock terminal CKB is high. Accordingly, the seventh transistor T7 can be turned on, and the ninth transistor T9 can be turned off. This allows the low-potential enable signal to be transmitted to the first child node Q1 via the enabled seventh transistor T7. Furthermore, since the potential of the third power signal provided by the third power supply terminal VGL2 is low, the first transistor T1 can be turned on, allowing the low-potential enable signal transmitted to the first child node Q1 to be transmitted to the second child node Q2 via the enabled first transistor T1. That is, in stage t01, the potentials of both the first child node Q1 and the second child node Q2 can be set to low. Based on this, both the eleventh transistor T11 and the twelfth transistor T12 can be turned on. This allows the high-potential first power signal supplied by the first power supply terminal VGH to be transmitted via the turned-on eleventh and twelfth transistors T11 and T12 to the gate of the tenth transistor T10 and the second node QB, respectively, thereby turning off both the eighth transistor T8 and the tenth transistor T10. In other words, during this stage t01, the potential of the second node QB can be set to a low potential.

[0289] With the potentials of the first child node Q1 and the second child node Q2 both low, and the potential of the second node QB high, transistors 16, 18, and 20 can be turned off, while transistors 15, 17, and 19 can be turned on. This allows the high-potential second clock signal provided by the second clock terminal CKB to be transmitted to the shift output terminal CR via the turned-on 15th transistor T15. <n>This causes the high-potential first power supply signal provided by the first power supply terminal VGH to be transmitted to the redundant output terminal GD via the activated seventeenth transistor T17, and causes the low-potential third clock signal provided by the third clock terminal GCK to be transmitted to the scan output terminal G via the activated nineteenth transistor T19. <n>That is, in this stage t01, the shift register unit can be shifted via the shift output terminal CR. <n>and scan output terminal G <n>It outputs a high-level second clock signal and a low-level third clock signal, and outputs a high-level first power supply signal through the redundant output terminal GD.

[0290] During stages t02 to t03, the potentials of the enable signal provided by the enable signal terminal STV and the first clock signal provided by the first clock terminal CKA are both high. The potential of the second clock signal provided by the second clock terminal CKB is first low and then high, and the potential of the third clock signal provided by the third clock terminal GCK is first high and then low. Furthermore, due to the coupling effect of the capacitor, the potentials of the second sub-node Q2 and the second node QB can be maintained at the low and high potentials of stage t01, respectively. That is, during stages t02 to t03, the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 can all remain off, while the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 can all remain on. Correspondingly, this allows the shift register unit to first pass through the shift output terminal CR... <n>and scan output terminal G <n>The second clock signal, which is at a low level, and the third clock signal, which is at a high level, are output respectively, and then the output is shifted to the CR terminal. <n>and scan output terminal G <n>It outputs a high-level second clock signal and a low-level third clock signal, as well as a high-level first power supply signal continuously output through the redundant output terminal GD.

[0291] In stage t04, the potential of the first clock signal provided by the first clock terminal CKA becomes low, while the potential of the turn-on signal provided by the turn-on signal terminal STV and the potential of the second clock signal provided by the second clock terminal CKB are both high, and the potential of the third clock signal provided by the third clock terminal GCK is low. Accordingly, the seventh transistor T7 can be turned on again, and the ninth transistor T9 can be turned off. This allows the high-potential turn-on signal to be transmitted to the first child node Q1 via the turned-on seventh transistor T7, and then to the second child node Q2 via the turned-on first transistor T1. That is, in stage t04, the potentials of both the first child node Q1 and the second child node Q2 can be set to high. Based on this, the eleventh transistor T11 and the twelfth transistor T12 can both be turned off, and the tenth transistor T10 remains off in response to the high-potential second clock signal. That is, in stage t04, the potential of the second node QB can remain high. With the potentials of the first child node Q1, the second child node Q2, and the second node QB all high, the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 can all be turned off, as can the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19, thereby turning off the shift output terminal CR. <n>and scan output terminal G <n>Under the coupling effect of the capacitor, the potentials are maintained at the high and low levels of the previous stage t03, respectively, and the redundant output terminal GD is also maintained at the high level of the previous stage t03.

[0292] In stage t05, firstly, the potential of the second clock signal provided by the second clock terminal CKB becomes low, while the potentials of the first clock signal provided by the first clock terminal CKA and the third clock signal provided by the third clock terminal GCK both become high, and the enable signal provided by the enable signal terminal STV remains high. Accordingly, the ninth transistor T9 and the tenth transistor T10 are both enabled, and the seventh transistor T7 is turned off. This allows the low-potential second clock signal to be transmitted to the second node QB via the enabled tenth transistor T10. Based on this, the eighth transistor T8 is enabled. With both the eighth transistor T8 and the ninth transistor T9 enabled, the high-potential first power signal provided by the first power terminal VGH is transmitted sequentially to the first child node Q1 via the enabled eighth transistor T8 and the ninth transistor T9, and then to the second child node Q2 via the enabled first transistor T1. That is, in stage t05, the potentials of the first child node Q1 and the second child node Q2 can both be set to high, and the potential of the second node QB can be set to low.

[0293] With the potentials of the first child node Q1 and the second child node Q2 both high, and the potential of the second node QB low, transistors 16, 18, and 20 can be turned on, while transistors 15, 17, and 19 can be turned off. This allows the first power signal supplied by the first power supply terminal VGH to be transmitted to the shift output terminal CR via the turned-on 16th transistor T16. <n>This causes the high-level first clock signal provided by the first clock terminal CKA to be transmitted to the redundant output terminal GD, and causes the low-level second power signal provided by the second power terminal VGL1 to be transmitted to the scan output terminal G via the activated twentieth transistor T20. <n>That is, in this stage t05, the shift register unit can first be shifted through the shift output terminal CR. <n>and scan output terminal G <n>It outputs a high-level first power supply signal and a low-level second power supply signal respectively, and outputs a high-level first clock signal through the redundant output terminal GD.

[0294] Subsequently, when the potential of the first clock signal provided by the first clock signal terminal CKA drops to a low level again, the low-level first clock signal can be output through the redundant output terminal GD. Under the coupling effect of the third capacitor C3, the potential of the second node QB can be pulled down to an even lower potential, thereby enabling the twentieth transistor T20 to be fully turned on. This allows the low-level second power supply signal to be reliably transmitted to the scan output terminal G through the turned-on twentieth transistor T20. <n>To achieve sufficient noise reduction.

[0295] That is, after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the first clock signal provided by the first clock terminal CKA changes from a high potential to a low potential, thus being sufficient to maintain the value of the scanned output terminal G. <n>The output is in a low-potential state. Referring to the signal simulation diagram shown in Figure 39, it can be seen that after stage t04, when the potential of the first clock signal changes from high to low, the potential of the second node QB can be coupled down to approximately -15V. This is because the output terminal G is scanned... <n>The output low-potential second power supply signal is typically around -5V, which ensures that the gate-source voltage difference Vgs - threshold voltage Vth of the twentieth transistor T20 is less than 0. This means the twentieth transistor T20 can be fully turned on, thereby transmitting power to the scan output terminal G. <n>It reliably outputs a low-potential second power supply signal to achieve sufficient noise reduction.

[0296] Optionally, referring to the above description of the structure shown in Figure 13, and taking the structure shown in Figure 14 as an example, that is, taking the second output circuit 03 with the reference clock terminal CKC and the second clock terminal CKB sharing the same connection, Figure 40 schematically shows the signal timing diagram of another shift register unit. Referring to Figure 40, it can be seen that after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the second clock signal provided by the second clock terminal CKB changes from a high potential to a low potential, thus being sufficient to maintain the scanned output terminal G... <n>The low-potential output state also achieves sufficient noise reduction.

[0297] Optionally, in conjunction with the above description of the structure shown in Figure 13, taking the structure shown in Figure 15 as an example, that is, taking the reference clock terminal CKC coupled to the second output circuit 03 as independent of the first clock terminal CKA and the second clock terminal CKB, and the falling edge of the reference clock signal provided by the reference clock terminal CKC as being located after the falling edge of the second clock signal provided by the second clock terminal CKB, Figure 41 schematically shows the signal timing diagram of another shift register unit, and Figure 42 also shows the corresponding signal simulation diagram. Referring to Figure 41, it can be seen that after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the reference clock signal provided by the reference clock terminal CKC changes from a high potential to a low potential, thus being sufficient to maintain the scanned output terminal G... <n>The low-potential output state also achieves sufficient noise reduction.

[0298] Optionally, in conjunction with the above description of the structure shown in Figure 13, taking the structure shown in Figure 19 as an example, Figure 43 also schematically illustrates the signal timing diagram of another shift register unit. In Figure 43, the first clock terminal CKA, the second clock terminal CKB, and the third clock terminals GCK1 and GCK3 correspond to the shift register units coupled to the odd-numbered rows of pixels, that is, the clock terminals coupled to the odd-level shift register units; the first clock terminal CKA2, the second clock terminal CKB2, and the third clock terminals GCK2 and GCK4 correspond to the shift register units coupled to the even-numbered rows of pixels, that is, the clock terminals coupled to the even-level shift register units. The fourth child node QB2-1 is a node in the odd-level shift register unit; the fourth child node QB2-2 is a node in the even-level shift register unit. Furthermore, as can be seen from Figure 43, since the reference clock terminal CKC and the second clock terminal CKB are shared by the odd-level shift register unit, after stage t04, the potential of the fourth child node QB2-1 can be coupled to a lower potential each time the potential of the second clock signal provided by the second clock terminal CKB changes from a high potential to a low potential, thus being sufficient to maintain the scanned output terminal G. <n>The low-level output also achieves sufficient noise reduction. Since the reference clock terminal CKC of the even-numbered shift register unit is shared with the second clock terminal CKB2, after stage t04, the potential of the fourth child node QB2-2 can be coupled to a lower potential each time the potential of the second clock signal provided by the second clock terminal CKB2 changes from high to low, thus sufficiently maintaining the scanned output terminal G. <n>The low-potential output state also achieves sufficient noise reduction.

[0299] Optionally, in conjunction with the above description of the structure shown in Figure 13, taking the structure shown in Figure 21 as an example, Figure 44 also schematically illustrates another signal timing diagram of a shift register unit. As can be seen from Figure 44, since the reference clock terminal CKC is shared with the first clock terminal CKA, after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the first clock signal provided by the first clock terminal CKA changes from a high potential to a low potential, thus being sufficient to maintain the scanned output terminal G. <n>The low-potential output state also achieves sufficient noise reduction.

[0300] Optionally, taking the structure shown in Figure 23 as an example, Figure 45 shows the corresponding signal timing diagram. Referring to Figure 45, the operation of the shift register unit in another embodiment provided by this disclosure is briefly described below (the operation of the structure shown in Figure 44 can be referred to the following description, which will not be repeated above):

[0301] In stage t01, the potentials of the turn-on signal provided by the turn-on signal terminal STV, the first clock signal provided by the first clock terminal CKA, and the third clock signal provided by the third clock terminal GCK are all low, while the potential of the second clock signal provided by the second clock terminal CKB is high. Correspondingly, this allows the seventh transistor T7, the tenth transistor T10, and the thirteenth transistor T13 to all turn on, and the ninth transistor T9 to turn off. Furthermore, the low-potential turn-on signal can be transmitted to the first child node Q1 via the turned-on seventh transistor T7, and the low-potential third power signal provided by the third power supply terminal VGL2 can be transmitted to the third child node QB1 via the turned-on tenth transistor T10, and to the sixth child node QB4 via the turned-on thirteenth transistor T13. Furthermore, since the third power supply signal is at a low potential, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 can all be turned on. Correspondingly, the low-potential turn-on signal transmitted to the first child node Q1 can be transmitted via the turned-on first transistor T1 to the second child node Q2, and then via the turned-on fourth transistor T4 to the child node Q3. Similarly, the low-potential third power supply signal transmitted to the third child node QB1 can be transmitted via the turned-on second transistor T2 to the fourth child node QB2, and then via the turned-on fifth transistor T5 to the fifth child node QB3. That is, in this stage t01, the potentials of the first child node Q1, the second child node Q2, the child node Q3, the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 can all be set to a low potential.

[0302] With the potentials of the first child node Q1, the second child node Q2, the child node Q3, the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 all at low potentials, the eighth transistor T8, the eleventh transistor T11, and the fourteenth transistor T14 can all be turned on. This allows the low-potential first clock signal provided by the first clock terminal CKA to be transmitted to the third child node QB1 and the sixth child node QB4 via the turned-on eleventh transistor T11 and fourteenth transistor T14, respectively, further ensuring that the potentials of the third child node QB1 and the sixth child node QB4 remain low. With all node potentials at low potentials, the sixth transistor T6, and the fifteenth transistor T15 through the twentieth transistor T20 can all be turned on. Because in this stage t01, the potential of the second clock signal is high and the potential of the third clock signal is low, the shift register unit can be activated via the shift output terminal CR. <n>and scan output terminal G <n>It outputs a high-level signal and a low-level signal respectively, and outputs the high-level signal through the redundant output terminal GD.

[0303] In stage t02, the potentials of the turn-on signal provided by the turn-on signal terminal STV, the first clock signal provided by the first clock terminal CKA, and the second clock signal provided by the second clock terminal CKB are all high, while the potential of the third clock signal provided by the third clock terminal GCK is low. Correspondingly, the first transistor T1, the tenth transistor T10, the thirteenth transistor T13, and the ninth transistor T9 are all turned off. Furthermore, due to capacitive coupling, the potential of the first sub-node Q1 can be maintained at the low potential of stage t01. Correspondingly, the potentials of the second sub-node Q2 and the sub-node Q3 can also be maintained at low potentials, thus allowing the eleventh transistor T11 and the fourteenth transistor T14 to remain on. This allows the high-potential first clock signal to be transmitted via the on-screen eleventh transistor T11 and fourteenth transistor T14 to the third sub-node QB1 and the sixth sub-node QB4, respectively, and then via the on-screen second transistor T2 and the fifth transistor T5 to the fourth sub-node QB2 and the fifth sub-node QB3, respectively. That is, in this stage t02, the potentials of the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 can all be set to high potentials. The potentials of the first child node Q1, the second child node Q2, and the child node Q3 can all be kept at low potentials.

[0304] With the potentials of the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 all high, and the potentials of the first child node Q1, the second child node Q2, and the child node Q3 all low, transistors T15, T17, and T19 can be turned on, while transistors T8, T16, T18, and T20 can be turned off. This allows the high-potential second clock signal provided by the second clock terminal CKB to be transmitted to the shift output terminal CR via the turned-on fifteenth transistor T15. <n>This causes the high-potential first power supply signal provided by the first power supply terminal VGH to be transmitted to the redundant output terminal GD via the activated seventeenth transistor T17, and causes the low-potential third clock signal provided by the third clock terminal GCK to be transmitted to the scan output terminal G via the activated nineteenth transistor T19. <n>That is, in this stage t02, the shift register unit can be shifted through the shift output terminal CR. <n>and scan output terminal G <n>It outputs a high-level second clock signal and a low-level third clock signal, and outputs a high-level first power supply signal through the redundant output terminal GD.

[0305] In stage t03, the potential of the third clock signal provided by the third clock terminal GCK becomes high, the potential of the second clock signal provided by the second clock terminal CKB becomes low, and the potential of the turn-on signal provided by the turn-on signal terminal STV and the potential of the first clock signal provided by the first clock terminal CKA remain high. Furthermore, due to capacitive coupling, the potentials of the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 can all remain at the high potential of stage t02. The potentials of the first child node Q1, the second child node Q2, and the child node Q3 can all remain at the low potential of stage t02. That is, in stage t03, the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 can remain off, while the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 can remain on. Correspondingly, the shift register unit can be shifted through the shift output terminal CR. <n>and scan output terminal G <n>It outputs a low-level second clock signal and a high-level third clock signal respectively, and continues to output a high-level first power supply signal through the redundant output terminal GD.

[0306] In stage t04, the potential of the first clock signal provided by the first clock terminal CKA becomes low. Simultaneously, the potential of the turn-on signal provided by the turn-on signal terminal STV and the potential of the second clock signal provided by the second clock terminal CKB are both high, while the potential of the third clock signal provided by the third clock terminal GCK is low. Accordingly, the seventh transistor T7, the tenth transistor T10, and the thirteenth transistor T13 can be turned on again, and the ninth transistor T9 can be turned off. This allows the high-potential turn-on signal to be transmitted via the turned-on seventh transistor T7 to the first child node Q1, then via the turned-on first transistor T1 to the second child node Q2, and via the turned-on fourth transistor T4 to the child node Q3. Similarly, the low-potential third power supply signal provided by the third power supply terminal VGL2 can be transmitted via the turned-on tenth transistor T10 and the thirteenth transistor T13 to the third child node QB1 and the sixth child node QB4, then via the turned-on second transistor T2 to the fourth child node QB2, and via the turned-on fifth transistor T5 to the fifth child node QB3. That is, in this stage t04, the potentials of the first child node Q1, the second child node Q2, and the child node Q3 can all be set to high potentials, while the potentials of the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 can all be set to low potentials.

[0307] With the potentials of the first child node Q1, the second child node Q2, and the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 all at high potentials, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 can all be turned off, while the eighth transistor T8, the sixteenth transistor T16, the sixth transistor T6, the eighteenth transistor T18, and the twentieth transistor T20 can all be turned on. This allows the high-potential first power signal supplied by the first power supply terminal VGH to be transmitted to the shift output terminal CR via the turned-on sixteenth transistor T16. <n>This causes the high-level second clock signal provided by the second clock terminal CKB to be transmitted to the redundant output terminal GD via the activated eighteenth transistor T18, and causes the low-level second power supply signal provided by the second power supply terminal VGL1 to be transmitted to the scan output terminal G via the activated twentieth transistor T20. <n>That is, in this stage t04, the shift register unit can be shifted via the shift output terminal CR. <n>and scan output terminal G <n>It outputs a high-level first power supply signal and a low-level second power supply signal respectively, and outputs a high-level second clock signal through the redundant output terminal GD.

[0308] In stage t05, the potentials of the first child node Q1, the second child node Q2, and the third child node Q3 are all kept high, while the potentials of the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 are all kept low. Correspondingly, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are all kept off, while the eighth transistor T8, the sixteenth transistor T16, the sixth transistor T6, the eighteenth transistor T18, and the twentieth transistor T20 are all kept on. Consequently, the high-potential first power signal provided by the first power supply terminal VGH can continue to be transmitted to the shift output terminal CR via the on-screen sixteenth transistor T16. <n>This allows the second clock signal provided by the second clock terminal CKB to be transmitted to the redundant output terminal GD via the activated eighteenth transistor T18, and allows the low-potential second power supply signal provided by the second power supply terminal VGL1 to continue being transmitted to the scan output terminal G via the activated twentieth transistor T20. <n>.

[0309] Furthermore, since the potential of the second clock signal provided by the second clock terminal CKB becomes low, the potential of the redundant output terminal GD can be controlled to become low in this stage t05. Under the coupling effect of the third capacitor C3, the potential of the fifth sub-node QB3 can be pulled down to an even lower potential first, so that the sixth transistor T6 is fully turned on. This allows the lower potential of the fifth sub-node QB3 to be transmitted to the fourth sub-node QB2 through the fully turned-on sixth transistor T6, pulling the potential of the fourth sub-node QB2 down to an even lower potential, so that the twentieth transistor T20 is fully turned on. This allows the low-potential second power supply signal to be reliably transmitted to the scan output terminal G through the turned-on twentieth transistor T20. <n>This is to achieve sufficient noise reduction. That is, in this stage t05, the shift register unit can be shifted through the shift output terminal CR. <n>and scan output terminal G <n>It continues to output a high-level first power supply signal and a low-level second power supply signal, and outputs a low-level second clock signal through the redundant output terminal GD.

[0310] In stage t06, the potentials of the first child node Q1, the second child node Q2, and the third child node Q3 are all kept high, while the potentials of the third child node QB1, the fourth child node QB2, the fifth child node QB3, and the sixth child node QB4 are all kept low. Correspondingly, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are all kept off, while the eighth transistor T8, the sixteenth transistor T16, the sixth transistor T6, the eighteenth transistor T18, and the twentieth transistor T20 are all kept on. Consequently, the high-potential first power signal provided by the first power supply terminal VGH can continue to be transmitted to the shift output terminal CR via the on-screen sixteenth transistor T16. <n>This allows the second clock signal provided by the second clock terminal CKB to be transmitted to the redundant output terminal GD via the activated eighteenth transistor T18, and allows the low-potential second power supply signal provided by the second power supply terminal VGL1 to continue being transmitted to the scan output terminal G via the activated twentieth transistor T20. <n>.

[0311] Furthermore, since the potential of the second clock signal provided by the second clock terminal CKB becomes high again, the potential of the redundant output terminal GD can be controlled to become high in this stage t06. Under the coupling effect of the third capacitor C3, the potential of the fifth sub-node QB3 can be raised first, causing the sixth transistor T6 to turn off. In this way, it can be ensured that the potential of the fourth sub-node QB2 remains at the low potential of stage t05 and is not affected by the raised potential of the fifth sub-node QB3. Correspondingly, the twentieth transistor T20 can be kept on, thereby allowing the low-potential second power supply signal to be reliably transmitted to the scan output terminal G through the on-screen twentieth transistor T20. <n>This is to achieve sufficient noise reduction. That is, in stage t06, the shift register unit can be shifted via the shift output terminal CR. <n>and scan output terminal G <n>The system continues to output a high-level first power supply signal and a low-level second power supply signal, and outputs a high-level second clock signal via the redundant output terminal GD. Based on the timing diagram shown in Figure 45, Figure 46 also schematically shows the corresponding signal simulation diagram.

[0312] In summary, this disclosure provides a driving method for a shift register unit. In this method, the input circuit can control the potentials of a first node and a second node. The first output circuit can respond to the potentials of the first and second nodes by controlling a second clock terminal or a first power supply terminal to output a signal to the shift output terminal. The second output circuit can respond to the potentials of the first and second nodes by controlling a first power supply terminal or a reference clock terminal to output a signal to a redundant output terminal, and can adjust the potential of the first node based on the potential of the redundant output terminal through coupling. The third output circuit can respond to the potentials of the first and second nodes by controlling a third clock terminal or a second power supply terminal to output a signal to the scan output terminal. Thus, by flexibly setting the reference clock signal provided by the reference clock terminal, the second output circuit can maintain a stable potential for the first node, thereby enabling the third output circuit to reliably output signals, such as gate drive signals, to the scan output terminal, thereby reliably driving pixel emission and ensuring a good display effect on the display panel.

[0313] This disclosure also provides a gate driving circuit. The gate driving circuit includes at least two cascaded shift register units (GOAs) as described above.

[0314] For example, the first input IN1 of the first-stage shift register unit GOA-1 can be coupled to the enable signal STV; in each stage of the shift register unit other than the first-stage shift register unit GOA-1, the first input IN1 of each stage can be coupled to the shift output CR of the cascaded previous stage shift register unit. <n>Coupled.

[0315] Optionally, taking the structure shown in Figure 19 as an example, Figure 47 shows a schematic diagram of a gate drive circuit. Referring to Figure 47, it can be further seen that odd-numbered shift register units (e.g., GOA-1, GOA-3, and GOA-5) and even-numbered shift register units (e.g., GOA-2 and GOA-4) can be coupled to different clock terminals respectively, and the first-stage shift register unit GOA-1 can also be coupled to the enable signal terminal STV. The remaining shift register units can be coupled to each other, as not shown in Figure 47.

[0316] Alternatively, taking the structure shown in Figure 23 as an example, Figure 48 shows a schematic diagram of another gate drive circuit. Figure 49 shows a schematic diagram of yet another gate drive circuit.

[0317] Referring to Figure 48, it can be seen that odd-level shift register units (e.g., GOA-1) can be coupled to the first clock terminal CKA, the second clock terminal CKB, and the third clock terminal GCK1, respectively. Even-level shift register units (e.g., GOA-2) can be coupled to the first clock terminal CKA2, the second clock terminal CKB2, and the third clock terminal GCK2, respectively. The first-level shift register unit GOA-1 can also be coupled to the enable signal terminal STV. Furthermore, odd-level shift register units can be coupled to each other, and even-level shift register units can be coupled to each other. That is, for example, the shift output terminal CR of the first-level shift register unit GOA-1... <1> It can be coupled to the first input IN1 (not shown in the figure) of the third-stage shift register unit GOA-3; the shift output CR of the third-stage shift register unit GOA-3 <3> It can be coupled to the fifth-stage shift register unit GOA-5; the shift output terminal CR of the second-stage shift register unit GOA-2 <2> It can be coupled to the fourth-level shift register unit GOA-4; and so on.

[0318] Referring to Figure 49, it can be seen that all shift register units (e.g., GOA-1, GOA-2, and GOA-3) are coupled to the same first clock terminal CKA and second clock terminal CKB. Only odd-numbered shift register units (e.g., GOA-1) are coupled to the third clock terminal GCK1, and even-numbered shift register units (e.g., GOA-2) are coupled to the third clock terminal GCK2. The first-stage shift register unit GOA-1 can also be coupled to the enable signal terminal STV, and each shift register unit can be coupled to the others. That is, the shift output terminal CR of the first-stage shift register unit GOA-1... <1> It can be coupled to the second-stage shift register unit GOA-2; the shift output terminal CR of the second-stage shift register unit GOA-2 <2> It can be coupled to the third-level shift register unit GOA-3; and so on.

[0319] That is, there can be one set of first clock terminal CKA and second clock terminal CKB, or there can be multiple sets of first clock terminal CKA and second clock terminal CKB. This disclosure does not limit this.

[0320] It is understood that since the gate drive circuit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the gate drive circuit will not be described again here for the sake of brevity.

[0321] This disclosure also provides a display device. As shown in FIG50, the display device includes: a display panel 100, and a gate driving circuit 000 as described above.

[0322] The display panel 100 includes multiple pixels. The gate driving circuit 000 is coupled to the multiple pixels and is used to transmit gate driving signals to the multiple pixels to drive the multiple pixels to emit light.

[0323] Of course, in some embodiments, the gate driving circuit 000 here can also be a circuit that provides other display driving signals to the pixel, such as a light-emitting driving circuit that provides light-emitting control signals to the pixel.

[0324] It is understood that since the display device can have essentially the same technical effect as the gate drive circuit described in the previous embodiments, the technical effect of the display device will not be repeated here for the sake of brevity.

[0325] Optionally, the display device can be any product or component with display functionality, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, or navigator.

[0326] It is understood that the terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0327] For example, the words "first," "second," or "third," and similar terms used in this patent application specification and claims, do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0328] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0329] The word "includes" or similar terms means that the elements or objects preceding "includes" or "include" cover the elements or objects listed after "includes" or "includes" and their equivalents, but do not exclude other elements or objects.

[0330] "Up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Coupled" or "coupled" refers to electrical coupling.

[0331] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0332] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the gate drive circuit, shift register unit, each circuit and each sub-circuit described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here.

[0333] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register unit, comprising: an input circuit coupled to a first clock terminal, a second clock terminal, a first input terminal, a first node and a second node respectively, and configured to control a potential of the first node and a potential of the second node based on a first clock signal provided by the first clock terminal, a second clock signal provided by the second clock terminal, and a first input signal provided by the first input terminal; a first output circuit coupled to the first node, the second node, the second clock terminal, a first power terminal and a shift output terminal respectively, and configured to control a conduction between the second clock terminal and the shift output terminal in response to the potential of the first node, and to control a conduction between the first power terminal and the shift output terminal in response to the potential of the second node, wherein the shift output terminal is configured to be coupled to a first input terminal of another stage of shift register unit in cascade; a second output circuit coupled to a first control node, the second node, the first power terminal, a reference clock terminal and a redundant output terminal respectively, and configured to control a conduction between the first power terminal and the redundant output terminal in response to a potential of the first control node, to control a conduction between the reference clock terminal and the redundant output terminal in response to the potential of the second node, and to include a first capacitor coupled between the second node and the redundant output terminal, wherein the first control node is the first node or is coupled to the shift output terminal; a third output circuit coupled to a second control node, the second node, a third clock terminal, a second power terminal and a scan output terminal respectively, and configured to control a conduction between the third clock terminal and the scan output terminal in response to a potential of the second control node, and to control a conduction between the second power terminal and the scan output terminal in response to the potential of the second node, wherein the scan output terminal is configured to be coupled to a pixel in a display panel, and the second control node is the first node or is coupled to the shift output terminal.

2. The shift register cell of claim 1, wherein, the reference clock terminal is shared with the first clock terminal; or, the reference clock terminal is shared with the second clock terminal; or, the reference clock terminal is independent of the first clock terminal and the second clock terminal, and a rising edge of a reference clock signal provided by the reference clock terminal is after a rising edge of the second clock signal provided by the second clock terminal.

3. The shift register cell of claim 1 or 2, wherein, the first node includes a first sub-node and a second sub-node, the input circuit is coupled to the first sub-node, the first output circuit is coupled to the second sub-node, the first control node is the first sub-node or the second sub-node, and the second control node is the first sub-node or the second sub-node, and the shift register unit further comprises: a first control circuit coupled to a third power terminal, the first sub-node and the second sub-node respectively, and configured to control a conduction between the first sub-node and the second sub-node in response to a third power signal provided by the third power terminal.

4. The shift register cell of claim 3, wherein, the first control circuit includes a first transistor. A gate of the first transistor is coupled with the third power supply end, a first pole of the first transistor is coupled with the first sub-node, and a second pole of the first transistor is coupled with the second sub-node.

5. The shift register cell of any one of claims 1 to 4, wherein, The second node comprises a third sub-node and a fourth sub-node; the input circuit and the first output circuit are coupled with the third sub-node, and the second output circuit and the third output circuit are coupled with the fourth sub-node; the shift register unit further comprises: A second control circuit is coupled with the third sub-node, the fourth sub-node and the third power supply end, and is configured to control the third sub-node and the fourth sub-node in response to a third power supply signal provided by the third power supply end.

6. The shift register cell of claim 5, wherein, The second control circuit comprises a second transistor. A gate of the second transistor is coupled with the third power supply end, a first pole of the second transistor is coupled with the third sub-node, and a second pole of the second transistor is coupled with the fourth sub-node.

7. The shift register cell of claim 5, wherein, The second control circuit comprises two second transistors connected in series. Gates of the two second transistors are coupled with the third power supply end, first poles of the two second transistors are coupled with the third sub-node and the fourth sub-node respectively, and second poles of the two second transistors are coupled with a series connection node; the shift register unit further comprises: An anti-leakage circuit is coupled with the fourth sub-node, a fourth power supply end and the series connection node respectively, and is configured to control the fourth power supply end and the series connection node in response to a potential of the fourth sub-node.

8. The shift register cell of claim 7, wherein, The anti-leakage circuit comprises a third transistor. A gate of the third transistor is coupled with the fourth sub-node, a first pole of the third transistor is coupled with the fourth power supply end, and a second pole of the third transistor is coupled with the series connection node.

9. The shift register cell of claim 5, wherein, The second control circuit is further coupled with the first node, and is further configured to control the third sub-node and the fourth sub-node in response to the third power supply signal and a potential of the first node.

10. The shift register cell of claim 9, wherein, The second control circuit comprises two second transistors connected in series. Gates of the two second transistors are coupled with the third power supply end and the first node respectively, first poles of the two second transistors are coupled with the third sub-node and the fourth sub-node respectively, and second poles of the two second transistors are coupled.

11. The shift register cell of any one of claims 1 to 10, wherein, Any one of the first control node and the second control node comprises a first control sub-node and a second control sub-node; the first control sub-node is the first node or is coupled with the shift output end, in a case where the any one of the control nodes is the second control node, the third output circuit is coupled with the second control sub-node, and in a case where the any one of the control nodes is the first control node and the second control node, the second output circuit and the third output circuit are both coupled with the second control sub-node; the shift register unit further comprises: A third control circuit is coupled with the third power supply end, the first control sub-node and the second control sub-node respectively, and is configured to control the third sub-node and the fourth sub-node in response to a third power supply signal provided by the third power supply end. The child node is coupled and configured to control the on-off of the first control sub-node and the second control sub-node in response to a third power signal provided by the third power terminal.

12. The shift register cell of claim 11, wherein, The third control circuit comprises a fourth transistor. The gate of the fourth transistor is coupled with the third power terminal, the first pole of the fourth transistor is coupled with the first control sub-node, and the second pole of the fourth transistor is coupled with the second control sub-node.

13. The shift register cell of any one of claims 1 to 12, wherein, The second node comprises a third sub-node and a fifth sub-node; the input circuit, the first output circuit and the third output circuit are coupled with the third sub-node, and the second output circuit is coupled with the fifth sub-node; the shift register unit further comprises: A fourth control circuit is coupled with the third power terminal, the third sub-node and the fifth sub-node, and configured to control the on-off of the third sub-node and the fifth sub-node in response to a third power signal provided by the third power terminal, and control the on-off of the third sub-node and the fifth sub-node in response to the potential of the fifth sub-node.

14. The shift register cell of claim 13, wherein, The fourth control circuit comprises a fifth transistor and a sixth transistor. The gate of the fifth transistor is coupled with the third power terminal, the first pole of the fifth transistor is coupled with the third sub-node, and the second pole of the fifth transistor is coupled with the fifth sub-node. The gate and the second pole of the sixth transistor are both coupled with the fifth sub-node, and the first pole of the sixth transistor is coupled with the third sub-node.

15. The shift register cell of any one of claims 1 to 14, wherein, The input circuit comprises: A first input sub-circuit is coupled with the first clock terminal, the first input terminal, the first node, the second node, the second clock terminal and the first power terminal, and configured to control the on-off of the first input terminal and the first node in response to the first clock signal, and control the on-off of the first power terminal and the first node in response to the potential of the second node and the second clock signal, so as to control the potential of the first node; A second input sub-circuit is coupled with an input control terminal, a second input terminal, the first node and the second node, and configured to control the on-off of the second input terminal and the second node in response to an input control signal provided by the input control terminal, and control the on-off of the input control terminal and the second node in response to the potential of the first node, so as to control the potential of the second node; wherein the input control terminal and the second input terminal are the first power terminal and the second clock terminal respectively; or, the input control terminal and the second input terminal are the first clock terminal and the third power terminal respectively. The first input sub-circuit comprises a seventh transistor, an eighth transistor and a ninth transistor; and the second input sub-circuit comprises a tenth transistor and an eleventh transistor.

16. The shift register cell of claim 15, wherein, The gate of the seventh transistor is coupled with the first clock terminal, the first pole of the seventh transistor is coupled with the first input terminal, and the second pole of the seventh transistor is coupled with the first node. The gate of the tenth transistor is coupled with the input control terminal, the first pole of the tenth transistor is coupled with the second input terminal, the second pole of the tenth transistor is coupled with the first node, and the third pole of the tenth transistor is coupled with the second node. A gate of the eighth transistor is coupled with the second node, a first pole of the eighth transistor is coupled with the first power supply end, and a second pole of the eighth transistor is coupled with a first pole of the ninth transistor; A gate of the ninth transistor is coupled with the second clock end, and a second pole of the ninth transistor is coupled with the first node; A gate of the tenth transistor is coupled with the input control end, a first pole of the tenth transistor is coupled with the second input end, and a second pole of the tenth transistor is coupled with the second node; A gate of the eleventh transistor is coupled with the first node, a first pole of the eleventh transistor is coupled with the input control end, and a second pole of the eleventh transistor is coupled with the second node.

17. The shift register cell of claim 15, wherein, When the input control end and the second input end are the first power supply end and the second clock end respectively, the second input sub-circuit further includes a second capacitor coupled between the second input end and the input control end, and the shift register unit further includes: A fifth control circuit is coupled with the first node, the input control end and the second input sub-circuit respectively, and is configured to control the input control end and the second input sub-circuit according to a potential of the first node. The fifth control circuit includes a twelfth transistor; 18. The shift register cell of claim 17, wherein, A gate of the twelfth transistor is coupled with the first node, a first pole of the twelfth transistor is coupled with the input control end, and a second pole of the twelfth transistor is coupled with the second input sub-circuit. The second node includes a third sub-node and a sixth sub-node; the first input sub-circuit, the second input sub-circuit, the first output circuit and the third output circuit are coupled with the third sub-node, and the fourth control circuit included in the shift register unit is coupled with the sixth sub-node; and the input circuit further includes:

19. The shift register cell of any of claims 15 to 18, wherein, A third input sub-circuit is coupled with the input control end, the second input end, the first node and the sixth sub-node respectively, and is configured to control the second input end and the sixth sub-node according to the input control signal, and control the input control end and the sixth sub-node according to the potential of the first node. The third input sub-circuit includes a thirteenth transistor and a fourteenth transistor; 20. The shift register cell of claim 19, wherein, A gate of the thirteenth transistor is coupled with the input control end, a first pole of the thirteenth transistor is coupled with the second input end, and a second pole of the thirteenth transistor is coupled with the second node; A gate of the fourteenth transistor is coupled with the first node, a first pole of the fourteenth transistor is coupled with the input control end, and a second pole of the fourteenth transistor is coupled with the second node. The first output circuit includes a fifteenth transistor, a sixteenth transistor and a third capacitor; the second output circuit further includes a seventeenth transistor and an eighteenth transistor; and the third output circuit includes a nineteenth transistor and a twentieth transistor; 21. The shift register cell of any one of claims 1 to 20, wherein, A gate of the fifteenth transistor is coupled with the first node, a first pole of the fifteenth transistor is coupled with the third sub-node, and a second pole of the fifteenth transistor is coupled with the third sub-node; ​ a second terminal of the fifteenth transistor is coupled with the shift output terminal; a gate of the sixteenth transistor is coupled with the second node, a first terminal of the sixteenth transistor is coupled with the first power supply terminal, and a second terminal of the sixteenth transistor is coupled with the shift output terminal; the third capacitor is coupled between the first node and the shift output terminal; a gate of the seventeenth transistor is coupled with the first control node, a first terminal of the seventeenth transistor is coupled with the first power supply terminal, and a second terminal of the seventeenth transistor is coupled with the redundancy output terminal; a gate of the eighteenth transistor is coupled with the second node, a first terminal of the eighteenth transistor is coupled with the reference clock terminal, and a second terminal of the eighteenth transistor is coupled with the redundancy output terminal; a gate of the nineteenth transistor is coupled with the second control node, a first terminal of the nineteenth transistor is coupled with the third clock terminal, and a second terminal of the nineteenth transistor is coupled with the scan output terminal; a gate of the twentieth transistor is coupled with the second node, a first terminal of the twentieth transistor is coupled with the second power supply terminal, and a second terminal of the twentieth transistor is coupled with the scan output terminal.

22. The shift register cell of any one of claims 1 to 21, wherein, The shift register unit includes P-type transistors, and the scan output terminal is coupled with N-type transistors in the pixels through a gate line.

23. A driving method of a shift register unit, for driving the shift register unit as claimed in any one of claims 1 to 22, the method comprising: in a first stage, an input circuit controls a potential of a first node to be a first potential and controls a potential of a second node to be a second potential based on a first clock signal provided by a first clock terminal, a second clock signal provided by a second clock terminal, and a first input signal provided by a first input terminal, a first output circuit controls the second clock terminal and a shift output terminal to be conductive in response to the potential of the first node, and a second output circuit controls a first power supply terminal and a redundancy output terminal to be conductive in response to the potential of the first control node; in a second stage, the input circuit controls the potential of the first node to be the second potential and controls the potential of the second node to be the first potential based on the first clock signal, the second clock signal, and the first input signal, the first output circuit controls the first power supply terminal and the shift output terminal to be conductive in response to the potential of the second node, the second output circuit controls a reference clock terminal and the redundancy output terminal to be conductive in response to the potential of the second node and adjusts the potential of the second node based on a potential of the redundancy output terminal through a coupling effect, and the third output circuit controls a second power supply terminal and the scan output terminal to be conductive in response to the potential of the second node. at least two shift register units as claimed in any one of claims 1 to 22 are cascaded.

24. A gate drive circuit, the gate drive circuit comprising: a display panel, and a gate driving circuit as claimed in claim 24, the display panel including a plurality of pixels.

25. A display device comprising: ​ The gate driving circuit is coupled with the plurality of pixels and is configured to transmit a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

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