Display panel and display apparatus

Abstract

Embodiments of the present invention relate to the field of display, and provide a display panel and a display apparatus, used for reducing the electrostatic risk of the display panel. The display panel comprises: a display area and a non-display area; a substrate; a light-emitting device layer, comprising a first electrode layer, a light-emitting functional layer, and a second electrode layer, wherein the second electrode layer is located on the side of the light-emitting functional layer away from the substrate, the first electrode layer comprises an overlapping portion, and the overlapping portion is located in the non-display area; a first power bus, located in the non-display area and located on the side of the first electrode layer close to the substrate, wherein the overlapping portion is electrically connected to the second electrode layer and the first power bus; auxiliary power lines, at least partially located in the display area and located on the side of the first electrode layer close to the substrate; and power supply connecting lines, at least partially located in the non-display area, wherein each auxiliary power line is electrically connected to the first power bus by means of at least one power supply connecting line, and the power supply connecting lines are located between the first electrode layer and the substrate.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202410674990.0, filed with the State Intellectual Property Office of China on May 28, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Organic light-emitting diode (OLED) display panels include light-emitting devices, which include an anode, a light-emitting functional layer, and a cathode.

[0004] Currently, a common practice is to place an overlap portion on the same layer as the anode in the non-display area. This overlap portion is used to transmit the negative power signal provided by the power bus to the cathode and some auxiliary power lines within the plane. However, the existing overlap portion design poses a significant risk of electrostatic discharge (ESD).

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a display panel and a display device to reduce the risk of electrostatic discharge from the display panel.

[0007] On one hand, embodiments of the present invention provide a display panel, including:

[0008] Display area and non-display area;

[0009] Substrate;

[0010] The light-emitting device layer includes a first electrode layer, a light-emitting functional layer, and a second electrode layer. The second electrode layer is located on the side of the light-emitting functional layer away from the substrate. The first electrode layer includes an overlap portion located in the non-display area.

[0011] The first power bus is located in the non-display area and on the side of the first electrode layer near the substrate. The overlapping portion is electrically connected to both the second electrode layer and the first power bus.

[0012] An auxiliary power line is at least partially located in the display area and on the side of the first electrode layer closest to the substrate;

[0013] A power connection line, at least partially located in the non-display area, is electrically connected to the auxiliary power line and the first power bus via at least one of the power connection lines, which is located between the first electrode layer and the substrate.

[0014] On the other hand, embodiments of the present invention provide a display device including the above-described display panel.

[0015] One of the above technical solutions has the following beneficial effects:

[0016] In this embodiment of the invention, the overlapping portion is electrically connected to both the second electrode layer and the first power bus. By providing a power connection line, the electrical connection between the first power bus and the auxiliary power line can be achieved, which helps to reduce the overall impedance of the first power bus and improve signal uniformity. In addition, the provision of the power connection line can also reduce the size of the overlapping portion, thereby reducing the accumulation of static electricity during the manufacturing process of the display panel and improving the reliability of signal transmission into the panel. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a top view of a display panel in the prior art;

[0019] Figure 2 is a cross-sectional view of Figure 1 along the A1-A2 direction;

[0020] Figure 3 is a schematic diagram of a display panel in the manufacturing process of the prior art;

[0021] Figure 4 is a top view of a display panel provided in an embodiment of the present invention;

[0022] Figure 5 is a cross-sectional view of Figure 4 along B1-B2;

[0023] Figure 6 is a schematic diagram of the structure of the display panel provided in the embodiment of the present invention during the manufacturing process;

[0024] Figure 7 is another top view of the display panel provided in an embodiment of the present invention;

[0025] Figure 8 is a cross-sectional view of Figure 7 along C1-C2;

[0026] Figure 9 is another sectional view of Figure 7 along C1-C2;

[0027] Figure 10 is another top view of the display panel provided in an embodiment of the present invention;

[0028] Figure 11 is a cross-sectional view of Figure 10 along D1-D2;

[0029] Figure 12 is another top view of the display panel provided in an embodiment of the present invention;

[0030] Figure 13 is another top view of the display panel provided in an embodiment of the present invention;

[0031] Figure 14 is a schematic diagram of a local membrane structure corresponding to Figure 13;

[0032] Figure 15 is another top view of the display panel provided in an embodiment of the present invention;

[0033] Figure 16 is a schematic diagram of a local membrane structure corresponding to Figure 15;

[0034] Figure 17 is a schematic diagram of a partial membrane structure corresponding to Figures 14 and 16 provided in an embodiment of the present invention;

[0035] Figure 18 is another top view of the display panel provided in an embodiment of the present invention;

[0036] Figure 19 is a schematic diagram of a first shift register provided in an embodiment of the present invention;

[0037] Figure 20 is a schematic diagram of a circuit structure of the first sub-shift register provided in an embodiment of the present invention;

[0038] Figure 21 is a schematic diagram of a membrane structure of the first sub-shift register corresponding to Figure 20;

[0039] Figure 22 is a schematic diagram of a second shift register provided in an embodiment of the present invention;

[0040] Figure 23 is a schematic diagram of a circuit structure of the second sub-shift register provided in an embodiment of the present invention;

[0041] Figure 24 is a schematic diagram of a membrane structure of the second sub-shift register corresponding to Figure 23;

[0042] Figure 25 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0043] Figure 26 is a schematic diagram of a film structure for a pixel circuit corresponding to Figure 25;

[0044] Figure 27 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention;

[0045] Figure 28 is a schematic diagram of a partial membrane structure corresponding to Figure 27;

[0046] Figure 29 is another top view of the display panel provided in an embodiment of the present invention;

[0047] Figure 30 is a schematic diagram of the arrangement of the first power connection line and connection wiring provided in an embodiment of the present invention;

[0048] Figure 31 is a schematic diagram of another arrangement of the first power connection line and connection wiring provided in an embodiment of the present invention;

[0049] Figure 32 is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0050] Figure 33 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0051] Figure 34 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0052] Figure 35 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0053] Figure 36 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0054] Figure 37 is another schematic diagram of the pixel circuit provided in an embodiment of the present invention;

[0055] Figure 38 is a schematic diagram of a film structure for a pixel circuit corresponding to Figure 37;

[0056] Figure 39 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0057] Figure 40 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0058] Figure 41 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0059] Figure 42 is a schematic diagram of a partial membrane structure corresponding to Figure 41;

[0060] Figure 43 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0061] Figure 44 is a schematic diagram of a membrane structure of the first power bus, shielding structure and power connection line provided in an embodiment of the present invention.

[0062] Figure 45 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention;

[0063] Figure 46 is a schematic diagram of another film structure of the first power bus, shielding structure and power connection line provided in the embodiment of the present invention.

[0064] Figure 47 is a schematic diagram of another film structure of the first power bus, shielding structure and power connection line provided in the embodiment of the present invention.

[0065] Figure 48 is a schematic diagram of another membrane structure of the first power bus, shielding structure and power connection line provided in the embodiment of the present invention.

[0066] Figure 49 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0067] Figure 50 is a schematic diagram of a structure of the data leads corresponding to Figure 49;

[0068] Figure 51 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0069] Figure 52 is a schematic diagram of a data lead structure corresponding to Figure 51;

[0070] Figure 53 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0071] Figure 54 is a cross-sectional view of Figure 53 along the E1-E2 direction;

[0072] Figure 55 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0073] Figure 56 is a cross-sectional view of Figure 55 along the F1-F2 direction;

[0074] Figure 57 is a schematic diagram of a film structure for a data line and data lead provided in an embodiment of the present invention;

[0075] Figure 58 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0076] Figure 59 is a cross-sectional view of Figure 58 along the G1-G2 direction;

[0077] Figure 60 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0078] Figure 61 is a cross-sectional view of Figure 60 along the H1-H2 direction;

[0079] Figure 62 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0080] Figure 63 is a cross-sectional view of Figure 62 along the I1-I12 direction;

[0081] Figure 64 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0082] Figure 65 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0083] Figure 66 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0084] Figure 67 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0085] Figure 68 is a schematic diagram of a partial membrane structure corresponding to Figure 67;

[0086] Figure 69 is another top view of the display panel provided in an embodiment of the present invention;

[0087] Figure 70 is a partially enlarged schematic diagram corresponding to Figure 69;

[0088] Figure 71 is another top view of the display panel provided in an embodiment of the present invention;

[0089] Figure 72 is a cross-sectional view of Figure 71 along the K1-K2 direction;

[0090] Figure 73 is another cross-sectional view of Figure 71 along the K1-K2 direction;

[0091] Figure 74 is another top view of the display panel provided in an embodiment of the present invention;

[0092] Figure 75 is another top view of the display panel provided in an embodiment of the present invention;

[0093] Figure 76 is another top view of the display panel provided in an embodiment of the present invention;

[0094] Figure 77 is a cross-sectional view of Figure 76 along the L1-L2 direction;

[0095] Figure 78 is another top view of the display panel provided in an embodiment of the present invention;

[0096] Figure 79 is another top view of the display panel provided in an embodiment of the present invention;

[0097] Figure 80 is another top view of the display panel provided in an embodiment of the present invention;

[0098] Figure 81 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0099] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0100] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0101] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0102] It should be understood that although the terms "first" and "second" may be used in the embodiments of the present invention to describe structures such as power connection lines, these terms are only used to distinguish the power connection lines and other structures from one another. For example, without departing from the scope of the embodiments of the present invention, the first power connection line may also be referred to as the second power connection line, and similarly, the second power connection line may also be referred to as the first power connection line.

[0103] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0104] Before describing the technical solution provided by this invention, this invention first explains the structure and existing problems of existing display panels.

[0105] As shown in Figures 1 and 2, Figure 1 is a top view of a display panel in the prior art, and Figure 2 is a cross-sectional view of Figure 1 along the A1-A2 direction. The display panel includes a display area 101 and a non-display area 102. The display panel also includes a substrate 103, an array layer 104 located on one side of the substrate 103, and a light-emitting device layer 105 located on the side of the array layer 104 away from the substrate 103.

[0106] The light-emitting device layer 105 includes a first electrode layer 106, a pixel definition layer 107, a light-emitting functional layer 108, and a second electrode layer 109. The first electrode layer 106 includes an anode 110, the light-emitting functional layer 108 includes a hole functional layer 112, a light-emitting layer 113, and an electron functional layer 114, and the second electrode layer 109 includes a cathode 115.

[0107] The array layer 104 includes an auxiliary power line 116, a first power bus 117, and a second power bus 118. The first power bus 117 and the second power bus 118 are located in the non-display area 102, and the auxiliary power line 116 is located at least in the display area 101. The auxiliary power line 116 is electrically connected to the second power bus 118.

[0108] The first electrode layer 106 also includes an overlap portion 111, which overlaps with the first power bus 117 and the cathode 115 respectively, and is also electrically connected to the second power bus 118. On the one hand, it transmits the negative power signal in the first power bus 117 to the cathode 115, and on the other hand, it further transmits it to the auxiliary power line 116 through the second power bus 118.

[0109] However, during the research process, the inventors discovered that in this structure, the width of the overlap portion 111 needs to be set very large. The width direction of the overlap portion 111 is perpendicular to its extension direction. For example, as shown in Figure 1, the width direction of the overlap portion 111 is parallel to the arrangement direction of the first power bus 117 and the second power bus 118, which can easily lead to the following problems:

[0110] First, the hole functional layer 112 and the electronic functional layer 114 in the light-emitting functional layer 108 typically cover the entire display area 101, with their edges located in the non-display area 102 and overlapping with the overlap portion 111. Thus, in the manufacturing process of the hole functional layer 112 and the electronic functional layer 114, as shown in Figure 3 (a schematic diagram of a prior art display panel in the manufacturing process), when these two film layers are formed using a mask 119, the opening boundary of the mask 119 overlaps with the overlap portion 111. Static electricity in the mask 119, such as static electricity generated by friction between the mask 119 and the supporting glass, accumulates at the boundary of the mask 119, forming a capacitor with the overlap portion 111. When the static electricity at the mask 119 accumulates to a certain amount, the film layer is electrostatically broken down, affecting the transmission of negative power signals, or the overlap portion 111 short-circuits with other signal lines, leading to malfunctioning displays.

[0111] Second, when the width of the overlap portion 111 is very large, it will overlap with the pixel definition layer 107 over a large area. Static electricity in the pixel definition layer 107 will continue to be conducted inward along the overlap portion 111, affecting the performance of transistors and other devices, causing device failure, and resulting in dark spots on the display panel.

[0112] In response, the present invention provides a display panel that can significantly reduce the extension distance of the overlapping portion 10 toward the display area 1 without affecting the normal transmission of negative power signals, thereby improving the electrostatic risk caused by the long extension distance of the overlapping portion 10.

[0113] As shown in Figures 4 and 5, Figure 4 is a top view of a display panel provided in an embodiment of the present invention, and Figure 5 is a cross-sectional view of Figure 4 along B1-B2. The display panel includes a display area 1 and a non-display area 2.

[0114] The display panel also includes a substrate 3, which can be a rigid substrate such as glass or a flexible substrate formed of materials such as polyimide.

[0115] The display panel also includes a light-emitting device layer 4, which includes a first electrode layer 5, a pixel definition layer 6, a light-emitting functional layer 7, and a second electrode layer 8. The first electrode layer 5 includes an anode 9 and an overlap portion 10, located in the non-display area 2. The pixel definition layer 6 is located on the side of the first electrode layer 5 away from the substrate 3, and has an opening that exposes at least a portion of the anode 9. The light-emitting functional layer 7 is located on the side of the pixel definition layer 6 away from the substrate 3, and includes a hole functional layer 11, a light-emitting layer 12, and an electron functional layer 13. Specifically, the hole functional layer 11 may include film layers such as a hole injection layer and a hole transport layer, and the electron functional layer 13 may specifically include film layers such as an electron injection layer and an electron transport layer. The hole functional layer 11 and the electron functional layer 13 typically cover the entire display area 1, with their edges located in the non-display area 2. The second electrode layer 8 is located on the side of the light-emitting functional layer 7 away from the substrate 3 and includes a cathode 14.

[0116] The display panel also includes a first power bus 15, which is located in the non-display area 2 and on the side of the first electrode layer 5 closest to the substrate 3. The overlapping portion 10 in the first electrode layer 5 is electrically connected to both the second electrode layer 8 and the first power bus 15.

[0117] For example, the overlap portion 10 can overlap with the first power bus 15 and the second electrode layer 8 respectively, so as to transmit the negative power signal in the first power bus 15 to the cathode 14 of the second electrode layer 8. The overlap portion 10 can also be provided with a plurality of openings 16, which can serve as exhaust channels for the organic layer below the first electrode layer 5.

[0118] The display panel also includes an auxiliary power line 17, which is at least partially located in the display area 1 and on the side of the first electrode layer 5 near the substrate 3, to reduce the load on the cathode 14 and improve the uniformity of the cathode transmission signal.

[0119] The display panel also includes a power connection line 18, which is at least partially located in the non-display area 2 and between the first electrode layer 5 and the substrate 3. The auxiliary power line 17 and the first power bus 15 are electrically connected through at least one power connection line 18.

[0120] The phrase "the auxiliary power line 17 and the first power bus 15 are electrically connected through the power connection line 18" means that a signal transmission path can be constructed between the first power bus 15 and the auxiliary power line 17 using the power connection line 18. In other words, the negative power signal in the first power bus 15 is first transmitted to the power connection line 18 and then to the auxiliary power line 17.

[0121] However, it should be noted that the power connection cable 18 does not necessarily have to be directly connected to the auxiliary power line 17 and / or the first power bus 15. For example, in one configuration, referring to Figure 5, the end of the power connection cable 18 furthest from the display area 1 is directly connected to the first power bus 15, and the end of the power connection cable 18 closest to the display area 1 is directly connected to the auxiliary power line 17. In this case, the negative power signal in the first power bus 15 is directly transmitted to the power connection cable 18, and consequently, the negative power signal in the power connection cable 18 is also directly transmitted to the auxiliary power line 17.

[0122] Alternatively, in another configuration, referring to Figure 8, the end of the power connection line 18 furthest from the display area 1 is directly connected to the overlap portion 10, and the end of the power connection line 18 closest to the display area 1 is directly connected to the auxiliary power line 17. In this case, the negative power signal in the first power bus 15 is indirectly transmitted to the power connection line 18 through the overlap portion 10, and then the negative power signal in the power connection line 18 is directly transmitted to the auxiliary power line 17.

[0123] In this embodiment of the invention, by setting the power connection line 18, a signal transmission path between the first power bus 15 and the auxiliary power line 17 can be constructed using the power connection line 18, and the negative power signal in the first power bus 15 can be transmitted to the auxiliary power line 17. At this time, the side of the overlapping portion 10 near the display area 1 does not need to be connected to the auxiliary power line 17, which can reduce the width of the overlapping portion 10 and prevent the overlapping portion 10 and the light-emitting functional layer 7 from overlapping in the direction perpendicular to the plane of the substrate 3.

[0124] In this embodiment, the width direction of the overlapping portion 10 is perpendicular to the extension direction of the overlapping portion 10. For example, the overlapping portion 10 shown in FIG4 extends along the first direction x, and the dimension of the overlapping portion 10 in the second direction y is the width of the overlapping portion 10. However, it should be noted that the structure of the first power bus 15 and the overlapping portion 10 shown in the accompanying drawings of this embodiment is only illustrative. In other cases, the first power bus 15 may also extend at least partially around the display area 1 in the non-display area 2. In this case, the overlapping portion 10 may also extend around the display area 1, and the overlapping portion 10 overlaps with the first power bus 15 at multiple locations. When the overlapping portion 10 extends around the display area 1, the width of the portion of the overlapping portion 10 extending along the first direction x is the dimension in the second direction y, and the width of the portion of the overlapping portion 10 extending along the second direction y is the dimension in the first direction x.

[0125] In the process of forming the hole functional layer 11 and the electron functional layer 13, as shown in Figure 6, which is a schematic diagram of the structure of the display panel provided in the embodiment of the present invention in the process, the opening boundary of the mask plate 01 will not overlap with the overlapping part 10, but will overlap with the power connection line 18. However, since the power connection line 18 is located on the side of the first electrode layer 5 facing the substrate 3 and is far away from the mask plate 01 in the longitudinal direction, even if static electricity accumulates at the opening boundary of the mask plate 01, the capacitance formed between the static electricity and the power connection line 18 will be very small, almost insulating, and there will be no problem of the film layer being broken down by static electricity. This improves the reliability of the negative power signal transmission into the surface and avoids display disorder.

[0126] Furthermore, as the width of the overlap portion 10 is reduced, the overlapping area between the overlap portion 10 and the pixel definition layer 6 will also be reduced accordingly. This can reduce the extent to which static electricity in the pixel definition layer 6 continues to conduct inward along the overlap portion 10, thereby reducing the impact of static electricity on the internal devices and improving the dark spot phenomenon.

[0127] In one feasible embodiment of the present invention, when the auxiliary power line 17 and the first power bus 15 are electrically connected by a power connection line 18, as shown in Figures 7 and 8, Figure 7 is another top view of the display panel provided in the embodiment of the present invention, and Figure 8 is a cross-sectional view of Figure 7 along C1-C2, at least one power connection line 18 can be connected between the auxiliary power line 17 and the overlapping part 10.

[0128] The phrase "the power connection cable 18 is connected between the auxiliary power cable 17 and the overlapping part 10" refers to the actual structural connection. That is, the auxiliary power cable 17 and the overlapping part 10 are connected by the power connection cable 18. The end of the power connection cable 18 away from the display area 1 is connected to the overlapping part 10, and the end closer to the display area 1 is electrically connected to the auxiliary power cable 17.

[0129] However, it should be noted that when the end of the power connection line 18 away from the display area 1 is connected to the overlapping part 10, referring to FIG7, the overlapping part 10 can be directly connected to the power connection line 18 through the through hole, or, as shown in FIG9, FIG9 is another cross-sectional view of FIG7 along C1-C2, the overlapping part 10 can also be connected to the power connection line 18 through at least one auxiliary connection electrode 19.

[0130] Based on this structure, the negative power signal in the first power bus 15, after being transmitted to the lap joint 10, is transmitted to the cathode 14 on one hand, and to the auxiliary power line 17 on the other hand through the power connection line 18. The power connection line 18 is relatively short in this configuration. It is understandable that some peripheral circuits, such as the shift register 28, will be located in the non-display area 2. Therefore, the wiring in the area between the first power bus 15 and the display area 1 will be more complex. A shorter extension distance for the power connection line 18 reduces conflicts between the power connection line 18 and the related traces of the peripheral circuits, thus lowering the wiring difficulty.

[0131] Alternatively, in another feasible implementation, referring again to Figures 4 and 5, at least one power connection line 18 can be electrically connected at one end to the auxiliary power line 17 and at the other end to the first power bus 15.

[0132] The phrase "the other end of the power connection cable 18 is connected to the first power bus 15" refers to the actual structural connection, that is, the auxiliary power cable 17 and the first power bus 15 are connected through the power connection cable 18.

[0133] However, it should be noted that when the end of the power connection line 18 away from the display area 1 is connected to the first power bus 15, referring to Figures 4 and 5, the first power bus 15 can be connected to the power connection line 18 through a via. Alternatively, as shown in Figures 10 and 11, Figure 10 is another top view of the display panel provided in the embodiment of the present invention, and Figure 11 is a cross-sectional view of Figure 10 along D1-D2. The first power bus 15 includes at least two stacked sub-power buses 20, one of which is on the same layer as the power connection line 18 and directly connected.

[0134] Based on this structure, the negative power signal in the first power bus 15 can be directly transmitted to the auxiliary power line 17 through the power connection line 18. In this configuration, the auxiliary power line 17 is directly connected to the first power bus 15. Since both the auxiliary power line 17 and the first power bus 15 are located on the side of the first electrode layer 5 facing the substrate 3, it is more convenient to connect them. For example, when the power connection line 18 is on the same layer as a sub-power bus 20 in the first power bus 15, the two can be directly connected.

[0135] In one feasible implementation, the display panel of the present invention may also adopt a design that arranges a portion of the fanout lines in display area 1 (Fanout in AA, FIAA):

[0136] As shown in Figure 12, which is another top view of the display panel provided in the embodiment of the present invention, the non-display area 2 includes a fan-out area 21, which is located on one side of the display area 1 along the first direction x, and the fan-out area 21 includes multiple fan-out lines 22.

[0137] Display area 1 includes a first display area 23 and a second display area 24. Along the second direction y, the first display area 23 is located on at least one side of the second display area 24, and the first direction x and the second direction y intersect. That is, the first display area 23 is closer to the outer edge of the display panel and can be regarded as the edge display area.

[0138] Display area 1 includes multiple data lines Data extending along a first direction x and arranged along a second direction y, and the data lines Data are electrically connected to fan-out traces 22. Display area 1 also includes multiple data leads 25, and the data lines Data in the first display area 23 are electrically connected to the fan-out traces 22 via the data leads 25.

[0139] In one structure, the data lead 25 includes a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y. The second data lead 27 is located on the side of the data line Data connected to it that is close to the second display area 24. This allows the fan-out trace 22 that needs to be connected to the data line Data to be led out from the lower center of the display area 1, avoiding the fan-out trace 22 connected to the data line Data in the first display area 23 from occupying a large space in the corner bezel, which helps to optimize the narrow bezel design.

[0140] In one feasible implementation, referring to Figures 13-16, the display panel further includes a shift register 28 located in the non-display area 2. The shift register 28 includes a first shift register 29, which includes a plurality of cascaded first sub-shift registers 30. At least a portion of the first shift register 29 is located between the first power bus 15 and the display area 1.

[0141] Here, "at least a portion of the first shift register 29 is located between the first power bus 15 and the display area 1" means that, in a direction perpendicular to the plane of the substrate 3, at least a portion of the projection of the first shift register 29 is located between the projection of the first power bus 15 and the display area 1. In this embodiment of the invention, the first shift register 29 may be entirely located between the first power bus 15 and the display area 1, or it may be only partially located between the first power bus 15 and the display area 1.

[0142] For example, as shown in Figures 13 and 14, Figure 13 is another top view of the display panel provided in an embodiment of the present invention, and Figure 14 is a schematic diagram of a partial film layer structure corresponding to Figure 13. In the direction perpendicular to the plane where the substrate 3 is located, the first power bus 15 and the first shift register 29 do not overlap. At this time, the first shift register 29 is entirely located between the first power bus 15 and the display area 1. Alternatively, as shown in Figures 15 and 16, Figure 15 is another top view of the display panel provided in an embodiment of the present invention, and Figure 16 is a schematic diagram of a partial film layer structure corresponding to Figure 15. The first power bus 15 includes at least two stacked sub-power buses 20, wherein the film layer where at least one sub-power bus 20 is located is on the side of the film layer where the circuit of the first shift register 29 is located away from the substrate 3. At this time, the sub-power bus 20 can overlap with the first shift register 29, and part of the first shift register 29 is located between the first power bus 15 and the display area 1.

[0143] The power connection line 18 includes a first power connection line 31, which extends at least between two adjacent first sub-shift registers 30.

[0144] It should be noted that, referring to Figures 14 and 16, the circuit structures included in the first sub-shift register 30 are independent of each other, and there is a certain interval between the circuit structures included in two adjacent first sub-shift registers 30 to separate them from each other. Here, "the first power supply connection line 31 extends at least between two adjacent first sub-shift registers 30" means that the first power supply connection line 31 extends within this interval.

[0145] However, it should be noted that when the first power connection line 31 extends within this interval, it can overlap with the related traces of the first sub-shift register 30. For example, as shown in Figure 17, which is a schematic diagram of a partial film structure corresponding to Figures 14 and 16 provided in an embodiment of the present invention, for two adjacent first sub-shift registers 30, the output terminal of the previous first sub-shift register 30 is electrically connected to the input terminal of the next first sub-shift register 30 through the first connection structure 46-1 (as shown in Figure 19, the first output terminal Out1 of the previous first sub-shift register 30 and the first input terminal IN1 of the next first sub-shift register 30 are electrically connected through the first connection structure 46-1) to achieve step-by-step downward shifting. In the direction perpendicular to the plane of the substrate 3, the first power connection line 31 overlaps with the first connection structure 46-1 connecting the two adjacent first sub-shift registers 30.

[0146] Understandably, the first sub-shift register 30 includes multiple transistors and capacitors 45, and its internal circuit layer wiring is relatively complex. The first power connection line 31 extends between adjacent first sub-shift registers 30. On the one hand, this can reduce the conflict between the first power connection line 31 and the internal circuit layer of the first sub-shift register 30, which helps to simplify the wiring design of the first power connection line 31. On the other hand, it can also reduce the coupling between the first power connection line 31 and the internal circuit layer of the first sub-shift register 30, thereby improving the reliability of signal transmission.

[0147] In one feasible implementation, as shown in FIG18, FIG18 is another top view of the display panel provided in the embodiment of the present invention. The display panel further includes a pixel circuit row 32 located in the display area 1. The pixel circuit row 32 includes a plurality of pixel circuits 33 arranged along the second direction y.

[0148] The shift register 28 also includes a second shift register 34, which is located on the side of the first shift register 29 away from the display area 1. The second shift register 34 includes a plurality of cascaded second sub-shift registers 35. The second sub-shift registers 35 are electrically connected to the pixel circuit row 32 through connecting traces 36, and the connecting traces 36 extend at least between two adjacent first sub-shift registers 30, thereby reducing the conflict between the connecting traces 36 and the internal circuit film layers of the first sub-shift registers 30 and simplifying the wiring design of the connecting traces 36.

[0149] Referring to Figure 17, the first shift register 29 can be a scan shift register 28, the first sub-shift register 30 is electrically connected to the pixel circuit row 32 through the scan signal line Scan, the second shift register 34 can be an emission shift register 28, and the second sub-shift register 35 is electrically connected to the pixel circuit row 32 through the emission control signal line Emit.

[0150] For the first sub-shift register 30, this embodiment of the invention provides a circuit structure.

[0151] As shown in Figures 19-21, Figure 19 is a schematic diagram of a first shift register 29 provided in an embodiment of the present invention, Figure 20 is a schematic diagram of a circuit structure of a first sub-shift register 30 provided in an embodiment of the present invention, and Figure 21 is a schematic diagram of a film structure of the first sub-shift register 30 corresponding to Figure 20. The first sub-shift register 30 may specifically include:

[0152] The first switching transistor M1 has its gate electrically connected to the first signal terminal ck1, its first terminal electrically connected to the first input terminal IN1, and its second terminal electrically connected to the first node N1.

[0153] The second switching transistor M2 has its gate electrically connected to the first signal terminal ck1, its first terminal electrically connected to the first low-potential signal line VGL1, and its second terminal electrically connected to the second node N2.

[0154] The third switching transistor M3 has its gate electrically connected to the first node N1, its first terminal electrically connected to the first signal terminal ck1, and its second terminal electrically connected to the second node N2.

[0155] The fourth switching transistor M4 has its gate electrically connected to the second signal terminal ck2, and its first terminal electrically connected to the first node N1.

[0156] The fifth switching transistor M5 has its gate electrically connected to the second node N2, its first terminal electrically connected to the first high-potential signal line VGH1, and its second terminal electrically connected to the second terminal of the fourth switching transistor M4.

[0157] The sixth switching transistor M6 has its first terminal electrically connected to the first low-potential signal line VGL1, its first terminal electrically connected to the first node N1, and its second terminal electrically connected to the third node N3.

[0158] The seventh switching transistor M7 has its gate electrically connected to the second node N2, its first terminal electrically connected to the first high-potential signal line VGH1, and its second terminal electrically connected to the first output terminal Out1.

[0159] The eighth switching transistor M8 has its gate electrically connected to the third node N3, its first terminal electrically connected to the second signal terminal ck2, and its second terminal electrically connected to the first output terminal Out1.

[0160] The first capacitor C1 is electrically connected between the first high-potential signal line VGH1 and the first node N1.

[0161] The second capacitor C2 is electrically connected between the third node N3 and the first output terminal Out1.

[0162] Referring to Figure 19, in the first shift register 29, the first signal terminal ck1 of the 4n+1th stage first sub-shift register 30 is electrically connected to the first clock line CK1, and the second signal terminal ck2 is electrically connected to the second clock line CK2. The first signal terminal ck1 of the 4n+2th stage first sub-shift register 30 is electrically connected to the second clock line CK2, and the second signal terminal ck2 is electrically connected to the third clock line CK3. The first signal terminal ck1 of the 4n+3th stage first sub-shift register 30 is electrically connected to the third clock line CK3, and the second signal terminal ck2 is electrically connected to the fourth clock line CK4. The first signal terminal ck1 of the 4n+4th stage first sub-shift register 30 is electrically connected to the fourth clock line CK4, and the second signal terminal ck2 is electrically connected to the first clock line CK1. The value of n is 0, 1, 2, ... in sequence.

[0163] The first input terminal IN1 of the first sub-shift register 30 of the first stage is electrically connected to the first frame start signal line STV1. Furthermore, for two adjacent first sub-shift registers 30, the first output terminal Out1 of the previous first sub-shift register 30 is electrically connected to the first input terminal IN1 of the next first sub-shift register 30.

[0164] For the second sub-shift register 35, this embodiment of the invention provides a circuit structure.

[0165] As shown in Figures 22-24, Figure 22 is a schematic diagram of a structure of the second shift register 34 provided in an embodiment of the present invention, Figure 23 is a schematic diagram of a circuit structure of the second sub-shift register 35 provided in an embodiment of the present invention, and Figure 24 is a schematic diagram of a film structure of the second sub-shift register 35 corresponding to Figure 23. The second sub-shift register 35 may specifically include:

[0166] The ninth switching transistor M9 has its gate electrically connected to the third signal terminal ck3, its first terminal electrically connected to the second input terminal IN2, and its second terminal electrically connected to the fourth node N4.

[0167] The tenth switching transistor M10 has its gate electrically connected to the third signal terminal ck3, its first terminal electrically connected to the second low-potential signal line VGL2, and its second terminal electrically connected to the fifth node N5.

[0168] The eleventh switching transistor M11 has its gate electrically connected to the fourth node N4, its first terminal electrically connected to the third signal terminal ck3, and its second terminal electrically connected to the fifth node N5.

[0169] The twelfth switching transistor M12 has its gate electrically connected to the second low-potential signal line VGL2, its first terminal electrically connected to the fifth node N5, and its second terminal electrically connected to the sixth node N6.

[0170] The thirteenth switching transistor M13 has its gate electrically connected to the sixth node N6, its first terminal electrically connected to the fourth signal terminal ck4, and its second terminal electrically connected to the seventh node N7.

[0171] The fourteenth switching transistor M14 has its gate electrically connected to the fourth node N4, its first terminal electrically connected to the second high-potential signal line VGH2, and its second terminal electrically connected to the eighth node N8.

[0172] The fifteenth switching transistor M15 has its gate electrically connected to the fourth signal terminal ck4, its first terminal electrically connected to the seventh node N7, and its second terminal electrically connected to the eighth node N8.

[0173] The sixteenth switching transistor M16 has its gate electrically connected to the second low-potential signal line VGL2, its first terminal electrically connected to the fourth node N4, and its second terminal electrically connected to the ninth node N9.

[0174] The seventeenth switching transistor M17 has its gate electrically connected to the eighth node N8, its first terminal electrically connected to the second high-potential signal line VGH2, and its second terminal electrically connected to the second output terminal Out2.

[0175] The eighteenth switching transistor M18 has its gate electrically connected to the ninth node N9, its first terminal electrically connected to the second low-potential signal line VGL2, and its second terminal electrically connected to the second output terminal Out2.

[0176] The nineteenth switching transistor M19 has its gate electrically connected to the ninth node N9, its first terminal electrically connected to the fourth signal terminal ck4, and its second terminal electrically connected to the tenth node N10.

[0177] The twentieth switching transistor M20 has its gate electrically connected to the fifth node N5, its first terminal electrically connected to the second high-potential signal line VGH2, and its second terminal electrically connected to the tenth node N10.

[0178] The third capacitor C3 is electrically connected between the second high-potential signal line VGH2 and the eighth node N8.

[0179] The fourth capacitor C4 is electrically connected between the sixth node N6 and the seventh node N7.

[0180] The fifth capacitor C5 is electrically connected between the tenth node N10 and the ninth node N9.

[0181] Referring to Figure 22, in the first shift register 29, the third signal terminal ck3 of the second sub-shift register 35 of the 2n+1th stage is electrically connected to the fifth clock line CK, and the fourth signal terminal ck4 is electrically connected to the sixth clock line XCK. The third signal terminal ck3 of the second sub-shift register 35 of the 2n+2th stage is electrically connected to the sixth clock line XCK, and the fourth signal terminal ck4 is electrically connected to the fifth clock line CK. n takes values ​​of 0, 1, 2, ... in sequence.

[0182] The second input terminal IN2 of the first-stage second sub-shift register 35 is electrically connected to the second frame start signal line STV2. Furthermore, for two adjacent second sub-shift registers 35, the second output terminal Out2 of the previous stage second sub-shift register 35 is electrically connected to the second input terminal IN2 of the next stage second sub-shift register 35.

[0183] For pixel circuit 33, this embodiment of the invention provides a circuit structure.

[0184] As shown in Figures 25 and 26, Figure 25 is a circuit diagram of a pixel circuit 33 provided in an embodiment of the present invention, and Figure 26 is a film structure diagram of the pixel circuit 33 corresponding to Figure 25. The pixel circuit 33 may specifically include:

[0185] Drive transistor M00.

[0186] The first gate reset transistor M01 has its gate electrically connected to the first scan signal line Scan1, its first terminal electrically connected to the reset signal line Vref, and its second terminal electrically connected to the gate of the driving transistor M00.

[0187] The data writing transistor M02 has its gate electrically connected to the second scan signal line Scan2, its first terminal electrically connected to the data line Data, and its second terminal electrically connected to the first terminal of the driving transistor M00.

[0188] The first threshold compensation transistor M03 has its gate electrically connected to the second scan signal line Scan2, its first terminal electrically connected to the second terminal of the driving transistor M00, and its second terminal electrically connected to the gate of the driving transistor M00.

[0189] The anode reset transistor M04 has its gate electrically connected to the first scan signal line Scan1, its first terminal electrically connected to the reset signal line Vref, and its second terminal electrically connected to the light-emitting element D.

[0190] The first light-emitting control transistor M05 has its gate electrically connected to the light-emitting control signal line Emit, its first terminal electrically connected to the positive power supply signal line PVDD, and its second terminal electrically connected to the first terminal of the driving transistor M00.

[0191] The second light-emitting control transistor M06 has its gate electrically connected to the light-emitting control signal line Emit, its first terminal electrically connected to the second terminal of the driving transistor M00, and its second terminal electrically connected to the light-emitting element D.

[0192] The storage capacitor Cst is electrically connected between the positive power supply signal line PVDD and the gate of the driving transistor M00.

[0193] It should be noted that, as shown in Figure 26, the anode reset transistor M04 of the pixel circuit 33 in the previous pixel circuit row 32 is electrically connected to the first scan signal line Scan1 corresponding to the next pixel circuit row 32. However, since the first scan signal line Scan1 corresponding to the next pixel circuit row 32 transmits the same signal as the second scan signal line Scan2 corresponding to the previous pixel circuit row 32, it can still be regarded as the anode reset transistor M04 being electrically connected to the second scan signal line Scan2 in the pixel circuit row 32.

[0194] Furthermore, it should be noted that the circuit structures of the first sub-shift register 30, the second sub-shift register 35, and the pixel circuit 33 provided in the embodiments of the present invention are merely illustrative. The embodiments of the present invention do not limit the structure of these three circuits. In other embodiments of the present invention, these three circuits may also adopt other circuit structures.

[0195] In one feasible implementation, referring to Figure 18, the first-level second sub-shift register 35 is electrically connected to at least two pixel circuit rows 32 via connection traces 36.

[0196] Referring to Figure 18, and as shown in Figures 27 and 28, Figure 27 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, and Figure 28 is a schematic diagram of a partial film layer structure corresponding to Figure 27. The connecting trace 36 includes a first trace 37 and a second trace 38. The first trace 37 is electrically connected to the second sub-shift register 35. The first trace 37 extends between adjacent first sub-shift registers 30 to the side of the first shift register 29 away from the second shift register 34, and is electrically connected to at least two pixel rows via the second trace 38 on the side of the first shift register 29 away from the second shift register 34. At least one first sub-shift register 30 is spaced between two adjacent first traces 37 and the first power connection line 31 in the first direction x.

[0197] When the first-level second sub-shift register 35 is electrically connected to at least two pixel circuit rows 32 via connecting lines 36, in a conventional arrangement of the connecting lines 36, as shown in FIG29, FIG29 is another top view of the display panel provided in the embodiment of the present invention, the second sub-shift register 35 is connected to two pixel circuit rows 32 respectively via two connecting lines 36, and these two connecting lines 36 extend between different adjacent first sub-shift registers 30 to the side of the first shift register 29 away from the second shift register 34.

[0198] Compared to Figure 29, the structures shown in Figures 18 and 27 have adjusted the routing method of the connection trace 36. The adjusted connection trace 36 only occupies space between two adjacent first sub-shift registers 30, thereby freeing up space between other adjacent first sub-shift registers 30 to accommodate the first power connection line 31, thus achieving reasonable routing between the connection trace 36 and the first power connection line 31.

[0199] Furthermore, it should be noted that while Figure 18 illustrates some connection points, such as the connection between adjacent first sub-shift registers 30 and the connection between the second sub-shift register 35 and the connecting trace 36, these connection points are merely for clearly indicating which structural parts are electrically connected in this simplified structural diagram. They do not represent the presence of vias at the connection points in the actual film structure. For example, in Figure 18, a connection point is drawn between the first trace 37 and the second trace 38. However, in Figure 27, the second segment 40 of the first trace 37, closer to the second trace 38, is on the same layer as the second trace 38, and the connection point between the second segment 40 and the second trace 38 is directly connected without any vias. The connection points in subsequent figures are similar and will not be elaborated upon further.

[0200] Furthermore, referring again to Figure 18, the first-level second sub-shift register 35 is electrically connected to m pixel circuit rows 32, where m ≥ 2 and is a positive integer. Along the first direction x, m first sub-shift registers 30 are provided between two adjacent first power connection lines 31. At this time, the multiple first power connection lines 31 in the display panel are basically evenly spaced, and the distribution of this type of wiring is more regular.

[0201] In one feasible implementation, in order to achieve a reasonable distribution of the first power connection line 31 and the connection trace 36, the first power connection line 31 and the connection trace 36 can be arranged alternately along the first direction x.

[0202] However, it should be noted that when the first power connection line 31 and the connection line 36 are arranged alternately, the first sub-shift register 30 may or may not be included between two adjacent first power connection lines 31 and connection lines 36.

[0203] For example, in one structure, as shown in FIG30, FIG30 is a schematic diagram of the arrangement of the first power connection line 31 and the connection trace 36 provided in an embodiment of the present invention. The first-level second sub-shift register 35 is electrically connected to two pixel circuit rows 32. Each pair of adjacent first traces 37, adjacent pairs of first power connection lines 31, and adjacent first traces and first power connection lines 31 may each include at least one level (two levels in FIG30) of first sub-shift register 30. Alternatively, in another structure, as shown in FIG31, FIG31 is a schematic diagram of another arrangement of the first power connection line 31 and the connection trace 36 provided in an embodiment of the present invention. The first-level second sub-shift register 35 is electrically connected to one pixel circuit row 32. A first trace 37 and a first power connection line 31 are provided between two adjacent first sub-shift registers 30.

[0204] In one feasible implementation, referring to Figures 27 and 28, at least one first power connection line 31 includes a first segment 39 and a second segment 40 that are electrically connected but disposed on different layers, and a first trace 37 includes a third segment 41 and a fourth segment 42 that are electrically connected but disposed on different layers. Specifically, the first segment 39 and the third segment 41 are disposed on the same layer, and the second segment 40 and the fourth segment 42 are disposed on the same layer.

[0205] The first power connection line 31 has a relatively long extension distance. When the first power connection line 31 is made of a single layer of metal, electrostatic discharge (ESD) damage due to static electricity accumulation may occur. This embodiment of the invention reduces the risk of ESD damage to the first power connection line 31 by implementing a rewiring design. Furthermore, the first trace 37 also typically employs a rewiring design. To simplify the design, this embodiment of the invention sets the first power connection line 31 to have the same rewiring method as the first trace 37.

[0206] As shown in Figure 32, which is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, the display panel further includes an array layer 43, which is located between the substrate 3 and the light-emitting device layer 4, and includes a first transistor 44 and a capacitor 45.

[0207] The first transistor 44 may include the first switching transistor M1 to the eighth switching transistor M8 in the first sub-shift register 30, or the ninth switching transistor M9 to the twentieth switching transistor M20 in the second sub-shift register 35, and may also include the driving transistor M00, the first gate reset transistor M01, the data writing transistor M02, the first threshold compensation transistor M03, the anode reset transistor M04, the first light emission control transistor M05, and the second light emission control transistor M06 in the pixel circuit 33.

[0208] Capacitor 45 may include the first capacitor C1 and the second capacitor C2 in the first sub-shift register 30, and may also include the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 in the second sub-shift register 35, and may also include the storage capacitor Cst in the pixel circuit 33.

[0209] The array layer 43 includes a first semiconductor layer ac1, a first metal layer m1, a second metal layer mc, and a first source / drain electrode layer sd1. The first semiconductor layer ac1 includes the active layer p1 of the first transistor 44; the first metal layer m1 is located on the side of the first semiconductor layer ac1 away from the substrate 3, and includes the gate g1 of the first transistor 44 and the first electrode c1 of the capacitor 45; the second metal layer mc is located on the side of the first metal layer m1 away from the substrate 3, and includes the second electrode c2 of the capacitor 45; the first source / drain electrode layer sd1 is located on the side of the second metal layer mc away from the substrate 3, and includes multiple connection structures 46, at least some of which are electrically connected to the active layer p1 of the first transistor 44 through vias.

[0210] In one feasible implementation, the first power connection line 31 is at least partially located on the side of the first source / drain electrode layer sd1 near the substrate 3.

[0211] Referring to Figure 17, as mentioned above, when the first power connection line 31 extends between adjacent first sub-shift registers 30, the first power connection line 31 will overlap with the first connection structure 46-1 connected between adjacent first sub-shift registers 30. The first connection structure 46-1 belongs to the aforementioned connection structure 46 and is also located in the first source / drain electrode layer sd1. Therefore, to avoid a short circuit between the first power connection line 31 and the first connection structure 46-1, the first power connection line 31 can be positioned on the side of the first source / drain electrode layer sd1 closer to the substrate 3.

[0212] Moreover, when the first power connection line 31 is located on the side of the first source / drain electrode layer sd1 close to the substrate 3, the first power connection line 31 is closer to the substrate 3. When the hole functional layer 11 and the electron functional layer 13 are formed using the mask plate 01, the longitudinal distance between the first power connection line 31 and the mask plate is larger. The static electricity accumulated at the opening boundary of the mask plate 01 is less likely to form a capacitor with the first power connection line 31, thus avoiding electrostatic breakdown of the film layer to a greater extent.

[0213] Furthermore, at least one of the first metal layer m1 and the second metal layer mc includes a first power connection line 31.

[0214] It should be noted that, in the embodiments of the present invention, a certain film layer includes a first power connection line, which includes the case where all of the first power connection lines are located in the film layer, and also the case where a portion of the first power connection lines are located in the film layer. That is to say, the phrase "at least one of the first metal layer m1 and the second metal layer mc includes the first power connection line 31" includes the case where the first power connection line 31 is only located in the first metal layer m1, the case where the first power connection line 31 is only located in the second metal layer mc, and the case where the first power connection line 31 is located in both the first metal layer m1 and the second metal layer mc.

[0215] That is, in one configuration, referring to Figure 28 and Figure 32, the first power connection line 31 includes a first segment 39 and a second segment 40. The first segment 39 is located on the side of the second segment 40 away from the display area 1. The first segment 39 is located in the first metal layer m1, and the second segment 40 is located in the second metal layer mc. Correspondingly, when the first power connection line 31 and the first trace 37 adopt the same crossover design, in the first trace 37, the third segment 41 is located on the side of the fourth segment 42 away from the display area 1. The third segment 41 is located in the first metal layer m1, and the fourth segment 42 is located in the second metal layer mc.

[0216] Alternatively, in another configuration, as shown in FIG33, FIG33 is a schematic diagram of another cross-sectional structure of the display panel provided in an embodiment of the present invention, wherein the first power connection line 31 is located in the first metal layer m1.

[0217] Alternatively, as shown in Figure 34, which is a schematic cross-sectional view of the display panel provided in an embodiment of the present invention, the first power connection line 31 is located in the second metal layer mc.

[0218] Alternatively, as shown in Figure 35, which is a schematic cross-sectional view of the display panel provided in an embodiment of the present invention, the first power connection line 31 is a double-layer wiring, and the first power connection line 31 includes a first connection line 31-1 and a second connection line 31-2 stacked together. The first connection line 31-1 is located in the first metal layer m1, and the second connection line 31-2 is located in the second metal layer mc.

[0219] When at least one of the first metal layer m1 and the second metal layer mc includes the first power connection line 31, on the one hand, the first power connection line 31 can be set in the same layer as the original structure in the display panel, without occupying an additional metal layer or adding an additional patterning process. On the other hand, when the hole functional layer 11 and the electronic functional layer 13 are formed using the mask plate 01, the longitudinal distance between the first power connection line 31 and the mask plate 01 is large, which can avoid the film layer from being electrostatically broken down to a greater extent.

[0220] In one feasible implementation, as shown in FIG36, FIG36 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, wherein the array layer 43 further includes a second transistor 47.

[0221] The array layer 43 also includes a second semiconductor layer ac2 and a third metal layer mg. The second metal layer mac includes the bottom gate g2 of the second transistor 47; the second semiconductor layer ac2 is located on the side of the second metal layer mac away from the substrate 3, and includes the active layer p2 of the second transistor 47; the third metal layer mg is located on the side of the second semiconductor layer ac2 away from the substrate 3, and includes the top gate g3 of the second transistor 47; the first source / drain electrode layer sd1 is located on the side of the third metal layer mg away from the substrate 3, and a portion of the connection structure 46 is electrically connected to the active layer p2 of the second transistor 47 through vias.

[0222] The second transistor 47 may include the transistor in the pixel circuit 33. In this regard, an embodiment of the present invention also provides a circuit structure for the pixel circuit 33.

[0223] As shown in Figures 37 and 38, Figure 37 is another circuit diagram of the pixel circuit 33 provided in an embodiment of the present invention, and Figure 38 is a film structure diagram of the pixel circuit 33 corresponding to Figure 37. The pixel circuit 33 may specifically include:

[0224] Drive transistor M00.

[0225] The gate of the second gate reset transistor M01' is electrically connected to the third scan signal line S1N1, the first terminal of the second gate reset transistor M01' is electrically connected to the first reset signal line Vref1, and the second terminal of the second gate reset transistor M01' is electrically connected to the gate of the driving transistor M00.

[0226] The data writing transistor M02 has its gate electrically connected to the fourth scan signal line S1P, its first terminal electrically connected to the data line Data, and its second terminal electrically connected to the first terminal of the driving transistor M00.

[0227] The gate of the second threshold compensation transistor M03' is electrically connected to the fifth scan signal line N2, the first terminal of the second threshold compensation transistor M03' is electrically connected to the second terminal of the driving transistor M00, and the second terminal of the second threshold compensation transistor M03' is electrically connected to the gate of the driving transistor M00.

[0228] The anode reset transistor M04 has its gate electrically connected to the fourth scan signal line S1P, its first terminal electrically connected to the second reset signal line Vref2, and its second terminal electrically connected to the light-emitting element D.

[0229] The first light-emitting control transistor M05 has its gate electrically connected to the light-emitting control signal line Emit, its first terminal electrically connected to the positive power supply signal line PVDD, and its second terminal electrically connected to the first terminal of the driving transistor M00.

[0230] The gates of the first light-emitting control transistor M05 and the second light-emitting control transistor M06 are electrically connected to the light-emitting control signal line Emit. The first terminal of the second light-emitting control transistor M06 is electrically connected to the second terminal of the driving transistor M00. The second terminal of the first light-emitting control transistor M05 is electrically connected to the light-emitting element D.

[0231] The storage capacitor Cst is electrically connected between the positive power supply signal line PVDD and the gate of the driving transistor M00.

[0232] The second transistor 47 may include a second gate reset transistor M01' and a second threshold compensation transistor M03'.

[0233] In this embodiment of the invention, the first transistor 44 can be a low-temperature polysilicon (LTPS) transistor, and its active layer can include polysilicon semiconductor material. The second transistor 47 can be an indium gallium zinc oxide (IGZO) transistor, and its active layer includes indium gallium zinc oxide semiconductor material.

[0234] In one feasible implementation, at least one of the first metal layer m1, the second metal layer mc, and the third metal layer mg includes a first power connection line 31.

[0235] As mentioned above, in the embodiments of the present invention, a certain film layer includes a first power connection line, which includes the case where all of the first power connection lines are located in the film layer, and also includes the case where a portion of the first power connection lines are located in the film layer. That is to say, "at least one of the first metal layer m1, the second metal layer mc, and the third metal layer mg includes the first power connection line 31" includes the case where the first power connection line 31 is located only in the first metal layer m1, only in the second metal layer mc, or only in the third metal layer mg, and also includes the case where the first power connection line 31 is located in at least two of the first metal layer m1, the second metal layer mc, and the third metal layer mg. The case where the first power connection line 31 is located in at least two of the first metal layer m1, the second metal layer mc, and the third metal layer mg further includes the case where the first power connection line 31 adopts a cross-line design, with some segments located in the first metal layer m1, and / or some segments located in the second metal layer mc, and / or the third metal layer mg. It also includes the case where the first power connection line 31 adopts double-layer wiring, with the two layers of wiring located in two of the first metal layer m1, the second metal layer mc, and the third metal layer mg, respectively.

[0236] In this invention, only the case where the first power connection line 31 is located only in the third metal layer mg is illustrated in Figure 36. Other cases will not be illustrated in the figures.

[0237] When at least one of the first metal layer m1, the second metal layer mc, and the third metal layer mg includes the first power connection line 31, on the one hand, the first power connection line 31 can be set in the same layer as the original structure in the display panel, without occupying an additional metal layer or adding an additional patterning process. On the other hand, when the hole functional layer 11 and the electronic functional layer 13 are formed using the mask plate 01, the longitudinal distance between the first power connection line 31 and the mask plate 01 is large, which can avoid the film layer from being electrostatically broken down to a greater extent.

[0238] In one feasible implementation, as shown in Figures 38 and 40, Figure 38 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention, and Figure 40 is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention. The first semiconductor layer ac1 includes a silicon semiconductor layer, for example, including polycrystalline silicon semiconductor material, that is, the first transistor 44 is an LTPS transistor.

[0239] The array layer 43 also includes a light-shielding metal layer m0, which is located on the side of the first semiconductor layer ac1 closest to the substrate 3. The light-shielding metal layer m0 includes a first power connection line 31.

[0240] When the first power connection line 31 is located in the light-shielding metal layer m0, the longitudinal distance between the first power connection line 31 and the mask plate 01 used to form the hole functional layer 11 and the electronic functional layer 13 reaches its maximum. This longitudinal distance is close to the thickness of the display panel during vapor deposition, resulting in better anti-static capability. Furthermore, since transistors and capacitors are typically not formed in the light-shielding metal layer m0, and wiring is less, parameters such as the extension distance of the first power connection line 31 can be designed more flexibly when it is located in the light-shielding metal layer m0. In addition, the first power connection line 31 located in the light-shielding metal layer m0 can also block ambient light from the bottom, preventing any impact on transistor performance.

[0241] Furthermore, when the first power connection line 31 is located in the light-shielding metal layer m0, as shown in FIG38, the first power bus 15 can be electrically connected to the first power connection line 31 only through a via, or, as shown in FIG40, the first power bus 15 can also be electrically connected to the first power connection line 31 only through at least one auxiliary connection electrode 19.

[0242] In one feasible implementation, referring to FIG18, and as shown in FIGS. 41-43, FIG41 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, FIG42 is a schematic diagram of a partial film layer structure corresponding to FIG41, and FIG43 is a schematic diagram of another cross-sectional structure of the display panel provided in the embodiment of the present invention. The display panel further includes a plurality of first shielding structures 48. The first shielding structures 48 are located in the light-shielding metal layer m0. In the direction perpendicular to the plane of the substrate 3, one first shielding structure 48 overlaps at least partially with one first sub-shift register 30. The first shielding structure 48 is used to shield the bottom ambient light, preventing the ambient light from shining on the active layer of the switching transistor in the first sub-shift register 30, thereby avoiding leakage current of the switching transistor and affecting the circuit performance.

[0243] When the shift register 28 also includes a second shift register 34, the display panel may further include multiple second blocking structures 49. Similar to the first blocking structure 48, the second blocking structure 49 is also located in the light-shielding metal layer m0. In a direction perpendicular to the plane of the substrate 3, one second blocking structure 49 at least partially overlaps with one second sub-shift register 35. The second blocking structure 49 is also used to block bottom ambient light, preventing ambient light from shining on the active layer of the switching transistor in the second sub-shift register 35. The second blocking structure 49 and the first blocking structure 48 can be interconnected.

[0244] In one feasible implementation, as shown in Figures 44 and 45, Figure 44 is a schematic diagram of a film structure of the first power bus 15, the shielding structure, and the power connection line 18 provided in an embodiment of the present invention, and Figure 45 is a schematic diagram of another cross-sectional structure of the display panel provided in an embodiment of the present invention. The first shielding structure 48 is electrically connected to the first power connection line 31. At this time, a fixed negative power supply voltage is transmitted on the first shielding structure 48, and the first shielding structure 48 can also play the role of electrostatic shielding.

[0245] When the first shielding structure 48 is electrically connected to the first power connection line 31, the first power connection line 31 can be directly connected to the first shielding structure 48. Therefore, the first shielding structure 48 will not restrict the wiring of the first power connection line 31, and there is no need for the first power connection line 31 and the first shielding structure 48 to avoid each other.

[0246] In this way, the first power connection line 31 can extend to the side of the second shielding structure 49 away from the first shielding structure 48 and connect to the first power bus 15. Thus, referring to Figure 45, the first power connection line 31 can be electrically connected to the sub-power bus 20 of the first power bus 15 that is closer to the substrate 3, reducing the via depth, making the connection more convenient, and at the same time avoiding the via occupying a larger area, achieving a narrow bezel. Furthermore, as shown in Figure 46, which is a schematic diagram of another film structure of the first power bus 15, the shielding structure, and the power connection line 18 provided in the embodiment of the present invention, when the first power connection line 31 extends to the side of the second shielding structure 49 away from the first shielding structure 48 and connects to the first power bus 15, the first power bus 15 can also be set only on the side of the second shielding structure 49 away from the first shielding structure 48. In this way, the first power bus 15 does not need to overlap with the signal lines connected to the shift register 28, such as low-potential signal lines, high-potential signal lines, clock signal lines, frame start signal lines, etc., so the film layer of this part of the signal lines and the first power bus 15 do not need to avoid each other, and the selection of the film layer position of this part of the signal lines is more flexible.

[0247] Alternatively, in another feasible implementation, referring again to Figures 42 and 43, the first shielding structure 48 is electrically insulated from the first power connection line 31. Adjacent first shielding structures 48 are connected by a connecting portion 50, with the end of the first power connection line 31 that is electrically connected to the first power bus 15 located on the side of the connecting portion 50 closer to the display area 1, to avoid the connecting portion 50.

[0248] More specifically, referring to Figures 42 and 43, in this configuration, the first power bus 15 may include at least two sub-power buses 20 stacked together. In the direction perpendicular to the plane of the substrate 3, one of the sub-power buses 20 may extend to the side of the connection portion 50 near the display area 1 so as to connect with the first power connection line 31.

[0249] Alternatively, in another feasible implementation, as shown in FIG47, FIG47 is a schematic diagram of another film structure of the first power bus 15, the shielding structure, and the power connection line 18 provided in the embodiment of the present invention. The first shielding structure 48 is electrically insulated from the first power connection line 31. Along the first direction x, at least two partially adjacent first shielding structures 48 are separated by a first gap 51. The first power connection line 31 extends at least within the first gap 51. The first shielding structures 48 on both sides of the first gap 51 are electrically connected on the side of the first power connection line 31 away from the first power bus 15. Further, when the light-shielding metal layer m0 also includes a second shielding structure 49, referring to FIG47, along the first direction x, at least two partially adjacent second shielding structures 49 are separated by a second gap 52, and the second gap 52 overlaps with the first gap 51 in the second direction y. The first power connection line 31 also extends at least within the first gap 51 and the second gap 52.

[0250] In this configuration, at least some adjacent first shielding structures 48 are disconnected, providing an extension path for the first power connection line 31. This allows the first power connection line 31 to extend to the side of the second shielding structure 49 furthest from the first shielding structure 48 and connect to the first power bus 15. Thus, referring to Figure 47, the first power connection line 31 can be electrically connected to the sub-power bus 20 closer to the substrate 3 within the first power bus 15, reducing via depth, facilitating connection, and simultaneously avoiding the via occupying a larger area, achieving a narrow bezel. Further, as shown in Figure 48, which is a schematic diagram of another film structure of the first power bus 15, the shielding structure, and the power connection line 18 provided in an embodiment of the present invention, the first power connection line 31 extends to the side of the second shielding structure 49 away from the first shielding structure 48 and connects to the first power bus 15. Alternatively, the first power bus 15 can be set only on the side of the second shielding structure 49 away from the first shielding structure 48. In this way, the first power bus 15 does not need to overlap with the signal lines connected to the shift register 28, such as low-potential signal lines, high-potential signal lines, clock signal lines, frame start signal lines, etc. Then, the film layer of this part of the signal lines and the first power bus 15 do not need to avoid each other, and the selection of the film layer position of this part of the signal lines is more flexible.

[0251] In one feasible implementation, as shown in Figures 49 to 52, Figure 49 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, Figure 50 is a schematic diagram of a structure of the data lead 25 corresponding to Figure 49, Figure 51 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 52 is a schematic diagram of a structure of the data lead 25 corresponding to Figure 51. The array layer 43 further includes a second source / drain electrode layer sd2, which is located on the side of the first source / drain electrode layer sd1 away from the substrate 3.

[0252] The data lead 25 includes a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y. Referring to FIG. 50, the first data lead 26 is located in the second source / drain electrode layer sd2, and the second data lead 27 is located on the side of the second source / drain electrode layer sd2 closest to the substrate 3. In this embodiment of the invention, the second data lead 27 is located in the first source / drain electrode layer sd1. In other optional embodiments of the invention, the second data lead 27 may also be located in the first metal layer m1, the second metal layer mc, or the third metal layer mg. Alternatively, referring to FIG. 52, both the first data lead 26 and the second data lead 27 may be located in the second source / drain electrode layer sd2.

[0253] As shown in Figures 53 and 54, Figure 53 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 54 is a cross-sectional view of Figure 53 along the E1-E2 direction. The first shift register 29 is electrically connected to at least one drive signal line 53. The drive signal line 53 can be used to transmit clock signals. Referring to Figure 19, the drive signal line 53 may include a first clock line CK1, a second clock line CK2, a third clock line CK3, and a fourth clock line CK4.

[0254] Among them, the drive signal line 53 is located at least in the second source-drain electrode layer sd2.

[0255] When the FIAA design requires the use of the second source / drain electrode layer sd2, the drive signal line 53 is at least located in the second source / drain electrode layer sd2. Firstly, it can be set in the same layer as at least part of the data lead 25, simplifying the process. Secondly, the first power connection line 31 is located on the side of the first source / drain electrode layer sd1 close to the substrate 3. The first power connection line 31 and the drive signal line 53 are located in different film layers. Even if the first power connection line 31 and the drive signal line 53 overlap, there will be no film layer conflict between them.

[0256] Further referring again to Figures 53 and 54, the drive signal line 53 is located on the side of the first shift register 29 away from and / or close to the display area 1. This embodiment of the invention is illustrated by taking the drive signal line 53 located on the side of the first shift register 29 away from the display area 1 as an example. A drive signal line 53 includes a first sub-drive line 54 and a second sub-drive line 55 that are electrically connected. In a direction perpendicular to the plane of the substrate 3, the first sub-drive line 54 and the second sub-drive line 55 at least partially overlap. The first sub-drive line 54 is located in the first source / drain electrode layer sd1, and the second sub-drive line 55 is located in the second source / drain electrode layer sd2.

[0257] It is understood that the internal circuit layer structure of the first shift register 29 includes multiple connection structures 46 located in the first source-drain electrode layer sd1, such as the first connection structure 46-1 connected between adjacent first sub-shift registers 30. In the above configuration, the drive signal line 53 is located on one side of the first shift register 29, and the first sub-drive line 54 is located in the first source-drain electrode layer sd1. The drive signal line 53 does not overlap with the first shift register 29, so the drive signal line 53 will not conflict with the connection structure 46 in the first shift register 29. Moreover, the drive signal line 53 further includes a second sub-drive line 55 located in the second source-drain electrode layer sd2. The drive signal line 53 adopts a double-layer routing design, which significantly reduces the load on the drive signal line 53.

[0258] Alternatively, as shown in Figures 55 and 56, Figure 55 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 56 is a cross-sectional view of Figure 55 along the F1-F2 direction. In the direction perpendicular to the plane where the substrate 3 is located, the driving signal line 53 overlaps at least partially with the first shift register 29, and the driving signal line 53 is located in the second source and drain electrode layer sd2.

[0259] In this structure, the drive signal line 53 is located only in the second source-drain electrode layer sd2 and overlaps with the first shift register 29. In this case, the drive signal line 53 will not conflict with the connection structure 46 in the first shift register 29. Moreover, it can save the space occupied by the drive signal line 53 on the side of the first shift register 29, which helps to reduce the width of the bezel.

[0260] In one feasible implementation, referring to FIG59, FIG57 is a schematic diagram of a film structure of the data line Data and data lead 25 provided in the embodiment of the present invention. The array layer 43 further includes a second source drain electrode layer sd2 and a third source drain electrode layer sd3. The second source drain electrode layer sd2 is located on the side of the first source drain electrode layer sd1 away from the substrate 3, and the third source drain electrode layer sd3 is located on the side of the second source drain electrode layer sd2 away from the substrate 3.

[0261] The data lead 25 includes a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y. One of the first data lead 26 and the second data lead 27 is located in the second source-drain electrode layer sd2, and the other is located in the third source-drain electrode layer sd3. Figure 57 is a schematic diagram with the data line Data and the first data lead 26 located in the third source-drain electrode layer sd3, and the second data lead 27 located in the second source-drain electrode layer sd2. Alternatively, the data line Data and the first data lead 26 can be simultaneously located in the second source-drain electrode layer sd2, and the second data lead 27 can be located in the third source-drain electrode layer sd3.

[0262] As shown in Figures 58 and 59, Figure 58 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 59 is a cross-sectional view of Figure 58 along the G1-G2 direction. The first shift register 29 is electrically connected to at least one drive signal line 53. The drive signal line 53 can be used to transmit clock signals. Referring to Figure 19, the drive signal line 53 may include a first clock line CK1, a second clock line CK2, a third clock line CK3, and a fourth clock line CK4.

[0263] Among them, at least one of the first source-drain electrode layer sd1, the second source-drain electrode layer sd2, and the third source-drain electrode layer sd3 includes a drive signal line 53.

[0264] It should be noted that, in the embodiments of the present invention, a certain film layer includes a driving signal line 53, which includes the case where all of the driving signal lines 53 are located in the film layer, and also includes the case where one of the driving signal lines 53 is located in the film layer. That is to say, the phrase "at least one of the first source / drain electrode layer sd1, the second source / drain electrode layer sd2, and the third source / drain electrode layer sd3 includes a driving signal line 53" includes the case where the driving signal line 53 is located only in the first source / drain electrode layer sd1, the second source / drain electrode layer sd2, or the third source / drain electrode layer sd3, and also includes the case where the driving signal line 53 includes two sub-driving lines, and the two sub-driving lines are respectively located in two of the first source / drain electrode layers sd1, the second source / drain electrode layer sd2, and the third source / drain electrode layer sd3.

[0265] When the FIAA design requires the use of the second source / drain electrode layer sd2 and the third source / drain electrode layer sd3, the drive signal line 53 can be selected to be located in at least one of the first source / drain electrode layers sd1, sd2, and sd3 to achieve reasonable utilization of the film layer where the FIAA is located and simplify the process. On the other hand, since the first power connection line 31 is located on the side of the first source / drain electrode layer sd1 closest to the substrate 3, the drive signal line 53 will not conflict with the first power connection line 31 regardless of which of the first source / drain electrode layers sd1, sd2, and sd3 it is located in.

[0266] Further referring again to Figures 58 and 59, in a direction perpendicular to the plane of substrate 3, the drive signal line 53 at least partially overlaps with the first shift register 29. The drive signal line 53 includes a first sub-drive line 54 and a second sub-drive line 55 that are electrically connected. In a direction perpendicular to the plane of substrate 3, the first sub-drive line 54 and the second sub-drive line 55 at least partially overlap. The first sub-drive line 54 is located in the second source / drain electrode layer sd2, and the second sub-drive line 55 is located in the third source / drain electrode layer sd3.

[0267] The drive signal line 53 adopts a double-layer routing design, resulting in a low load. Moreover, the internal circuit film structure of the first shift register 29 is located on the side of the second source-drain electrode layer sd2 close to the substrate 3. Therefore, when the double-layer routing in the drive signal line 53 is located on the second source-drain electrode layer sd2 and the third source-drain electrode layer sd3 respectively, the drive signal line 53 can be set to overlap with the first shift register 29, saving the space occupied by the drive signal line 53 on the side of the first shift register 29 and helping to reduce the bezel width.

[0268] In one feasible implementation, as shown in Figures 60 and 61, Figure 60 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 61 is a cross-sectional view of Figure 60 along the H1-H2 direction. The first power connection line 31 is located on the side of the first source / drain electrode layer sd1 away from the substrate 3, and is disposed in the same layer as at least a portion of the data lead 25.

[0269] Unlike the previous embodiments, in this embodiment, the film layer where the first power connection line 31 is located is above the first source / drain electrode layer sd1 and within the film layer occupied by the data lead 25. Since the internal circuit film layer structure of the first shift register 29 is located on the side of the second source / drain electrode layer sd2 closest to the substrate 3, when the first power connection line 31 extends between adjacent first sub-shift registers 30, the first power connection line 31 will not be on the same layer as the internal circuit film layer in the first sub-shift register 30. Therefore, there is no need to consider the situation where the first power connection line 31 avoids the internal circuit film layer in the first sub-shift register 30.

[0270] Furthermore, referring again to Figures 60 and 61, the array layer 43 also includes a second source / drain electrode layer sd2, which is located on the side of the first source / drain electrode layer sd1 away from the substrate 3.

[0271] Data leads 25 include a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y. Referring again to Figures 49 and 50, the first data lead 26 is located in the second source / drain electrode layer sd2, and the second data lead 27 is located on the side of the second source / drain electrode layer sd2 closest to the substrate 3. In this embodiment, the second data lead 27 is illustrated as being located in the first source / drain electrode layer sd1. In other optional embodiments of this invention, the second data lead 27 may also be located in the first metal layer m1, the second metal layer mc, or the third metal layer mg. Alternatively, referring again to Figures 51 and 52, both the first data lead 26 and the second data lead 27 are located in the second source / drain electrode layer sd2.

[0272] Referring again to Figures 60 and 61, the first shift register 29 is electrically connected to at least one drive signal line 53, which is located on the side of the first shift register 29 away from and / or close to the display area 1, and is located on the first source-drain electrode layer sd1.

[0273] The second source / drain electrode layer sd2 includes a first power connection line 31.

[0274] When the FIAA design occupies only one source-drain electrode layer above the first source-drain electrode layer sd1, the drive signal line 53 is set on the side of the first shift register 29 and on the first source-drain electrode layer sd1, and the second source-drain electrode layer sd2 is set to include the first power connection line 31. This can not only make reasonable use of the film layer where the FIAA is located, but also avoid film layer conflicts between the first power connection line 31 and the drive signal line 53.

[0275] Alternatively, in conjunction with Figures 57 and 63, the array layer 43 further includes a second source / drain electrode layer sd2 and a third source / drain electrode layer sd3, with the second source / drain electrode layer sd2 located on the side of the first source / drain electrode layer sd1 away from the substrate 3, and the third source / drain electrode layer sd3 located on the side of the second source / drain electrode layer sd2 away from the substrate 3.

[0276] The data lead 25 includes a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y; wherein, one of the first data lead 26 and the second data lead 27 is located in the second source-drain electrode layer sd2 and the other is located in the third source-drain electrode layer sd3.

[0277] As shown in Figures 62 and 63, Figure 62 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 63 is a cross-sectional view of Figure 62 along the I1-I12 direction. The first shift register 29 is electrically connected to at least one drive signal line 53. The drive signal line 53 is located on the side of the first shift register 29 away from and / or close to the display area 1, and the drive signal line 53 is located in the first source and drain electrode layer sd1.

[0278] At least one of the second source / drain electrode layer sd2 and the third source / drain electrode layer sd3 includes a first power connection line 31.

[0279] When the FIAA design occupies two source-drain electrode layers above the first source-drain electrode layer sd1, setting the drive signal line 53 on one side of the first shift register 29 and in the first source-drain electrode layer sd1, and setting the first power connection line 31 in the second source-drain electrode layer sd2 and / or the third source-drain electrode layer sd3, can not only make reasonable use of the film layer where the FIAA is located, but also avoid film layer conflicts between the first power connection line 31 and the drive signal line 53.

[0280] Alternatively, in conjunction with Figures 57, 64 and 65, the array layer 43 further includes a second source / drain electrode layer sd2 and a third source / drain electrode layer sd3, wherein the second source / drain electrode layer sd2 is located on the side of the third source / drain electrode layer sd3 away from the substrate 3, and the third source / drain electrode layer sd3 is located on the side of the second source / drain electrode layer sd2 away from the substrate 3.

[0281] The data lead 25 includes a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y. One of the first data lead 26 and the second data lead 27 is located in the second source / drain electrode layer sd2, and the other is located in the third source / drain electrode layer sd3.

[0282] The first shift register 29 is electrically connected to at least one drive signal line 53, and the drive signal line 53 and the first power connection line 31 are disposed in different layers. As shown in FIG64, FIG64 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention, wherein the drive signal line 53 is located at least in the second source-drain electrode layer sd2, and the first power connection line 31 is located in the third source-drain electrode layer sd3. Alternatively, as shown in FIG65, FIG65 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention, wherein the drive signal line 53 is located at least in the third source-drain electrode layer sd3, and the first power connection line 31 is located in the second source-drain electrode layer sd2.

[0283] When the FIAA design occupies two source / drain electrode layers above the first source / drain electrode layer sd1, the drive signal line 53 and the first power supply connection line 31 overlap. Therefore, by setting them as separate layers, with one located in the second source / drain electrode layer sd2 and the other in the third source / drain electrode layer sd3, the film layer conflict is avoided while making reasonable use of the FIAA film layer.

[0284] Furthermore, referring again to Figures 64 and 65, in the direction perpendicular to the plane where the substrate 3 is located, the drive signal line 53 at least partially overlaps with the first shift register 29. The drive signal line 53 is located in the second source-drain electrode layer sd2 or the third source-drain electrode layer sd3. At this time, the drive signal line 53 is wired in a single layer and overlaps with the first shift register 29, which can save the space occupied by the drive signal line 53 on the side of the first shift register 29 and help to reduce the width of the bezel.

[0285] Alternatively, as shown in Figure 66, which is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention, the driving signal line 53 is located on the side of the first shift register 29 away from and / or close to the display area 1. The driving signal line 53 includes a first sub-driving line 54 and a second sub-driving line 55 that are electrically connected. In the direction perpendicular to the plane where the substrate 3 is located, the first sub-driving line 54 and the second sub-driving line 55 at least partially overlap. The first sub-driving line 54 is located in the first source-drain electrode layer sd1, and the second sub-driving line 55 is located in the second source-drain electrode layer sd2 or the third source-drain electrode layer sd3. In this case, the driving signal line 53 is a double-layer wiring, which can reduce its load.

[0286] In one feasible implementation, as shown in Figures 67 and 68, Figure 67 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention, and Figure 68 is a schematic diagram of a partial film layer structure corresponding to Figure 67. The connection structure 46 includes a first connection structure 46-1, which is connected between adjacent first sub-shift registers 30. The end of the first power connection line 31 that is electrically connected to the first power bus 15 is located on the side of the first connection structure 46-1 closer to the display area 1, and the first power connection line 31 is located in the first source-drain electrode layer sd1.

[0287] Unlike the previous embodiments, in this embodiment, the first power connection line 31 is located on the first source / drain electrode layer sd1. By placing the end of the first power connection line 31 that is electrically connected to the first power bus 15 on the side of the first connection structure 46-1 near the display area 1, the first power connection line 31 and the first connection structure 46-1 can avoid each other, and will not short-circuit even if they are located on the same layer.

[0288] In one feasible implementation, as shown in Figures 69 and 70, Figure 69 is another top view of the display panel provided in an embodiment of the present invention, and Figure 70 is a partially enlarged schematic diagram of Figure 69. The non-display area 2 includes a first non-display area 56 and a second non-display area 57, which are located on opposite sides of the display area 1 in the first direction x. The second non-display area 57 includes a fan-out area 21. That is, the first non-display area 56 corresponds to the upper border, and the second non-display area 57 corresponds to the lower border.

[0289] The power connection cable 18 includes a second power connection cable 58, which is at least partially located in the first non-display area 56.

[0290] Because the wiring inside the lower frame is complex, some second power connection lines 58 can be set in the upper frame to synchronously transmit the negative power signal in the first power bus 15 to the cathode 14 and auxiliary power line 17 in the plane. Moreover, the auxiliary power line 17 is further connected to the first power bus 15 through the second power connection lines 58, which can also reduce the overall load of the wiring.

[0291] Further, as shown in FIG71, which is another top view of the display panel provided in an embodiment of the present invention, the first non-display area 56 includes a virtual pixel circuit 59, which includes a first transistor 44 and a capacitor 45. The virtual pixel circuit 59 does not need to be used for display; it is only used to improve etching uniformity in the manufacturing process of the display panel. Moreover, the circuit structure of the virtual pixel circuit 59 is usually the same as the circuit structure of the pixel circuit 33 in the display area 1.

[0292] As shown in Figure 72, which is a cross-sectional view of Figure 71 along the K1-K2 direction, at least part of the second power connection line 58 is located on the side of the first metal layer m1 near the substrate 3, for example, on the light-shielding metal layer m0, to avoid conflict with the film layer in the virtual pixel circuit 59.

[0293] And / or, as shown in Figure 73, which is another cross-sectional view of Figure 71 along the K1-K2 direction, at least a portion of the second power connection line 58 is located on the side of the first source / drain electrode layer sd1 away from the substrate 3 to avoid conflict with the film layers in the virtual pixel circuit 59. Specifically, when the data lead 25 is located on both the first and second source / drain electrode layers sd1 and sd2, or only on the second source / drain electrode layer sd2, the second power connection line 58 can be located on the side of the first source / drain electrode layer sd1 away from the substrate 3, which is on the second source / drain electrode layer sd2. When the data lead 25 is located on both the second and third source / drain electrode layers sd2 and sd3, the second power connection line 58 can be located on the side of the first source / drain electrode layer sd1 away from the substrate 3, which is on the second source / drain electrode layer sd2 and / or the third source / drain electrode layer sd3.

[0294] Alternatively, the virtual pixel circuit 59 may not be provided in the first non-display area 56. In this case, the film layer position of the second power connection line 58 is more flexible. The second power connection line 58 can be located in at least one of the light-shielding metal layer m0, the first metal layer m1, the second metal layer mc, the third metal layer mg, the first source / drain electrode layer sd1, the second source / drain electrode layer sd2, and the third source / drain electrode layer sd3.

[0295] In one feasible implementation, as shown in Figures 74 and 75, Figure 74 is another top view of the display panel provided in an embodiment of the present invention, and Figure 75 is another top view of the display panel provided in an embodiment of the present invention. The display panel further includes a second power bus 60, which is located between the first power bus 15 and the display area 1. An auxiliary power line 17 is electrically connected to the first power bus 15 through the second power bus 60.

[0296] The second power bus 60 is electrically connected to the first power bus 15 through at least one power connection line 18. Specifically, the second power bus 60 and the first power bus 15 can be electrically connected through the first power connection line 31 and / or the second power connection line 58.

[0297] In this configuration, multiple auxiliary power lines 17 are first connected to the second power bus 60 to achieve electrical connection between all auxiliary power lines 17 and the second power bus 60. Then, power connection lines 18 are set between the second power bus 60 and the first power bus 15. This method allows for flexible design of parameters such as the number and spacing of power connection lines 18. For example, only a small number of power connection lines 18 can be set to connect between the second power bus 60 and the first power bus 15.

[0298] In one feasible implementation, as shown in FIG76, FIG76 is another top view of the display panel provided in the embodiment of the present invention, the power connection line 18 includes a third power connection line 61.

[0299] The display panel also includes a shift register 28, which includes a plurality of sub-shift registers 62. The plurality of sub-shift registers 62 include a first sub-shift register 62 to the Nth sub-shift register 62 cascaded in sequence. A second power bus 60 is located on the side of at least one sub-shift register 62 near the display area 1, where N≥2 and is an integer.

[0300] On the side of the first sub-shift register 62 away from the second sub-shift register 62, the second power bus 60 is electrically connected to the first power bus 15 via at least one third power connection line 61, and / or, on the side of the Nth sub-shift register 62 away from the (N-1)th sub-shift register 62, the second power bus 60 is electrically connected to the first power bus 15 via at least one third power connection line 61.

[0301] That is, this method involves setting a third power supply connection line 61 at both ends of the shift register 28, and using the third power supply connection line 61 to make an electrical connection between the first power bus 15 and the second power bus 60. Because the third power supply connection line 61 is located on the outer side of the end of the shift register 28, the position of the film layer of the third power supply connection line 61 is not limited by the position of the film layer of the internal circuit of the shift register 28, and the selection range of the film layer position of the third power supply connection line 61 is wider.

[0302] Further, as shown in Figure 77, which is a cross-sectional view of Figure 76 along the L1-L2 direction, the second power bus 60 includes a first sub-power bus 63. The first sub-power bus 63 is disposed on the same layer as at least a portion of the data lead 25, and the third power connection line 61 is disposed on the same layer as the first sub-power bus 63. In this case, the third power connection line 63 can be directly connected to the first sub-power bus 63 to realize the electrical connection between the third power connection line 63 and the second power bus 60.

[0303] In this embodiment of the invention, the second power bus 60 may include at least two sub-power buses 20.

[0304] Specifically, referring to Figures 60 and 61, when the first data lead 26 is located in the second source / drain electrode layer sd2 and the second data lead 27 is located on the side of the second source / drain electrode layer sd2 close to the substrate, the second power bus 60 may include two sub-power buses 20, one of which may be located in the second source / drain electrode layer sd2, and the other sub-power bus 20 is on the same layer as the second data lead 27, for example, it may be located in the first source / drain electrode layer sd1.

[0305] Alternatively, referring to Figures 62 and 63, when one of the first data lead 26 and the second data lead 27 is located in the second source-drain electrode layer sd2 and the other is located in the third source-drain electrode layer sd3, the second power bus 60 may include three sub-power buses 20, wherein two sub-power buses 20 are located in the second source-drain electrode layer sd2 and the third source-drain electrode layer sd3 respectively, and the other sub-power bus 20 may be located in the first source-drain electrode layer sd1.

[0306] The first sub-power bus 63 can be any one of the sub-power buses 20 mentioned above.

[0307] In one feasible implementation, as shown in FIG78, which is another top view of the display panel provided in an embodiment of the present invention, the non-display area 2 includes a first straight line area 64, a second straight line area 65, and a corner area 66. The first straight line area 64 extends along a first direction x, the second straight line area 65 extends along a second direction y, and the corner area 66 connects the first straight line area 64 and the second straight line area 65. The shift register 28 may be located at least in the first straight line area 64 and / or at least in the second straight line area 65.

[0308] In this invention, the third power connection line 61 can be set in the corner area 66. The corner area 66 has fewer wirings, which can provide more space for the third power connection line 63.

[0309] In one feasible implementation, referring to FIG69, FIG79 and FIG80, FIG79 is another top view of the display panel provided in the embodiment of the present invention, FIG80 is another top view of the display panel provided in the embodiment of the present invention, the data lead 25 includes a first data lead 26 extending along a first direction x and a second data lead 27 extending along a second direction y.

[0310] The auxiliary power line 17 includes a first sub-auxiliary power line 67 and a second sub-auxiliary power line 68. The first sub-auxiliary power line 67 is arranged on the same layer as the first data lead 26, and the second sub-auxiliary power line 68 is arranged on the same layer as the second data lead 27. More specifically, a first sub-auxiliary power line 67 can be aligned with a first data lead 26 with a gap between them, and a second sub-auxiliary power line 68 can be aligned with a second data lead 27 with a gap between them.

[0311] It should be noted that, referring to Figure 79, when the first data lead 26 and the second data lead 27 are arranged on the same layer, the first sub-auxiliary power line 67 and the second sub-auxiliary power line 68 are also arranged on the same layer. When the first data lead 26 and the second data lead 27 are arranged on different layers, referring to Figure 80, the first sub-auxiliary power line 67 and the second sub-auxiliary power line 68 are also arranged on different layers.

[0312] Furthermore, the second power bus 60 can be configured on the same layer as the second sub-auxiliary power line 68, and thus directly connected to achieve electrical connection between the two.

[0313] In the above configuration, the auxiliary power line 17 is located only in the film layer where the data lead 25 is located, without needing to occupy other film layers. This allows for the rational use of the FIAA film layer. Moreover, the auxiliary power line 17 and the data lead 25 can be distributed together throughout the entire display area 1, resulting in better reflection uniformity in the display area 1.

[0314] For easy distinction, in Figure 69, the connection point between the first data lead 26 and the second data lead 27 is indicated by a circle, and the connection point between the first auxiliary power line 67 and the second auxiliary power line 68 is indicated by a square.

[0315] Furthermore, referring to Figure 69, the display panel may also include a light-transmitting hole 70, within which a camera or other optical writing component is correspondingly disposed. Some data lines (Data) are disconnected on both sides of the light-transmitting hole 70, and these disconnected data lines can be connected via a data connection line 71. The data connection line 71 includes a first data connection line 72 extending along the second direction y and a second data connection line 73 extending along the first direction x. The first data connection line 72 is on the same layer as the second sub-auxiliary power line 68 and the second data lead 27, while the second data connection line 73 is on the same layer as the first sub-auxiliary power line 67 and the first data lead 26. The connection point between the first data connection line 72 and the second data connection line 73 is illustrated using a triangle.

[0316] Based on the same inventive concept, this embodiment of the invention also provides a display device, as shown in FIG81. FIG81 is a schematic diagram of a structure of the display device provided in this embodiment of the invention, which includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, the display device shown in FIG81 is merely illustrative; the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0317] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0318] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention. Moreover, in the absence of contradiction, the multiple embodiments provided by the present invention can be freely combined to form new solutions, and the new solutions formed by the free combination of multiple embodiments are also within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, include: Display area and non-display area; Substrate; The light-emitting device layer includes a first electrode layer, a light-emitting functional layer, and a second electrode layer. The second electrode layer is located on the side of the light-emitting functional layer away from the substrate. The first electrode layer includes an overlap portion located in the non-display area. The first power bus is located in the non-display area and on the side of the first electrode layer near the substrate. The overlapping portion is electrically connected to both the second electrode layer and the first power bus. An auxiliary power line is at least partially located in the display area and on the side of the first electrode layer closest to the substrate; A power connection line, at least partially located in the non-display area, is electrically connected to the auxiliary power line and the first power bus via at least one of the power connection lines, which is located between the first electrode layer and the substrate.

2. The display panel according to claim 1, characterized in that, At least one of the power connection lines is connected between the auxiliary power line and the overlap.

3. The display panel according to claim 1, characterized in that, At least one of the power connection lines is electrically connected at one end to the auxiliary power line and at the other end to the first power bus.

4. The display panel according to claim 1, characterized in that, The non-display area includes a fan-out area located on one side of the display area along a first direction, and the fan-out area includes multiple fan-out traces; The display area includes a first display area and a second display area. Along a second direction, the first display area is located on at least one side of the second display area, and the first direction and the second direction intersect. The display area includes a plurality of data lines extending along the first direction and arranged along the second direction, and the data lines are electrically connected to the fan-out routing lines. The display area also includes multiple data leads, and the data lines in the first display area are electrically connected to the fan-out wiring through the data leads.

5. The display panel according to claim 4, characterized in that, The display panel further includes a shift register located in the non-display area. The shift register includes a first shift register, at least a portion of which is located between the first power bus and the display area. The first shift register includes a plurality of cascaded first sub-shift register units. The power connection line includes a first power connection line that extends at least between two adjacent first sub-shift registers.

6. The display panel according to claim 5, characterized in that, The display panel further includes a pixel circuit row, which is located in the display area; The shift register further includes a second shift register located on the side of the first shift register away from the display area. The second shift register includes a plurality of cascaded second sub-shift registers. The second sub-shift registers are electrically connected to the pixel circuit via connecting traces, and the connecting traces extend at least between two adjacent first sub-shift registers.

7. The display panel according to claim 6, characterized in that, The first-level second sub-shift register is electrically connected to at least two of the pixel circuits via the connection traces; The connection trace includes a first trace and a second trace. The first trace is electrically connected to the second sub-shift register. The first trace extends between adjacent first sub-shift registers to the side of the first shift register away from the second shift register, and is electrically connected to at least two pixel rows on the side of the first shift register away from the second shift register via the second trace. Wherein, at least one first sub-shift register is spaced between two adjacent first traces and the first power connection line in the first direction.

8. The display panel according to claim 7, characterized in that, The first-level second sub-shift register is electrically connected to m of the pixel circuits, where m ≥ 2 and is a positive integer. Along the first direction, m first sub-shift registers are provided between two adjacent first power supply connection lines.

9. The display panel according to claim 6, characterized in that, Along the first direction, the first power connection line and the connection trace are arranged alternately.

10. The display panel according to claim 6, characterized in that, At least one of the first power connection lines includes a first segment and a second segment that are disposed in different layers and electrically connected, and the first trace includes a third segment and a fourth segment that are disposed in different layers and electrically connected. The first line segment and the third line segment are arranged on the same layer, and the second line segment and the fourth line segment are arranged on the same layer.

11. The display panel according to claim 5, characterized in that, The display panel further includes an array layer located between the substrate and the light-emitting device layer, the array layer including a first transistor and a capacitor; The array layer includes a first semiconductor layer, a first metal layer, a second metal layer, and a first source / drain electrode layer. The first metal layer is located on the side of the first semiconductor layer away from the substrate, the second metal layer is located on the side of the first metal layer away from the substrate, and the first source / drain electrode layer is located on the side of the second metal layer away from the substrate. Wherein, the first semiconductor layer includes the active layer of the first transistor, the first metal layer includes the gate of the first transistor and the first electrode of the capacitor, the second metal layer includes the second electrode of the capacitor, and the first source-drain electrode layer includes a plurality of connection structures, at least a portion of the connection structures being electrically connected to the active layer of the first transistor through vias; The first power connection line is at least partially located on the side of the first source / drain electrode layer closest to the substrate.

12. The display panel according to claim 11, characterized in that, At least one of the first metal layer and the second metal layer includes the first power connection line.

13. The display panel according to claim 11, characterized in that, The array layer also includes a second transistor; The array layer further includes a second semiconductor layer and a third metal layer. The second semiconductor layer is located on the side of the second metal layer away from the substrate, and the third metal layer is located on the side of the second semiconductor layer away from the substrate. The first source / drain electrode layer is located on the side of the third metal layer away from the substrate. The second metal layer further includes the bottom gate of the second transistor, the second semiconductor layer includes the active layer of the second transistor, and the third metal layer includes the top gate of the second transistor. A portion of the connection structure is electrically connected to the active layer of the second transistor through vias. Wherein, at least one of the first metal layer, the second metal layer, and the third metal layer includes the first metal layer. One power connection cable.

14. The display panel according to claim 5, characterized in that, The display panel further includes an array layer located between the substrate and the light-emitting device layer, the array layer including a first transistor; The array layer includes a first semiconductor layer and a first metal layer. The first semiconductor layer includes a silicon semiconductor layer, and the first metal layer is located on the side of the first semiconductor layer away from the substrate. The first semiconductor layer includes the active layer of the first transistor, and the first metal layer includes the gate of the first transistor. The array layer further includes a light-shielding metal layer located on the side of the first semiconductor layer closest to the substrate; The light-shielding metal layer includes the first power connection line.

15. The display panel according to claim 14, characterized in that, The display panel further includes a plurality of first shielding structures located on the light-shielding metal layer, wherein in a direction perpendicular to the plane of the substrate, one of the first shielding structures at least partially overlaps with one of the first sub-shift registers.

16. The display panel according to claim 15, characterized in that, The first shielding structure is electrically connected to the first power connection line.

17. The display panel according to claim 15, characterized in that, The first shielding structure is electrically insulated from the first power connection line; The adjacent first shielding structures are connected by a connecting part, and the end of the first power connection line that is electrically connected to the first power bus is located on the side of the connecting part closer to the display area.

18. The display panel according to claim 15, characterized in that, The first shielding structure is electrically insulated from the first power connection line; Along the first direction, at least two partially adjacent first shielding structures have a first gap, the first power connection line extends at least within the first gap, and the first shielding structures on both sides of the first gap are electrically connected on the side of the first power connection line away from the first power bus.

19. The display panel according to claim 11 or 13, characterized in that, The array layer further includes a second source / drain electrode layer, which is located on the side of the first source / drain electrode layer away from the substrate; The data leads include a first data lead extending along the first direction and a second data lead extending along the second direction; the first data lead is located in the second source / drain electrode layer, and the second data lead is located on the side of the second source / drain electrode layer close to the substrate, or both the first data lead and the second data lead are located in the second source / drain electrode layer. The first shift register is electrically connected to at least one drive signal line, which is located at least in the second source-drain electrode layer.

20. The display panel according to claim 19, characterized in that, The driving signal line is located on the side of the first shift register away from and / or close to the display area. The driving signal line includes a first sub-driving line and a second sub-driving line that are electrically connected. In a direction perpendicular to the plane of the substrate, the first sub-driving line and the second sub-driving line at least partially overlap. The first sub-driving line is located in the first source / drain electrode layer, and the second sub-driving line is located in the second source / drain electrode layer.

21. The display panel according to claim 19, characterized in that, In a direction perpendicular to the plane of the substrate, the drive signal line at least partially overlaps with the first shift register, and the drive signal line is located in the second source / drain electrode layer.

22. The display panel according to claim 11 or 13, characterized in that, The array layer further includes a second source / drain electrode layer and a third source / drain electrode layer, wherein the second source / drain electrode layer is located on the side of the first source / drain electrode layer away from the substrate, and the third source / drain electrode layer is located on the side of the second source / drain electrode layer away from the substrate. The data leads include a first data lead extending along the first direction and a second data lead extending along the second direction; one of the first data lead and the second data lead is located in the second source / drain electrode layer and the other is located in the third source / drain electrode layer. The first shift register is electrically connected to at least one drive signal line, and at least one of the first source-drain electrode layer, the second source-drain electrode layer, and the third source-drain electrode layer includes the drive signal line.

23. The display panel according to claim 22, characterized in that, In a direction perpendicular to the plane of the substrate, the drive signal line at least partially overlaps with the first shift register; The driving signal line includes a first sub-driving line and a second sub-driving line that are electrically connected. In a direction perpendicular to the plane of the substrate, the first sub-driving line and the second sub-driving line at least partially overlap. The first sub-driving line is located in the second source / drain electrode layer, and the second sub-driving line is located in the third source / drain electrode layer.

24. The display panel according to claim 5, characterized in that, The display panel further includes an array layer located between the substrate and the light-emitting device layer, the array layer including a first transistor; The array layer includes a first source / drain electrode layer, which includes a plurality of connection structures, at least some of which are electrically connected to the active layer of the first transistor through vias. The first power connection line is located on the side of the first source / drain electrode layer away from the substrate, and is disposed in the same layer as at least a portion of the data lead.

25. The display panel according to claim 24, characterized in that, The array layer further includes a second source / drain electrode layer, which is located on the side of the first source / drain electrode layer away from the substrate; The data leads include a first data lead extending along the first direction and a second data lead extending along the second direction; wherein the first data lead is located in the second source / drain electrode layer, and the second data lead is located on the side of the second source / drain electrode layer close to the substrate, or the first data lead and the second data lead are located in the second source / drain electrode layer. The first shift register is electrically connected to at least one drive signal line, the drive signal line being located on the side of the first shift register away from and / or close to the display area, and the drive signal line being located in the first source-drain electrode layer; The second source / drain electrode layer includes the first power connection line.

26. The display panel according to claim 24, characterized in that, The array layer further includes a second source / drain electrode layer and a third source / drain electrode layer, wherein the second source / drain electrode layer is located on the side of the first source / drain electrode layer away from the substrate, and the third source / drain electrode layer is located on the side of the second source / drain electrode layer away from the substrate. The data leads include a first data lead extending along the first direction and a second data lead extending along the second direction; wherein, one of the first data lead and the second data lead is located in the second source / drain electrode layer and the other is located in the third source / drain electrode layer; The first shift register is electrically connected to at least one drive signal line, the drive signal line being located on the side of the first shift register away from and / or close to the display area, and the drive signal line being located in the first source-drain electrode layer; At least one of the second source / drain electrode layer and the third source / drain electrode layer includes the first power connection line.

27. The display panel according to claim 24, characterized in that, The array layer further includes a second source / drain electrode layer and a third source / drain electrode layer, wherein the second source / drain electrode layer is located on the side of the third source / drain electrode layer away from the substrate, and the third source / drain electrode layer is located on the side of the second source / drain electrode layer away from the substrate. The data leads include a first data lead extending along the first direction and a second data lead extending along the second direction; wherein, one of the first data lead and the second data lead is located in the second source / drain electrode layer and the other is located in the third source / drain electrode layer; The first shift register is electrically connected to at least one drive signal line, and the drive signal line and the first power connection line are disposed on different layers; wherein, the drive signal line is at least located on the second source-drain electrode layer and the first power connection line is located on the third source-drain electrode layer, or, the drive signal line is at least located on the third source-drain electrode layer and the first power connection line is located on the second source-drain electrode layer.

28. The display panel according to claim 27, characterized in that, In a direction perpendicular to the plane of the substrate, the drive signal line at least partially overlaps with the first shift register, and the drive signal line is located in the second source / drain electrode layer or the third source / drain electrode layer; Alternatively, the driving signal line is located on the side of the first shift register away from and / or close to the display area. The driving signal line includes a first sub-driving line and a second sub-driving line that are electrically connected. In a direction perpendicular to the plane of the substrate, the first sub-driving line and the second sub-driving line at least partially overlap. The first sub-driving line is located in the first source / drain electrode layer, and the second sub-driving line is located in the second source / drain electrode layer or the third source / drain electrode layer.

29. The display panel according to claim 5, characterized in that, The display panel further includes an array layer located between the substrate and the light-emitting device layer, the array layer including a first transistor; The array layer includes a first source / drain electrode layer, which includes a plurality of connection structures, at least some of which are electrically connected to the active layer of the first transistor through vias. The connection structure includes a first connection structure, which is connected between adjacent first sub-shift registers; The end of the first power connection line that is electrically connected to the first power bus is located on the side of the first connection structure closer to the display area, and the first power connection line is located on the first source-drain electrode layer.

30. The display panel according to claim 1, characterized in that, The non-display area includes a first non-display area and a second non-display area, which are located on opposite sides of the display area in a first direction. The second non-display area includes a fan-out area. The power connection cable includes a second power connection cable, which is at least partially located in the first non-display area.

31. The display panel according to claim 30, characterized in that, The display panel further includes an array layer located between the substrate and the light-emitting device layer, the array layer including a first transistor and a capacitor; The array layer includes a first semiconductor layer, a first metal layer, a second metal layer, and a first source / drain electrode layer. The first metal layer is located on the side of the first semiconductor layer away from the substrate, the second metal layer is located on the side of the first metal layer away from the substrate, and the first source / drain electrode layer is located on the side of the second metal layer away from the substrate. Wherein, the first semiconductor layer includes the active layer of the first transistor, the first metal layer includes the gate of the first transistor and the first plate of the capacitor, the second metal layer includes the second plate of the capacitor, and the first source-drain electrode layer includes a plurality of connection structures, at least a portion of the connection structures being electrically connected to the active layer of the first transistor through vias. The first non-display area includes a virtual pixel circuit, which includes the first transistor and the capacitor; At least a portion of the second power connection line is located on the side of the first metal layer closer to the substrate, and / or at least a portion of the second power connection line is located on the side of the first source / drain electrode layer away from the substrate.

32. The display panel according to claim 4, characterized in that, The display panel further includes a second power bus, which is located between the first power bus and the display area. The auxiliary power line is electrically connected to the first power bus through the second power bus. The second power bus is electrically connected to the first power bus via at least one of the power connection lines.

33. The display panel according to claim 32, characterized in that, The power connection cable includes a third power connection cable; The display panel further includes a shift register, which includes multiple sub-shift registers. The multiple sub-shift registers include a first sub-shift register to the Nth sub-shift register in sequential cascade. The second power bus is located on the side of at least one sub-shift register closer to the display area, where N≥2 and is an integer. On the side of the first sub-shift register away from the second sub-shift register, the second power bus is electrically connected to the first power bus via at least one of the third power connection lines, and / or, on the side of the Nth sub-shift register away from the (N-1)th sub-shift register, the second power bus is electrically connected to the first power bus via at least one of the third power connection lines.

34. The display panel according to claim 33, characterized in that, in, The second power bus includes a first sub-power bus, which is at least partially disposed on the same layer as the data leads, and the third power connection line is disposed on the same layer as the first sub-power bus.

35. The display panel according to claim 33, characterized in that, The non-display area includes a first straight line area, a second straight line area, and a corner area, wherein the first straight line area extends along the first direction, the second straight line area extends along the second direction, and the corner area connects the first straight line area and the second straight line area; The third power supply connection line is located in the corner area.

36. The display panel according to claim 4, characterized in that, The data lead includes a first data lead extending along the first direction and a second data lead extending along the second direction; The auxiliary power line includes a first sub-auxiliary power line and a second sub-auxiliary power line. The first sub-auxiliary power line is arranged on the same layer as the first data lead, and the second sub-auxiliary power line is arranged on the same layer as the second data lead.

37. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 36.

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