Display panel and display apparatus

Abstract

The present application discloses a display panel and a display apparatus. A plurality of pixel driving circuits are arranged in a first direction and a second direction, and the first direction intersects with the second direction; a plurality of reset signal lines extend in the first direction and are arranged in the second direction, and one reset signal line is connected to the plurality of pixel driving circuits that are arranged in the first direction; connecting lines are connected between any two adjacent reset signal lines, and the connecting lines and the reset signal lines are arranged in different layers.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202410703816.4, filed with the Chinese Patent Office on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] With the continuous development of the display industry, flexible screens, foldable screens, and rollable screens are increasingly appearing in consumers' view. Among them, organic light-emitting diode (OLED) display panels have broad application prospects in automotive, mobile phones, tablets, computers, and television products.

[0004] Currently, in display panels, the gate driving circuits located on both sides of the display panel provide reset signals to the pixel driving circuits in the display area through reset signal lines. Each reset signal line needs to connect multiple pixel driving circuits located in the same row. Therefore, the reset signal line is relatively long in the row direction. When the reset signal line is subjected to coupling interference from other signals, the part of the reset signal line near the gate driving circuit is closer to the driving source and has a more stable signal with less coupling interference. However, the part of the reset signal line in the middle of the display area has poor signal stability and is subjected to greater coupling interference due to impedance. This can easily lead to different reset signals received by the pixel driving circuits in different areas, resulting in uneven display on the display panel. Invention Overview

[0005] This application provides a display panel and display device that can reduce the impedance of the reset signal line, improve the signal transmission uniformity of the reset signal line, and improve the display uniformity of the display panel.

[0006] This application provides a display panel, which includes:

[0007] Multiple pixel driving circuits are arranged along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0008] Multiple reset signal lines extend along the first direction and are arranged along the second direction, with one of the reset signal lines connected to multiple pixel driving circuits arranged along the first direction.

[0009] A connecting line is provided between any two adjacent reset signal lines, and the connecting line is disposed on a different layer from the reset signal lines.

[0010] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including a display panel, the display panel comprising:

[0011] Multiple pixel driving circuits are arranged along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0012] Multiple reset signal lines extend along the first direction and are arranged along the second direction, with one of the reset signal lines connected to multiple pixel driving circuits arranged along the first direction.

[0013] A connecting line is provided between any two adjacent reset signal lines, and the connecting line is disposed on a different layer from the reset signal lines. Attached Figure Description

[0014] Figure 1 is a schematic diagram of a display panel provided in one embodiment;

[0015] Figure 2 is a schematic diagram of a display panel provided in an embodiment of this application;

[0016] Figure 3 is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0017] Figure 4 is a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0018] Figure 5 is a schematic diagram of the device distribution of a pixel driving circuit provided in an embodiment of this application;

[0019] Figure 6 is an enlarged structural schematic diagram of point M in Figure 5 provided in an embodiment of this application;

[0020] Figure 7 is a schematic diagram of a reset signal line and connecting line provided in an embodiment of this application;

[0021] Figure 8 is a schematic diagram of another device distribution of the pixel driving circuit provided in an embodiment of this application;

[0022] Figure 9 is a schematic diagram of another structure of the reset signal line and connecting line provided in an embodiment of this application;

[0023] Figure 10 is a schematic diagram of another structure of the reset signal line and connecting line provided in an embodiment of this application;

[0024] Figure 11 is a schematic diagram of another structure of the reset signal line and connecting line provided in an embodiment of this application;

[0025] Figure 12 is a schematic cross-sectional view of another display panel provided in an embodiment of this application;

[0026] Figure 13 is a schematic diagram of a display device provided in an embodiment of this application. Embodiments of the present invention

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0029] Referring to Figure 1, the display panel 1 includes multiple pixel driving circuits 2 arranged in rows and columns. The pixel driving circuits 2 provide reset signals through reset signal lines 3 to reset some nodes in the pixel driving circuits 2. The reset signal lines 3 output signals through gate driving circuits 4. Specifically, the reset signal lines 3 extend in the horizontal direction and are connected to the gate driving circuits 4 on both sides of the display panel. The reset signal lines 3 are relatively long in the row direction. When the reset signal lines 3 are subjected to coupling interference from other signals, such as when the timing signal changes from a low potential to a high potential, the part of the reset signal lines 3 near the gate driving circuits 4 is closer to the driving source and the signal is more stable, and the coupling interference is less. However, the part of the reset signal lines 3 in the middle of the display area is less stable due to the impedance effect and is subjected to greater coupling interference. This can easily lead to different reset signals received by the pixel driving circuits 4 in different areas, resulting in uneven display on the display panel.

[0030] Referring to Figure 2, this application embodiment provides a display panel, which includes multiple pixel driving circuits 10, multiple reset signal lines 20, and connecting lines 30.

[0031] The plurality of pixel driving circuits 10 are arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect; a plurality of reset signal lines 20 extend along the first direction X and are arranged along the second direction Y, and one reset signal line 20 is connected to the plurality of pixel driving circuits 10 arranged along the first direction X; a connecting line 30 is connected between any two adjacent reset signal lines 20, and the connecting line 30 is set on a different layer from the reset signal lines 20.

[0032] In the implementation process, this embodiment of the application adds a connecting line 30 to the display panel, so that the connecting line 30 is connected to any two adjacent reset signal lines 20, thereby effectively reducing the impedance of the reset signal line 20, improving the signal transmission uniformity of the reset signal line 20, and improving the display uniformity of the display panel.

[0033] In one embodiment of this application, the connecting line extends along the second direction and is connected to a plurality of reset signal lines arranged along the second direction.

[0034] In one embodiment of this application, the display panel includes a plurality of connecting lines arranged along the first direction, each connecting line being connected to a plurality of reset signal lines arranged along the second direction, and the plurality of connecting lines intersecting with the plurality of reset signal lines to form a mesh structure.

[0035] In one embodiment of this application, the connecting line includes a plurality of connecting groups arranged along the first direction, each connecting group including at least two connecting sub-parts arranged along the second direction, each connecting sub-part being connected to at least two reset signal lines arranged along the second direction, and adjacent connecting sub-parts being spaced apart.

[0036] In one embodiment of this application, between two adjacent connection groups, the connecting sub-parts in one connection group are staggered, partially overlapped, or aligned with the connecting sub-parts in the other connection group.

[0037] In one embodiment of this application, within the same connection group, at least one pixel driving circuit is provided at an interval between two adjacent connection sub-parts.

[0038] In one embodiment of this application, any two adjacent reset signal lines are connected by at least one of the connecting sub-sections.

[0039] In one embodiment of this application, the display panel further includes a first type of transistor and a second type of transistor;

[0040] The display panel also includes:

[0041] substrate;

[0042] A first semiconductor layer is disposed on one side of the substrate. The material of the first semiconductor layer includes polycrystalline silicon, and the first semiconductor layer includes the active layer of the first type of transistor.

[0043] A second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate. The material of the second semiconductor layer includes metal oxide, and the second semiconductor layer includes the active layer of the second type of transistor.

[0044] A first gate layer is disposed on the side of the second semiconductor layer away from the first semiconductor layer. The first gate layer includes a plurality of reset signal lines and the gate of the second type of transistor.

[0045] The connection line is located on the side of the first gate layer away from or close to the substrate and is connected to the reset signal line through a via.

[0046] In one embodiment of this application, the display panel further includes a source / drain layer disposed on the side of the first gate layer away from the second semiconductor layer, and a conductive layer disposed on the side of the source / drain layer away from the first gate layer;

[0047] The source-drain layer includes the source-drain electrodes of the first type of transistor and the source-drain electrodes of the second type of transistor, and the conductive layer includes the connecting line.

[0048] In one embodiment of this application, the conductive layer further includes a plurality of data lines extending along the second direction and arranged along the first direction, with two adjacent data lines disposed between two adjacent pixel driving circuits, and a connecting line disposed between two adjacent data lines.

[0049] In one embodiment of this application, the pixel driving circuit includes a reset transistor, a switching transistor, a driving transistor, and a light-emitting device. The drain of the reset transistor, the drain of the switching transistor, and the source of the driving transistor are all connected to a first node. The source of the switching transistor is connected to the data line. The drain of the driving transistor is electrically connected to the light-emitting device. The gate of the reset transistor is connected to a timing signal. The source of the reset transistor is connected to the reset signal line.

[0050] In one embodiment of this application, the pixel driving circuit further includes a first reset transistor, a second reset transistor, a compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first capacitor, and a second capacitor;

[0051] In this configuration, the drain of the first light-emitting control transistor is connected to the first node; the source of the second light-emitting control transistor, the drain of the driving transistor, and the source of the compensation transistor are all connected to the second node; the gate of the driving transistor, the drain of the first reset transistor, and the drain of the compensation transistor are all connected to the third node; the drain of the second reset transistor, the drain of the second light-emitting control transistor, and the light-emitting device are all connected to the fourth node; the first capacitor is connected between the third node and the source of the first light-emitting control transistor; and the second capacitor is connected between the third node and the gate of the switching transistor.

[0052] In one embodiment of this application, the first gate layer further includes an anode reset signal line extending along the first direction and arranged along the second direction, the anode reset signal line being disposed adjacent to the reset signal line along the second direction, and the anode reset signal line being connected to the source of the second reset transistor;

[0053] The first semiconductor layer further includes a light-emitting control active layer of the first light-emitting control transistor, and the anode reset signal line partially overlaps with the light-emitting control active layer in a direction perpendicular to the substrate.

[0054] In one embodiment of this application, the reset signal line includes a first line segment located between two adjacent pixel driving circuits and a second line segment connected to opposite ends of the first line segment. The first line segment is located on the side of the second line segment away from the anode reset signal line. The connecting line is connected to the first line segment through a via. The first line segment does not overlap with the light-emitting control active layer in a direction perpendicular to the substrate.

[0055] In one embodiment of this application, the first type of transistor includes the switching transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the reset transistor, and the second reset transistor;

[0056] The second type of transistor includes the compensation transistor and the first reset transistor.

[0057] In one embodiment of this application, the second semiconductor layer includes the interconnect line.

[0058] Specifically, in one embodiment, please continue to refer to FIG2, a plurality of pixel driving circuits 10 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y can be perpendicular to each other, that is, the plurality of pixel driving circuits 10 are arranged in multiple rows and columns.

[0059] Furthermore, each reset signal line 20 is connected to a plurality of pixel driving circuits 10 arranged along the first direction X, that is, each reset signal line 20 is connected to a plurality of pixel driving circuits 10 located in the same row.

[0060] In one embodiment, the display panel further includes gate driving circuits 40 disposed on one side or opposite sides of the display panel along the first direction X, and a reset signal line 20 is also connected to the gate driving circuit 40. The gate driving circuit 40 inputs a reset signal into the reset signal line 20, and then transmits it to the pixel driving circuit 10 through the reset signal line 20. For example, when the display panel includes gate driving circuits 40 disposed on opposite sides of the display panel along the first direction X, the two ends of the reset signal line 20 are connected to the gate driving circuits 40 located on both sides of the display panel, and the middle part of the reset signal line 20 is connected to multiple pixel driving circuits 10 in the same row.

[0061] Referring to Figures 2, 3, 4, and 5, the pixel driving circuit 10 includes a light-emitting device, a driving transistor T01, a switching transistor T02, a compensation transistor T03, a first reset transistor T04, a first light-emitting control transistor T05, a second light-emitting control transistor T06, a second reset transistor T07, a reset transistor T08, a first capacitor Cst, and a second capacitor Cboost.

[0062] The drain of driving transistor T01 is connected to the second node B, the gate of driving transistor T01 is connected to the second node Q, and the source of driving transistor T01 is connected to the first node A.

[0063] The source of the first switching transistor T02 is connected to the data signal Data, the gate of the first switching transistor T02 is connected to the first scan signal Pscan, and the drain of the first switching transistor T02 is connected to the first node A.

[0064] The source of compensation transistor T03 is connected to the second node B, the gate of compensation transistor T03 is connected to the second scan signal NscanT3, and the drain of compensation transistor T03 is connected to the third node Q.

[0065] The source of the first reset transistor T04 is connected to the first reset signal Vi_G, the gate of the first reset transistor T04 is connected to the third scan signal NscanT4, and the drain of the first reset transistor T04 is connected to the third node Q.

[0066] The source of the first light-emitting control transistor T05 is connected to the first power supply signal VDD, the gate of the first light-emitting control transistor T05 is connected to the light-emitting control signal EM, and the drain of the first light-emitting control transistor T05 is connected to the first node A.

[0067] The source of the second light-emitting control transistor T06 is connected to the second node B, the gate of the second light-emitting control transistor T06 is connected to the light-emitting control signal EM, and the drain of the second light-emitting control transistor T06 is connected to the fourth node C.

[0068] The source of the second reset transistor T07 is connected to the anode reset signal Vi_ANo, the gate of the second reset transistor T07 is connected to the fourth scan signal Pscan2, and the drain of the second reset transistor T07 is connected to the fourth node C.

[0069] The source of reset transistor T08 is connected to the third reset signal Vi, the gate of reset transistor T08 is connected to the fourth scan signal Pscan2, and the drain of reset transistor T08 is connected to the first node A.

[0070] The first electrode of the light-emitting device is connected to the fourth node C, and the second electrode of the light-emitting device is connected to the second power supply signal VSS.

[0071] The first capacitor Cst is connected between the third node Q and the source of the first light-emitting control transistor T05; that is, it is connected between the third node Q and the first power supply signal VDD; the second capacitor Cboost is connected between the third node Q and the gate of the switching transistor T02; that is, it is connected between the third node Q and the first scan signal Pscan.

[0072] The display panel also includes multiple data lines 51 extending along the second direction Y and arranged along the first direction X. The drain of the reset transistor T08, the drain of the switching transistor T02, and the source of the driving transistor T01 are all connected to the first node A. The drain of the driving transistor T01 is electrically connected to the light-emitting device. The source of the switching transistor T02 is connected to the data line 51. The gate of the reset transistor T08 is connected to the timing signal (i.e., the fourth scan signal Pscan2). The source of the reset transistor T08 is connected to the reset signal line 20, i.e., connected to the third reset signal Vi.

[0073] It should be noted that when the fourth scan signal Pscan2 changes from a low potential to a high potential, the reset signal line 20 near the gate drive circuit 40 is closer to the drive source and has a more stable signal with less coupling interference. However, the reset signal line 20 in the middle of the display area has poor signal stability and is subject to greater coupling interference due to impedance. This can easily lead to different reset signals received by the pixel drive circuit 10 in different areas, which in turn has a greater impact on the electrical properties of the drive transistor T01, resulting in uneven display on the display panel.

[0074] In this embodiment of the application, the display panel further includes a connecting line 30, and the connecting line 30 is connected between any two adjacent reset signal lines 20 to realize the parallel connection of multiple reset signal lines 20, which can reduce the impedance of multiple reset signal lines 20, improve the uniformity of the transmitted signal of multiple reset signal lines 20, and thus improve the display uniformity of the display panel.

[0075] Furthermore, please refer to Figures 2, 3, 4, and 5 for the following explanation of the film structure of the display panel.

[0076] In one embodiment, the display panel includes a substrate 80, a plurality of spacer layers disposed on the substrate 80, and devices such as transistors, wirings, and electrodes located between adjacent spacer layers.

[0077] Specifically, the display panel includes a barrier layer 81 disposed on a substrate 80, a buffer layer 82 disposed on the side of the barrier layer 81 away from the substrate 80, a first semiconductor layer 73 disposed on the side of the buffer layer 82 away from the barrier layer 81, a first gate insulating layer 83 disposed on the buffer layer 82 and covering the first semiconductor layer 73, a second gate layer 74 disposed on the side of the first gate insulating layer 83 away from the buffer layer 82, a second gate insulating layer 84 disposed on the side of the first gate insulating layer 83 away from the buffer layer 82 and covering the second gate layer 74, a third gate layer 75 disposed on the side of the second gate insulating layer 84 away from the first gate insulating layer 83, a first interlayer dielectric layer 85 disposed on the side of the second gate insulating layer 84 away from the first gate insulating layer 83 and covering the third gate layer 75, and a first interlayer dielectric layer 85 disposed on the side of the first interlayer dielectric layer 85 away from the second gate insulating layer 84. The first interlayer dielectric layer 85 comprises a second semiconductor layer 76, a third gate insulating layer 86 disposed on the side of the first interlayer dielectric layer 85 away from the second gate insulating layer 84 and covering the second semiconductor layer 76, a first gate layer 60 disposed on the side of the third gate insulating layer 86 away from the first interlayer dielectric layer 85, a second interlayer dielectric layer 87 disposed on the side of the third gate insulating layer 86 away from the first interlayer dielectric layer 85 and covering the first gate layer 60, a source / drain layer 71 disposed on the side of the second interlayer dielectric layer 87 away from the third gate insulating layer 86, a first planarization layer 88 disposed on the side of the second interlayer dielectric layer 87 away from the third gate insulating layer 86 and covering the source / drain layer 71, a conductive layer 50 disposed on the side of the first planarization layer 88 away from the second interlayer dielectric layer 87, and a second planarization layer 89 disposed on the side of the first planarization layer 88 away from the second interlayer dielectric layer 87 and covering the conductive layer 50.

[0078] The display panel includes a first type of transistor T1 and a second type of transistor T2; the display panel includes a light-shielding layer 72 disposed in the blocking layer 81, and the light-shielding layer 72 can be located below the first type of transistor T1 to shield the first type of transistor T1 and improve the electrical stability of the first type of transistor T1.

[0079] The first type of transistor T1 includes a first active layer, a first gate, a second gate, a first source, and a first drain. The second type of transistor T2 includes a second active layer, a third gate, a fourth gate, a second source, and a second drain. The first semiconductor layer 73 includes a first active layer, the second gate layer 74 includes a first gate, the third gate layer 75 includes a second gate and a third gate, the second semiconductor layer 76 includes a second active layer, the first gate layer 60 includes a fourth gate, and the source-drain layer 71 includes a first source, a first drain, a second source, and a second drain.

[0080] The first active layer, the first gate, the second gate, the first source, and the first drain are all located on the side of the light-shielding layer 72 away from the substrate 80. The first source and the first drain are respectively connected to both sides of the first active layer; the second source and the second drain are connected to both sides of the second active layer.

[0081] In one embodiment, the material of the first semiconductor layer 73 includes polysilicon, such as Poly Si, and the material of the second semiconductor layer 76 includes metal oxide, such as IGZO. That is, the first type of transistor T1 can be a transistor in the pixel driving circuit 10 that uses polysilicon to fabricate the active layer. For example, the first type of transistor T1 may include a switching transistor T02, a driving transistor T01, a first light-emitting control transistor T05, a second light-emitting control transistor T06, a second reset transistor T07, and a reset transistor T08. The second type of transistor T2 can be a transistor in the pixel driving circuit 10 that uses metal oxide to fabricate the active layer. For example, the second type of transistor T2 may include a compensation transistor T03 and a first reset transistor T04.

[0082] In addition, referring to Figures 4, 5 and 6, the first gate layer 60 also includes an anode reset signal line 63, which extends along the first direction X and is arranged along the second direction Y, and is connected to the source of the second reset transistor T07; the anode reset signal line 63 is arranged adjacent to the reset signal line 20 along the second direction Y.

[0083] In one embodiment, the first semiconductor layer 73 includes a light-emitting control active layer 731 of the first light-emitting control transistor T05, and the anode reset signal line 63 partially overlaps with the light-emitting control active layer 731 in a direction perpendicular to the substrate 80.

[0084] The reset signal line 20 includes a first segment 21 located between two adjacent pixel driving circuits 10 and a second segment 22 connected to the opposite ends of the first segment 21. The first segment 21 is located on the side of the second segment 22 away from the anode reset signal line 63. The connecting line 30 is connected to the first segment 21 through a via. The first segment 21 and the light-emitting control active layer 731 do not partially overlap in the direction perpendicular to the substrate 80. That is, in this embodiment, the reset signal line 20 is bent in a direction away from the anode reset signal line 63. The first line segment 21 is connected to the connecting line 30, thereby increasing the distance between the via of the first line segment 21 and the connecting line 30 and the light-emitting control active layer 731. This avoids overlap between the via of the first line segment 21 and the connecting line 30 and the light-emitting control active layer 731, thereby effectively improving the film flatness of the opening between the first line segment 21 and the connecting line 30, as well as the stress and electrical effects of the opening on the light-emitting control active layer 731, improving the yield of the opening and the stability of the light-emitting control active layer 731.

[0085] Furthermore, the structure of the reset signal line 20 and the connecting line 30 in the embodiments of this application will be described below in conjunction with the specific film structure described above.

[0086] In one embodiment of this application, please continue to refer to Figures 2, 3, 4 and 5. The first gate layer 60 includes a reset signal line 20.

[0087] Furthermore, the conductive layer 50 includes a connecting line 30 and a data line 51, and the source-drain layer 71 may also include a transition portion 711. The connecting line 30 passes through the first planarization layer 88 and connects to the transition portion 711. The transition portion 711 passes through the second interlayer dielectric layer 87 and connects to the reset signal line 20, so as to realize the connection between the connecting line 30 and the reset signal line 20. The connecting line 30 is connected between any two adjacent reset signal lines 20 to realize the parallel connection of multiple reset signal lines 20, which can reduce the impedance of multiple reset signal lines 20, improve the uniformity of the transmitted signal of multiple reset signal lines 20, and thus improve the display uniformity of the display panel.

[0088] In addition, please refer to Figures 2, 3, 4 and 5, where Figure 5 is a schematic diagram of the distribution structure of the first gate layer 60 and the conductive layer 50 in the pixel driving circuit 10; wherein, the first gate layer 60 includes a reset signal line 20, a first scan signal line 61, a second scan signal line 62 and an anode reset signal line 63; wherein, the first scan signal line 61 and the second scan signal line 62 are both used to transmit the first scan signal Pscan, and the anode reset signal line 63 is used to transmit the anode reset signal Vi_ANo.

[0089] The conductive layer 50 may include data lines 51 and connecting lines 30, wherein two adjacent data lines 51 are provided between two adjacent pixel driving circuits 10, and a connecting line 30 is provided between two adjacent data lines 51.

[0090] In one embodiment, as shown in FIG7, the display panel includes multiple connecting lines 30, which extend along the second direction Y and are arranged along the first direction X. Each connecting line 30 is located between two adjacent data lines 51, and each connecting line 30 is continuously arranged in the second direction Y. Each connecting line 30 connects to multiple reset signal lines 20 arranged along the second direction Y, and the multiple connecting lines 30 and the multiple reset signal lines 20 intersect to form a mesh structure.

[0091] It is understood that, in this embodiment of the application, by adding multiple connecting lines 30 and cross-connecting multiple connecting lines 30 with multiple data lines 51 to form a mesh structure, the impedance of the reset signal line 20 can be reduced more effectively, the signal transmission uniformity in the multiple reset signal lines 20 can be improved, and the display uniformity of the display panel can be improved.

[0092] In another embodiment, referring to Figures 2 and 8, the connecting line 30 is discontinuous. Specifically, the connecting line 30 includes a plurality of connecting groups 300 arranged along a first direction. Each connecting group 300 includes at least two connecting sub-sections 31 arranged along a second direction Y. Each connecting sub-section 31 is connected to at least two reset signal lines 20 arranged along the second direction Y. Adjacent connecting sub-sections 31 are spaced apart.

[0093] It should be noted that adjacent connecting sub-parts 31 can be two adjacent connecting sub-parts 31 along the first direction X or two adjacent connecting sub-parts 31 along the second direction Y; that is, each connecting sub-part 31 is spaced apart from its adjacent connecting sub-part 31 along the first direction X and the second direction Y.

[0094] In one embodiment, referring to Figures 8 and 9, between two adjacent connection groups 300, the connection sub-parts 31 in one connection group 300 are staggered from the connection sub-parts 31 in the other connection group 300. Each connection sub-part 31 is connected to two adjacent reset signal lines 20 along the second direction Y, and a pixel driving circuit 10 is spaced between two adjacent connection sub-parts 31 along the second direction Y. Thus, the connection sub-parts 31 in multiple connection groups 300 and multiple reset signal lines 20 are connected to form a mesh structure as shown in Figure 9.

[0095] In another embodiment, referring to Figures 8 and 10, between two adjacent connection groups 300, the connection sub-part 31 in one connection group 300 partially overlaps with the connection sub-part 31 in the other connection group 300. The overlapping portion of the connection sub-part 31 in one connection group 300 and the connection sub-part 31 in the other connection group 300 is the length of a pixel driving circuit 10 along the second direction Y. Each connection sub-part 31 is connected to three adjacent reset signal lines 20 along the second direction Y, and there is a pixel driving circuit 10 between two adjacent connection sub-parts 31 along the second direction Y. Thus, the connection sub-parts 31 in multiple connection groups 300 and multiple reset signal lines 20 are connected to form a mesh structure as shown in Figure 10.

[0096] In another embodiment, referring to Figures 8 and 11, between two adjacent connection groups 300, the connection sub-parts 31 in one connection group 300 are aligned with the connection sub-parts 31 in the other connection group 300. The overlapping portion of the connection sub-parts 31 in one connection group 300 and the connection sub-parts 31 in the other connection group 300 is a pixel driving circuit 10 aligned along the first direction X. Each connection sub-part 31 is connected to two adjacent reset signal lines 20 along the second direction Y, and a pixel driving circuit 10 is spaced between two adjacent connection sub-parts 31 along the second direction Y. Thus, the connection sub-parts 31 in multiple connection groups 300 and multiple reset signal lines 20 are connected to form a mesh structure as shown in Figure 11.

[0097] It should be noted that in other embodiments of this application, the number of reset signal lines 20 connected to each connecting sub-part 31 along the second direction Y can be more, such as four, five, or six, and the number of pixel driving circuits 10 spaced between two adjacent connecting sub-parts 31 along the second direction Y can also be more, such as two, three, or four, etc., which is not limited here; however, it must be ensured that any two adjacent reset signal lines 20 are connected through at least one connecting sub-part 31, so that multiple reset signal lines 20 are all arranged in parallel; and in this embodiment of the application, by adding multiple connecting lines 30, and the multiple connecting lines 30 and multiple data lines 51 are cross-connected to form a mesh structure, the impedance of the reset signal lines 20 can be reduced more effectively, the signal transmission uniformity in the multiple reset signal lines 20 can be improved, and the display uniformity of the display panel can be improved.

[0098] In another embodiment of this application, referring to Figures 2 and 12, the difference between this embodiment and the embodiment shown in Figure 4 is that the second semiconductor layer 76 may include a second active layer and a connection line 30, that is, the connection line 30 is disposed on the same layer as the second active layer of the first type of transistor T1.

[0099] It should be noted that the connecting line 30 is obtained by conducting the semiconductor material in the semiconductor layer, so the connecting line 30 can achieve the function of conducting electricity.

[0100] The reset signal line 20 is located in the first gate layer 60, and the reset signal line 20 is connected to the connection line 30 through a via. Specifically, the reset signal line 20 passes through the third gate insulating layer 86 and is connected to the connection line 30.

[0101] In summary, this embodiment of the application, by adding a connecting line 30 to the display panel, allows the connecting line 30 to be connected to any two reset signal lines 20, thereby effectively reducing the impedance of the reset signal lines 20, improving the signal transmission uniformity of the reset signal lines 20, and improving the display uniformity of the display panel. Furthermore, by designing the connection method between the connecting line 30 and the reset signal lines 20, this embodiment of the application can form various mesh structures between the connecting line 30 and the reset signal lines 20, further reducing the impedance of the reset signal lines 20, further improving the signal transmission uniformity of the reset signal lines 20, and further improving the display uniformity of the display panel.

[0102] Referring to Figure 13, this application embodiment also provides a display device 90, which includes a display panel 91, and the display panel 91 can be the display panel described in the above embodiment.

[0103] It is understood that since the display device 90 has the same display panel as in the above embodiments, the embodiments of this application can effectively reduce the impedance of the reset signal line 20 in the display device 90, improve the signal transmission uniformity of the reset signal line 20, and improve the display uniformity of the display device 90. Furthermore, in the embodiments of this application, by designing the connection method between the connecting line 30 and the reset signal line 20, the connection between the connecting line 30 and the reset signal line 20 can form a variety of mesh structures, so as to further reduce the impedance of the reset signal line 20, further improve the signal transmission uniformity of the reset signal line 20, and further improve the display uniformity of the display device 90.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0105] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, comprising: a plurality of pixel driving circuits arranged along a first direction and a second direction, the first direction and the second direction intersecting each other; a plurality of reset signal lines extending along the first direction and arranged along the second direction, one of the reset signal lines being connected to a plurality of the pixel driving circuits arranged along the first direction; a connection line connected between any two adjacent reset signal lines, the connection line being disposed in a different layer from the reset signal lines.

2. The display panel of claim 1, wherein, The connection line extends along the second direction, and the connection line is connected to a plurality of the reset signal lines arranged along the second direction.

3. The display panel of claim 2, wherein, The display panel comprises a plurality of the connection lines arranged along the first direction, each of the connection lines being connected to a plurality of the reset signal lines arranged along the second direction, and a plurality of the connection lines and a plurality of the reset signal lines intersecting each other to form a mesh structure.

4. The display panel of claim 1, wherein, The connection line comprises a plurality of connection groups arranged along the first direction, each of the connection groups comprising at least two connection subparts arranged along the second direction, each of the connection subparts being connected to at least two of the reset signal lines arranged along the second direction, and adjacent connection subparts being spaced apart from each other.

5. The display panel of claim 4, wherein, Between any two adjacent connection groups, the connection subparts in one of the connection groups are staggered, partially overlapped, or aligned with the connection subparts in the other of the connection groups.

6. The display panel of claim 4, wherein, Between any two adjacent connection subparts in the same connection group, at least one of the pixel driving circuits is arranged therebetween.

7. The display panel according to any one of claims 4 to 6, wherein, Any two adjacent reset signal lines are connected through at least one of the connection subparts.

8. The display panel of claim 1, wherein, The display panel further comprises a first type of transistor and a second type of transistor. The display panel further comprises: a substrate; a first semiconductor layer disposed on one side of the substrate, a material of the first semiconductor layer comprising polysilicon, and the first semiconductor layer comprising an active layer of the first type of transistor; a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate, a material of the second semiconductor layer comprising metal oxide, and the second semiconductor layer comprising an active layer of the second type of transistor; a first gate layer disposed on a side of the second semiconductor layer away from the first semiconductor layer, the first gate layer comprising a plurality of the reset signal lines and gates of the second type of transistor; wherein the connection line is disposed on a side of the first gate layer away from or close to the substrate and connected to the reset signal lines through a via.

9. The display panel of claim 8, wherein, The display panel further comprises a source-drain layer disposed on a side of the first gate layer away from the second semiconductor layer, and a conductive layer disposed on a side of the source-drain layer away from the first gate layer; wherein the source-drain layer comprises sources and drains of the first type of transistor and sources and drains of the second type of transistor, and the conductive layer comprises the connection line.

10. The display panel of claim 9, wherein, The conductive layer further comprises a plurality of data lines extending along the second direction and arranged along the first direction, two adjacent data lines being arranged between any two adjacent pixel driving circuits, and the connection line being arranged between the two adjacent data lines.

11. The display panel of claim 10, wherein, The pixel driving circuit comprises a reset transistor, a switch transistor, a driving transistor and a light emitting device, the drain of the reset transistor, the drain of the switch transistor and the source of the driving transistor are all connected to a first node, the source of the switch transistor is connected to the data line, the drain of the driving transistor is electrically connected to the light emitting device, the gate of the reset transistor is connected to a timing signal, and the source of the reset transistor is connected to the reset signal line.

12. The display panel of claim 11, wherein, The pixel driving circuit further comprises a first reset transistor, a second reset transistor, a compensation transistor, a first light emitting control transistor, a second light emitting control transistor, a first capacitor and a second capacitor. The drain of the first light emitting control transistor is connected to the first node, the source of the second light emitting control transistor, the drain of the driving transistor and the source of the compensation transistor are all connected to a second node, the gate of the driving transistor, the drain of the first reset transistor and the drain of the compensation transistor are all connected to a third node, the drain of the second reset transistor, the drain of the second light emitting control transistor and the light emitting device are all connected to a fourth node, the first capacitor is connected between the third node and the source of the first light emitting control transistor, and the second capacitor is connected between the third node and the gate of the switch transistor.

13. The display panel of claim 12, wherein, The first gate layer further comprises anode reset signal lines extending along the first direction and arranged along the second direction, the anode reset signal lines are arranged adjacent to the reset signal lines along the second direction, and the anode reset signal lines are connected to the sources of the second reset transistors. The first semiconductor layer further comprises light emitting control active layers of the first light emitting control transistors, and the anode reset signal lines partially overlap the light emitting control active layers in a direction perpendicular to the substrate.

14. The display panel of claim 13, wherein, The reset signal line comprises a first line segment between adjacent two pixel driving circuits and a second line segment connected to opposite ends of the first line segment, the first line segment is located on a side of the second line segment away from the anode reset signal lines, the connection line is connected to the first line segment through a via, and the first line segment does not overlap the light emitting control active layers in a direction perpendicular to the substrate.

15. The display panel of claim 11, wherein, The first type of transistor comprises the switch transistor, the driving transistor, the first light emitting control transistor, the second light emitting control transistor, the reset transistor and the second reset transistor. The second type of transistor comprises the compensation transistor and the first reset transistor.

16. The display panel of claim 8, wherein, The second semiconductor layer comprises the connection line.

17. A display device, comprising a display panel, the display panel comprising: a plurality of pixel driving circuits arranged along a first direction and a second direction, the first direction and the second direction intersecting; a plurality of reset signal lines extending along the first direction and arranged along the second direction, one reset signal line being connected to a plurality of pixel driving circuits arranged along the first direction; A connection line is connected between any two adjacent reset signal lines and is arranged in a different layer from the reset signal lines.

18. The display device of claim 17, wherein, The connection line extends along the second direction and is connected to a plurality of reset signal lines arranged along the second direction.

19. The display device of claim 17, wherein, The connection line comprises a plurality of connection groups arranged along the first direction, each connection group comprises at least two connection subparts arranged along the second direction, each connection subpart is connected to at least two reset signal lines arranged along the second direction, and adjacent connection subparts are arranged at intervals.

20. The display device of claim 17, wherein, The display panel further comprises a first type of transistor and a second type of transistor. The display panel further comprises: A substrate; A first semiconductor layer arranged on one side of the substrate, a material of the first semiconductor layer comprises polysilicon, and the first semiconductor layer comprises an active layer of the first type of transistor; A second semiconductor layer arranged on a side of the first semiconductor layer away from the substrate, a material of the second semiconductor layer comprises metal oxide, and the second semiconductor layer comprises an active layer of the second type of transistor; A first gate layer arranged on a side of the second semiconductor layer away from the first semiconductor layer, the first gate layer comprises a plurality of reset signal lines and gates of the second type of transistor; The connection line is arranged on a side of the first gate layer away from or close to the substrate and is connected to the reset signal lines through a via.

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