Display panel and display apparatus

Abstract

The present invention relates to the technical field of display. Provided are a display panel and a display apparatus, which are used for narrowing the bezel width of the display panel and improving the display uniformity of the display panel. A display area of the display panel comprises a first edge and a second edge arranged in a first direction, a plurality of first signal lines, a plurality of connecting lines, and a plurality of load compensation lines electrically connected to second signal sub-lines; the plurality of first signal lines are arranged in the first direction, and the first signal lines extend in the first direction; the plurality of first signal lines at least comprise a plurality of first signal sub-lines and a plurality of second signal sub-lines, and each second signal sub-line is located on the side of a first signal sub-line that is away from the first edge; a non-display area comprises a first fan-out line and a second fan-out line, the connecting lines are electrically connected to the first signal sub-lines and the first fan-out line, and the second fan-out line is electrically connected to the second signal sub-lines; and in a direction from the first edge to the second edge, the resistance values of the load compensation lines electrically connected to the second signal sub-lines gradually decrease.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202410703376.2, filed with the State Intellectual Property Office of China on May 31, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology

[0003] With the continuous development of science and technology, more and more display devices are being widely used in people's daily lives and work, becoming indispensable tools. Moreover, with the continuous development of display technology, consumers' demands for monitors are constantly increasing, leading to the emergence of various types of displays, including liquid crystal displays (LCDs) and active display technologies such as organic light-emitting diode (OLED) displays. OLED display panels have become the mainstream display technology in the market due to their advantages such as simple manufacturing process, low cost, high luminous efficiency, easy formation of flexible structures, low power consumption, high color saturation, and wide viewing angle.

[0004] However, current organic light-emitting diode (OLED) display panels have relatively wide bezels and suffer from uneven brightness, which affects the display effect.

[0005] Summary of the Invention

[0006] In view of this, the present invention provides a display panel and a display device to narrow the width of the non-display area of ​​the display panel and improve the display uniformity of the display panel.

[0007] In a first aspect, embodiments of the present invention provide a display panel, including a display area and a non-display area, wherein the display area includes a plurality of first signal lines and a plurality of connecting lines; the plurality of first signal lines are arranged along a first direction and extend along the first direction;

[0008] The display panel also includes a first edge and a second edge arranged along a first direction;

[0009] The plurality of first signal lines include at least a plurality of first sub-signal lines and a plurality of second sub-signal lines, wherein the second sub-signal lines are located on the side of the first sub-signal lines away from the first edge;

[0010] The non-display area includes a first sector output line and a second sector output line. The connecting line electrically connects the first sub-signal line and the first sector output line, and the second sector output line is electrically connected to the second sub-signal line.

[0011] The display panel also includes multiple load compensation lines electrically connected to the second sub-signal lines, with the resistance of the load compensation lines electrically connected to the second sub-signal lines gradually decreasing along the direction from the first edge to the second edge.

[0012] Secondly, embodiments of the present invention provide a display device, including the display panel described above.

[0013] The display panel and display device provided in this invention, by providing a connecting line to the first sub-signal line in the display area, can move the first fan-out line connected to the first sub-signal line from the edge fan-out area to the side of the edge fan-out area away from the first edge. This reduces the number of fan-out lines in the edge fan-out area corresponding to the first sub-signal line in the first direction, thereby reducing the width of the non-display area. Furthermore, by providing a load compensation line electrically connected to the second sub-signal line, this invention can balance the load difference between the first and second sub-signal lines, improving the display uniformity of the sub-pixels connected to the first and second sub-signal lines and avoiding display unevenness problems. Moreover, by gradually decreasing the resistance value of the load compensation line electrically connected to the second sub-signal line along the direction from the first edge to the second edge, this invention improves the brightness consistency of the sub-pixels electrically connected to the first and second sub-signal lines while simultaneously reducing the power consumption of the display panel. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0016] Figure 2 is an equivalent circuit diagram of a sub-pixel provided in an embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of the working timing of a pixel driving circuit provided in an embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 6 is a wiring diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0021] Figure 7 is a partially enlarged schematic diagram of a display panel provided in an embodiment of the present invention;

[0022] Figure 8 is a schematic diagram of a cross section along BB' in Figure 7;

[0023] Figure 9 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0024] Figure 10 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0025] Figure 11 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0026] Figure 12 is a partially enlarged schematic diagram of another display panel provided in an embodiment of the present invention;

[0027] Figure 13 is a schematic diagram of a cross section along CC' in Figure 12;

[0028] Figure 14 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0029] Figure 15 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0030] Figure 16 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0031] Figure 17 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0032] Figure 18 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0033] Figure 19 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0034] Figure 20 is a schematic diagram showing the relative positions of a load compensation line, a constant signal trace, and a first electrode according to an embodiment of the present invention.

[0035] Figure 21 is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0036] Figure 22 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0037] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0039] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0040] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0041] It should be understood that although the terms "first," "second," etc., may be used to describe signal lines in embodiments of the present invention, these signal lines should not be limited to these terms. These terms are only used to distinguish the individual signal lines from one another. For example, without departing from the scope of embodiments of the present invention, a first signal line may also be referred to as a second signal line, and similarly, a second signal line may also be referred to as a first signal line.

[0042] This invention provides a display panel, as shown in FIG1, which is a schematic diagram of a display panel according to an embodiment of this invention. The display panel 100 includes a display area AA and a non-display area NA. The non-display area NA at least partially surrounds the display area AA. The display area AA includes a plurality of sub-pixels (not shown in FIG1). Each sub-pixel includes a pixel driving circuit and a light-emitting element that are electrically connected to each other.

[0043] Optionally, as shown in Figure 2, which is an equivalent circuit diagram of a sub-pixel provided in an embodiment of the present invention, the sub-pixel 1 includes a pixel driving circuit 10 and a light-emitting element 20 electrically connected. The pixel driving circuit 10 includes a driving transistor T0, a first reset module 101, a second reset module 102, a data writing module 103, a light-emitting control module 104, and a threshold compensation module 105. The gate of the driving transistor T0 is electrically connected to a first node N1, the first electrode of the driving transistor T0 is electrically connected to a second node N2, and the second electrode of the driving transistor T0 is electrically connected to a third node N3.

[0044] The light-emitting control module 104 includes a first sub-control module 1041 and a second sub-control module 1042. The input terminal of the first sub-control module 1041 is electrically connected to the first power signal line PVDD, which transmits a first power supply voltage. The output terminal of the first sub-control module 1041 is electrically connected to the first electrode of the driving transistor T0. The input terminal of the second sub-control module 1042 is electrically connected to the second electrode of the driving transistor T0, and its output terminal is electrically connected to the first electrode of the light-emitting element 20. The second electrode of the light-emitting element 20 is electrically connected to the second power signal line PVEE, which transmits a second power supply voltage. The control terminals of both the first sub-control module 1041 and the second sub-control module 1042 are electrically connected to the light-emitting control signal line E.

[0045] The control terminal of the first reset module 101 is electrically connected to the first scan line S1, the input terminal is electrically connected to the first reset signal line Ref1, and the output terminal is electrically connected to the first electrode of the light-emitting element 20. The control terminal of the second reset module 102 is electrically connected to the first scan line S1, the input terminal is electrically connected to the second reset signal line Ref2, and the output terminal is electrically connected to the gate of the driving transistor M0.

[0046] The control terminal of the data writing module 103 is electrically connected to the second scan line S2, the input terminal is electrically connected to the data signal line Data, and the output terminal is electrically connected to the first terminal of the driving transistor T0. The control terminal of the threshold compensation module 105 is electrically connected to the second scan line S2, the input terminal is electrically connected to the second terminal of the driving transistor T0, and the output terminal is electrically connected to the gate of the driving transistor T0.

[0047] For example, as shown in Figure 2, the first sub-control module 1041 includes a first transistor T1, the data writing module 103 includes a second transistor T2, the threshold compensation module 105 includes a third transistor T3, the second reset module 102 includes a fourth transistor T4, the second sub-control module 1042 includes a fifth transistor T5, and the first reset module 101 includes a sixth transistor T6. The pixel driving circuit 10 also includes a storage capacitor Cst. The first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate is electrically connected to the first power signal line PVDD.

[0048] Referring to Figures 2 and 3, Figure 3 is a schematic diagram of the working timing of a pixel driving circuit provided in an embodiment of the present invention. The working process of the pixel driving circuit 10 includes a reset stage t1, a charging stage t2, and a light emission stage t3.

[0049] During the reset phase t1, the first scan line S1 controls the fourth transistor T4 and the sixth transistor T6 to turn on, and the second reset signal provided by the second reset signal line Ref2 resets the first node N1 through the fourth transistor T4. The first reset signal provided by the first reset signal line Ref1 resets the first electrode of the light-emitting element 20 through the sixth transistor T6. For example, the first reset signal and the second reset signal can be equal, or they can be unequal.

[0050] During the charging phase t2, the second scan line S2 controls the second transistor T2 to turn on, and the data voltage Vdata provided by the data signal line Data is written to the second node N2 through the second transistor T2. The driving transistor T0 is then turned on. During this phase, the second scan line S2 controls the third transistor T3 to turn on. Throughout this process, the potential of the first node N1 continuously changes until the potential VN1 of the first node N1 changes to VN1 = Vdata - |Vth|, where Vth is the threshold voltage of the driving transistor T0.

[0051] During the light-emitting stage t3, the first transistor T1, the fifth transistor T5, and the driving transistor T0 are turned on, and the light-emitting element 20, which is electrically connected to the pixel driving circuit 10, is lit.

[0052] In this embodiment of the invention, the display area AA includes multiple first signal lines 11. The multiple first signal lines 11 are arranged along a first direction h1 and extend along a second direction h2; the first direction h1 and the second direction h2 intersect. Figure 1 illustrates this by showing the first direction h1 and the second direction h2 being perpendicular. In this embodiment of the invention, one first signal line 11 is electrically connected to multiple pixel driving circuits 10 arranged along the second direction h2.

[0053] Optionally, as shown in Figure 1, the aforementioned data signal line Data includes a first signal line 11.

[0054] As shown in Figure 1, in this embodiment of the invention, the plurality of first signal lines 11 include at least a plurality of first sub-signal lines 111 and a plurality of second sub-signal lines 112, wherein the second sub-signal lines 112 are located on the side of the first sub-signal lines 111 away from the first edge E1.

[0055] For example, as shown in FIG1, the first sub-signal line 111 and the second sub-signal line 112 are located between the first edge E1 and the first symmetry line X1 of the display area AA. The first symmetry line X1 extends along the second direction h2. The first edge E1 is the edge in the display panel 100 that has the shortest distance between itself and the first sub-signal line 111 among the two edges opposite each other along the first direction h1. The other edge in the display panel 100 that has the same distance is the second edge E2. That is, the distance between the first sub-signal line 111 and the first edge E1 is less than the distance between the first sub-signal line 111 and the second edge E2, and the distance between the second sub-signal line 112 and the first edge E1 is less than the distance between the second sub-signal line 112 and the second edge E2.

[0056] Depending on the position of the first sub-signal line 111, the positions of the first edge E1 and the second edge E2 will change accordingly. For example, as shown in FIG1, the plurality of first signal lines 11 include two sets of first sub-signal lines and two sets of second sub-signal lines located on both sides of the first symmetry line X1. In FIG1, the two sets of first sub-signal lines are labeled as 111_1 and 111_2, and the two sets of second sub-signal lines are labeled as 112_1 and 112_2, respectively. Optionally, in this embodiment of the invention, the two sets of first sub-signal lines 111 can be symmetrically arranged about the first symmetry line X1 of the display area AA, and the two sets of second sub-signal lines 112 can be arranged about the first symmetry line X1 of the display area AA. Taking the orientation shown in FIG1 as an example, for the second sub-signal line 112_1 located to the left of the first symmetry line X1, the first edge E1_1 is the left edge of the display panel 100, and the second edge E2_1 is the right edge of the display panel 100. For the second sub-signal line 112_2 located to the right of the first symmetry line X1, the first edge E1_2 is the right edge of the display panel 100, and the second edge E2_2 is the left edge of the display panel 100.

[0057] Referring again to Figure 1, the display area AA also includes multiple connecting lines 2. The non-display area NA includes a first fan-out line 31 and a second fan-out line 32. The connecting lines 2 are electrically connected to the first sub-signal line 111 and the first fan-out line 31, and the second fan-out line 32 is electrically connected to the second sub-signal line 112; that is, the second fan-out line 32 is not electrically connected to the second sub-signal line 112 via a connecting line. The first fan-out line 31 and the second fan-out line 32 are electrically connected to pin 5. Pin 5 is electrically connected to a driver chip (not shown).

[0058] In this embodiment of the invention, as shown in FIG1, the display panel 100 further includes a plurality of load compensation lines 4 electrically connected to the second sub-signal line 112. The load compensation lines 4 are used to increase the load of the second sub-signal line 112 and reduce the load difference between the second sub-signal line 112 and the first sub-signal line 111.

[0059] In this embodiment of the invention, the resistance value of the load compensation line 4, which is electrically connected to the second sub-signal line 112, gradually decreases along the direction from the first edge E1 to the second edge E2.

[0060] When the display panel 100 is operating, the first sub-signal line 111 can receive signals provided by the corresponding pin 5 through the connection line 2 located in the display area AA and the first fan-out line 31 located in the non-display area NA, thereby driving the sub-pixels electrically connected to the first sub-signal line 111 to light up. The second sub-signal line 112 can directly receive driving signals through the second fan-out line 32 located in the non-display area NA, thereby driving the sub-pixels electrically connected to the second sub-signal line 112 to light up.

[0061] In this embodiment of the invention, by setting the connecting line 2 connecting the first sub-signal line 111 and the corresponding pin 5 in the display area AA, the first fan-out line 31 connected to the first sub-signal line 111 can be moved from the edge fan-out area FA to the side of the edge fan-out area FA away from the first edge E1. This reduces the number of fan-out lines corresponding to the first sub-signal line 111 passing through the edge fan-out area FA, thus reducing the width of the edge fan-out area FA. As shown in Figure 1, the edge fan-out area FA refers to the area traversed by the extension line of the first sub-signal line 111 in the non-display area NA. While ensuring the minimum spacing of the fan-out lines in the edge fan-out area FA, based on the method provided by this embodiment of the invention, the number of fan-out lines in the edge fan-out area FA can be reduced, and even fan-out lines can be omitted from the edge fan-out area FA, thereby compressing the width of the edge fan-out area FA in the second direction h2.

[0062] Specifically, as shown in Figure 1, when the display panel 100 is designed as an irregularly shaped display panel with an R-angle, the extension line of the first sub-signal line 111 passes through the R-angle, that is, the outline of the edge fan-out area NA1 also presents an arc shape. In this embodiment of the invention, by setting the connecting line 2 connecting the first sub-signal line 111 in the irregularly shaped display panel in the display area AA, the width of the edge fan-out area NA1 in the second direction h2 can be reduced, which is beneficial to improving the visual effect of the irregularly shaped display panel.

[0063] Because the first sub-signal line 111 is connected to the connecting line 2, while the second sub-signal line 112 is not connected, there is a load difference between the first sub-signal line 111 and the second sub-signal line 112. When the display panel 100 is displaying, the brightness of the sub-pixels electrically connected to the first sub-signal line 111 and the sub-pixels electrically connected to the second sub-signal line 112 will differ. This embodiment of the invention, by providing a load compensation line 4 electrically connected to the second sub-signal line 112, can balance the load difference between the first sub-signal line 111 and the second sub-signal line 112. Furthermore, along the direction from the first edge E1 to the second edge E2, this embodiment of the invention gradually reduces the resistance value of the load compensation line 4 electrically connected to the second sub-signal line 112. This improves the brightness consistency of the sub-pixels electrically connected to the first sub-signal line 111 and the sub-pixels electrically connected to the second sub-signal line 112. Compared to setting the resistance value of each load compensation line 4 to be equal to the resistance value of the load compensation line 4 electrically connected to the first second sub-signal line 112, where the first second sub-signal line 112 refers to the second sub-signal line 112 adjacent to the first sub-signal line 111, this also avoids setting the resistance value of all load compensation lines 4 to be too large, which is beneficial to reducing the power consumption of the display panel 100.

[0064] It should be noted that the structure of the pixel driving circuit 10 shown in Figure 2, and the types of transistors therein, are only schematic. Depending on the different design requirements of the display panel, the pixel driving circuit 10 can be designed with other structures. For example, the pixel driving circuit 10 can be designed as a 2T1C structure including two transistors and one storage capacitor, or it can be designed as an 8T1C structure including eight transistors and one storage capacitor. Optionally, the third transistor T3 or the fourth transistor T4 in Figure 2 can also be configured to include oxide transistors. The specific structure of the pixel driving circuit 10 and the specific types of transistors therein are not limited in the embodiments of the present invention.

[0065] For example, in this embodiment of the invention, the resistance difference value of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually increases along the direction from the first edge E1 to the second edge E2. This configuration balances the load difference between the first sub-signal line 111 and the second sub-signal line 112, improving the brightness consistency of the sub-pixels electrically connected to the first sub-signal line 111 and the sub-pixels electrically connected to the second sub-signal line 112. Simultaneously, it allows for a smaller resistance difference value between two adjacent second sub-signal lines 112 closer to the first sub-signal line 111, and a larger resistance difference value between two adjacent second sub-signal lines 112 farther from the first sub-signal line 111. The closer the second sub-signal line 112 is to the first sub-signal line 111, the easier it is for the human eye to observe the brightness inconsistency between the sub-pixels driven by the second sub-signal line 112 and the sub-pixels driven by the first sub-signal line 111 due to load differences. In this embodiment of the invention, by setting a smaller resistance difference between two adjacent second sub-signal lines 112 close to the first sub-signal line 111, the load of the second sub-signal line 112 can be compensated more precisely, which is beneficial to improving the display effect. Furthermore, by setting a larger resistance difference between two adjacent second sub-signal lines 112 far from the first sub-signal line 111, this embodiment of the invention improves display uniformity while avoiding the need for excessive load compensation lines 4, which is beneficial to reducing the power consumption of the display panel 100.

[0066] In one embodiment, the cross-sectional area and conductivity of the load compensation lines 4 electrically connected to two adjacent second sub-signal lines 112 are made to be the same. Based on this design, along the direction from the first edge E1 to the second edge E2, the length difference of the load compensation lines 4 electrically connected to the two adjacent second sub-signal lines 112 can be gradually increased, so that the resistance difference of the load compensation lines 4 electrically connected to the two adjacent second sub-signal lines 112 gradually increases.

[0067] Optionally, the resistance difference value of the load compensation line 4 electrically connected to the two adjacent second sub-signal lines 112 is the same along the direction from the first edge E1 to the second edge E2. Based on this setting, while reducing the load difference between the first sub-signal line 111 and the second sub-signal line 112 and reducing the power consumption of the display panel 100, the resistance value distribution of the different load compensation lines 4 can be made more regular, reducing the design difficulty of the resistance value of the load compensation lines 4.

[0068] In another embodiment, the cross-sectional area and conductivity of the load compensation lines 4 electrically connected to two adjacent second sub-signal lines 112 can be made the same. Based on this design, the length difference of the load compensation lines 4 electrically connected to two adjacent second sub-signal lines 112 can be made the same, so that the resistance difference of the load compensation lines 4 electrically connected to two adjacent second sub-signal lines 112 can be the same.

[0069] For example, in this embodiment of the invention, the number of first signal lines 11 is N, the number of first sub-signal lines 111 is N1, and the number of second sub-signal lines 112 is N2, wherein N2 ≤ N1 < N. As shown in FIG1, the first signal line 11 further includes a third sub-signal line 113, which is not electrically connected to the connecting line and the load compensation line. In this embodiment of the invention, the number of third sub-signal lines 113 is N3. N1 + N2 + N3 = N.

[0070] Optionally, 30% ≤ N1 / N ≤ 40%, for example, N1 / N = 35%.

[0071] For example, 2% ≤ N² / N ≤ 8%, such as N² / N = 5%.

[0072] Optionally, in this embodiment of the invention, the length of the connecting line 2 electrically connected to the first sub-signal line 111 adjacent to the second sub-signal line 112 can be x, and the length difference of the load compensation line 4 electrically connected to any two adjacent second sub-signal lines 112 can be y, where y = x / N2, so that the resistance difference value of the load compensation line 4 electrically connected to the two adjacent second sub-signal lines 112 is the same.

[0073] For example, in this embodiment of the invention, the length of the connecting line 2 electrically connected to the first sub-signal line 111 adjacent to the second sub-signal line 112 is L1; the length of the load compensation line 4 electrically connected to the second sub-signal line 112 adjacent to the first sub-signal line 111 is L21; and the length of the load compensation line 4 electrically connected to the second sub-signal line 112 adjacent to the third sub-signal line 113 is L22; wherein, L1-L21=x / N2. L22=x / N2. By using this configuration, the load difference between adjacent first sub-signal lines 111 and second sub-signal lines 112, and the load difference between adjacent third sub-signal lines 113 and second sub-signal lines 112, can be the same as the load difference between any two adjacent second sub-signal lines 112. This improves the display uniformity of the sub-pixels driven by the first sub-signal lines 111 and second sub-signal lines 112, and also improves the display uniformity of the sub-pixels driven by the second sub-signal lines 112 and third sub-signal lines 113, thereby improving the display effect of the display panel 100.

[0074] It should be noted that the process parameters such as length and cross-sectional area involved in the embodiments of the present invention are all design values. Due to limitations in process accuracy, the actual length and actual cross-sectional area of ​​the traces such as the first signal line 11, the connecting line 2, and the load compensation line 4 can fluctuate within the allowable range of process error. Taking the dimensional accuracy of the load compensation line 4 as m as an example, when the actual length L21' of the load compensation line 4 electrically connected to the second sub-signal line 112 adjacent to the first sub-signal line 111 satisfies L21-m≤L21'≤L21+m, it is included within the scope of protection claimed by the present invention.

[0075] Furthermore, the terms "same length" and "same cross-sectional area" mentioned in the embodiments of the present invention refer to the same length within the allowable range of process error, and the same cross-sectional area within the allowable range of process error, respectively.

[0076] For example, embodiments of the present invention can make the cross-sectional area and conductivity of the connecting line 2 and the load compensation line 4 the same, and / or make the cross-sectional area and conductivity of the first sub-signal line 111, the second sub-signal line 112, and the third sub-signal line 113 the same. Based on this design, while making the load difference between adjacent first sub-signal lines 111 and second sub-signal lines 112, and the load difference between adjacent third sub-signal lines 113 and second sub-signal lines 112, the same as the load difference between any two adjacent second sub-signal lines 112, only the lengths of the different load compensation lines 4 need to be adjusted, thereby reducing the design difficulty of the load compensation lines 4.

[0077] For example, as shown in FIG1, along the direction from the first edge E1 to the second edge E2, the length of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually decreases, so that the resistance value of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually decreases.

[0078] In one alternative implementation, embodiments of the present invention can make the conductivity and / or cross-sectional area of ​​different load compensation lines 4 the same. Based on this design, while gradually reducing the resistance value of the load compensation line 4 electrically connected to the second sub-signal line 112, the design difficulty of the load compensation line 4 can be reduced.

[0079] Optionally, as shown in Figure 4, which is a schematic diagram of another display panel provided in an embodiment of the present invention, the cross-sectional area of ​​the load compensation line 4 electrically connected to the second sub-signal line 112 gradually increases along the direction from the first edge E1 to the second edge E2, so that the resistance value of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually decreases. Here, the cross-sectional area refers to the area of ​​the cross section perpendicular to the extension direction of the load compensation line 4. Figure 4 uses lines of different thicknesses to illustrate load compensation lines 4 with different cross-sectional areas. Specifically, in this embodiment of the present invention, the cross-sectional area can be changed by adjusting the thickness and width of the load compensation line 4. The thickness of the load compensation line 4 refers to the dimension of the cross section in the direction perpendicular to the plane of the display panel 100, and the width of the load compensation line 4 refers to the dimension of the cross section in the direction parallel to the plane of the display panel 100.

[0080] For example, in embodiments of the present invention, the lengths and / or conductivity of different load compensation lines 4 can be made the same. Based on this setting, while the resistance value of the load compensation line 4 electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 is gradually reduced, only the cross-sectional area of ​​different load compensation lines 4 can be adjusted to reduce the design difficulty of the load compensation line 4.

[0081] For example, as shown in FIG5, which is a schematic diagram of another display panel provided in an embodiment of the present invention, the cross-sectional area of ​​multiple second sub-signal lines 112 gradually increases along the direction from the first edge E1 to the second edge E2, so that the resistance value of the second sub-signal lines 112 gradually decreases. Combined with the above-mentioned load compensation line 4, the load difference between the first sub-signal line 111 and the second sub-signal line 112 can be further reduced, improving the display uniformity of the sub-pixels connected to them. FIG5 uses lines of different thicknesses to illustrate second sub-signal lines 112 with different cross-sectional areas. As shown in FIG5, the maximum value of the cross-sectional area of ​​the first sub-signal line 111 and the third sub-signal line 113 is the same as that of the second sub-signal line 112.

[0082] Optionally, in embodiments of the present invention, the lengths and / or conductivity of different second sub-signal lines 112 can be made the same. Figure 5 illustrates this by showing different second sub-signal lines 112 with the same length. Based on this arrangement, while gradually reducing the resistance value of the load compensation line 4 electrically connected to the second sub-signal line 112 along the direction from the first edge E1 to the second edge E2, only the cross-sectional area of ​​the second sub-signal line 112 needs to be adjusted, thereby reducing the design difficulty of the second sub-signal line 112.

[0083] For example, in embodiments of the present invention, at least a portion of the load compensation line 4 can be located in the display area AA. Figures 1, 4, and 5 all illustrate this by showing the load compensation line 4 located in the display area AA. Based on this arrangement, the load compensation line 4 can be prevented from occupying the space of the non-display area NA, thereby reducing the area of ​​the non-display area NA, which is beneficial for the narrow bezel design of the display panel 100 and increases the screen-to-body ratio of the display panel 100.

[0084] Optionally, as shown in Figures 1, 4, and 5, the connecting line 2 includes a first sub-connecting line 21 extending along a first direction h1 and a second sub-connecting line 22 extending along a second direction h2; wherein the second sub-connecting line 22 is located on the side of the first sub-signal line 111 away from the first edge E1. The load compensation line 4 includes a first sub-compensation line 41 extending along the first direction h1. As shown in Figures 1, 4, and 5, the first sub-compensation line 41 is located in the display area AA to avoid increasing the width of the non-display area NA due to placing the first sub-compensation line 41 in the non-display area NA.

[0085] For example, in embodiments of the present invention, the first sub-connection line 21 and the first sub-signal line 111 can be arranged on different layers, as shown in Figures 1, 4 and 5, and the two are electrically connected through the first via K11; and the first sub-compensation line 41 and the second sub-signal line 112 can be arranged on different layers, as shown in Figures 1, 4 and 5, and the two are electrically connected through the second via K21.

[0086] The film layer structure of the display panel provided in the embodiment of the present invention will be described below with reference to Figures 6, 7 and 8. Figure 6 is a wiring diagram of a pixel driving circuit provided in the embodiment of the present invention, and Figure 7 is a partially enlarged schematic diagram of a display panel provided in the embodiment of the present invention. In Figure 7, 4×4 pixel driving circuits arranged in an array along the first direction h1 and the second direction h2 are shown. Each pixel driving circuit can have the circuit structure shown in Figures 2 and 6. Figure 8 is a cross-sectional schematic diagram along BB' in Figure 7. As shown in Figure 8, the display panel 100 includes a substrate 500, a semiconductor layer S, a first insulating layer IS1, a first conductor layer M1, a second insulating layer IS2, a second conductor layer M2, a third insulating layer IS3, a third conductor layer M3, a fourth insulating layer IS4, a fourth conductor layer M4, a fifth insulating layer IS5 and a fifth conductor layer M5. Semiconductor layer S is located on one side of substrate 500. First insulating layer IS1 is located on the side of semiconductor layer S away from substrate 500. First conductor layer M1 is located on the side of first insulating layer IS1 away from semiconductor layer S. Second insulating layer IS2 is located on the side of first conductor layer M1 away from semiconductor layer S. Second conductor layer M2 is located on the side of second insulating layer IS2 away from first conductor layer M1. Third insulating layer IS3 is located on the side of second conductor layer M2 away from second insulating layer IS2. Third conductor layer M3 is located on the side of third insulating layer IS3 away from second conductor layer M2. Fourth insulating layer IS4 is located on the side of third conductor layer M3 away from third insulating layer IS3. Fourth conductor layer M4 is located on the side of fourth insulating layer IS4 away from third conductor layer M3. Fifth insulating layer IS5 is located on the side of fourth conductor layer M4 away from fourth insulating layer IS4. Fifth conductor layer M5 is located on the side of fifth insulating layer IS5 away from fourth conductor layer M4.

[0087] For example, the semiconductor layer S includes a channel region and a doped region for forming the various transistors described above. For example, the doped region includes a source doped region and a drain doped region. The semiconductor layer S includes any one or more of low-temperature polycrystalline silicon, amorphous silicon, and oxide semiconductor layers.

[0088] Optionally, the first scan line S1, the second scan line S2, the light emission control signal line E, the first reset signal line Ref1 and the second reset signal line Ref2 can extend along the first direction h1, and the first power signal line PVDD and the data signal line Data can extend along the second direction, with each signal line intersecting in the aforementioned extension directions being insulated from each other.

[0089] For example, the first scan line S1, the second scan line S2, and the light emission control signal line E can be arranged on the same layer or on different layers. The first reset signal line Ref1 and the second reset signal line Ref2 can be arranged on the same layer or on different layers. The first power signal line PVDD and the data signal line Data can be arranged on the same layer or on different layers.

[0090] Referring to Figure 6, the storage capacitor Cst's first electrode, first scan line S1, second scan line S2, and light emission control signal line E are disposed on the first conductor layer M1; the first reset signal line Ref1, second reset signal line Ref2, and the storage capacitor Cst's second electrode are disposed on the second conductor layer M2; the first power signal line PVDD includes a first sub-power signal line PVDD1 located on the third conductor layer M3 and a second sub-power signal line PVDD2 located on the second conductor layer M2; and the data signal line Data is disposed on the fourth conductor layer M4 as an illustration. Optionally, the materials of the above conductor layers include metals or metal alloys. For example, the materials of each conductor layer include one or more of molybdenum, aluminum, titanium, silver, and copper.

[0091] Optionally, as shown in Figure 6, the third conductor layer M3 further includes a first connection portion X1, a second connection portion X2, a third connection portion X3, and a fourth connection portion X4. The data signal line Data located on the fifth conductor layer M5 is electrically connected to one end of the first connection portion X1 through a third via K3 penetrating the fifth insulating layer (not shown). The other end of the first connection portion X1 is electrically connected to the source-doped region or drain-doped region of the second transistor T2 located on the semiconductor layer S through a fourth via K4 penetrating the third insulating layer (not shown), the second insulating layer (not shown), and the first insulating layer (not shown), to transmit data voltage to the second transistor T2.

[0092] One end of the second connection part X2 is electrically connected to the first reset signal line Ref1 located in the second conductor layer through the fifth via K5 penetrating the third insulating layer. The other end of the second connection part X2 is electrically connected to the source doped region or drain doped region of the sixth transistor T6 located in the semiconductor layer S through the sixth via K6 penetrating the third insulating layer, the second insulating layer and the first insulating layer, so as to transmit the first reset signal to the sixth transistor T6.

[0093] One end of the third connection part X3 is electrically connected to the second reset signal line Ref2 located in the second conductor layer through the seventh via K7 penetrating the third insulating layer. The other end of the third connection part X3 is electrically connected to the source doped region or drain doped region of the fourth transistor T4 located in the semiconductor layer through the eighth via K8 penetrating the third insulating layer, the second insulating layer and the first insulating layer, so as to transmit the second reset signal to the fourth transistor T4.

[0094] One end of the fourth connection part X4 is electrically connected to the source doped region or drain doped region of the fourth transistor T4 located in the semiconductor layer through the ninth via K9, and the other end of the fourth connection part X4 is electrically connected to the first plate of the storage capacitor Cst through the tenth via K10.

[0095] As shown in Figure 6, the first power signal line PVDD includes a first sub-power signal line PVDD1 located in the third conductor layer M3 and a second sub-power signal line PVDD2 located in the second conductor layer M2. The first sub-power signal line PVDD1 is electrically connected to the source doped region or drain doped region of the first transistor T1 located in the semiconductor layer S through the eleventh via K101 to transmit the first power supply voltage to the first transistor T1.

[0096] Referring to Figure 7, the first sub-signal line 111 and the second sub-signal line 112 are disposed on the fourth conductor layer M4, and the first sub-connection line 21 and the first sub-compensation line 41 are disposed on the fifth conductor layer M5. As shown in Figure 8, a fifth insulating layer IS5 is included between the fourth conductor layer M4 and the fifth conductor layer M5. The fifth insulating layer IS5 includes the aforementioned second via K21, through which the second sub-signal line 112 is electrically connected to the first sub-compensation line 41. This arrangement ensures good insulation between the first sub-compensation line 41 and other second sub-signal lines 112 while simultaneously allowing the first sub-compensation line 41 to be electrically connected to the corresponding second sub-signal line 112.

[0097] Optionally, as shown in Figure 9, which is a schematic diagram of another display panel provided in an embodiment of the present invention, the lines connecting multiple first vias K11 and second vias K21 are located on a straight line, so that the arrangement of the first vias K11 and second vias K21 is more regular, which is beneficial to improving the uniformity of the distribution of each via in the display area AA, thereby improving the display effect.

[0098] In another possible implementation, as shown in Figures 1, 4 and 5, the arrangement direction of the plurality of first vias K11 is parallel to the arrangement direction of the plurality of second vias K21.

[0099] In another possible implementation, as shown in FIG10, FIG10 is a schematic diagram of another display panel provided by an embodiment of the present invention. In this embodiment of the present invention, the arrangement direction of the plurality of first vias K11 may intersect with the arrangement direction of the plurality of second vias K21.

[0100] For example, along the direction from the first edge E1 to the second edge E2, the resistance value of the first sub-compensation line 41 electrically connected to the second sub-signal line 112 gradually decreases. Based on this setting, while balancing the load difference between the first sub-signal line 111 and the second sub-signal line 112 and improving the brightness consistency of the sub-pixels electrically connected to the first sub-signal line 111 and the sub-pixels electrically connected to the second sub-signal line 112, it is possible to avoid setting the resistance value of all the first sub-compensation lines 41 too high, which is beneficial to reducing the power consumption of the display panel 100.

[0101] Optionally, as shown in Figure 11, which is a schematic diagram of another display panel provided in an embodiment of the present invention, in addition to the first sub-compensation line 41, the load compensation line 4 also includes a second sub-compensation line 42 extending along the second direction h2. Along the direction from the first edge E1 to the second edge E2, the resistance value of the second sub-compensation line 42, which is electrically connected to the second sub-signal line 112, gradually decreases. By setting the first sub-compensation line 41 and the second sub-compensation line 42, this embodiment of the present invention increases the load on the second sub-signal line 112 while avoiding setting the length of the load compensation line 4 too long in a single direction.

[0102] For example, in embodiments of the present invention, the resistance values ​​of the first sub-compensation lines 41 in different load compensation lines 4 can be made consistent, so that the resistance value of the load compensation line 4 can be adjusted simply by adjusting the length of the second sub-compensation line 42, which is a simple design.

[0103] Optionally, in embodiments of the present invention, at least one of the length, conductivity, and cross-sectional area of ​​different first sub-compensation lines 41 can be the same to reduce the design difficulty of the load compensation line 4.

[0104] For example, as shown in FIG11, in the direction from the first edge E1 to the second edge E2, the length of the second sub-compensation line 42 electrically connected to different second sub-signal lines 112 can be gradually shortened in this embodiment of the invention. Alternatively, the cross-sectional area of ​​the second sub-compensation line 42 can be gradually increased in this embodiment of the invention to reduce the resistance value of different second sub-compensation lines 42.

[0105] Optionally, in embodiments of the present invention, the second sub-compensation line 42 and the second sub-connecting line 22 can be disposed in the same layer. This arrangement allows the second sub-compensation line 42 and the second sub-connecting line 22 to use the same material and be formed in the same patterning process, which simplifies the process flow and reduces manufacturing costs. Furthermore, it also helps to reduce the number of film layers in the display panel 100, enabling a thinner design for the display panel. Exemplarily, the patterning process includes steps such as film formation, exposure, etching, and development.

[0106] For example, in embodiments of the present invention, the first sub-compensation line 41 and the second sub-signal line 112 can be disposed in different layers, while the second sub-compensation line 42 and the second sub-signal line 112 can be disposed in the same layer. This arrangement allows the second sub-compensation line 42 and the second sub-signal line 112 to use the same material and be formed in the same patterning process, which simplifies the process flow and reduces manufacturing costs. Furthermore, it also helps to reduce the number of film layers in the display panel 100, achieving a thinner design for the display panel. Referring to Figures 12 and 13, Figure 12 is a partially enlarged schematic diagram of another display panel provided by an embodiment of the present invention, and Figure 13 is a cross-sectional schematic diagram along CC' of Figure 12, illustrating that the first sub-signal line 111, the second sub-signal line 112, the second sub-compensation line 42, and the second sub-connecting line 22 are all disposed in the fourth metal layer M4. As shown in Figure 12, the first sub-connecting line 21 and the second sub-connecting line 22 are electrically connected through the twelfth via K12, and the first sub-compensation line 41 and the second sub-compensation line 42 are electrically connected through the thirteenth via K22.

[0107] It should be noted that the layout design of the pixel driving circuit shown in Figures 6, 7, and 12, and the distribution of each structure in different film layers in Figures 6, 7, 12, and 13 are only schematic diagrams. Depending on the different design requirements of the display panel, the layout of the pixel driving circuit and the film layers containing different structures in the display panel can be adjusted accordingly. For example, in embodiments of the present invention, at least two of the first sub-power signal line PVDD1, data signal line Data, second sub-connection line 22, and second sub-compensation line 42 can be disposed on the same layer. For example, the first sub-power signal line PVDD1, data signal line Data, second sub-connection line 22, and second sub-compensation line 42 can all be disposed on the third conductor layer M3, and the first sub-connection line 21 and the first sub-compensation line 41 can be disposed on the side of the third conductor layer M3 away from the substrate 500. For example, the first sub-connection line 21 and the first sub-compensation line 41 can both be disposed on the fourth conductor layer M4. Embodiments of the present invention do not limit the specific layout design of the pixel driving circuit.

[0108] For example, when the first sub-compensation line 41 and the second sub-compensation line 42 are located in different conductor layers, they can be made of the same material or different materials. This embodiment of the invention does not limit this.

[0109] Optionally, embodiments of the present invention may also allow the second sub-compensation line 42 and the first sub-compensation line 41 to be disposed on the same layer. For example, embodiments of the present invention may allow the first sub-power signal line PVDD1 and the data signal line Data to be disposed on the same layer on the third conductor layer M3, and the second sub-compensation line 42 and the first sub-compensation line 41 to be disposed on the same layer on the fourth conductor layer M4. In this case, the first sub-compensation line 41 is electrically connected to the second sub-signal line 112 through the aforementioned second via K21, and the second sub-compensation line 42 and the first sub-compensation line 41 are directly electrically connected without needing to pass through a via.

[0110] For example, as shown in Figures 1, 9 and 10, when the load compensation line 4 includes only the first sub-compensation line 41, the length of the load compensation line 4 that is electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 gradually becomes shorter, including: the length of the first sub-compensation line 41 that is electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 gradually becomes shorter.

[0111] Optionally, as shown in Figure 4, when the load compensation line 4 only includes the first sub-compensation line 41, the cross-sectional area of ​​the load compensation line 4, which is electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2, gradually increases, including: the cross-sectional area of ​​the first sub-compensation line 41, which is electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2, gradually increases.

[0112] For example, when the load compensation line 4 only includes the first sub-compensation line 41, the lengths of the different load compensation lines 4 are all the same, including: the lengths of the different first sub-compensation lines 41 are all the same; the conductivity of the different load compensation lines 4 is the same, including: the conductivity of the different first sub-compensation lines 41 is all the same; and the cross-sectional areas of the different load compensation lines 4 are all the same, including: the cross-sectional areas of the different first sub-compensation lines 41 are all the same.

[0113] For example, when the load compensation line 4 includes a first sub-compensation line 41 and a second sub-compensation line 42, the length of the load compensation line 4 electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 gradually becomes shorter, including: the sum of the lengths of the first sub-compensation line 41 and the second sub-compensation line 42 electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 gradually becomes shorter.

[0114] For example, as shown in FIG11, in an embodiment of the present invention, the length of the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 along the direction from the first edge E1 to the second edge E2 is equal, and the length of the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually becomes shorter.

[0115] Alternatively, in this embodiment of the invention, the length of the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 along the direction from the first edge E1 to the second edge E2 may gradually decrease, while the length of the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 may be equal.

[0116] Alternatively, in this embodiment of the invention, the length of the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 along the direction from the first edge E1 to the second edge E2 can be gradually shortened, and the length of the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 can be gradually shortened.

[0117] For example, when the load compensation line 4 includes a first sub-compensation line 41 and a second sub-compensation line 42, the cross-sectional area of ​​the load compensation line 4 electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 gradually increases, including: the cross-sectional area of ​​the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 in the direction from the first edge E1 to the second edge E2 gradually increases, and / or the cross-sectional area of ​​the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually increases.

[0118] For example, in an embodiment of the present invention, the cross-sectional area of ​​the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 along the direction from the first edge E1 to the second edge E2 can be gradually increased, while the cross-sectional area of ​​the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 can be equal.

[0119] Alternatively, in this embodiment of the invention, the cross-sectional areas of the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 along the direction from the first edge E1 to the second edge E2 are equal, and the cross-sectional area of ​​the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually increases.

[0120] Alternatively, in this embodiment of the invention, the cross-sectional area of ​​the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually increases along the direction from the first edge E1 to the second edge E2, and the cross-sectional area of ​​the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 also gradually increases. As shown in FIG14, FIG14 is a schematic diagram of another display panel provided by this embodiment of the invention, wherein the cross-sectional areas of the first sub-compensation line 41 and the second sub-compensation line 42 in the same load compensation line 4 are equal, and the cross-sectional area of ​​the first sub-compensation line 41 of the load compensation line 4 electrically connected to the second sub-signal line 112 gradually increases along the direction from the first edge E1 to the second edge E2, and the cross-sectional area of ​​the second sub-compensation line 42 of the load compensation line 4 electrically connected to the second sub-signal line 112 also gradually increases.

[0121] For example, when the load compensation line 4 includes a first sub-compensation line 41 and a second sub-compensation line 42, the conductivity of the different load compensation lines 4 is the same, including: the conductivity of the first sub-compensation line 41 of the different load compensation lines 4 is the same, and the conductivity of the second sub-compensation line 42 of the different load compensation lines 4 is the same; the cross-sectional area of ​​the different load compensation lines 4 is the same, including: the cross-sectional area of ​​the first sub-compensation line 41 of the different load compensation lines 4 is the same, and the cross-sectional area of ​​the second sub-compensation line 42 of the different load compensation lines 4 is the same. The length of the different load compensation lines 4 is the same, including: the sum of the lengths of the first sub-compensation line 41 and the second sub-compensation line 42 of the different load compensation lines 4 is the same; for example, the length of the first sub-compensation line 41 of the different load compensation lines 4 is the same, and the length of the second sub-compensation line 42 of the different load compensation lines 4 is the same.

[0122] Optionally, as shown in Figures 11 and 14, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2 arranged along the second direction h2, and the display area AA is located between the first non-display area NA1 and the second non-display area NA2; the first non-display area NA1 includes the aforementioned pin 5, the first fan-out line 31, and the aforementioned second fan-out line 32. At least a portion of the second sub-compensation line 42 is located on the side of the first sub-compensation line 41 near the first non-display area NA1. Alternatively, as shown in Figures 15 and 16, which are schematic diagrams of two other display panels provided in embodiments of the present invention, embodiments of the present invention may also have at least a portion of the second sub-compensation line 42 located on the side of the first sub-compensation line 41 near the second non-display area NA2.

[0123] For example, as shown in FIG15, in an embodiment of the present invention, the length of the first sub-compensation line 41 and the length of the first sub-connecting line 21 can be the same.

[0124] Alternatively, as shown in Figure 16, in this embodiment of the invention, the ends of the multiple second sub-compensation lines 42 that are away from the first sub-compensation line 41 can be aligned with each other in the first direction h1 to improve the visual effect.

[0125] Optionally, as shown in Figure 17, which is a schematic diagram of another display panel provided in an embodiment of the present invention, the connecting line 2 includes a first sub-connecting line 21 extending along a first direction h1 and a second sub-connecting line 22 extending along a second direction h2; the two are electrically connected. At least a portion of the extension line of the second sub-compensation line 42 to the non-display area overlaps with at least a portion of the second sub-connecting line 22, that is, at least a portion of the extension line of the second sub-compensation line 42 to the non-display area passes through at least a portion of the second sub-connecting line 22. Figure 17 illustrates the overlap of the extension lines of multiple second sub-compensation lines 42 with different second sub-connecting lines 22. This arrangement is simple to implement and facilitates improved line segment uniformity.

[0126] Optionally, as shown in Figures 7 and 12, the display area AA further includes multiple second signal lines 12. The second signal lines 12 extend along the first direction h1 and intersect with the aforementioned first signal lines 11 insulated from each other. The second signal lines 12 are electrically connected to the pixel driving circuit.

[0127] As shown in Figures 7 and 12, along direction h3 perpendicular to the plane of the display panel 100, at least a portion of the second signal line 12 overlaps with the first sub-connecting line 21, and at least a portion of the second signal line 12 overlaps with the first sub-compensation line 41. Furthermore, the type of signal transmitted by the second signal line 12 overlapping with the first sub-connecting line 21 and the first sub-compensation line 41 is consistent. By having at least a portion of the second signal line 12 overlap with the first sub-connecting line 21 and at least a portion of the second signal line 12 overlap with the first sub-compensation line 41 along direction h3 perpendicular to the plane of the display panel 100, this embodiment of the invention can make the coupling capacitance of the first sub-connecting line 21 to the second signal line 12 and the coupling capacitance of the first sub-compensation line 41 to the second signal line 12 tend to be consistent, thereby making their loads tend to be consistent.

[0128] Optionally, any one of the first scan line S1, the second scan line S2, the light emission control signal line E, and the reference voltage signal line ref includes the second signal line 12. Figures 7 and 12 illustrate that the second signal line 12 includes the first reset signal line Ref1, that is, the first sub-connection line 21 and the first sub-compensation line 41 both overlap with the first reset signal line Ref1.

[0129] For example, the first sub-compensation line 41 and the first sub-connecting line 21 are arranged in the same layer. This arrangement allows the first sub-compensation line 41 and the first sub-connecting line 21 to be made of the same material and formed in the same patterning process, which helps to simplify the process flow and reduce manufacturing costs. Figures 7 and 12 illustrate this by showing that the first sub-compensation line 41 and the first sub-connecting line 21 are both located in the fifth metal layer M5.

[0130] For example, as shown in Figures 11, 14, 15, 16, and 17, embodiments of the present invention may have at least a portion of the first sub-compensation line 41 located on the side of the second sub-signal line 112 near the second edge E2. Alternatively, as shown in Figure 18, which is a schematic diagram of another display panel provided by an embodiment of the present invention, embodiments of the present invention may have at least a portion of the first sub-compensation line 41 located on the side of the second sub-signal line 112 near the first edge E1.

[0131] For example, as shown in Figures 1, 4, 5, 9, 10, 11, 14, 15, 16, 17, and 18, the distance between the first sub-compensation line 41 and the first sub-connecting line 21 is greater than or equal to the distance between two adjacent first sub-connecting lines 21. Based on this setting, the distance between the first sub-compensation line 41 and the first sub-connecting line 21 can be avoided from being set too close, which helps to reduce interference between the first sub-compensation line 41 and the first sub-connecting line 21. Optionally, as shown in Figures 7 and 12, along the second direction h2, the first sub-connecting line 21 and the adjacent first sub-compensation line 41 can be spaced two rows of sub-pixels apart.

[0132] It should be noted that Figures 11, 14, 15, 16, 17, and 18 are only used as illustrations to show the load compensation line 4 including one first sub-compensation line 41 and one second sub-compensation line 42. It is understood that embodiments of the present invention may also configure the load compensation line 4 as a broken line structure including at least two first sub-compensation lines 41 and / or at least two second sub-compensation lines 42; this embodiment of the present invention does not limit this.

[0133] For example, as shown in Figure 19, which is a schematic diagram of another display panel provided in an embodiment of the present invention, the display area AA further includes multiple constant signal traces 6. At least some of the extensions of the constant signal traces 6 overlap with the load compensation line 4, and at least some of the extensions of the constant signal traces 6 overlap with the connecting line 2. The constant signal traces 6 are used to transmit constant signals. Optionally, the constant signal includes any one of the first power supply voltage, the second power supply voltage, the first reset signal, and the second reset signal. Ambient light is reflected after shining on the connecting line 2, and the reflected light enters the human eye, affecting the display effect of the display panel. By setting constant signal traces 6 in areas where load compensation lines 4 and connecting lines 2 are not provided, the present invention can improve the uniformity of reflection of ambient light in areas where load compensation lines 4 and connecting lines 2 are provided and areas where load compensation lines 4 and connecting lines 2 are not provided. Moreover, by having the constant signal traces 6 transmit the constant signals required for the operation of the pixel driving circuit, the present invention can reduce the voltage drop of the corresponding constant signals, which is beneficial to improving the brightness uniformity of the display panel 100.

[0134] For example, as shown in FIG19, the load compensation line 4 includes a first sub-compensation line 41 extending along a first direction h1 and a second sub-compensation line 42 extending along a second direction h2; the constant signal trace 6 includes a first sub-line 61 extending along the first direction h1 and a second sub-line 62 extending along the second direction h2. Optionally, in embodiments of the present invention, the first sub-line 61 and the first sub-compensation line 41 can be arranged in the same layer so that the first sub-line 61 and the first sub-compensation line 41 are formed in the same patterning process using the same material. And / or, in embodiments of the present invention, the second sub-line 62 and the second sub-compensation line 42 can also be arranged in the same layer so that the second sub-line 62 and the second sub-compensation line 42 are formed in the same patterning process using the same material. For example, the first sub-line 61 and the second sub-line 62 are electrically connected.

[0135] Referring to Figures 7 and 12, the first sub-line 61 and the first sub-compensation line 41 are both located in the fifth conductor layer M5, as shown in Figure 12, while the second sub-line 62 and the second sub-compensation line 42 are both located in the fourth conductor layer M4.

[0136] For example, as shown in FIG2, the display area AA includes a light-emitting element 20 electrically connected to the pixel driving circuit 10. The light-emitting element 20 includes a first electrode, a light-emitting layer, and a second electrode stacked together. Optionally, the first electrode includes an anode, and the second electrode includes a cathode. As shown in FIG20, FIG20 is a schematic diagram of the relative positions of a load compensation line, a constant signal line, and a first electrode provided in an embodiment of the present invention. The constant signal line 6 and the load compensation line 4 are spaced apart, and the orthographic projection of the first electrode 1011 on the plane where the display panel is located covers the break position between the constant signal line 6 and the load compensation line 4. Based on this arrangement, the first electrode 1011 can block the break position between the constant signal line 6 and the load compensation line 4, avoiding the visibility of the break position caused by the different degree of reflection of ambient light between the break position between the constant signal line 6 and the load compensation line 4 and other non-break positions, thus avoiding the problem of inconsistent visual effects at different positions in the display area AA.

[0137] Optionally, as shown in Figures 1, 4, 5, 9, 10, 11, 14, 15, 16, 17, 18, and 19, the length of the connecting line 2 electrically connected to the first sub-signal line 111 gradually increases along the direction from the first edge E1 to the second edge E2. Optionally, in embodiments of the present invention, multiple first sub-connecting lines 21 can be of the same length, while the length of the second sub-connecting line 22 can gradually increase to facilitate layout.

[0138] For example, as shown in FIG21, FIG21 is a schematic diagram of another display panel provided in an embodiment of the present invention. At least a portion of the load compensation line 4 is located in the non-display area NA to avoid increasing the wiring complexity in the display area AA. FIG21 illustrates that the load compensation line 4 is configured to include a first portion 401 and a second portion 402 with electrical connections, the first portion 401 being at least partially located in the display area AA and the second portion 402 being at least partially located in the non-display area NA.

[0139] Optionally, the first portion 401 may include a line segment extending along a first direction h1 and / or a line segment extending along a second direction h2. The second portion 402 may include a line segment extending along the first direction h1 and / or a line segment extending along the second direction h2. Figure 21 illustrates that the first portion 401 includes a line segment extending along the first direction h1 and a line segment extending along the second direction h2, and the second portion 402 includes a line segment extending along the first direction h1 and a line segment extending along the second direction h2.

[0140] Of course, in this embodiment of the invention, all load compensation lines 4 can be set in the non-display area NA to further reduce the wiring complexity in the display area AA, which will not be shown in the accompanying drawings here.

[0141] This invention also provides a display device, as shown in FIG22. FIG22 is a schematic diagram of a display device provided in this invention, the display device including the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, the display device shown in FIG22 is merely illustrative, and the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a non-display area, the display area comprises a plurality of first signal lines and a plurality of connection lines; the plurality of first signal lines are arranged along a first direction, and the first signal lines extend along a second direction; The display panel further comprises a first edge and a second edge arranged along the first direction; The plurality of first signal lines at least comprise a plurality of first sub-signal lines and a plurality of second sub-signal lines, and the second sub-signal lines are located on a side of the first sub-signal lines away from the first edge; The non-display area comprises a first fan-out line and a second fan-out line, the connection lines are electrically connected to the first sub-signal lines and the first fan-out line, and the second fan-out line is electrically connected to the second sub-signal lines; The display panel further comprises a plurality of load compensation lines electrically connected to the second sub-signal lines, and the resistance values of the load compensation lines electrically connected to the second sub-signal lines gradually decrease in a direction along the first edge pointing to the second edge.

2. The display panel of claim 1, wherein The resistance difference values of the load compensation lines electrically connected to the second sub-signal lines gradually increase in the direction along the first edge pointing to the second edge.

3. The display panel of claim 1, wherein The resistance difference values of the load compensation lines electrically connected to adjacent two second sub-signal lines are the same in the direction along the first edge pointing to the second edge.

4. The display panel of claim 1, wherein The number of the first sub-signal lines is N1, the number of the second sub-signal lines is N2, the length of the connection line electrically connected to the first sub-signal line adjacent to the second sub-signal line is x, and the length difference of the load compensation lines electrically connected to adjacent two second sub-signal lines is y; wherein N2≤N1 and y=x / N2.

5. The display panel of claim 4, wherein The length of the connection line electrically connected to the first sub-signal line adjacent to the second sub-signal line is L1, The length of the load compensation line electrically connected to the second sub-signal line adjacent to the first sub-signal line is L2; wherein L1-L2=x / N2.

6. The display panel of claim 1, wherein The lengths of the load compensation lines electrically connected to the second sub-signal lines gradually decrease in the direction along the first edge pointing to the second edge.

7. The display panel of claim 1, wherein The cross-sectional areas of the load compensation lines electrically connected to the second sub-signal lines gradually increase in the direction along the first edge pointing to the second edge.

8. The display panel of claim 1, wherein The cross-sectional areas of the plurality of second sub-signal lines gradually increase in the direction along the first edge pointing to the second edge.

9. The display panel of claim 1, wherein At least part of the load compensation lines is located in the display area.

10. The display panel of claim 9, wherein The connection lines include first sub-connection lines extending along the first direction and second sub-connection lines extending along the second direction. The load compensation lines include first sub-compensation lines extending along the first direction.

11. The display panel of claim 10, wherein, The resistance value of the first sub-compensation line electrically connected to the second sub-signal line gradually decreases in a direction from the first edge to the second edge.

12. The display panel of claim 10, wherein, The lengths of different first sub-compensation lines are the same. The load compensation lines further include second sub-compensation lines extending along the second direction, and the resistance value of the second sub-compensation line electrically connected to the second sub-signal line gradually decreases in a direction from the first edge to the second edge.

13. The display panel of claim 12, wherein, The second sub-compensation lines and the second sub-connection lines are arranged on the same layer.

14. The display panel of claim 12, wherein, The second sub-compensation lines and the second sub-signal lines are arranged on the same layer.

15. The display panel of claim 12, wherein, The non-display area includes a first non-display area and a second non-display area arranged along the second direction, and the display area is located between the first non-display area and the second non-display area; the first non-display area includes the first fan-out line and the second fan-out line; At least part of the second sub-compensation line is located on one side of the first sub-compensation line close to the first non-display area, or, At least part of the second sub-compensation line is located on one side of the first sub-compensation line close to the second non-display area.

16. The display panel of claim 12, wherein, At least part of the second sub-compensation line and at least part of the second sub-connection line overlap.

17. The display panel of claim 10, wherein, The display area further includes a plurality of second signal lines extending along the first direction, and at least part of the second signal lines overlaps with the first sub-connection line and the first sub-compensation line in a direction perpendicular to the plane on which the display panel is located.

18. The display panel of claim 10, wherein, The first sub-compensation lines and the first sub-connection lines are arranged on the same layer.

19. The display panel of claim 10, wherein, The first sub-compensation lines and the second sub-signal lines are arranged on different layers.

20. The display panel of claim 10, wherein, At least part of the first sub-compensation line is located on one side of the second sub-signal line close to the first edge, or at least part of the first sub-compensation line is located on one side of the second sub-signal line close to the second edge.

21. The display panel of claim 10, wherein, The distance between the first sub-compensation line and the first sub-connection line is greater than or equal to the distance between two adjacent first sub-connection lines.

22. The display panel of claim 9, wherein, The display area further comprises a constant signal line, a length of the constant signal line overlaps with the load compensation line; the constant signal line is used for transmitting a constant signal. 23.The display panel of claim 22, wherein, The load compensation line comprises a first sub compensation line extending along the first direction and a second sub compensation line extending along the second direction; the constant signal line comprises a first sub line extending along the first direction and a second sub line extending along the second direction; The first sub line and the first sub compensation line are arranged in the same layer; and / or, the second sub line and the second sub compensation line are arranged in the same layer. 24.The display panel of claim 22, wherein, The display area further comprises a light emitting element, the light emitting element comprises a first electrode, a light emitting layer and a second electrode arranged in a stack; The constant signal line and the load compensation line are arranged in a spaced manner, and a normal projection of the first electrode on a plane in which the display panel is located covers a position of a break between the constant signal line and the load compensation line. 25.The display panel of claim 1, wherein, A length of the connection line electrically connected with the first sub signal line gradually increases in a direction from the first edge to the second edge. 26.The display panel of claim 1, wherein, At least part of the load compensation line is located in the non-display area.

27. A display device comprising: A display panel according to any one of claims 1-26.

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