Pixel circuit, pixel driving method, pixel unit, and display apparatus

Abstract

A pixel circuit, a pixel driving method, a pixel unit, and a display apparatus. The pixel circuit comprises stacked light-emitting elements (E1, E2, E3), a driving circuit (10), a node control unit circuit (11, 12, 13), and a display control unit circuit (21, 22, 23); the stacked light-emitting elements (E1, E2, E3) include N light-emitting elements (E1, E2, E3) that are connected in series; N is an integer greater than 1; m is a positive integer less than or equal to N; under the control of the potential of an mth node (M1, M2, M3), an mth display control circuit (21, 22, 23) controls the connection or disconnection between the anode of an mth light-emitting element (E1, E2, E3) and the cathode of the mth light-emitting element (E1, E2, E3); under the control of a control scanning signal, an mth node control circuit (M1, M2, M3) writes an mth control data voltage into the mth node (M1, M2, M3). By means of the pixel circuit, the aperture ratio is increased, the service life of a display product is prolonged, and an ultrahigh PPI display product is realized.

Description

Pixel circuit, pixel driving method, pixel unit and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410680780.2, filed on May 28, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel driving method, a pixel unit and a display device. BACKGROUND

[0004] The related pixel circuit cannot increase the aperture ratio while improving the performance of the pixel circuit, cannot improve the service life of the display product, and cannot provide technical support for ultra-high PPI (pixel density) display products.

[0005] SUMMARY

[0006] The main purpose of the present disclosure is to provide a pixel circuit, a pixel driving method, a pixel unit and a display device, which solve the problem that the prior art cannot increase the aperture ratio while improving the performance of the pixel circuit.

[0007] In one aspect, the pixel circuit comprises a stacked light emitting element, a driving circuit, a node control unit circuit and a display control unit circuit; the node control unit circuit comprises N node control circuits, and the display control unit circuit comprises N display control circuits; the stacked light emitting element comprises N light emitting elements connected in series with each other; N is an integer greater than 1; m is a positive integer less than or equal to N;

[0008] The cathode of the nth light emitting element is electrically connected to the anode of the (n+1)th light emitting element; n is a positive integer less than N; the anode of the first light emitting element is electrically connected to a display node, and the cathode of the Nth light emitting element is electrically connected to a first voltage terminal;

[0009] The driving circuit is electrically connected to the control node and the display node, respectively, and is configured to generate and output a driving current through the display node under the control of the potential of the control node;

[0010] The mth display control circuit is electrically connected to the mth node, the anode of the mth light emitting element and the cathode of the mth light emitting element, respectively, and is configured to control the anode of the mth light emitting element and the cathode of the mth light emitting element to be connected or disconnected under the control of the potential of the mth node;

[0011] The mth node control circuit is electrically connected with the mth node, the mth control data line and the control scanning end respectively, and is configured to write the mth control data voltage provided by the mth control data line into the mth node under the control of a control scanning signal provided by the control scanning end.

[0012] Optionally, the pixel circuit further comprises a data writing circuit and a display energy storage circuit.

[0013] The data writing circuit is electrically connected with the display scanning end, the display data line and the control node respectively, and is configured to write the display data voltage provided by the display data line into the control node under the control of a display scanning signal provided by the display scanning end.

[0014] The first end of the display energy storage circuit is electrically connected with the control node, and the second end of the display energy storage circuit is electrically connected with the display node, and the display energy storage circuit is configured to store electric energy.

[0015] Optionally, the pixel circuit further comprises N energy storage circuits.

[0016] The mth energy storage circuit is electrically connected with the mth node, and is configured to maintain the potential of the mth node.

[0017] Optionally, the pixel circuit further comprises a switch control circuit.

[0018] The switch control circuit is electrically connected with the display scanning end, the display node and an external sensing line respectively, and is configured to control the display node to be connected or disconnected with the external sensing line under the control of a display scanning signal provided by the display scanning end.

[0019] Optionally, the mth display control circuit comprises an mth first transistor, and the mth node control circuit comprises an mth second transistor.

[0020] The gate of the mth first transistor is electrically connected with the mth node, the first pole of the mth first transistor is electrically connected with the anode of the mth light emitting element, and the second pole of the mth first transistor is electrically connected with the cathode of the mth light emitting element.

[0021] The gate of the mth second transistor is electrically connected with the control scanning end, the first pole of the mth second transistor is electrically connected with the mth control data line, and the second pole of the mth second transistor is electrically connected with the mth node.

[0022] The driving circuit comprises a driving transistor.

[0023] A gate of the driving transistor is electrically connected with the control node, a first electrode of the driving transistor is electrically connected with the second voltage terminal, and a second electrode of the driving transistor is electrically connected with the display node.

[0024] Optionally, the data writing circuit comprises a third transistor, and the display energy storage circuit comprises a storage capacitor.

[0025] A gate of the third transistor is electrically connected with the display scanning terminal, a first electrode of the third transistor is electrically connected with the display data line, and a second electrode of the third transistor is electrically connected with the control node.

[0026] A first terminal of the storage capacitor is electrically connected with the control node, and a second terminal of the storage capacitor is electrically connected with the display node.

[0027] Optionally, the mth energy storage circuit comprises an mth capacitor.

[0028] A first terminal of the mth capacitor is electrically connected with the mth node, and a second terminal of the mth capacitor is electrically connected with the direct-current voltage terminal.

[0029] Optionally, the switch control circuit comprises a fourth transistor.

[0030] A gate of the fourth transistor is electrically connected with the display scanning terminal, a first electrode of the fourth transistor is electrically connected with the display node, and a second electrode of the fourth transistor is electrically connected with the external sensing line.

[0031] In a second aspect, the pixel driving method is applied to the pixel circuit, and a display period comprises N display time periods; the mth display time period comprises an mth writing stage and an mth light emitting stage arranged in sequence; and the pixel driving method comprises the following steps.

[0032] In the mth writing stage, the mth node control circuit writes the mth control data voltage provided by the mth control data line into the mth node under the control of the scanning signal.

[0033] In the mth writing stage and the mth light emitting stage, the mth display control circuit controls the anode of the mth light emitting element to be disconnected from the cathode of the mth light emitting element under the control of the potential of the mth node.

[0034] In the mth light emitting stage, the driving circuit drives the mth light emitting element to emit light.

[0035] N is an integer greater than 1, and m is a positive integer less than or equal to N.

[0036] Optionally, the pixel driving method further comprises the following steps.

[0037] In the mth write stage, the a node control circuit writes the a control data voltage provided by the a control data line into the a node under the control of a scanning signal;

[0038] In the mth write stage and the mth light emitting stage, the a display control circuit controls the a light emitting element to be in communication between the anode of the a light emitting element and the cathode of the a light emitting element under the control of the potential of the a node;

[0039] a is a positive integer less than or equal to N, and a is not equal to m.

[0040] Optionally, the pixel circuit further comprises a data write circuit; and the pixel driving method further comprises:

[0041] In the mth write stage, the data write circuit writes the display data voltage provided by the display data line into the control node under the control of a display scanning signal.

[0042] Optionally, the pixel circuit further comprises a switch control circuit; and the mth display time period comprises an mth reset stage arranged before the mth write stage.

[0043] The pixel driving method further comprises:

[0044] In the mth reset stage, the switch control circuit controls the display node to be in communication with an external sensing line under the control of a display scanning signal, the external sensing line providing an initial voltage; the n display control circuit controls the n light emitting element to be in communication between the anode of the n light emitting element and the cathode of the n light emitting element under the control of the potential of the n node; and the N display control circuit controls the N light emitting element to be in disconnection between the anode of the N light emitting element and the cathode of the N light emitting element under the control of the potential of the N node.

[0045] Optionally, the pixel circuit further comprises a switch control circuit; and the mth display time period comprises an mth reset stage arranged before the mth write stage.

[0046] The pixel driving method further comprises:

[0047] In the mth reset stage, the switch control circuit controls the display node to be in communication with an external sensing line under the control of a display scanning signal, the external sensing line providing an initial voltage; the n display control circuit controls the n light emitting element to be in communication between the anode of the n light emitting element and the cathode of the n light emitting element under the control of the potential of the n node; and the N display control circuit controls the N light emitting element to be in communication between the anode of the N light emitting element and the cathode of the N light emitting element under the control of the potential of the N node.

[0048] In a third aspect, the present disclosure provides a display device, comprising a plurality of rows and a plurality of columns of the pixel circuit.

[0049] Optionally, the pixel circuit in the bth row and the 2c-1th column shares the node control unit circuit with the pixel circuit in the bth row and the 2cth column.

[0050] b and c are positive integers.

[0051] In a fourth aspect, the present disclosure provides a pixel unit, comprising a first stacked light emitting element, a second stacked light emitting element, a first driving circuit, a second driving circuit, a node control unit circuit, a first display control unit circuit and a second display control unit circuit; the first stacked light emitting element comprises N light emitting elements connected in series with each other, the second stacked light emitting element comprises N light emitting elements connected in series with each other; N is an integer greater than 1; m is a positive integer less than or equal to N; the node control unit circuit comprises N node control circuits, the first display control unit circuit comprises N first display control circuits, and the second display control unit circuit comprises N second display control circuits.

[0052] the cathode of the n th light emitting element in the first stacked light emitting element is electrically connected with the anode of the n+1 th light emitting element in the first stacked light emitting element, the anode of the first light emitting element in the first stacked light emitting element is electrically connected with a first display node, and the cathode of the N th light emitting element in the first stacked light emitting element is electrically connected with a first voltage terminal;

[0053] the cathode of the n th light emitting element in the second stacked light emitting element is electrically connected with the anode of the n+1 th light emitting element in the second stacked light emitting element, the anode of the first light emitting element in the second stacked light emitting element is electrically connected with a second display node, and the cathode of the N th light emitting element in the second stacked light emitting element is electrically connected with the first voltage terminal;

[0054] the first driving circuit is electrically connected with a first control node and a first display node respectively, and the first driving circuit is configured to generate and output a first driving current through the first display node under the control of the potential of the first control node;

[0055] the second driving circuit is electrically connected with a second control node and a second display node respectively, and the second driving circuit is configured to generate and output a second driving current through the second display node under the control of the potential of the second control node;

[0056] The mth display control circuit in the first display control unit circuit is electrically connected with a first mth node, an anode of an mth light emitting element in the first stacked light emitting element and a cathode of the mth light emitting element in the first stacked light emitting element respectively, for controlling the anode of the mth light emitting element in the first stacked light emitting element and the cathode of the mth light emitting element in the first stacked light emitting element to be connected or disconnected under the control of the potential of the first mth node;

[0057] The mth display control circuit in the second display control unit circuit is electrically connected with a second mth node, an anode of an mth light emitting element in the second stacked light emitting element and a cathode of the mth light emitting element in the second stacked light emitting element respectively, for controlling the anode of the mth light emitting element in the second stacked light emitting element and the cathode of the mth light emitting element in the second stacked light emitting element to be connected or disconnected under the control of the potential of the second mth node;

[0058] The mth node control circuit is electrically connected with the first mth node, the second mth node, an mth control data line and a control scanning end respectively, for writing an mth control data voltage provided by the mth control data line into the first mth node and the second mth node under the control of a control scanning signal provided by the control scanning end.

[0059] Optionally, the pixel unit also includes a first energy storage unit circuit and a second energy storage unit circuit.

[0060] The first energy storage unit circuit includes N energy storage circuits, and the second energy storage unit circuit includes N energy storage circuits.

[0061] The mth energy storage circuit included in the first energy storage unit circuit is electrically connected with the first mth node, for maintaining the potential of the first mth node.

[0062] The mth energy storage circuit included in the second energy storage unit circuit is electrically connected with the second mth node, for maintaining the potential of the second mth node.

[0063] Optionally, the pixel unit also includes a first data writing circuit, a second data writing circuit, a first display energy storage circuit and a second display energy storage circuit.

[0064] The first data writing circuit is electrically connected with a display scanning end, a first display data line and a first control node respectively, for writing a display data voltage provided by the first display data line into the first control node under the control of a display scanning signal provided by the display scanning end.

[0065] The second data writing circuit is electrically connected with a display scanning end, a second display data line and a second control node respectively, and is configured to write a display data voltage provided by the second display data line into the second control node under control of a display scanning signal provided by the display scanning end.

[0066] A first end of the first display energy storage circuit is electrically connected with a first control node, and a second end of the first display energy storage circuit is electrically connected with a first display node, and the first display energy storage circuit is configured to store electric energy.

[0067] A first end of the second display energy storage circuit is electrically connected with a second control node, and a second end of the second display energy storage circuit is electrically connected with a second display node, and the second display energy storage circuit is configured to store electric energy.

[0068] Optionally, the pixel unit also includes a first switch control circuit and a second switch control circuit.

[0069] The first switch control circuit is electrically connected with the display scanning end, the first display node and a first external sensing line respectively, and is configured to control the first display node and the first external sensing line to be connected or disconnected under control of a display scanning signal provided by the display scanning end.

[0070] The second switch control circuit is electrically connected with the display scanning end, the second display node and a second external sensing line respectively, and is configured to control the second display node and the second external sensing line to be connected or disconnected under control of a display scanning signal provided by the display scanning end.

[0071] In a fifth aspect, the display device includes the pixel unit.

[0072] The pixel circuit based on the stacked light-emitting element is proposed, which improves the performance of the pixel circuit, increases the aperture ratio, improves the service life of the display product, and provides technical support for the ultra-high PPI (pixel density) display product. BRIEF DESCRIPTION OF DRAWINGS

[0073] FIG. 1 is a structure diagram of the pixel circuit according to at least one embodiment of the present disclosure.

[0074] FIG. 2 is a structure diagram of the pixel circuit according to at least one embodiment of the present disclosure.

[0075] FIG. 3 is a structure diagram of the pixel circuit according to at least one embodiment of the present disclosure.

[0076] FIG. 4 is a structure diagram of the pixel circuit according to at least one embodiment of the present disclosure.

[0077] FIG. 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG. 6 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0079] FIG. 7A is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0080] FIG. 7B is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0081] FIG. 7C is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0082] FIG. 7D is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0083] FIG. 7E is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0084] FIG. 7F is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0085] FIG. 7G is a diagram of states of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0086] FIG. 8 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0087] FIG. 9 is a simulated timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 5;

[0088] FIG. 10 is a diagram of a structure of a pixel unit according to at least one embodiment of the present disclosure;

[0089] FIG. 11 is a diagram of a structure of a pixel unit according to at least one embodiment of the present disclosure;

[0090] FIG. 12 is a circuit diagram of a pixel unit according to at least one embodiment of the present disclosure;

[0091] FIG. 13 is a timing diagram of operation of at least one embodiment of the pixel unit of FIG. 12. DETAILED DESCRIPTION

[0092] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0093] The transistor used in all embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is called the first pole and the other pole is called the second pole.

[0094] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0095] The pixel circuit in the embodiments of the present disclosure includes a stacked light emitting element, a driving circuit, a node control unit circuit and a display control unit circuit; the node control unit circuit includes N node control circuits, and the display control unit circuit includes N display control circuits; the stacked light emitting element includes N light emitting elements connected in series with each other; N is an integer greater than 1; m is a positive integer less than or equal to N;

[0096] The cathode of the nth light emitting element is electrically connected to the anode of the (n+1)th light emitting element; n is a positive integer less than N; the anode of the first light emitting element is electrically connected to a display node, and the cathode of the Nth light emitting element is electrically connected to a first voltage terminal;

[0097] The driving circuit is electrically connected to the control node and the display node respectively, and the driving circuit is used to generate and output a driving current through the display node under the control of the potential of the control node;

[0098] The mth display control circuit is electrically connected to the mth node, the anode of the mth light emitting element and the cathode of the mth light emitting element respectively, and is used to control the anode of the mth light emitting element and the cathode of the mth light emitting element to be connected or disconnected under the control of the potential of the mth node;

[0099] The mth node control circuit is electrically connected to the mth node, the mth control data line and a control scanning terminal respectively, and is used to write the mth control data voltage provided by the mth control data line into the mth node under the control of the control scanning signal provided by the control scanning terminal.

[0100] The pixel circuit in the embodiments of the present disclosure uses a stacked light emitting element, and the stacked light emitting element includes N light emitting elements connected in series with each other, so that the area of the light emitting material layer of the light emitting element included in the pixel circuit can be improved, the aperture ratio is increased, and the life of the display product is improved.

[0101] In at least one embodiment of the present disclosure, the pixel circuit can be arranged on a substrate, and the stacked light emitting element can include a plurality of light emitting elements connected in series with each other, which can be arranged in sequence along a direction away from the substrate, thereby increasing the area occupied by the light emitting element, facilitating the increase of the aperture ratio, and in the case of the same brightness, the current density flowing through the light emitting element can be reduced, thereby improving the life of the display product.

[0102] In at least one embodiment of the present disclosure, the pixel driving can be performed by a smaller number of transistors, thereby facilitating the realization of high PPI (pixel density).

[0103] The present disclosure proposes a pixel circuit based on a stacked light emitting element, which increases the aperture ratio and improves the life of the display product while improving the performance of the pixel circuit, thereby providing technical support for super-high PPI display products.

[0104] Optionally, the first voltage terminal can be a low voltage terminal.

[0105] In at least one embodiment of the present disclosure, taking N equal to 3 as an example, the stacked light emitting element can include a red light emitting element, a blue light emitting element, and a green light emitting element.

[0106] In specific implementation, N can be an integer greater than 1, for example, N can be equal to 4, and the stacked light emitting element can include a red light emitting element, a blue light emitting element, a green light emitting element, and a white light emitting element, but is not limited thereto.

[0107] Optionally, the light emitting element can be an OLED (organic light emitting diode), a MiroLED (micro light emitting diode), or a Mini LED (mini light emitting diode), but is not limited thereto.

[0108] In at least one embodiment of the present disclosure, the pixel circuit can be arranged on a substrate, and the stacked light emitting element can include a plurality of light emitting elements connected in series with each other, which can be arranged in sequence along a direction away from the substrate, thereby increasing the area occupied by the light emitting element, facilitating the increase of the aperture ratio, and in the case of the same brightness, the current density flowing through the light emitting element can be reduced, thereby improving the life of the display product.

[0109] In the mth write-in stage, the mth node control circuit writes the mth control data voltage provided by the mth control data line into the mth node under the control of the scanning signal.

[0110] In the mth write-in stage and the mth light emitting stage, the mth display control circuit controls the disconnection between the anode of the mth light emitting element and the cathode of the mth light emitting element under the control of the potential of the mth node.

[0111] In the mth light emitting stage, the driving circuit drives the mth light emitting element to emit light.

[0112] In the mth write stage, the ath node control circuit writes the ath control data voltage provided by the ath control data line into the ath node under the control of a scanning signal;

[0113] In the mth write stage and the mth light emitting stage, the ath display control circuit controls the ath light emitting element to be in communication between the anode of the ath light emitting element and the cathode of the ath light emitting element under the control of the potential of the ath node.

[0114] N is an integer greater than 1, m is a positive integer less than or equal to N; a is a positive integer less than or equal to N, and a is not equal to m.

[0115] As shown in FIG. 1, the pixel circuit according to the embodiments of the present disclosure includes a stacked light emitting element, a driving circuit 10, a node control unit circuit, and a display control unit circuit.

[0116] The node control unit circuit includes a first node control circuit 11, a second node control circuit 12, and a third node control circuit 13.

[0117] The display control unit circuit includes a first display control circuit 21, a second display control circuit 22, and a third display control circuit 23.

[0118] The stacked light emitting element includes a first light emitting element E1, a second light emitting element E2, and a third light emitting element E3 connected in series with each other.

[0119] The anode of the first light emitting element E1 is electrically connected to a display node S, and the cathode of the first light emitting element E1 is electrically connected to the anode of the second light emitting element E2.

[0120] The cathode of the second light emitting element E2 is electrically connected to the anode of the third light emitting element E3, and the cathode of the third light emitting element E3 is electrically connected to a first voltage terminal V1.

[0121] The driving circuit 10 is electrically connected to a control node G and a display node S, respectively, and is configured to generate and output a driving current through the display node S under the control of the potential of the control node G.

[0122] The first display control circuit 21 is electrically connected to a first node M1, the anode of the first light emitting element E1, and the cathode of the first light emitting element E1, respectively, and is configured to control the first light emitting element E1 to be in communication or disconnected between the anode and the cathode of the first light emitting element E1 under the control of the potential of the first node M1.

[0123] The second display control circuit 22 is electrically connected with the second node M2, the anode of the second light emitting element E2 and the cathode of the second light emitting element E2 respectively, and is used for controlling the communication or disconnection between the anode of the second light emitting element E2 and the cathode of the second light emitting element E2 under the control of the potential of the second node M2.

[0124] The third display control circuit 23 is electrically connected with the third node M3, the anode of the third light emitting element E3 and the cathode of the third light emitting element E3 respectively, and is used for controlling the communication or disconnection between the anode of the third light emitting element E3 and the cathode of the third light emitting element E3 under the control of the potential of the third node M3.

[0125] The first node control circuit 11 is electrically connected with the first node M1, the first control data line DA and the control scanning end G2 respectively, and is used for writing the first control data voltage provided by the first control data line DA into the first node M1 under the control of the control scanning signal provided by the control scanning end G2.

[0126] The second node control circuit 12 is electrically connected with the second node M2, the second control data line DB and the control scanning end G2 respectively, and is used for writing the second control data voltage provided by the second control data line DB into the second node M2 under the control of the control scanning signal provided by the control scanning end G2.

[0127] The third node control circuit 13 is electrically connected with the third node M3, the third control data line DC and the control scanning end G2 respectively, and is used for writing the third control data voltage provided by the third control data line DC into the third node M3 under the control of the control scanning signal provided by the control scanning end G2.

[0128] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a data writing circuit and a display energy storage circuit.

[0129] The data writing circuit is electrically connected with the display scanning end, the display data line and the control node respectively, and is used for writing the display data voltage provided by the display data line into the control node under the control of the display scanning signal provided by the display scanning end.

[0130] The first end of the display energy storage circuit is electrically connected with the control node, the second end of the display energy storage circuit is electrically connected with the display node, and the display energy storage circuit is used for storing electric energy.

[0131] In specific implementation, the pixel circuit can further comprise a data writing circuit and a display energy storage circuit, the data writing circuit writes the display data voltage into the control node under the control of the display scanning signal, and data voltage writing is performed.

[0132] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the pixel circuit in at least one embodiment of the present disclosure further comprises a data writing circuit 31 and a display energy storage circuit 32.

[0133] The data writing circuit 31 is electrically connected with a display scanning end G1, a display data line DL and the control node G respectively, and is used for writing a display data voltage Vdata provided by the display data line DL into the control node G under the control of a display scanning signal provided by the display scanning end G1.

[0134] The first end of the display energy storage circuit 32 is electrically connected with the control node G, and the second end of the display energy storage circuit 32 is electrically connected with the display node S, and the display energy storage circuit 32 is used for storing electric energy.

[0135] The pixel circuit in at least one embodiment of the present disclosure further comprises N energy storage circuits.

[0136] The mth energy storage circuit is electrically connected with the mth node, and is used for maintaining the electric potential of the mth node.

[0137] In specific implementation, the pixel circuit can further comprise N energy storage circuits, and the mth energy storage circuit maintains the electric potential of the mth node.

[0138] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure can further comprise a first energy storage circuit 41, a second energy storage circuit 42 and a third energy storage circuit 43.

[0139] The first energy storage circuit 41 is electrically connected with the first node M1, and is used for maintaining the electric potential of the first node M1.

[0140] The second energy storage circuit 42 is electrically connected with the second node M2, and is used for maintaining the electric potential of the second node M2.

[0141] The third energy storage circuit 43 is electrically connected with the third node M3, and is used for maintaining the electric potential of the third node M3.

[0142] The pixel circuit in at least one embodiment of the present disclosure further comprises a switch control circuit.

[0143] The switch control circuit is electrically connected with a display scanning end, the display node and an external sensing line respectively, and is used for controlling the display node and the external sensing line to be connected or disconnected under the control of a display scanning signal provided by the display scanning end.

[0144] In a specific implementation, the pixel circuit further includes a switch control circuit, which is controlled by a display scanning signal to control the connection and disconnection between the display node and an external sensing line.

[0145] As shown in FIG. 4, based on at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 40.

[0146] The switch control circuit 40 is electrically connected with a display scanning end G1, the display node S and an external sensing line SL, and is configured to control the connection and disconnection between the display node S and the external sensing line SL under the control of a display scanning signal provided by the display scanning end G1.

[0147] In operation, when the display panel is about to be powered off, the switch control circuit 40 controls the connection between the display node S and the external sensing line SL under the control of a display scanning signal, so as to obtain a compensation voltage signal according to an electrical signal on the external sensing line SL, and the display data voltage is compensated by the compensation voltage signal after the next display panel is powered on.

[0148] Optionally, the mth display control circuit includes an mth first transistor, and the mth node control circuit includes an mth second transistor.

[0149] The gate of the mth first transistor is electrically connected with the mth node, the first electrode of the mth first transistor is electrically connected with the anode of the mth light emitting element, and the second electrode of the mth first transistor is electrically connected with the cathode of the mth light emitting element.

[0150] The gate of the mth second transistor is electrically connected with the control scanning end, the first electrode of the mth second transistor is electrically connected with the mth control data line, and the second electrode of the mth second transistor is electrically connected with the mth node.

[0151] The driving circuit includes a driving transistor.

[0152] The gate of the driving transistor is electrically connected with the control node, the first electrode of the driving transistor is electrically connected with a second voltage end, and the second electrode of the driving transistor is electrically connected with the display node.

[0153] Optionally, the data writing circuit includes a third transistor, and the display energy storage circuit includes a storage capacitor.

[0154] The gate of the third transistor is electrically connected with the display scanning end, the first electrode of the third transistor is electrically connected with the display data line, and the second electrode of the third transistor is electrically connected with the control node.

[0155] The first end of the storage capacitor is electrically connected with the control node, and the second end of the storage capacitor is electrically connected with the display node.

[0156] Optionally, the mth energy storage circuit comprises an mth capacitor.

[0157] The first end of the mth capacitor is electrically connected with the mth node, and the second end of the mth capacitor is electrically connected with the direct current voltage end.

[0158] Optionally, the switch control circuit comprises a fourth transistor.

[0159] The gate of the fourth transistor is electrically connected with the display scanning end, the first pole of the fourth transistor is electrically connected with the display node, and the second pole of the fourth transistor is electrically connected with the external sensing line.

[0160] Optionally, the second voltage end can be a high voltage end.

[0161] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the first display control circuit comprises a first first transistor T11, and the first node control circuit comprises a first second transistor T12; the second display control circuit comprises a second first transistor T21, and the second node control circuit comprises a second second transistor T22; the third display control circuit comprises a third first transistor T31, and the third node control circuit comprises a third second transistor T32; the first light emitting element is a first organic light emitting diode O1, the second light emitting element is a second organic light emitting diode O2, and the third light emitting element is a second organic light emitting diode O3.

[0162] The anode of O1 is electrically connected with the display node S, the cathode of O1 is electrically connected with the anode of O2, the cathode of O2 is electrically connected with the anode of O3, and the cathode of O3 is electrically connected with the low voltage end VSS.

[0163] The gate of T11 is electrically connected with the first node M1, the source of T11 is electrically connected with the anode of O1, and the drain of T11 is electrically connected with the cathode of O1.

[0164] The gate of T21 is electrically connected with the second node M2, the source of T21 is electrically connected with the anode of O2, and the drain of T21 is electrically connected with the cathode of O2.

[0165] The gate of T31 is electrically connected with the third node M3, the source of T31 is electrically connected with the anode of O3, and the drain of T31 is electrically connected with the cathode of O3.

[0166] A gate of the T12 is electrically connected with the control scanning end G2, a drain of the T12 is electrically connected with the first control data line DA, and a source of the T12 is electrically connected with the first node M1;

[0167] A gate of the T22 is electrically connected with the control scanning end G2, a drain of the T22 is electrically connected with the second control data line DB, and a source of the T22 is electrically connected with the second node M2;

[0168] A gate of the T32 is electrically connected with the control scanning end G2, a drain of the T32 is electrically connected with the third control data line DC, and a source of the T32 is electrically connected with the third node M3;

[0169] The driving circuit comprises a driving transistor DT;

[0170] A gate of the driving transistor DT is electrically connected with the control node G, a drain of the driving transistor DT is electrically connected with the high voltage end VDD, and a source of the driving transistor DT is electrically connected with the display node S;

[0171] The data writing circuit comprises a third transistor T3, and the display energy storage circuit comprises a storage capacitor Cst;

[0172] A gate of the third transistor T3 is electrically connected with the display scanning end G1, a drain of the third transistor T3 is electrically connected with the display data line DL, and a source of the third transistor T3 is electrically connected with the control node G;

[0173] A first end of the storage capacitor Cst is electrically connected with the control node G, and a second end of the storage capacitor Cst is electrically connected with the display node S;

[0174] The first energy storage circuit comprises a first capacitor C1, the second energy storage circuit comprises a second capacitor C2, and the third energy storage circuit comprises a third capacitor C3;

[0175] A first end of the C1 is electrically connected with the first node M1, and a second end of the C1 is electrically connected with the high voltage end VDD;

[0176] A first end of the C2 is electrically connected with the second node M2, and a second end of the C2 is electrically connected with the high voltage end VDD;

[0177] A first end of the C3 is electrically connected with the third node M3, and a second end of the C3 is electrically connected with the high voltage end VDD;

[0178] The switch control circuit comprises a fourth transistor T4;

[0179] The gate of the fourth transistor T4 is electrically connected with the display scanning end G1, the drain of the fourth transistor T4 is electrically connected with the display node S, and the source of the fourth transistor T4 is electrically connected with the external sensing line SL.

[0180] In at least one embodiment shown in FIG. 5, O1 can be a red OLED, O2 can be a blue OLED, and O3 can be a green OLED.

[0181] In at least one embodiment of the present disclosure, O1 can be a red OLED, O2 can be a green OLED, and O3 can be a blue OLED; or, O1 can be a green OLED, O2 can be a blue OLED, and O3 can be a red OLED; or, O1 can be a green OLED, O2 can be a red OLED, and O3 can be a blue OLED; or, O1 can be a blue OLED, O2 can be a red OLED, and O3 can be a green OLED; or, O1 can be a blue OLED, O2 can be a green OLED, and O3 can be a red OLED.

[0182] In at least one embodiment shown in FIG. 5, T11, T12 and T13 are p-type transistors, and other transistors are n-type transistors.

[0183] As shown in FIG. 6, at least one embodiment of the pixel circuit shown in FIG. 5 works as follows: one frame time includes a first display time period S1, a second display time period S2 and a third display time period S3; the first display time period S1 includes a first reset stage S11, a first write stage S12 and a first light emitting stage S13 arranged in sequence; the second display time period S2 includes a second reset stage S21, a second write stage S22 and a second light emitting stage S23 arranged in sequence; and the third display time period S3 includes a third reset stage S31, a third write stage S32 and a third light emitting stage S33 arranged in sequence.

[0184] In the first reset stage S11, G1 and G2 provide high voltage signals, DL provides a red data voltage VdataR, DA and DB both provide low voltage signals Vgl, DC provides a high voltage signal Vgh, and SL provides an initial voltage Vini; as shown in FIG. 7A, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, DL provides the red data voltage VdataR to G, T11 and T21 are turned on, SL provides Vini to the anodes of O2 and O3, and the anodes of O2 and O3 are reset; T31 is turned off; and O1, O2 and O3 do not emit light;

[0185] In the first write stage S12, G1 and G2 provide high voltage signals, DL provides red data voltage VdataR, DA provides high voltage signal Vgh, DB and DC both provide low voltage signal Vgl, and SL provides initial voltage Vini. As shown in FIG. 7B, T11 is off, T21 and T31 are on, T21, T22 and T32 are all open, T3 and T4 are both open, the current generated by DT flows to SL through T4, and O1, O2 and O3 do not emit light;

[0186] In the first light-emitting stage S13, G1 and G2 both provide low voltage signals, C1 maintains the potential of M1, C2 maintains the potential of M2, C3 maintains the potential of M3, the potential of M1 is high, and the potentials of M2 and M3 are low. As shown in FIG. 7C, T11 is off, T21 and T31 are on, and DT drives O1 to emit light, wherein T21 and T31 operate in the linear region, DT operates in the saturation region, the luminance of O1 is controlled by VdataR, and different luminance displays are realized.

[0187] In the second reset stage S21, G1 and G2 provide high voltage signals, DL provides blue data voltage VdataB, DA and DB both provide low voltage signal Vgl, DC provides high voltage signal Vgh, and SL provides initial voltage Vini. T21, T22 and T32 are all open, T3 and T4 are both open, DL provides blue data voltage VdataB to G, T11 and T21 are open, SL provides Vini to the anodes of O2 and O3, and the anodes of O2 and O3 are reset. T31 is off, and O1, O2 and O3 do not emit light.

[0188] In the second write stage S22, G1 and G2 provide high voltage signals, DL provides blue data voltage VdataB, DB provides high voltage signal Vgh, DA and DC both provide low voltage signal Vgl, and SL provides initial voltage Vini. As shown in FIG. 7D, T21 is off, T11 and T31 are on, T21, T22 and T32 are all open, T3 and T4 are both open, the current generated by DT flows to SL through T4, and O1, O2 and O3 do not emit light.

[0189] In the second light-emitting stage S23, G1 and G2 both provide low voltage signals, C1 maintains the potential of M1, C2 maintains the potential of M2, C3 maintains the potential of M3, the potential of M1 is high, and the potentials of M2 and M3 are low. As shown in FIG. 7E, T21 is off, T11 and T31 are on, and DT drives O2 to emit light, wherein T11 and T31 operate in the linear region, DT operates in the saturation region, the luminance of O2 is controlled by VdataB, and different luminance displays are realized.

[0190] In the third reset stage S31, G1 and G2 provide high voltage signals, DL provides green data voltage VdataG, DA and DB both provide low voltage signals Vgl, DC provides high voltage signal Vgh, SL provides initial voltage Vini, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, DL provides green data voltage VdataG to G, T11 and T21 are turned on, SL provides Vini to the anode of O2 and the anode of O3, and the anode of O2 and the anode of O3 are reset; T31 is turned off; O1, O2 and O3 do not emit light;

[0191] In the third write stage S32, G1 and G2 provide high voltage signals, DL provides green data voltage VdataG, DC provides high voltage signal Vgh, DA and DB both provide low voltage signals Vgl, and SL provides initial voltage Vini. As shown in FIG. 7F, T31 is turned off, T11 and T21 are turned on, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, the current generated by DT flows to SL through T4, and O1, O2 and O3 do not emit light;

[0192] In the third light-emitting stage S33, G1 and G2 both provide low voltage signals, C1 maintains the potential of M1, C2 maintains the potential of M2, C3 maintains the potential of M3, the potential of M1 is high, and the potentials of M2 and M3 are low. As shown in FIG. 7G, T31 is turned off, T11 and T21 are turned on, and DT drives O3 to emit light. Here, T11 and T21 work in the linear region, DT works in the saturation region, the luminance of O3 is controlled by VdataG, and different luminance displays are realized.

[0193] In the working process of at least one embodiment of the pixel circuit shown in FIG. 5, the stacked light-emitting element can be driven in time sharing, different colors can be displayed in time sharing within a frame frequency, and finally full-color light-emitting design can be realized through color mixing. Since the resistance of the LTPS device in the linear region is smaller than that of the Oxide device, T11, T21 and T31 are more suitable to be LTPS (low temperature polysilicon) devices. In addition, since the mobility of the LTPS device is high, the channel width-length ratio of the LTPS device can be set to be small, which is beneficial to the layout space optimization of high PPI design. In the light-emitting process, in addition to T11, T21 and T31, the transistors need to maintain the voltage of the corresponding nodes. The Oxide device with small drain current can realize low-frequency refresh without affecting the picture quality.

[0194] The pixel circuit and timing based on the new stacked OLED device are provided in the embodiments of the present disclosure. The LTPO (low temperature polysilicon oxide) process is adopted to improve the performance of the pixel circuit, increase the aperture ratio, improve the service life of the display product, and provide technical support for super-high PPI display products.

[0195] As shown in FIG. 8, at least one embodiment of the pixel circuit shown in FIG. 5 is in operation,

[0196] A frame time includes a first display time period S1, a second display time period S2 and a third display time period S3; the first display time period S1 includes a first reset stage S11, a first write stage S12 and a first light-emitting stage S13 arranged in sequence; the second display time period S2 includes a second reset stage S21, a second write stage S22 and a second light-emitting stage S23 arranged in sequence; the third display time period S3 includes a third reset stage S31, a third write stage S32 and a third light-emitting stage S33 arranged in sequence;

[0197] In the first reset stage S11, G1 and G2 provide high voltage signals, DL provides a red data voltage VdataR, DA, DB and DC all provide low voltage signals Vgl, SL provides an initial voltage Vini, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, DL provides the red data voltage VdataR to G, T11, T21 and T32 are turned on, SL provides Vini to the anode of O2, the anode of O3 and VSS, and the anodes of O2 and O3 are reset; O1, O2 and O3 do not emit light; the voltage value of Vini is the same as that of the low voltage signal provided by VSS;

[0198] In the first write stage S12, G1 and G2 provide high voltage signals, DL provides a red data voltage VdataR, DA provides a high voltage signal Vgh, DB and DC all provide low voltage signals Vgl, SL provides an initial voltage Vini, T11 is turned off, T21 and T31 are turned on, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, the current generated by DT flows to SL through T4, and O1, O2 and O3 do not emit light;

[0199] In the first light-emitting stage S13, G1 and G2 both provide low voltage signals, C1 maintains the potential of M1, C2 maintains the potential of M2, C3 maintains the potential of M3, the potential of M1 is high, the potentials of M2 and M3 are low, T11 is turned off, T21 and T31 are turned on, and DT drives O1 to emit light, wherein T21 and T31 operate in a linear region, and DT operates in a saturation region, the luminance of O1 is controlled by VdataR, and different luminance display is realized;

[0200] In the second reset stage S21, G1 and G2 provide high voltage signals, DL provides blue data voltage VdataB, DA, DB and DC all provide low voltage signals Vgl, SL provides initial voltage Vini, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, DL provides blue data voltage VdataB to G, T11, T21 and T32 are turned on, SL provides Vini to the anode of O2, the anode of O3 and VSS, and the anodes of O2 and O3 are reset; O1, O2 and O3 do not emit light; the voltage value of Vini is the same as that of the low voltage signal provided by VSS;

[0201] In the second write stage S22, G1 and G2 provide high voltage signals, DL provides blue data voltage VdataB, DB provides high voltage signal Vgh, DA and DC both provide low voltage signals Vgl, SL provides initial voltage Vini, T21 is turned off, T11 and T31 are turned on, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, the current generated by DT flows to SL through T4, and O1, O2 and O3 do not emit light;

[0202] In the second light-emitting stage S23, G1 and G2 both provide low voltage signals, C1 maintains the potential of M1, C2 maintains the potential of M2, C3 maintains the potential of M3, the potential of M1 is high, the potentials of M2 and M3 are low, T21 is turned off, T11 and T31 are turned on, and DT drives O2 to emit light, wherein T11 and T31 work in the linear region, DT works in the saturation region, the luminance of O2 is controlled by VdataB, and different luminance displays are realized;

[0203] In the third reset stage S31, G1 and G2 provide high voltage signals, DL provides green data voltage VdataG, DA, DB and DC all provide low voltage signals Vgl, SL provides initial voltage Vini, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, DL provides green data voltage VdataG to G, T11, T21 and T32 are turned on, SL provides Vini to the anode of O2, the anode of O3 and VSS, and the anodes of O2 and O3 are reset; O1, O2 and O3 do not emit light; the voltage value of Vini is the same as that of the low voltage signal provided by VSS;

[0204] In the third write stage S32, G1 and G2 provide high voltage signals, DL provides green data voltage VdataG, DC provides high voltage signal Vgh, DA and DB both provide low voltage signals Vgl, SL provides initial voltage Vini, T31 is turned off, T11 and T21 are turned on, T21, T22 and T32 are all turned on, T3 and T4 are both turned on, the current generated by DT flows to SL through T4, and O1, O2 and O3 do not emit light.

[0205] In the third light emitting stage S33, G1 and G2 both provide low voltage signals, C1 maintains the potential of M1, C2 maintains the potential of M2, C3 maintains the potential of M3, the potential of M1 is high, the potentials of M2 and M3 are low, T31 is off, T11 and T21 are on, DT drives O3 to emit light, wherein T11 and T21 work in the linear region, DT works in the saturation region, the light emitting brightness of O3 is controlled by VdataG, and different brightness display is realized.

[0206] FIG. 9 is a simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 5.

[0207] In FIG. 9, one frame time includes a first display time period S1, a second display time period S2 and a third display time period S3;

[0208] In the first display time period S1, the current value of the driving current Id generated by DT is 2μA, the current value of the light emitting current Io1 flowing through O1 is 2μA, the current value of the current flowing through O2 is 300pA, the current value of the current flowing through O3 is 0.2pA, and O1 emits light;

[0209] In the second display time period S2, the current value of the driving current Id generated by DT is 1μA, the current value of the current flowing through O1 is 300pA, the light emitting current flowing through O2 is 1μA, and the current value of the current flowing through O3 is 4pA; O2 emits light;

[0210] In the third display time period S3, the current value of the driving current Id generated by DT is 0.4μA, the current value of the current flowing through O1 is 300pA, the current value of the current flowing through O2 is 200pA, and the current value of the light emitting current flowing through O3 is 0.4μA; O3 emits light;

[0211] O1, O2 and O3 emit light respectively, and full color display is finally realized.

[0212] The pixel driving method provided in the embodiments of the present disclosure is applied to the pixel circuit described above, a display period includes N display time periods; the mth display time period includes an mth write-in stage and an mth light emitting stage arranged in sequence; and the pixel driving method includes:

[0213] In the mth write-in stage, the mth node control circuit writes the mth control data voltage provided by the mth control data line into the mth node under the control of a scanning signal;

[0214] In the mth write-in stage and the mth light emitting stage, the mth display control circuit controls the disconnection between the anode of the mth light emitting element and the cathode of the mth light emitting element under the control of the potential of the mth node;

[0215] In the mth light emitting stage, the driving circuit drives the mth light emitting element to emit light.

[0216] N is an integer greater than 1, and m is a positive integer less than or equal to N.

[0217] The pixel driving method also includes the following steps:

[0218] In the mth write stage, the a th node control circuit writes the a th control data voltage provided by the a th control data line into the a th node under the control of the scanning signal.

[0219] In the mth write stage and the mth light emitting stage, the a th display control circuit controls the a th light emitting element to be in communication between the anode of the a th light emitting element and the cathode of the a th light emitting element under the control of the potential of the a th node.

[0220] a is a positive integer less than or equal to N, and a is not equal to m.

[0221] In at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit, and the pixel driving method further includes the following steps:

[0222] In the mth write stage, the data writing circuit writes the display data voltage provided by the display data line into the control node under the control of the display scanning signal.

[0223] Optionally, the pixel circuit further includes a switch control circuit, and the mth display time period includes an mth reset stage arranged before the mth write stage.

[0224] The pixel driving method also includes the following steps:

[0225] In the mth reset stage, the switch control circuit controls the display node to be in communication with an external sensing line under the control of the display scanning signal, the external sensing line provides an initial voltage; the n th display control circuit controls the n th light emitting element to be in communication between the anode of the n th light emitting element and the cathode of the n th light emitting element under the control of the potential of the n th node; and the N th display control circuit controls the N th light emitting element to be disconnected between the anode of the N th light emitting element and the cathode of the N th light emitting element under the control of the potential of the N th node.

[0226] Optionally, the pixel circuit further includes a switch control circuit, and the mth display time period includes an mth reset stage arranged before the mth write stage.

[0227] The pixel driving method also includes the following steps:

[0228] In the mth reset stage, the switch control circuit controls the display node to be in communication with an external sensing line under the control of a display scanning signal, the external sensing line providing an initial voltage; the nth display control circuit controls the anode of the nth light emitting element to be in communication with the cathode of the nth light emitting element under the control of the potential of the nth node; and the Nth display control circuit controls the anode of the Nth light emitting element to be in communication with the cathode of the Nth light emitting element under the control of the potential of the Nth node.

[0229] The display device provided in the embodiments of the present disclosure comprises a plurality of rows and a plurality of columns of the pixel circuit.

[0230] In at least one embodiment of the present disclosure, the node control unit circuit of the pixel circuit in the bth row and the 2c-1th column and the pixel circuit in the bth row and the 2cth column are shared.

[0231] b and c are positive integers.

[0232] In a specific implementation, two pixel circuits in the same row and adjacent columns can share the node control circuit and the N control data lines, thereby saving the number of signal lines and the number of transistors, and providing technical support for high PPI display products.

[0233] The pixel unit provided in the embodiments of the present disclosure comprises a first stacked light emitting element, a second stacked light emitting element, a first driving circuit, a second driving circuit, a node control unit circuit, a first display control unit circuit and a second display control unit circuit; the first stacked light emitting element comprises N light emitting elements connected in series with each other, and the second stacked light emitting element comprises N light emitting elements connected in series with each other; N is an integer greater than 1; m is a positive integer less than or equal to N; the node control unit circuit comprises N node control circuits, the first display control unit circuit comprises N first display control circuits, and the second display control unit circuit comprises N second display control circuits.

[0234] The cathode of the nth light emitting element in the first stacked light emitting element is electrically connected to the anode of the n+1th light emitting element in the first stacked light emitting element, the anode of the first light emitting element in the first stacked light emitting element is electrically connected to a first display node, and the cathode of the Nth light emitting element in the first stacked light emitting element is electrically connected to a first voltage terminal.

[0235] The cathode of the nth light emitting element in the second stacked light emitting element is electrically connected to the anode of the n+1th light emitting element in the second stacked light emitting element, the anode of the first light emitting element in the second stacked light emitting element is electrically connected to a second display node, and the cathode of the Nth light emitting element in the second stacked light emitting element is electrically connected to the first voltage terminal.

[0236] The first driving circuit is electrically connected with the first control node and the first display node respectively, and is used for generating and outputting a first driving current through the first display node under the control of the potential of the first control node.

[0237] The second driving circuit is electrically connected with the second control node and the second display node respectively, and is used for generating and outputting a second driving current through the second display node under the control of the potential of the second control node.

[0238] The first display control circuit in the first display control unit circuit is electrically connected with the first m node, the anode of the mth light-emitting element in the first stacked light-emitting element and the cathode of the mth light-emitting element in the first stacked light-emitting element respectively, and is used for controlling the anode of the mth light-emitting element in the first stacked light-emitting element and the cathode of the mth light-emitting element in the first stacked light-emitting element to be connected or disconnected under the control of the potential of the first m node.

[0239] The mth display control circuit in the second display control unit circuit is electrically connected with the second m node, the anode of the mth light-emitting element in the second stacked light-emitting element and the cathode of the mth light-emitting element in the second stacked light-emitting element respectively, and is used for controlling the anode of the mth light-emitting element in the second stacked light-emitting element and the cathode of the mth light-emitting element in the second stacked light-emitting element to be connected or disconnected under the control of the potential of the second m node.

[0240] The mth node control circuit is electrically connected with the first m node, the second m node, the mth control data line and the control scanning end respectively, and is used for writing the mth control data voltage provided by the mth control data line into the first m node and the second m node under the control of the control scanning signal provided by the control scanning end.

[0241] The pixel unit in at least one embodiment of the present disclosure is a minimum pixel repeating unit, the pixel unit includes the first stacked light-emitting element and the second stacked light-emitting element, and only one node control unit circuit is used, thereby saving the number of signal lines and the number of transistors, and providing technical support for high-PPI display products.

[0242] As shown in FIG. 10, the pixel unit in at least one embodiment of the present disclosure includes the first stacked light-emitting element, the second stacked light-emitting element, the first driving circuit 101, the second driving circuit 102, the node control unit circuit, the first display control unit circuit and the second display control unit circuit.

[0243] The first stacked light-emitting element includes the first light-emitting element E1, the second light-emitting element E2 and the third light-emitting element E3.

[0244] The second stacked light emitting element includes a fourth light emitting element E4, a fifth light emitting element E5, and a sixth light emitting element E6;

[0245] The node control unit circuit includes a first node control circuit 51, a second node control circuit 52, and a third node control circuit 53;

[0246] The first display control unit circuit includes a first first display control circuit 611, a first second display control circuit 612, and a first third display control circuit 613; and the second display control unit circuit includes a second first display control circuit 621, a second second display control circuit 622, and a second third display control circuit 623;

[0247] The anode of E1 is electrically connected to the first display node S01, the cathode of E1 is electrically connected to the anode of E2, the cathode of E2 is electrically connected to the anode of E3, and the cathode of E3 is electrically connected to the low voltage end VSS;

[0248] The anode of E4 is electrically connected to the second display node S02, the cathode of E4 is electrically connected to the anode of E5, the cathode of E5 is electrically connected to the anode of E6, and the cathode of E6 is electrically connected to the low voltage end VSS;

[0249] The first driving circuit 101 is electrically connected to the first control node G01 and the first display node S01, respectively, and is configured to generate and output a first driving current through the first display node S01 under the control of the potential of the first control node G01;

[0250] The second driving circuit 102 is electrically connected to the second control node G02 and the second display node S02, respectively, and is configured to generate and output a second driving current through the second display node S02 under the control of the potential of the second control node G02;

[0251] The first first display control circuit 611 is electrically connected to the first first node M11, the anode of E1, and the cathode of E1, respectively, and is configured to control the communication or disconnection between the anode of E1 and the cathode of E1 under the control of the potential of the first first node M11;

[0252] The first second display control circuit 612 is electrically connected to the first second node M12, the anode of E2, and the cathode of E2, respectively, and is configured to control the communication or disconnection between the anode of E2 and the cathode of E2 under the control of the potential of the first second node M12;

[0253] The first third display control circuit 613 is electrically connected with the anode of the first third node M13 and the cathode of E3 respectively, for controlling the communication or disconnection between the anode of E3 and the cathode of E3 under the control of the potential of the first third node M13;

[0254] The second first display control circuit 621 is electrically connected with the anode of the second first node M21 and the cathode of E4 respectively, for controlling the communication or disconnection between the anode of E4 and the cathode of E4 under the control of the potential of the second first node M21;

[0255] The second second display control circuit 622 is electrically connected with the anode of the second second node M22 and the cathode of E5 respectively, for controlling the communication or disconnection between the anode of E5 and the cathode of E5 under the control of the potential of the second second node M22;

[0256] The second third display control circuit 623 is electrically connected with the anode of the second third node M23 and the cathode of E6 respectively, for controlling the communication or disconnection between the anode of E6 and the cathode of E6 under the control of the potential of the second third node M23;

[0257] The first node control circuit 51 is electrically connected with the first first node M11, the second first node M21, the first control data line DA and the control scanning end G2 respectively, for writing the first control data voltage provided by the first control data line DA into the first first node M11 and the second first node M21 under the control of the control scanning signal provided by the control scanning end G2;

[0258] The second node control circuit 52 is electrically connected with the first second node M12, the second second node M22, the second control data line DB and the control scanning end G2 respectively, for writing the second control data voltage provided by the second control data line DB into the second first node M21 and the second second node M22 under the control of the control scanning signal provided by the control scanning end G2;

[0259] The third node control circuit 53 is electrically connected with the first third node M13, the second third node M23, the third control data line DC and the control scanning end G2 respectively, for writing the second control data voltage provided by the third control data line DC into the third first node M31 and the third second node M32 under the control of the control scanning signal provided by the control scanning end G2;

[0260] M11 is electrically connected with M21, M12 is electrically connected with M22, and M13 is electrically connected with M23.

[0261] The pixel unit also includes a first energy storage unit circuit and a second energy storage unit circuit.

[0262] The first energy storage unit circuit includes N energy storage circuits, and the second energy storage unit circuit includes N energy storage circuits.

[0263] The mth energy storage circuit included in the first energy storage unit circuit is electrically connected with the first mth node, and is configured to maintain the electric potential of the first mth node.

[0264] The mth energy storage circuit included in the second energy storage unit circuit is electrically connected with the second mth node, and is configured to maintain the electric potential of the second mth node.

[0265] The pixel unit also includes a first data writing circuit, a second data writing circuit, a first display energy storage circuit, and a second display energy storage circuit.

[0266] The first data writing circuit is electrically connected with a display scanning end, a first display data line, and a first control node, respectively, and is configured to write a display data voltage provided by the first display data line to the first control node under the control of a display scanning signal provided by the display scanning end.

[0267] The second data writing circuit is electrically connected with the display scanning end, a second display data line, and a second control node, respectively, and is configured to write a display data voltage provided by the second display data line to the second control node under the control of a display scanning signal provided by the display scanning end.

[0268] A first end of the first display energy storage circuit is electrically connected with the first control node, a second end of the first display energy storage circuit is electrically connected with a first display node, and the first display energy storage circuit is configured to store electric energy.

[0269] A first end of the second display energy storage circuit is electrically connected with the second control node, a second end of the second display energy storage circuit is electrically connected with a second display node, and the second display energy storage circuit is configured to store electric energy.

[0270] The pixel unit also includes a first switch control circuit and a second switch control circuit.

[0271] The first switch control circuit is electrically connected with the display scanning end, the first display node, and a first external sensing line, respectively, and is configured to control the first display node and the first external sensing line to be connected or disconnected under the control of a display scanning signal provided by the display scanning end.

[0272] The second switch control circuit is electrically connected with a display scanning end, the second display node and a second external sensing line, and is used for controlling the second display node to be in communication or disconnected with the second external sensing line under the control of a display scanning signal provided by the display scanning end.

[0273] As shown in FIG. 11, on the basis of at least one embodiment of the pixel unit shown in FIG. 10, the pixel unit provided in at least one embodiment of the present disclosure further comprises a first energy storage unit circuit and a second energy storage unit circuit.

[0274] The first energy storage unit circuit comprises a first first energy storage circuit 711, a first second energy storage circuit 712 and a first third energy storage circuit 713.

[0275] The second energy storage unit circuit comprises a second first energy storage circuit 721, a second second energy storage circuit 722 and a second third energy storage circuit 723.

[0276] The first first energy storage circuit 711 is electrically connected with a first first node M11, and is used for maintaining the potential of the first first node M11.

[0277] The first second energy storage circuit 712 is electrically connected with a first second node M12, and is used for maintaining the potential of the first second node M12.

[0278] The first third energy storage circuit 713 is electrically connected with a first third node M13, and is used for maintaining the potential of the first third node M13.

[0279] The second first energy storage circuit 721 is electrically connected with a second first node M21, and is used for maintaining the potential of the second first node M21.

[0280] The second second energy storage circuit 722 is electrically connected with a second second node M22, and is used for maintaining the potential of the second second node M22.

[0281] The second third energy storage circuit 723 is electrically connected with a second third node M23, and is used for maintaining the potential of the second third node M23.

[0282] The pixel unit provided in at least one embodiment of the present disclosure further comprises a first data writing circuit 81, a second data writing circuit 82, a first display energy storage circuit 83 and a second display energy storage circuit 84.

[0283] The first data writing circuit 81 is electrically connected with a display scanning end G1, a first display data line DL1 and a first control node G01, respectively, and is used for writing a display data voltage provided by the first display data line DL1 into the first control node G01 under the control of a display scanning signal provided by the display scanning end G1.

[0284] The second data writing circuit 82 is electrically connected with the display scanning end G1, the second display data line DL2 and the second control node G02 respectively, and is configured to write the display data voltage provided by the second display data line DL2 into the second control node G02 under the control of the display scanning signal provided by the display scanning end G1;

[0285] The first end of the first display energy storage circuit 83 is electrically connected with the first control node G01, and the second end of the first display energy storage circuit 83 is electrically connected with the first display node S01, and the first display energy storage circuit 83 is configured to store electric energy;

[0286] The first end of the second display energy storage circuit 84 is electrically connected with the second control node G02, and the second end of the second display energy storage circuit 84 is electrically connected with the second display node S02, and the second display energy storage circuit 84 is configured to store electric energy;

[0287] The pixel unit provided in at least one embodiment of the present disclosure further comprises a first switch control circuit 85 and a second switch control circuit 86;

[0288] The first switch control circuit 85 is electrically connected with the display scanning end G1, the first display node S01 and the first external sensing line SL1 respectively, and is configured to control the communication or disconnection between the first display node S01 and the first external sensing line SL1 under the control of the display scanning signal provided by the display scanning end G1;

[0289] The second switch control circuit 86 is electrically connected with the display scanning end G1, the second display node S02 and the second external sensing line SL2 respectively, and is configured to control the communication or disconnection between the second display node S02 and the second external sensing line SL2 under the control of the display scanning signal provided by the display scanning end G1.

[0290] As shown in FIG. 12, on the basis of at least one embodiment of the pixel unit shown in FIG. 11,

[0291] The first display control circuit comprises a first transistor T11, the first node control circuit comprises a second transistor T12; the second display control circuit comprises a second transistor T21, and the second node control circuit comprises a second transistor T22; the third display control circuit comprises a third transistor T31, and the third node control circuit comprises a second transistor T32;

[0292] The second first display control circuit includes a fourth first transistor T41; the second second display control circuit includes a fifth first transistor T51; the third second display control circuit includes a sixth first transistor T61;

[0293] The first light-emitting element is a first organic light-emitting diode O1, the second light-emitting element is a second organic light-emitting diode O2, and the third light-emitting element is a second organic light-emitting diode O3;

[0294] The fourth light-emitting element is the fourth organic light-emitting diode O4, the fifth light-emitting element is the fifth organic light-emitting diode O5, and the sixth light-emitting element is the sixth organic light-emitting diode O6;

[0295] The anode of O1 is electrically connected to the first display node S01, the cathode of O1 is electrically connected to the anode of O2, the cathode of O2 is electrically connected to the anode of O3, and the cathode of O3 is electrically connected to the low voltage terminal VSS.

[0296] The anode of O4 is electrically connected to the second display node S02, the cathode of O4 is electrically connected to the anode of O5, the cathode of O5 is electrically connected to the anode of O6, and the cathode of O6 is electrically connected to the low voltage terminal VSS.

[0297] The gate of T11 is electrically connected to the first node M11, the source of T11 is electrically connected to the anode of O1, and the drain of T11 is electrically connected to the cathode of O1.

[0298] The gate of T21 is electrically connected to the first second node M12, the source of T21 is electrically connected to the anode of O2, and the drain of T21 is electrically connected to the cathode of O2.

[0299] The gate of T31 is electrically connected to the first third node M13, the source of T31 is electrically connected to the anode of O3, and the drain of T31 is electrically connected to the cathode of O3.

[0300] The gate of T41 is electrically connected to the second first node M21, the source of T41 is electrically connected to the anode of O4, and the drain of T41 is electrically connected to the cathode of O4.

[0301] The gate of T51 is electrically connected to the second node M22, the source of T51 is electrically connected to the anode of O5, and the drain of T51 is electrically connected to the cathode of O5.

[0302] The gate of T61 is electrically connected to the second third node M23, the source of T61 is electrically connected to the anode of O6, and the drain of T61 is electrically connected to the cathode of O6.

[0303] The gate of T12 is electrically connected to the control scan terminal G2, the drain of T12 is electrically connected to the first control data line DA, and the source of T12 is electrically connected to the first node M1.

[0304] A gate of the T22 is electrically connected with the control scanning end G2, a drain of the T22 is electrically connected with the second control data line DB, and a source of the T22 is electrically connected with the second node M2;

[0305] A gate of the T32 is electrically connected with the control scanning end G2, a drain of the T32 is electrically connected with the third control data line DC, and a source of the T32 is electrically connected with the third node M3;

[0306] The first driving circuit comprises a first driving transistor DT1, and the second driving circuit comprises a second driving transistor DT2;

[0307] A gate of the first driving transistor DT1 is electrically connected with the first control node G01, a drain of the first driving transistor DT1 is electrically connected with the high voltage end VDD, and a source of the first driving transistor DT1 is electrically connected with the first display node S01;

[0308] A gate of the second driving transistor DT2 is electrically connected with the second control node G02, a drain of the second driving transistor DT2 is electrically connected with the high voltage end VDD, and a source of the second driving transistor DT2 is electrically connected with the second display node S02;

[0309] The first data writing circuit comprises a first third transistor T13, the first display energy storage circuit comprises a first storage capacitor Cst1, the second data writing circuit comprises a second third transistor T23, and the second display energy storage circuit comprises a second storage capacitor Cst2;

[0310] A gate of the first third transistor T13 is electrically connected with the display scanning end G1, a drain of the first third transistor T13 is electrically connected with the first display data line DL1, and a source of the first third transistor T13 is electrically connected with the first control node G01;

[0311] A first end of the first storage capacitor Cst1 is electrically connected with the first control node G01, and a second end of the first storage capacitor Cst1 is electrically connected with the first display node S01;

[0312] A gate of the second third transistor T23 is electrically connected with the display scanning end G1, a drain of the second third transistor T23 is electrically connected with the second display data line DL2, and a source of the second third transistor T23 is electrically connected with the second control node G02;

[0313] A first end of the second storage capacitor Cst2 is electrically connected with the second control node G02, and a second end of the second storage capacitor Cst2 is electrically connected with the second display node S02;

[0314] The first first energy storage circuit includes a first capacitor C1; the first second energy storage circuit includes a second capacitor C2; and the first third energy storage circuit includes a third capacitor C3.

[0315] A first end of the C1 is electrically connected to the first first node M11, and a second end of the C1 is electrically connected to a high voltage end VDD.

[0316] A first end of the C2 is electrically connected to the first second node M12, and a second end of the C2 is electrically connected to the high voltage end VDD.

[0317] A first end of the C3 is electrically connected to the first third node M13, and a second end of the C3 is electrically connected to the high voltage end VDD.

[0318] The second first energy storage circuit includes a fourth capacitor C4; the second second energy storage circuit includes a fifth capacitor C5; and the second third energy storage circuit includes a sixth capacitor C6.

[0319] A first end of the C4 is electrically connected to the second first node M21, and a second end of the C4 is electrically connected to the high voltage end VDD.

[0320] A first end of the C5 is electrically connected to the second second node M22, and a second end of the C5 is electrically connected to the high voltage end VDD.

[0321] A first end of the C6 is electrically connected to the second third node M23, and a second end of the C6 is electrically connected to the high voltage end VDD.

[0322] The first switch control circuit includes a first fourth transistor T14.

[0323] A gate of the first fourth transistor T14 is electrically connected to the display scanning end G1, a drain of the first fourth transistor T14 is electrically connected to the first display node S01, and a source of the first fourth transistor T14 is electrically connected to the first external sensing line SL1.

[0324] The second switch control circuit includes a second fourth transistor T14.

[0325] A gate of the second fourth transistor T24 is electrically connected to the display scanning end G1, a drain of the second fourth transistor T24 is electrically connected to the second display node S02, and a source of the second fourth transistor T24 is electrically connected to the second external sensing line SL2.

[0326] FIG. 13 is a working timing diagram of at least one embodiment of the pixel unit shown in FIG. 12.

[0327] The display device described in the embodiments of the present disclosure includes the pixel unit described above.

[0328] The above describes the preferred embodiments of the present disclosure, and it should be pointed out that for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising stacked light-emitting elements, a driving circuit, a node control unit circuit, and a display control unit circuit; wherein the node control unit circuit comprises N node control circuits, and the display control unit circuit comprises N display control circuits; the stacked light-emitting elements comprise N light-emitting elements connected in series; N is an integer greater than 1; m is a positive integer less than or equal to N; The cathode of the nth light-emitting element is electrically connected to the anode of the (n+1)th light-emitting element; n is a positive integer less than N; The anode of the first light-emitting element is electrically connected to the display node, and the cathode of the Nth light-emitting element is electrically connected to the first voltage terminal. The driving circuit is electrically connected to the control node and the display node respectively. The driving circuit is used to generate and output a driving current through the display node under the control of the potential of the control node. The m-th display control circuit is electrically connected to the m-th node, the anode of the m-th light-emitting element, and the cathode of the m-th light-emitting element, respectively, and is used to control the connection or disconnection between the anode and the cathode of the m-th light-emitting element under the control of the potential of the m-th node. The control circuit of the m-th node is electrically connected to the m-th node, the m-th control data line, and the control scan terminal, respectively, and is used to write the m-th control data voltage provided by the m-th control data line into the m-th node under the control of the control scan signal provided by the control scan terminal.

2. The pixel circuit as described in claim 1, wherein, It also includes a data writing circuit and a display energy storage circuit; The data writing circuit is electrically connected to the display scanning end, the display data line and the control node respectively, and is used to write the display data voltage provided by the display data line into the control node under the control of the display scanning signal provided by the display scanning end; The first terminal of the display energy storage circuit is electrically connected to the control node, and the second terminal of the display energy storage circuit is electrically connected to the display node. The display energy storage circuit is used to store electrical energy.

3. The pixel circuit as described in claim 1, wherein, It also includes N energy storage circuits; The m-th energy storage circuit is electrically connected to the m-th node and is used to maintain the potential of the m-th node.

4. The pixel circuit as described in claim 1, wherein, It also includes a switch control circuit; The switch control circuit is electrically connected to the display scanning end, the display node, and the external sensing line, respectively, and is used to control the connection or disconnection between the display node and the external sensing line under the control of the display scanning signal provided by the display scanning end.

5. The pixel circuit as described in claim 1, wherein, The m-th display control circuit includes the m-th first transistor, and the m-th node control circuit includes the m-th second transistor; The gate of the m-th first transistor is electrically connected to the m-th node, the first electrode of the m-th first transistor is electrically connected to the anode of the m-th light-emitting element, and the second electrode of the m-th first transistor is electrically connected to the cathode of the m-th light-emitting element. The gate of the m-th second transistor is electrically connected to the control scan terminal, the first terminal of the m-th second transistor is electrically connected to the m-th control data line, and the second terminal of the m-th second transistor is connected to the m-th node. Electrical connection; The driving circuit includes a driving transistor; The gate of the driving transistor is electrically connected to the control node, the first terminal of the driving transistor is electrically connected to the second voltage terminal, and the second terminal of the driving transistor is electrically connected to the display node.

6. The pixel circuit as described in claim 2, wherein, The data writing circuit includes a third transistor, and the display energy storage circuit includes a storage capacitor; The gate of the third transistor is electrically connected to the display scanning terminal, the first electrode of the third transistor is electrically connected to the display data line, and the second electrode of the third transistor is electrically connected to the control node. The first end of the storage capacitor is electrically connected to the control node, and the second end of the storage capacitor is electrically connected to the display node.

7. The pixel circuit as described in claim 3, wherein, The m-th energy storage circuit includes the m-th capacitor; The first terminal of the m-th capacitor is electrically connected to the m-th node, and the second terminal of the m-th capacitor is electrically connected to the DC voltage terminal.

8. The pixel circuit as described in claim 4, wherein, The switch control circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the display scanning terminal, the first electrode of the fourth transistor is electrically connected to the display node, and the second electrode of the fourth transistor is electrically connected to the external sensing line.

9. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 8, wherein the display cycle includes N display time periods; the m-th display time period includes a sequentially set m-th writing stage and m-th light emission stage; The pixel driving method includes: During the m-th write stage, the m-th node control circuit, under the control of the control scan signal, writes the m-th control data voltage provided by the m-th control data line into the m-th node. During the m-th writing stage and the m-th light-emitting stage, the m-th display control circuit, under the control of the potential of the m-th node, controls the anode of the m-th light-emitting element to disconnect from the cathode of the m-th light-emitting element; During the m-th luminescence stage, the driving circuit drives the m-th luminescence element to emit light. N is an integer greater than 1, and m is a positive integer less than or equal to N.

10. The pixel driving method as described in claim 9, wherein, Also includes: During the m-th write stage, the node a control circuit, under the control of the control scan signal, writes the a-th control data voltage provided by the a-th control data line into the a-th node. During the m-th writing stage and the m-th light emission stage, the a-th display control circuit, under the control of the potential of the a-th node, controls the connection between the anode and the cathode of the a-th light emission element; a is a positive integer less than or equal to N, and a is not equal to m.

11. The pixel driving method as described in claim 10, wherein, The pixel circuit further includes a data writing circuit; the pixel driving method further includes: During the m-th writing stage, the data writing circuit, under the control of the display scan signal, writes the display data voltage provided by the display data line to the control node.

12. The pixel driving method according to any one of claims 9 to 11, wherein, The pixel circuit further includes a switch control circuit; the m-th display time period includes a m-th reset stage set before the m-th write stage; The pixel driving method further includes: During the m-th reset phase, the switch control circuit, under the control of the display scan signal, controls the connection between the display node and the external sensing line, and the external sensing line provides an initial voltage; the n-th display control circuit, under the control of the potential of the n-th node, controls the connection between the anode and the cathode of the n-th light-emitting element; and the N-th display control circuit, under the control of the potential of the N-th node, controls the disconnection between the anode and the cathode of the N-th light-emitting element.

13. The pixel driving method according to any one of claims 9 to 11, wherein, The pixel circuit further includes a switch control circuit; the m-th display time period includes a m-th reset stage set before the m-th write stage; The pixel driving method further includes: During the m-th reset phase, the switch control circuit, under the control of the display scan signal, controls the connection between the display node and the external sensing line, and the external sensing line provides an initial voltage; the n-th display control circuit, under the control of the potential of the n-th node, controls the connection between the anode and the cathode of the n-th light-emitting element; the N-th display control circuit, under the control of the potential of the N-th node, controls the connection between the anode and the cathode of the N-th light-emitting element.

14. A display device, wherein, Includes a multi-row, multi-column pixel circuit as described in any one of claims 1 to 8.

15. The display device as claimed in claim 14, wherein, The pixel circuit in row b, column 2c-1 and the pixel circuit in row b, column 2c share the same node control unit circuit; b and c are positive integers.

16. A pixel unit, comprising a first stacked light-emitting element, a second stacked light-emitting element, a first driving circuit, a second driving circuit, a node control unit circuit, a first display control unit circuit, and a second display control unit circuit; the first stacked light-emitting element comprises N light-emitting elements connected in series, the second stacked light-emitting element comprises N light-emitting elements connected in series; N is an integer greater than 1; m is a positive integer less than or equal to N; the node control unit circuit comprises N node control circuits, the first display control unit circuit comprises N first display control circuits, and the second display control unit circuit comprises N second display control circuits; The cathode of the nth light-emitting element in the first stacked light-emitting element is electrically connected to the anode of the (n+1)th light-emitting element in the first stacked light-emitting element, the anode of the first light-emitting element in the first stacked light-emitting element is electrically connected to the first display node, and the cathode of the Nth light-emitting element in the first stacked light-emitting element is electrically connected to the first voltage terminal. The cathode of the nth light-emitting element in the second stacked light-emitting element is electrically connected to the anode of the (n+1)th light-emitting element in the second stacked light-emitting element; the anode of the first light-emitting element in the second stacked light-emitting element is electrically connected to the second display node; and the cathode of the Nth light-emitting element in the second stacked light-emitting element is electrically connected to the first voltage terminal. The first driving circuit is electrically connected to the first control node and the first display node respectively. The first driving circuit is used to generate and output a first driving current through the first display node under the control of the potential of the first control node. The second driving circuit is electrically connected to the second control node and the second display node respectively. The second driving circuit is used to generate and output a second driving current through the second display node under the control of the potential of the second control node. The m-th display control circuit in the first display control unit circuit is electrically connected to the first m-th node, the anode of the m-th light-emitting element in the first stacked light-emitting element, and the cathode of the m-th light-emitting element in the first stacked light-emitting element, respectively, and is used to control the connection or disconnection between the anode of the m-th light-emitting element in the first stacked light-emitting element and the cathode of the m-th light-emitting element in the first stacked light-emitting element under the control of the potential of the first m-th node. The m-th display control circuit in the second display control unit circuit is electrically connected to the second m-th node, the anode of the m-th light-emitting element in the second stacked light-emitting element, and the cathode of the m-th light-emitting element in the second stacked light-emitting element, respectively, and is used to control the connection or disconnection between the anode of the m-th light-emitting element in the second stacked light-emitting element and the cathode of the m-th light-emitting element in the second stacked light-emitting element under the control of the potential of the second m-th node. The control circuit of the m-th node is electrically connected to the first m-th node, the second m-th node, the m-th control data line, and the control scan terminal, respectively, and is used to write the m-th control data voltage provided by the m-th control data line into the first m-th node and the second m-th node under the control of the control scan signal provided by the control scan terminal.

17. The pixel unit as claimed in claim 16, wherein, It also includes a first energy storage unit circuit and a second energy storage unit circuit; The first energy storage unit circuit includes N energy storage circuits, and the second energy storage unit circuit includes N energy storage circuits; The first energy storage unit circuit includes an m-th energy storage circuit that is electrically connected to the first m-th node to maintain the potential of the first m-th node; The second energy storage unit circuit includes an m-th energy storage circuit that is electrically connected to the second m-th node to maintain the potential of the second m-th node.

18. The pixel unit as claimed in claim 16 or 17, wherein, It also includes a first data writing circuit, a second data writing circuit, a first display energy storage circuit, and a second display energy storage circuit; The first data writing circuit is electrically connected to the display scanning end, the first display data line and the first control node respectively, and is used to write the display data voltage provided by the first display data line into the first control node under the control of the display scanning signal provided by the display scanning end; The second data writing circuit is electrically connected to the display scanning end, the second display data line, and the second control node, respectively, and is used to write the display data voltage provided by the second display data line into the second control node under the control of the display scanning signal provided by the display scanning end. The first terminal of the first display energy storage circuit is electrically connected to the first control node, and the second terminal of the first display energy storage circuit is electrically connected to the first display node. The first display energy storage circuit is used to store electrical energy. The first end of the second display energy storage circuit is electrically connected to the second control node, and the second end of the second display energy storage circuit is electrically connected to the second display node. The second display energy storage circuit is used to store electrical energy.

19. The pixel unit as claimed in claim 18, wherein, It also includes a first switch control circuit and a second switch control circuit; The first switch control circuit is electrically connected to the display scanning end, the first display node and the first external sensing line respectively, and is used to control the connection or disconnection between the first display node and the first external sensing line under the control of the display scanning signal provided by the display scanning end. The second switch control circuit is electrically connected to the display scanning end, the second display node, and the second external sensing line, respectively, and is used to control the connection or disconnection between the second display node and the second external sensing line under the control of the display scanning signal provided by the display scanning end.

20. A display device comprising a pixel unit as claimed in any one of claims 16 to 19.

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