Solar cell structure, preparation method therefor, and solar cell

Abstract

Embodiments of the present application disclose a solar cell structure, a preparation method therefor, and a solar cell. The method comprises: forming a precursor structure on the surface of a substrate, the precursor structure comprising: a first tunneling layer covering the surface of the substrate and an amorphous silicon layer covering the surface of the first tunneling layer; performing annealing treatment on the amorphous silicon layer and forming a first polycrystalline silicon contact layer; performing patterned laser oxidation on the first polycrystalline silicon contact layer, so that part of the thickness of the first polycrystalline silicon contact layer is oxidized to form a patterned silicon oxide mask layer; removing the amorphous silicon layer and / or the first polycrystalline silicon contact layer outside the area covered by the patterned silicon oxide mask layer; removing the silicon oxide mask layer; and forming a first metal electrode on the surface of the remaining first polycrystalline silicon contact layer.

Description

Solar cell structure, preparation method thereof and solar cell

[0001] Cross-reference to related applications

[0002] The present application is based on the Chinese patent application No. 202410668742.5, filed on May 28, 2024, entitled "Dual-sided TOPCon structure of solar cell and preparation method thereof", and claims priority to the Chinese patent application No. 202410668742.5, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the technical field of solar cell manufacturing. BACKGROUND

[0004] N-type tunnel oxide passivated contact (TOPCon) solar cells have become the first technology for new production lines of crystalline silicon (c-Si) solar cells because of their high photoelectric conversion efficiency and compatible preparation process with traditional P-type passivated emitter and rear cell (PERC) solar cell preparation process. The back tunnel passivation contact layer (n-TOPCon) of the TOPCon solar cell has been greatly optimized to provide good passivation quality and low contact resistance, while the front structure of the solar cell still affects the efficiency of the solar cell and has a large optimization space.

[0005] SUMMARY

[0006] The technical problem to be solved by embodiments of the present application is to provide a solar cell structure, a preparation method thereof and a solar cell.

[0007] In one aspect, the present application provides a preparation method of a solar cell structure, comprising:

[0008] forming a precursor structure on the surface of the substrate; the precursor structure comprises a first tunnel layer covering the surface of the substrate and an amorphous silicon layer covering the surface of the first tunnel layer;

[0009] annealing the amorphous silicon layer to form a first polycrystalline silicon contact layer;

[0010] performing patterned laser oxidation on the first polycrystalline silicon contact layer to oxidize part of the first polycrystalline silicon contact layer to form a patterned silicon oxide mask layer;

[0011] removing the amorphous silicon layer and / or the first polycrystalline silicon contact layer outside the coverage area of the patterned silicon oxide mask layer.

[0012] removing the first tunneling layer except for the area covered by the silicon oxide mask layer;

[0013] forming a first metal electrode on the surface of the remaining first polysilicon contact layer.

[0014] In some embodiments, the annealing process on the amorphous silicon layer forms a first polysilicon contact layer, including:

[0015] laser annealing the amorphous silicon layer to form the first polysilicon contact layer; or

[0016] thermally annealing the amorphous silicon layer to form the first polysilicon contact layer.

[0017] In some embodiments, the laser annealing process on the amorphous silicon layer forms a first polysilicon contact layer, including:

[0018] patterned laser annealing the amorphous silicon layer to form a patterned first polysilicon contact layer; wherein the patterned area of the silicon oxide mask layer falls within the patterned area of the first polysilicon contact layer.

[0019] In some embodiments, the patterned area of the silicon oxide mask layer and the patterned area of the first polysilicon contact layer are coincident in projection in a direction perpendicular to the surface of the substrate.

[0020] In some embodiments, the forming a precursor structure on the surface of the substrate includes:

[0021] preparing a silicon oxide material on the surface of the substrate to form the first tunneling layer;

[0022] preparing an amorphous silicon material doped with boron elements on the surface of the first tunneling layer to form the amorphous silicon layer; wherein the amorphous silicon layer is a P-type amorphous silicon layer.

[0023] In some embodiments, the preparing a silicon oxide material on the surface of the substrate to form the first tunneling layer includes:

[0024] preparing the silicon oxide material on the surface of the substrate by a plasma enhanced chemical vapor deposition (PECVD) process to form the first tunneling layer.

[0025] In some embodiments, the preparing an amorphous silicon material doped with boron elements on the surface of the first tunneling layer to form the amorphous silicon layer includes:

[0026] An amorphous silicon layer doped with boron element is formed on the surface of the first tunneling layer by PECVD or by low pressure chemical vapor deposition (LPCVD).

[0027] In some embodiments, the annealing the amorphous silicon layer to form a first polysilicon contact layer includes:

[0028] The amorphous silicon layer is annealed in a vacuum environment or an inert gas environment to form the first polysilicon contact layer.

[0029] In some embodiments, the laser oxidation of the first polysilicon contact layer to form a patterned silicon oxide mask layer includes:

[0030] The first polysilicon contact layer is laser scanned in an oxygen-containing environment to oxidize a portion of the first polysilicon contact layer to form the patterned silicon oxide mask layer.

[0031] In some embodiments, the thickness of the silicon oxide mask layer is less than the thickness of the remaining first polysilicon contact layer.

[0032] In some embodiments, the thickness of the silicon oxide mask layer is between 10 nanometers and 200 nanometers; and the thickness of the first polysilicon contact layer is between 30 nanometers and 200 nanometers.

[0033] In some embodiments, the thickness of the amorphous silicon layer is between 50 nanometers and 500 nanometers.

[0034] In some embodiments, the removing the amorphous silicon layer and / or the first polysilicon contact layer outside the patterned silicon oxide mask layer coverage area includes:

[0035] The amorphous silicon layer and / or the first polysilicon contact layer outside the patterned silicon oxide mask layer coverage area is cleaned using an alkaline etching process.

[0036] In some embodiments, the removing the silicon oxide mask layer and the first tunneling layer outside the silicon oxide mask layer coverage area includes:

[0037] The silicon oxide mask layer and the first tunneling layer outside the silicon oxide mask layer coverage area is removed using an acid etching process.

[0038] In some embodiments, the forming a first metal electrode on the surface of the remaining first polysilicon contact layer includes:

[0039] screen-printing a patterned metal paste on the surface of the first polysilicon contact layer;

[0040] sintering the metal paste, a first metal electrode is formed.

[0041] In some embodiments, the preparation method further comprises:

[0042] performing boron ion doping on a surface of a crystalline silicon substrate to form a P-type emitter; wherein the crystalline silicon substrate and the P-type emitter constitute the base.

[0043] In some embodiments, the preparation method further comprises:

[0044] stacking a first passivation layer and a first anti-reflection layer in sequence on the surface of the base on which the first metal electrode is formed, to cover a region other than the first metal electrode.

[0045] In some embodiments, the preparation method further comprises:

[0046] stacking a second tunneling layer and a second polysilicon contact layer in sequence on a back surface of the base; wherein a doping polarity of the second polysilicon contact layer is opposite to a doping polarity of the first polysilicon contact layer.

[0047] forming a second metal electrode on a surface of the second polysilicon contact layer.

[0048] forming a second passivation layer on a region other than the second metal electrode on the surface of the second polysilicon contact layer.

[0049] In another aspect, embodiments of the present application provide a solar cell structure, comprising:

[0050] a base;

[0051] a tunnel oxide passivation contact (TOPCon) structure on the base; the TOPCon structure comprises a patterned first tunneling layer, a first polysilicon contact layer and a first metal electrode stacked in sequence; wherein projections of the first tunneling layer, the first polysilicon contact layer and the first metal electrode on the surface of the base coincide.

[0052] In some embodiments, the solar cell structure further comprises:

[0053] a first passivation layer and a first anti-reflection layer stacked in sequence to cover the surface of the base other than the TOPCon structure.

[0054] In some embodiments, the base comprises:

[0055] a crystalline silicon substrate;

[0056] a P-type emitter layer on a surface of the crystalline silicon substrate.

[0057] In some embodiments, the solar cell structure further includes:

[0058] A second tunneling layer and a second polysilicon contact layer are sequentially stacked to cover the back side of the substrate;

[0059] The second metal electrode is located on the surface of the second polycrystalline silicon contact layer;

[0060] A second passivation layer located on the surface of the second polysilicon contact layer, outside the area of ​​the second metal electrode.

[0061] In some embodiments, the solar cell structure is made by any of the above-described preparation methods.

[0062] In another aspect, embodiments of this application provide a solar cell, including one or more of the above-described solar cell structures.

[0063] The technical solution of this application embodiment uses laser to achieve patterning of the TOPCon structure, which can effectively reduce the line width of the pattern and reduce costs, and is suitable for mass production of TOPCon solar cells. Attached Figure Description

[0064] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not to be limited in scale unless otherwise stated.

[0065] Figure 1 is a schematic diagram of a solar cell structure;

[0066] Figure 2 is a schematic diagram of another solar cell structure;

[0067] Figure 3 is a flowchart of the method for fabricating a solar cell structure provided in an embodiment of this application;

[0068] Figure 4 is a schematic diagram of the fabrication process of the solar cell structure provided in the embodiment of this application;

[0069] Figure 5 is a schematic diagram of a solar cell structure provided in an embodiment of this application;

[0070] Figure 6 is a block diagram of the structural composition of a solar cell provided in an embodiment of this application.

[0071] Wherein: 11: N-type crystalline silicon, 12: tunneling oxide layer, 13: polycrystalline silicon thin film layer, 14: silicon nitride passivation layer, 15: emitter, 16: aluminum oxide passivation layer, 17: silicon nitride antireflection layer, 18: positive gate line, 19: back gate line; 210: selective emitter;

[0072] 41: Silicon substrate, 42: Ultrathin silicon oxide tunneling layer, 43: P-type amorphous silicon layer, 44: First laser, 45: Second laser, 46: Polycrystalline silicon contact layer, 47: Silicon oxide mask layer, 46(1) Polycrystalline silicon thin film layer remaining after partial oxidation 46;

[0073] 500: Solar cell structure; 510: Substrate; 520: TOPCon structure; 521: First tunneling layer; 522: First polycrystalline silicon contact layer; 523: First metal electrode; 511: Crystalline silicon substrate; 512: P-type emitter layer; 530: First passivation layer; 540: First antireflection layer; 550: Second tunneling layer; 560: Second polycrystalline silicon contact layer; 570: Second metal electrode; 580: Second passivation layer.

[0074] 600: Solar cell. Detailed Implementation

[0075] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0076] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.

[0077] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0078] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0079] In detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0080] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0081] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” to other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0082] In the context of this application, the structure described above the second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0083] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0084] N-type TOPCon solar cells have become the preferred technology for new crystalline silicon solar cell production lines due to their high photoelectric conversion efficiency and compatibility with traditional P-type PERC solar cell fabrication processes. The structure of an N-type TOPCon solar cell is shown in Figure 1. An ultrathin tunneling oxide layer 12 (SiOx) and a high-phosphorus (P) doped polycrystalline silicon thin film layer 13 (n0) are fabricated on the back side of N-type crystalline silicon 11. ++ The polysilicon oxide layer 12 and the silicon oxide layer 13 together form a passivation contact structure, which provides good surface passivation for the back side of the silicon wafer. The ultrathin oxide layer 12 allows majority carriers to enter the polycrystalline silicon thin film layer 13 through tunneling or pinhole transport while blocking minority carriers. The majority carriers are laterally transported in the polycrystalline silicon thin film layer 13 and collected by the metal of the negative electrode grid line 19, thereby greatly reducing the metal contact recombination current and improving the open-circuit voltage and short-circuit current of the battery. In addition, a silicon nitride passivation layer 14 (SiNx) can be deposited on the polycrystalline silicon thin film layer 13 on the back side to complete the selective contact and passivation of the back side of the battery. The front side of the battery uses conventional boron (B) diffusion technology to form the emitter 15, and then deposits an aluminum oxide passivation layer 16 (Al2O3) and a silicon nitride antireflection layer 17 (SiNx) on the front side. Finally, silver paste or silver-aluminum paste is screen-printed and sintered to form the positive electrode grid line 18 and the negative electrode grid line 19 of the battery. The back tunneling passivation contact layer (n-TOPCon) of TOPCon solar cells has been greatly optimized, providing good passivation quality and low contact resistance. Compared with PERC cells, the efficiency has been greatly improved, and the mass production efficiency can reach 25.0%-26.0%.

[0085] Further improving the efficiency of N-type TOPCon solar cells requires optimizing the front-side cell structure. This can be achieved by covering most of the front-side area of ​​the TOPCon solar cell with Al2O3 and SiNx passivation and antireflection layers. The electrode grid lines are formed by screen printing and sintering on Al2O3 and SiNx. During sintering, the paste penetrates Al2O3 and SiNx to directly contact the underlying P-type emitter. Since the boron doping concentration of the P-type emitter is not high enough, the contact resistance between the grid lines and the emitter directly affects the fill factor (FF) of the cell. Furthermore, the grid lines and the P-type emitter are in direct metal / semiconductor contact, resulting in a high number of interface defect states, which affects the passivation quality and thus reduces the open-circuit voltage (Voc) of the cell.

[0086] To address the issues of contact resistance between the gate line and the P-type emitter, and the impact of gold / semi-contact on passivation, a selective emitter (SE) can be used. This involves introducing a highly boron-doped region (p0.05) between the metal gate line and the P-type emitter. ++ The battery structure at this point is shown in Figure 2, where the highly boron-doped region is the selective emitter 210. The introduction of this highly boron-doped region effectively reduces the contact resistance of the grid lines, thereby improving the battery's flyback efficiency (FF). Furthermore, it effectively reduces the recombination center density at the interface between the metal electrode and the highly boron-doped region, thus improving the passivation quality and the battery's Voc. However, because the diffusion coefficient of boron in silicon is smaller than that of phosphorus (P) in silicon, forming a highly boron-doped region in N-type c-Si is difficult and requires higher temperatures (greater than 1000℃). Laser annealing and thermal oxidation techniques can effectively prepare highly doped emitters (SEs) on the production line, thereby improving the efficiency of TOPCon solar cells. Using laser SE technology can increase the mass production efficiency of TOPCon solar cells to over 26.0%.

[0087] In some embodiments, Laser-Assisted Contact Optimization (LECO) technology can also be used. This technology involves generating a strong reverse photocurrent by laser irradiation under reverse bias after screen printing, thereby creating localized heating at the metal / emitter interface and forming a silver-silicon alloy, effectively reducing contact resistance and achieving the same effect as laser SE. LECO is simpler and has lower equipment costs than laser SE.

[0088] However, regardless of whether it's laser SE technology or LECO technology, the contact between the grid line and silicon is still a gold / semiconductor contact. To solve the gold / semiconductor contact problem, this application provides a method for fabricating a solar cell, as shown in Figure 3. The method includes:

[0089] Step 101: Form a precursor structure on the substrate surface; the precursor structure includes: a first tunneling layer covering the substrate surface and an amorphous silicon layer covering the surface of the first tunneling layer;

[0090] Step 102: Anneal the amorphous silicon layer to form the first polycrystalline silicon contact layer;

[0091] Step 103: Perform patterned laser oxidation on the first polysilicon contact layer to oxidize a portion of the first polysilicon contact layer to form a patterned silicon oxide mask layer.

[0092] Step 104: Remove the amorphous silicon layer and / or the first polycrystalline silicon contact layer outside the area covered by the patterned silicon oxide mask layer;

[0093] Step 105: Remove the silicon oxide mask layer and the first tunneling layer outside the area covered by the silicon oxide mask layer;

[0094] Step 106: Form a first metal electrode on the surface of the remaining first polysilicon contact layer.

[0095] Here, the first tunneling layer can be an ultrathin silicon oxide layer, used to allow majority carriers to tunnel into the first polycrystalline silicon contact layer and effectively block minority carriers. The majority carriers are collected by the first metal electrode through the first polycrystalline silicon contact layer, thereby reducing the recombination current of the metal contact and increasing the open-circuit voltage and short-circuit current of the battery.

[0096] The first polycrystalline silicon contact layer can be a thin film formed of highly phosphorus-doped polycrystalline silicon material, i.e., n ++ -poly-Si. In the embodiments of this application, a precursor can be formed on the substrate first, and the first polycrystalline silicon layer described above can be obtained by processing the precursor.

[0097] Specifically, the precursor includes an amorphous silicon layer, which is crystallized to obtain polycrystalline silicon. Here, the crystallization process can be performed using annealing. After crystallization, a patterned silicon oxide mask layer is formed through laser oxidation. In other words, laser oxidation oxidizes the surface of the polycrystalline silicon to form a patterned mask, facilitating subsequent removal of excess amorphous silicon layers or the first polycrystalline silicon contact layer through etching or cleaning processes.

[0098] Here, the amorphous silicon layer covers the entire surface. The annealing process in step 102 can be either patterned annealing or full-surface annealing. If it is patterned annealing, only the area where the first metal electrode needs to be formed can be annealed, and the upper polycrystalline silicon layer can be further laser-oxidized. In this case, the area outside the coverage of the silicon oxide mask layer is the amorphous silicon layer, so step 104 removes the amorphous silicon layer. It should be noted that the pattern range corresponding to the patterned degradation process can be larger than the pattern range corresponding to the laser oxidation. Therefore, the area outside the coverage of the silicon oxide mask layer may contain not only the amorphous silicon layer but also part of the crystallized polycrystalline silicon layer. Therefore, step 104 can remove both the amorphous silicon layer and the polycrystalline silicon layer.

[0099] Then the silicon oxide mask layer and excess first tunneling layer can be removed simultaneously.

[0100] This forms a locally patterned p-TOPCon structure stacked on the substrate surface. A gate-line structure is then formed on the p-TOPCon structure as the top electrode, resulting in a selective emitter with the p-TOPCon structure.

[0101] Understandably, lasers can achieve patterning with narrow linewidths, and the patterning range can be adjusted by changing the laser spot size. The diameter can be controlled to within 10 μm or even smaller, while the current linewidth of solar cells is around 30 μm. Therefore, the above method is applicable to current and future solar cell manufacturing processes. Furthermore, high-speed laser scanning enables rapid processing, eliminating the need for auxiliary materials such as masks, photoresists, and inks compared to photolithography. This results in fewer steps, offering advantages in efficiency and low cost. Additionally, laser processing does not require contact with the film surface, reducing the risk of scratches and other process problems.

[0102] In some embodiments, the above-described annealing process of the amorphous silicon layer to form the first polycrystalline silicon contact layer includes:

[0103] The amorphous silicon layer is laser annealed to form the first polycrystalline silicon contact layer; or

[0104] The amorphous silicon layer is thermally annealed to form the first polycrystalline silicon contact layer.

[0105] In the embodiments of this application, the annealing process for crystallizing amorphous silicon described above can be either laser annealing or thermal annealing. It is understood that if laser annealing is used, the same patterning process as laser oxidation can be performed, i.e., only a portion of the amorphous silicon area is annealed. Conversely, if thermal annealing is used, the entire surface of amorphous silicon is crystallized.

[0106] It should be noted that thermal annealing not only crystallizes the entire amorphous silicon surface into polycrystalline silicon, but also diffuses some of the boron atoms doped in the polycrystalline silicon into the substrate, thereby increasing the emitter doping concentration and improving battery efficiency.

[0107] In some embodiments, the above-described annealing process of the amorphous silicon layer to form the first polycrystalline silicon contact layer includes:

[0108] The amorphous silicon layer is annealed in a vacuum or inert gas environment to form the first polycrystalline silicon contact layer.

[0109] Conversely, in some embodiments, patterning the first polysilicon contact layer with laser oxidation is described to oxidize a portion of the first polysilicon contact layer to form a patterned silicon oxide mask layer, including:

[0110] The first polysilicon contact layer is patterned by laser scanning in an oxygen-containing environment, so that a portion of the first polysilicon contact layer is oxidized to form a patterned silicon oxide mask layer.

[0111] In some embodiments, the amorphous silicon layer is laser annealed to form a first polycrystalline silicon contact layer, including:

[0112] The amorphous silicon layer is patterned by laser annealing to form a patterned first polycrystalline silicon contact layer; wherein the patterned region of the silicon oxide mask layer falls within the patterned region of the first polycrystalline silicon contact layer.

[0113] In other words, the laser annealing process here is a patterning process similar to laser oxidation, which can achieve crystallization efficiently and quickly, and only needs to be processed within the area where the TOPCon structure is located. It is highly efficient and the patterning process is more flexible.

[0114] It is understandable that laser oxidation process forms a patterned mask layer, and the area covered by the patterned region is the location of the TOPCon structure. The patterned region of laser annealing can be larger than the area covered by laser oxidation process, thereby ensuring that the amorphous silicon in the area covered by laser oxidation process has been crystallized into polycrystalline silicon.

[0115] In some embodiments, the patterned region of the silicon oxide mask layer and the patterned region of the first polysilicon contact layer are projected onto the substrate surface in a direction perpendicular to the substrate surface.

[0116] Here, the graphic regions corresponding to laser annealing and laser oxidation are the same, and can be achieved using the same laser beam. That is, the above-mentioned laser annealing and laser oxidation processes can be achieved by performing two scans with the same laser beam in both oxygen-free and oxygen-rich environments, resulting in higher efficiency and eliminating the need for complex parameter adjustments. Of course, different lasers can also be used depending on the specific laser annealing and laser oxidation processes.

[0117] In some embodiments, forming a precursor structure on the substrate surface includes:

[0118] A silicon oxide material is prepared on the substrate surface to form the first tunneling layer;

[0119] Boron-doped amorphous silicon material is prepared on the surface of the first tunneling layer to form a P-type amorphous silicon layer.

[0120] In some embodiments, the above-described preparation of silicon oxide material on the substrate surface to form a first tunneling layer includes:

[0121] Silicon oxide material is prepared by plasma-assisted oxidation on the substrate surface using plasma-enhanced chemical vapor deposition (PECVD) to form the first tunneling layer.

[0122] Specifically, an ultrathin silicon oxide layer can be prepared on the substrate surface using tubular or plate-type PECVD as the aforementioned first tunneling layer.

[0123] The reaction chamber of a tubular PECVD equipment can be constructed using a quartz tube. Process gases enter the reaction chamber through an inlet flange, thereby depositing thin films. Tubular PECVD offers advantages such as low temperature, high speed, and high film uniformity, making it a highly efficient and flexible thin film deposition technology.

[0124] Plate-type PECVD consists of components such as a deposition chamber, a gas delivery system, a discharge power supply, and a vacuum system. The parallel plate design allows for uniform plasma distribution within the deposition region, thereby improving the uniformity and quality of the thin film.

[0125] Tubular PECVD and plate PECVD can not only be used to prepare silicon dioxide thin films with the aforementioned tunneling layers, but also to deposit antireflection films and passivation films.

[0126] In some embodiments, the preparation of boron-doped amorphous silicon material on the surface of the first tunneling layer to form a P-type amorphous silicon layer includes:

[0127] Boron-doped amorphous silicon material is prepared on the surface of the first tunneling layer by PECVD or by low-pressure chemical vapor deposition (LPCVD) to form an amorphous silicon layer.

[0128] Amorphous silicon layers can also be formed by the above-mentioned plate or tubular PECVD, and can also be formed by LPCVD.

[0129] LPCVD involves chemical reactions at lower pressures (below atmospheric pressure) to deposit gaseous materials as solid thin films on a wafer surface. The low-pressure environment reduces molecular density, minimizes contamination and molecular interference, and increases the mean free path of molecules, thereby contributing to improved reaction rates and uniformity, and ultimately enhancing film quality.

[0130] LPCVD equipment is divided into vertical and horizontal types, mainly differing in the substrate placement and gas flow methods. Vertical LPCVD helps achieve uniformity in thin film deposition, while horizontal LPCVD systems are simpler and less expensive.

[0131] In practical applications, the deposition of the aforementioned silicon dioxide thin film and amorphous silicon thin film can be selected according to the equipment of the actual production line and the specific requirements of the film layer, or other deposition methods not exemplified in the embodiments of this application. This application does not impose specific limitations.

[0132] In some embodiments, the thickness of the silicon oxide mask layer is less than the thickness of the remaining first polysilicon contact layer. Exemplarily, in some embodiments, the thickness of the silicon oxide mask layer is between 10 nanometers and 200 nanometers; the thickness of the first polysilicon contact layer is between 30 nanometers and 200 nanometers. Furthermore, the thickness of the amorphous silicon layer is between 50 nanometers and 500 nanometers. Since the silicon oxide mask layer only needs to serve as a mask and will be removed in the intermediate process, a thinner thickness is sufficient to ensure good anti-etching properties, while the thickness of the first polysilicon contact layer needs to meet the requirements of the TOPCon structure. Therefore, the thickness of the silicon oxide mask layer can be less than the thickness of the first polysilicon contact layer; that is, only a very thin layer of the original first polysilicon contact layer needs to be oxidized.

[0133] In some embodiments, the removal of the amorphous silicon layer and / or the first polycrystalline silicon contact layer outside the patterned silicon oxide mask layer coverage area includes:

[0134] The amorphous silicon layer and / or the first polycrystalline silicon contact layer outside the patterned silicon oxide mask layer coverage area are cleaned using an alkaline etching process.

[0135] Alkaline etching utilizes strong alkaline solutions, such as sodium hydroxide or potassium hydroxide solutions, to chemically react with the material to be etched, dissolving specific layers or impurities on its surface. By controlling the reaction time and conditions, the target portion can be precisely removed. In the embodiments of this application, alkaline etching is used to remove excess amorphous silicon layers or the first polycrystalline silicon contact layer without reacting with silicon oxide. Therefore, the first polycrystalline silicon contact layer under the coverage of the silicon oxide mask layer will not be removed.

[0136] In some embodiments, the removal of the first tunneling layer outside the area covered by the silicon oxide mask layer includes:

[0137] The silicon oxide mask layer and the first tunneling layer outside the area covered by the silicon oxide mask layer are removed by acid etching.

[0138] The precursor includes a first tunneling layer covering the substrate. Both the first tunneling layer and the aforementioned silicon oxide mask layer are made of silicon oxide and can be removed simultaneously. Here, an acidic solution is used for cleaning to remove excess silicon oxide. The first tunneling layer, covered by the first polysilicon contact layer, is not removed. Thus, the remaining first tunneling layer and the first polysilicon contact layer constitute a patterned p-TOPCon structure.

[0139] Acid etching is similar to alkaline etching, but it uses an acidic solution for etching. It can react chemically with silicon oxide to remove the silicon oxide material, but it will not remove the polycrystalline silicon material.

[0140] In some embodiments, forming a first metal electrode on the surface of the remaining first polysilicon contact layer includes:

[0141] A patterned metal paste is screen-printed onto the surface of the first polycrystalline silicon contact layer.

[0142] The metal slurry was sintered to form the first metal electrode.

[0143] In some embodiments, the above preparation method further includes:

[0144] Boron ions are doped on the surface of a crystalline silicon substrate to form a P-type emitter; wherein the crystalline silicon substrate and the P-type emitter constitute the substrate.

[0145] In some embodiments, the above preparation method further includes:

[0146] On the surface of the substrate on which the first metal electrode is formed, a first passivation layer and a first antireflection layer are sequentially stacked to cover the area outside the first metal electrode.

[0147] Specifically, the first passivation layer can be aluminum oxide (Al2O3), and the first antireflection layer can be made of silicon nitride (SiNx). The first passivation layer and the first antireflection layer achieve surface passivation of the selectively contacting P-type emitter.

[0148] In some embodiments, the above preparation method further includes:

[0149] A second tunneling layer and a second polysilicon contact layer are sequentially formed on the back side of the substrate; wherein the doping polarity of the second polysilicon contact layer is opposite to that of the first polysilicon contact layer, i.e., an N-type polysilicon layer.

[0150] A second metal electrode is formed on the surface of the second polycrystalline silicon contact layer;

[0151] A second passivation layer is formed on the surface of the second polycrystalline silicon contact layer, in the region other than the second metal electrode. The second passivation layer can be SiNx or an Al2O3 / SiNx bilayer structure.

[0152] The solar cell structure provided in this application embodiment can be a bifacial TOPCon structure, therefore, the back side of the substrate also has a tunneling layer and a polycrystalline silicon contact layer. Here, the second polycrystalline silicon contact layer can be a highly phosphorus-doped polycrystalline silicon material, thereby forming a passivation layer contact structure for the entire electrode surface. In addition, in the area outside the second metal electrode on its surface, a single layer of silicon nitride or a double layer of aluminum oxide / silicon nitride material can be covered to form a second passivation layer, thereby achieving surface passivation of the back side of the cell.

[0153] This application also provides the following examples in its embodiments:

[0154] As shown in Figure 4, this application provides a method for fabricating a solar cell structure, including the following steps:

[0155] a. An ultrathin silicon oxide tunneling layer 42 is prepared on the surface of a silicon substrate 41 using tubular or plate-type PECVD. A boron-doped amorphous silicon layer 43 is formed by depositing boron-doped amorphous silicon using a vacuum deposition process. The ultrathin silicon oxide tunneling layer and the amorphous silicon layer form a composite layer as the basic structure (precursor) for preparing p-TOPCon.

[0156] b. In a vacuum or inert gas environment, the amorphous silicon layer is crystallized by laser annealing using the first laser 44 to obtain a patterned polycrystalline silicon contact layer 46, thereby crystallizing the pa-Si:H layer to form a patterned SiOx / p layer. ++ -The p-TOPCon is a poly-Si bilayer structure; this step can also be achieved by thermal annealing crystallization. If thermal annealing is used, the entire pa-Si:H is crystallized to form p. ++ -poly-Si, while also being able to p ++Some B atoms in poly-Si diffuse into c-Si, increasing the doping concentration in the emitter and changing the distribution of B atoms in the emitter, thereby further improving the efficiency of the battery.

[0157] c. In an oxygen-containing atmosphere, a second laser 45 is used to perform a secondary laser scan to oxidize the patterned polycrystalline silicon contact layer, forming a silicon oxide mask layer 47 on the surface of the patterned polycrystalline silicon contact layer. At the same time, most of the bottom thickness is left unoxidized to form a patterned polycrystalline silicon thin film layer 46(1) as the contact layer of p-TOPCon. The laser oxidation process is adjusted and optimized so that only the surface forms a silicon oxide mask layer with a design thickness. For example, the thickness of the oxide film layer can be adjusted by adjusting parameters such as laser intensity and wavelength, or by adjusting the oxygen concentration in the environment. The width of the patterned polycrystalline silicon thin film layer and the silicon oxide mask layer is 5μm-30μm, the thickness of the polycrystalline silicon thin film layer is 30nm-200nm, and the thickness of the silicon oxide mask layer is 10nm-200nm. The laser crystallization and laser oxidation are fast, and the time required for crystallization and oxidation is determined by the laser scanning speed, ensuring a large single-machine capacity and eliminating the need for additional consumables, such as photoresist in photolithography. Therefore, the production and operation costs are low, which is unmatched by photolithography technology.

[0158] d. Use alkaline etching to clean the amorphous silicon layer in areas not scanned by laser;

[0159] e. Acid cleaning is then performed to remove excess silicon oxide mask layers from the localized patterned polycrystalline silicon thin film layer and the ultrathin silicon oxide tunneling layer, forming a localized patterned p-TOPCon structure. Screen printing is then performed on the fabricated patterned p-TOPCon structure, followed by sintering to form the upper electrode with a gate structure, resulting in a selective emitter stage with a p-TOPCon structure. By combining laser crystallization and laser oxidation, p-TOPCon structures with very narrow lines can be fabricated. ++ -The poly-Si contact layer currently has a screen-printed gate line width of approximately 30 μm, which can be optimized to approach 20 μm. The line width of laser crystallization and laser oxidation is determined by the laser spot size, and its diameter can be easily controlled within 10 μm or smaller. Therefore, the p-type contact layer disclosed in this invention... ++ The poly-Si patterning scheme can provide any linewidth required for TOPCon solar cell metallization, an advantage that stencil masking and ink patterning techniques cannot achieve.

[0160] Specifically, the vacuum coating process includes PECVD or LPCVD. In step a, the thickness of the amorphous silicon layer and the patterned polycrystalline silicon contact layer is 30nm-500nm, and exemplarily, it can be 50nm. In steps b and c, the laser used in the laser process includes an ultraviolet laser, a visible laser, or an infrared laser.

[0161] In summary, the present invention discloses a method for fabricating a bifacial TOPCon structure for solar cells, which employs PECVD deposition of B-doped a-Si:H thin films and combines laser annealing crystallization and laser oxidation techniques to fabricate patterned p-Si structures on the c-Si surface. ++ -poly-Si / SiOx, where the SiOx formed by laser oxidation serves as a protective layer for alkaline etching. Alkaline etching is then used to remove the amorphous silicon (pa-Si:H) or polycrystalline silicon (p-Si:H) from the areas not subjected to laser oxidation. ++ The poly-Si is etched away to form a p-TOPCon structure corresponding to the screen-printed pattern, thereby improving the efficiency of TOPCon solar cells. This technique can also utilize low-pressure chemical vapor deposition (LPCVD) to prepare intrinsic poly-Si, followed by boron diffusion to transform it into p-TOPCon. ++ -poly-Si utilizes laser oxidation to form SiOx patterns corresponding to the gate lines, which are then etched with alkaline to form patterned p-TOPCon. Due to the high precision of laser technology, narrower linewidths can be achieved, meeting the high efficiency requirements of solar cells. The high-speed scanning of the laser process ensures low production and operation costs. The non-contact nature of the laser process avoids process problems such as scratches, ensuring high yield in the production process.

[0162] Furthermore, this application embodiment also provides a solar cell structure, as shown in FIG5, the solar cell structure 500 including:

[0163] Substrate 510;

[0164] A tunnel oxide passivation contact TOPCon structure 520 is located on the substrate 510; the TOPCon structure 520 includes a patterned first tunneling layer 521, a first polysilicon contact layer 522 and a first metal electrode 523 stacked sequentially; wherein the projections of the first tunneling layer 521, the first polysilicon contact layer 522 and the first metal electrode 523 on the surface of the substrate 510 coincide.

[0165] In some embodiments, the solar cell structure further includes:

[0166] A first passivation layer 530 and a first antireflection layer 540 are sequentially stacked to cover the surface of the substrate 510, excluding the TOPCon structure 520.

[0167] In some embodiments, the substrate 510 includes:

[0168] 511 crystalline silicon substrate;

[0169] The P-type emitter layer 512 is located on the surface of the crystalline silicon substrate 511.

[0170] In some embodiments, the solar cell structure further includes:

[0171] The second tunneling layer 550 and the second polysilicon contact layer 560 are stacked sequentially to cover the back side of the substrate 510.

[0172] The second metal electrode 570 is located on the surface of the second polycrystalline silicon contact layer 560;

[0173] The second passivation layer 580 is located on the surface of the second polysilicon contact layer 560, in the area other than the second metal electrode 570.

[0174] The solar cell structure provided in this application embodiment can be made by any of the above-mentioned preparation methods provided in this application embodiment. The solar cell structure and the above-mentioned preparation methods are based on the same inventive concept. The specific implementation can be understood based on the relevant descriptions in the above-mentioned preparation method embodiments, and will not be repeated here.

[0175] Furthermore, this application also provides a solar cell, as shown in FIG6, which includes one or more of the aforementioned solar cell structures 500. Moreover, one or more solar cell structures 500 in the solar cell 600 can be simultaneously formed during the production process according to the steps in the above-described preparation method. This solar cell is based on the same inventive concept as the above-described preparation method and solar cell structure, and the specific implementation can be understood from the relevant descriptions in any of the above embodiments, which will not be repeated here.

[0176] It is understood that although some inventive embodiments that are currently considered useful have been discussed through various examples in the above disclosure, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover any combination of modifications and equivalents that conform to the substance and scope of the embodiments of this application.

[0177] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0178] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0179] Furthermore, unless expressly stated in the claims, the order of processing elements and sequences, the use of numbers and letters, or other names described in this application are not intended to limit the order of the processes and methods of this application. Although the foregoing disclosure has discussed some currently considered useful embodiments of the invention through various examples, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments; rather, the claims are intended to cover all modifications and equivalent combinations that conform to the substance and scope of the embodiments of this application. For example, while the system components described above can be implemented using hardware devices, they can also be implemented solely through software solutions, such as installing the described system on existing servers or mobile devices.

[0180] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0181] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0182] Although this application has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, any changes or modifications to the above embodiments within the essential spirit of this application will fall within the scope of the claims of this application.

Claims

1. A method for preparing a solar cell structure, comprising: forming a precursor structure on a substrate surface; the precursor structure comprises a first tunneling layer covering the substrate surface and an amorphous silicon layer covering a surface of the first tunneling layer; annealing the amorphous silicon layer to form a first polycrystalline silicon contact layer; performing a patterned laser oxidation on the first polycrystalline silicon contact layer to oxidize a partial thickness of the first polycrystalline silicon contact layer to form a patterned silicon oxide mask layer; removing the amorphous silicon layer and / or the first polycrystalline silicon contact layer outside a coverage area of the patterned silicon oxide mask layer; removing the silicon oxide mask layer and the first tunneling layer outside the coverage area of the silicon oxide mask layer; forming a first metal electrode on a surface of the remaining first polycrystalline silicon contact layer.

2. The production method according to claim 1, wherein, the annealing the amorphous silicon layer to form a first polycrystalline silicon contact layer comprises: performing a laser annealing on the amorphous silicon layer to form the first polycrystalline silicon contact layer; or performing a thermal annealing on the amorphous silicon layer to form the first polycrystalline silicon contact layer.

3. The method of making according to claim 2, wherein, the performing a laser annealing on the amorphous silicon layer to form the first polycrystalline silicon contact layer comprises: performing a patterned laser annealing on the amorphous silicon layer to form a patterned first polycrystalline silicon contact layer; wherein a patterned area of the silicon oxide mask layer falls within a patterned area of the first polycrystalline silicon contact layer.

4. The production method according to claim 3, wherein a projection of the patterned area of the silicon oxide mask layer and the patterned area of the first polycrystalline silicon contact layer in a direction perpendicular to the substrate surface is coincident.

5. The production process according to any one of claims 1 to 4, wherein the forming a precursor structure on a substrate surface comprises: preparing a silicon oxide material on the substrate surface to form the first tunneling layer; preparing a boron-doped amorphous silicon material on a surface of the first tunneling layer to form the amorphous silicon layer.

6. The production method according to claim 5, wherein the preparing a silicon oxide material on the substrate surface to form the first tunneling layer comprises: preparing the silicon oxide material on the substrate surface by a plasma-enhanced chemical vapor deposition (PECVD) process to form the first tunneling layer.

7. The preparation method according to claim 5, wherein, the preparing a boron-doped amorphous silicon material on a surface of the first tunneling layer to form the P-type amorphous silicon layer comprises: preparing the boron-doped amorphous silicon material on the surface of the first tunneling layer by a PECVD or by a low-pressure chemical vapor deposition (LPCVD) to form the amorphous silicon layer.

8. The production process according to any one of claims 1 to 7, wherein the annealing the amorphous silicon layer to form a first polycrystalline silicon contact layer comprises: annealing the amorphous silicon layer in a vacuum environment or an inert gas environment to form the first polycrystalline silicon contact layer.

9. The production process according to any one of claims 1 to 7, wherein the performing a patterned laser oxidation on the first polycrystalline silicon contact layer to oxidize a partial thickness of the first polycrystalline silicon contact layer to form a patterned silicon oxide mask layer comprises: performing a patterned laser scanning on the first polycrystalline silicon contact layer in an oxygen-containing environment to oxidize a partial thickness of the first polycrystalline silicon contact layer to form the patterned silicon oxide mask layer.

10. The production method according to claim 9, wherein a thickness of the silicon oxide mask layer is less than a thickness of the remaining first polycrystalline silicon contact layer.

11. The production method according to claim 9, wherein The thickness of the silicon oxide mask layer is between 10 nm and 200 nm; the thickness of the first poly-silicon contact layer is between 30 nm and 200 nm.

12. The production process according to any one of claims 1 to 11, wherein The thickness of the amorphous silicon layer is between 50 nm and 500 nm.

13. The production process according to any one of claims 1 to 11, wherein The removing the amorphous silicon layer and / or the first poly-silicon contact layer outside the patterned silicon oxide mask layer covered area comprises: Cleaning the amorphous silicon layer and / or the first poly-silicon contact layer outside the patterned silicon oxide mask layer covered area by using alkali etching process.

14. The production process according to any one of claims 1 to 11, wherein The removing the silicon oxide mask layer and the first tunnel layer outside the silicon oxide mask layer covered area comprises: Removing the silicon oxide mask layer and the first tunnel layer outside the silicon oxide mask layer covered area by using acid etching process.

15. The production process according to any one of claims 1 to 11, wherein The forming a first metal electrode on the surface of the remaining first poly-silicon contact layer comprises: Screen-printing a patterned metal paste on the surface of the first poly-silicon contact layer; Sintering the metal paste to form the first metal electrode.

16. The preparation method of any one of claims 1 to 11, further comprising: Performing boron ion doping on the surface of a crystalline silicon substrate to form a P-type emitter; wherein the crystalline silicon substrate and the P-type emitter constitute the base.

17. The preparation method of claim 16, further comprising: Stacking a first passivation layer and a first anti-reflection layer successively on the surface of the base with the first metal electrode to cover the area outside the first metal electrode.

18. The preparation method of claim 16, further comprising: Forming a second tunnel layer and a second poly-silicon contact layer successively on the back surface of the base; wherein the doping polarity of the second poly-silicon contact layer is opposite to that of the first poly-silicon contact layer; Forming a second metal electrode on the surface of the second poly-silicon contact layer; Forming a second passivation layer on the surface of the second poly-silicon contact layer and the area outside the second metal electrode.

19. A solar cell structure, comprising: a base; a tunnel oxide passivation contact (TOPCon) structure on the base; the TOPCon structure comprises a patterned first tunnel layer, a first poly-silicon contact layer, and a first metal electrode stacked successively; wherein the projections of the first tunnel layer, the first poly-silicon contact layer, and the first metal electrode on the surface of the base coincide.

20. The solar cell structure of claim 19, further comprising: a first passivation layer and a first anti-reflection layer stacked successively to cover the surface of the base outside the TOPCon structure.

21. The solar cell structure of claim 19, wherein, the base comprises: a crystalline silicon substrate; a P-type emitter layer on the surface of the crystalline silicon substrate.

22. The solar cell structure of claim 19, further comprising: a second tunnel layer and a second poly-silicon contact layer stacked successively to cover the back surface of the base; a second metal electrode on the surface of the second poly-silicon contact layer; a second passivation layer on the surface of the second poly-silicon contact layer and the area outside the second metal electrode.

23. The solar cell structure of claim 19, wherein, The solar cell structure is prepared by the preparation method of any one of claims 1 to 18.

24. A solar cell comprising one or more solar cell structures according to any one of claims 19 to 23.

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