Ferroelectric random access memory, reading method and electronic device

Abstract

Disclosed in the present application are a ferroelectric random access memory, a reading method and an electronic device. The ferroelectric random access memory comprises a plurality of word lines, a plurality of bit lines and a plurality of ferroelectric memory cells, wherein a first ferroelectric memory cell and a second ferroelectric memory cell that are connected to the same word line form a cell group, with a plurality of cell groups being defined in this way; and in any cell group, at least one bit line is spaced between a bit line connected to the first ferroelectric memory cell and a bit line connected to the second ferroelectric memory cell, so as to use the bit line between the bit lines respectively connected to the first ferroelectric memory cell and the second ferroelectric memory cell as a shield line, thereby alleviating the problem of mutual coupling during signal readout from a bit line, and improving the accuracy of signal reading. Moreover, in two adjacent cell groups connected to the same word line, a bit line connected to a first ferroelectric memory cell in one cell group is adjacent to a bit line connected to a second ferroelectric memory cell in the other cell group. On this basis, the density of ferroelectric memory cells can be improved.

Description

A ferroelectric memory, a reading method, and an electronic device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410663248.X, filed on May 27, 2024, entitled "A Ferroelectric Memory, Reading Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a ferroelectric memory, a reading method, and an electronic device. Background Technology

[0004] Ferroelectric random access memory (FeRAM) is a non-volatile memory that can be widely used in electronic devices due to its advantages such as high-speed read / write, high-density storage, low power consumption and radiation resistance.

[0005] Ferroelectric memories can include multiple ferroelectric memory cells. Signals read from multiple ferroelectric memory cells are passed through a multiplexer and then input to a comparator to identify whether the read signal is "1" or "0". Typically, ferroelectric memory cells are connected to the comparator via bit lines. When multiple ferroelectric memory cells are read simultaneously, signals read from adjacent bit lines may couple with each other, affecting the identification result. Summary of the Invention

[0006] This application provides a ferroelectric memory, a reading method, and an electronic device to improve the mutual coupling problem when reading signals from adjacent bit lines and to improve the accuracy of signal reading.

[0007] In a first aspect, embodiments of this application provide a ferroelectric memory, which includes multiple word lines, multiple bit lines, and multiple ferroelectric memory cells. Each of the multiple ferroelectric memory cells is connected to one word line and one bit line from the multiple word lines. Furthermore, any word line can connect to alternating first and second ferroelectric memory cells, forming a cell group by combining a first ferroelectric memory cell and a second ferroelectric memory cell connected to the same word line. This divides the memory into multiple cell groups. In any cell group, at least one bit line separates the bit lines connected to the first and second ferroelectric memory cells. Therefore, when reading from either cell group, the bit lines connecting the first and second ferroelectric memory cells can be used as shielding lines, reducing the mutual coupling problem during bit line readout and improving signal readout accuracy. Furthermore, in two adjacent cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group. Based on this, the density of ferroelectric memory cells can be increased.

[0008] In some embodiments, in any group of cells, there is a space between the bit lines connecting the first ferroelectric memory cell and the bit lines connecting the second ferroelectric memory cell. This configuration minimizes the number of bit lines required.

[0009] In some embodiments, the multiple word lines include adjacent first word lines and second word lines. The first word line connects to a first ferroelectric memory cell, and the second word line connects to a second ferroelectric memory cell. Corresponding first and second ferroelectric memory cells are connected to the same bit line. This configuration allows corresponding first and second ferroelectric memory cells to share the same bit line, further reducing the number of bit lines used.

[0010] In some embodiments, each ferroelectric memory cell includes a transistor and a ferroelectric capacitor, wherein the gate of the transistor is connected to a corresponding word line, the first terminal of the transistor is connected to a corresponding bit line, and the second terminal of the transistor is connected to the ferroelectric capacitor. This configuration allows control over the switching on and off of the transistor to write and read information stored in the ferroelectric capacitor. Furthermore, multiple word lines can extend along a first direction and be spaced apart along a second direction, and multiple bit lines can extend along a second direction and be spaced apart along the first direction, thus arranging the word lines and bit lines in an orthogonal configuration. Based on this, the channels of the transistors in each ferroelectric memory cell can also be arranged to extend along the second direction, eliminating the need for additional tilting of the channels for each transistor and reducing manufacturing complexity.

[0011] For example, the transistor can be a horizontal transport transistor (e.g., a Fin Field Effect Transistor (FinFET) or a Gate All Around Field Effect Transistor (GAAFET)) or a Vertical Transport Field Effect Transistor (VTFET).

[0012] For example, a ferroelectric capacitor may have a first electrode, a second electrode, and a ferroelectric functional layer disposed between the first electrode and the second electrode. In some embodiments, the ferroelectric capacitor may be a stacked structure; in other embodiments, the ferroelectric capacitor may also be a columnar electrode, for example, the second electrode is a columnar electrode, the ferroelectric functional layer surrounds the bottom and sidewalls of the second electrode, and the first electrode surrounds the ferroelectric functional layer.

[0013] For example, the channel has a channel region and a first source / drain region and a second source / drain region located on both sides of the channel region. The first source / drain region is connected to the corresponding bit line, and the second source / drain region is connected to the first electrode of the ferroelectric capacitor. The corresponding word line covers the channel through a gate dielectric layer to form the gate. With this configuration, the gate can be formed using the word line, eliminating the need for additional structures and reducing the area occupied by the gate. It is understood that the first and second source / drain regions can be heavily doped regions for signal transmission.

[0014] In some embodiments, the channels of transistors connected to the same bit line can be arranged sequentially along a second direction, thereby allowing the channels to be arranged closely and reducing the occupied area of ​​the channels.

[0015] In some embodiments, the ferroelectric capacitors connected to transistors on the same bit line can be arranged sequentially along a second direction. This arrangement allows all ferroelectric capacitors connected to transistors on the same bit line to be arranged sequentially along the second direction, and also allows the ferroelectric capacitors in each ferroelectric memory cell to correspond to their connected second source / drain regions, thus uniformly arranging the ferroelectric capacitors.

[0016] In some embodiments, in order to further improve the density of ferroelectric memory cells, when multiple word lines include adjacent first word lines and second word lines, since the first ferroelectric memory cells connected by the first word line correspond to the second ferroelectric memory cells connected by the second word line, the first source and drain regions of the transistors in the corresponding first ferroelectric memory cells and second ferroelectric memory cells can be set to the same region, thereby sharing the first source and drain regions of the transistors in the corresponding first ferroelectric memory cells and second ferroelectric memory cells, further reducing the occupied area of ​​the channel, and also allowing the channels of the transistors connected by adjacent bit lines to be staggered.

[0017] For example, multiple word lines, multiple bit lines, and multiple ferroelectric memory cells are disposed on a substrate, which may be a semiconductor substrate or other insulating material substrate.

[0018] In some embodiments, the orthographic projection of any ferroelectric capacitor onto the substrate and the orthographic projection of the second source / drain region connected to that ferroelectric capacitor onto the substrate may overlap. This arrangement allows all ferroelectric capacitors connected to the same bit line to be arranged sequentially along a second direction, and also allows the ferroelectric capacitors in each ferroelectric memory cell to be correspondingly arranged with their connected second source / drain regions, thus uniformly arranging the ferroelectric capacitors.

[0019] In some embodiments, the ferroelectric memory further includes multiple board lines, with the board lines located on a layer between the word line layer and the bit line layer. Furthermore, the second electrode of the ferroelectric capacitor in each ferroelectric memory cell is connected to one of the multiple board lines. This configuration allows the board lines to be used as the second electrodes of the ferroelectric capacitors for signal transmission.

[0020] In some embodiments, the ferroelectric capacitors of the first and second ferroelectric memory cells in any cell group can be connected to the same board line so that some memory cells share the same board line, thereby reducing the number of board lines.

[0021] In some embodiments, ferroelectric capacitors in different cell groups connected to the same word line can be connected to different board lines. This configuration allows different board lines to be used to transmit signals to adjacent cell groups, so that when any word line is selected, all or part of the ferroelectric memory cells can be read, increasing the flexibility of the read operation.

[0022] In some embodiments, in order to further reduce the number of board lines, when multiple word lines include adjacent first word lines and second word lines, multiple cell groups connected by the first word lines can be made to include a first cell group, multiple cell groups connected by the second word lines can be made to include a second cell group, and the bit line connected to the first ferroelectric memory cell in the second cell group is located between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first cell group, so that the first cell group connected to different word lines and the ferroelectric capacitor in the second cell group can share the same board line, thereby reducing the number of board lines.

[0023] In some embodiments, when connecting multiple ferroelectric capacitors, the staggered arrangement of transistor channels allows for sufficient space to be reserved for the inclined zigzag lines. This staggered channel arrangement allows the ferroelectric capacitors in different ferroelectric memory cells to form a unique stepped arrangement from the upper left to the lower right, thus enabling the board lines to be configured as stepped zigzag lines. Alternatively, the stepped arrangement of the ferroelectric capacitors can also allow the board lines to be configured as straight lines extending in an inclined direction. Furthermore, the stepped arrangement of the ferroelectric capacitors avoids the board lines obstructing the contact holes where the first conductive portion is located, preventing short circuits between the board lines and bit lines.

[0024] In some embodiments, in any unit group, the ferroelectric capacitors in the first ferroelectric memory unit and the second ferroelectric memory unit are connected to different board lines. This arrangement allows the first ferroelectric memory unit and the second ferroelectric memory unit in the same unit group to transmit signals using different board lines.

[0025] In some embodiments, the ferroelectric capacitors in the first and second ferroelectric memory cells connected to the same word line are connected to different board lines. This configuration allows the first and second ferroelectric memory cells corresponding to the same word line to transmit signals using different board lines.

[0026] In some embodiments, in order to reduce the number of board lines, when multiple word lines include adjacent first word lines and second word lines, the multiple unit groups connected by the first word lines can be made to include the first unit group, the multiple unit groups connected by the second word lines can be made to include the second unit group, and the bit line connected to the first ferroelectric memory cell in the second unit group is located between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first unit group, so that the ferroelectric capacitor in the first ferroelectric memory cell in the first unit group and the first ferroelectric memory cell in the second unit group can be connected to the same board line, thereby reducing the number of board lines.

[0027] In some embodiments, when board lines connect multiple ferroelectric capacitors, sufficient inclined straight space can be reserved for board line routing due to the staggered arrangement of transistor channels. For example, based on the staggered arrangement of channels, the ferroelectric capacitors in different ferroelectric memory cells can form unique straight lines extending in a direction that intersects both the first and second directions in the direction from the upper left to the lower right.

[0028] In some embodiments, multiple board wires are divided into multiple board wire groups, wherein each board wire group includes two adjacent board wires. Furthermore, the two board wires in each board wire group are electrically connected to each other, and the board wires in different board wire groups are insulated from each other.

[0029] Furthermore, two boards in any board line group can be connected to each other using a connecting line.

[0030] In some embodiments, the ferroelectric capacitors in ferroelectric memory cells corresponding to the same word line can be connected to the same board line, while the ferroelectric capacitors in ferroelectric memory cells corresponding to different word lines can be connected to different board lines.

[0031] In some embodiments, based on the stepped arrangement of ferroelectric capacitors and the staggered arrangement of transistor channels, sufficient space can be reserved for board wiring so that the board wiring is a zigzag line extending along the first direction.

[0032] Secondly, embodiments of this application also provide an electronic device, which includes a circuit board and a ferroelectric memory, the ferroelectric memory being disposed on the circuit board. The ferroelectric memory is the same as that in the first aspect or various embodiments of the first aspect. Furthermore, the technical effects of the corresponding solutions in the second aspect can be referred to the technical effects obtainable by the corresponding solutions in the first aspect; repeated details will not be elaborated.

[0033] Thirdly, embodiments of this application also provide a method for reading a ferroelectric memory. The ferroelectric memory includes: multiple word lines, multiple bit lines, and multiple ferroelectric memory cells. Each ferroelectric memory cell is connected to one word line and one bit line among the multiple word lines. Any word line connects to ferroelectric memory cells including alternating first and second ferroelectric memory cells. A first ferroelectric memory cell and a second ferroelectric memory cell connected to the same word line form a cell group. In any cell group, at least one bit line separates the bit lines connected to the first ferroelectric memory cell and the bit lines connected to the second ferroelectric memory cell. In two adjacent cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group. Furthermore, the method includes: selecting any word line among the multiple word lines, controlling at least a portion of the bit lines connected to the selected word line to be floating, and controlling the unconnected bit lines of the ferroelectric memory cells to input a fixed potential. With this configuration, for any unit group, when reading the first ferroelectric memory unit and the second ferroelectric memory unit, the bit line connecting the first ferroelectric memory unit and the second ferroelectric memory unit can be used as a shielding line, thereby reducing the mutual coupling problem when reading signals from the bit lines and improving the accuracy of signal reading.

[0034] The ferroelectric memory of the present application embodiment can be used as a ferroelectric memory of a 1T1C array or a 2T2C array.

[0035] Furthermore, based on the stepped arrangement of ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cell can be written, increasing the freedom of the write operation.

[0036] Furthermore, based on the stepped arrangement of ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be read, increasing the freedom of read operations. Attached Figure Description

[0037] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0038] Figure 2a is a schematic diagram of charge movement in a ferroelectric capacitor;

[0039] Figure 2b is a schematic diagram of another type of charge movement in a ferroelectric capacitor;

[0040] Figure 3 shows the relationship between the coercive field voltage and the amount of residual polarization charge.

[0041] Figure 4 is a circuit diagram of the 1T1C ferroelectric memory cell in the related technology;

[0042] Figure 5 is the timing diagram of the ferroelectric memory cell in Figure 4;

[0043] Figure 6 is a circuit diagram of a 2T2C ferroelectric memory cell in related technologies;

[0044] Figure 7 is a schematic diagram of the bit lines in an embodiment of this application;

[0045] Figure 8 is a circuit diagram of a ferroelectric memory according to an embodiment of this application;

[0046] Figure 9 is a schematic diagram of a unit group composed of ferroelectric storage voltages as shown in Figure 8;

[0047] Figure 10 is the layout structure diagram corresponding to the circuit diagram shown in Figure 8;

[0048] Figure 11 is a cross-sectional view along the AA' direction in the layout structure diagram shown in Figure 10;

[0049] Figure 12 is a circuit diagram of another ferroelectric memory according to an embodiment of this application;

[0050] Figure 13 is the layout structure diagram corresponding to the circuit diagram shown in Figure 12;

[0051] Figure 14 is a cross-sectional view of the layout structure shown in Figure 13 along the AA' direction;

[0052] Figure 15 is a circuit diagram of another ferroelectric memory according to an embodiment of this application;

[0053] Figure 16 is the layout structure diagram corresponding to the circuit diagram shown in Figure 15;

[0054] Figure 17 is a circuit diagram of another ferroelectric memory according to an embodiment of this application;

[0055] Figure 18 is the layout structure diagram corresponding to the circuit diagram shown in Figure 17. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0057] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0058] The storage solution provided in this application can be widely applied to devices with storage functions. For example, it can be applied to storage devices with only storage functions, such as ferroelectric memories, or to electronic devices with storage functions and other functions (such as read / write functions). The electronic device can be a terminal device, such as a portable electronic device containing functions like a personal digital assistant and / or a music player, such as a mobile phone, tablet computer, wearable device with wireless communication functions (such as a smartwatch), or in-vehicle equipment. Exemplary embodiments of the terminal device include, but are not limited to, devices equipped with… Alternatively, it can be a portable electronic device with another operating system. The terminal device can also be a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of this application, the above-mentioned electronic device can also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0059] Figure 1 illustrates a schematic diagram of an electronic device. Referring to Figure 1, the electronic device includes a housing 100 and a circuit board 200 disposed within the housing 100. A processor 400 and a memory 300 are disposed on the circuit board 200. The memory 300 can be used to store computer-executable program code, which may include instructions. The processor 400 executes various functional applications and data processing of the electronic device by running the instructions stored in the memory 300. In some embodiments, the memory 300 can also store instructions or data that the processor 400 has just used or that is being reused. If the processor 400 needs to reuse the instruction or data, it can directly retrieve it from the memory 300, avoiding repeated access, reducing processor waiting time, and thus improving the efficiency of the mobile phone.

[0060] Ferroelectric memories, due to their advantages such as high-speed read / write, high-density storage, low power consumption, and radiation resistance, can be configured as ferroelectric memories. Typically, a ferroelectric memory includes ferroelectric memory bits, each containing a ferroelectric capacitor. Referring to Figures 2a and 2b, Figure 2a exemplarily illustrates one type of charge movement within the ferroelectric capacitor, and Figure 2b exemplarily illustrates another type of charge movement within the ferroelectric capacitor. The ferroelectric capacitor may include a first electrode 11, a second electrode 12, and a ferroelectric functional layer 13 disposed between the first electrode 11 and the second electrode 12. The ferroelectric functional layer 13 can generate polarization according to the direction and magnitude of the applied electric field. After the electric field is removed, some polarization can still be maintained; this partial polarization is called residual polarization. Because the residual polarization has a residual polarization charge Pr, it has a potential difference. To balance this potential difference, the first electrode 11 and the second electrode 12 can induce opposite induced charges. Since the residual polarization is not lost after the electric field is removed, the induced charge can also be retained on the first electrode 11 and the second electrode 12. The ferroelectric memory can achieve non-volatile information storage by reading the induced charge.

[0061] Figure 3 illustrates the relationship between the coercive field voltage and the remaining polarization charge. Referring to Figure 3, when a reverse electric field is applied and its strength exceeds the coercive field, polarization reverses. The information stored in the ferroelectric capacitor C can be read by identifying the amount of charge released during the polarization reversal process. The center voltage of the ferroelectric polarization reversal process is called the coercive voltage Vc. To ensure the reliability of the information stored in the ferroelectric capacitor C, the ferroelectric functional layer 13 should be fully flipped. During the writing and reading phases, the potential difference input to the first and second electrodes should be 2 to 4 times the coercive voltage Vc.

[0062] Figure 4 illustrates an exemplary circuit diagram of a 1T1C ferroelectric memory cell. Referring to Figure 4, the ferroelectric memory may include a word line WL, a bit line BL, a board line PL, and multiple ferroelectric memory cells. Each ferroelectric memory cell includes at least one ferroelectric capacitor C and at least one transistor T. The gate of transistor T is electrically connected to the word line WL, the first electrode of transistor T is electrically connected to the first electrode of the ferroelectric capacitor C, and the second electrode of transistor T is electrically connected to the bit line BL.

[0063] Figure 5 illustrates the timing diagram of the ferroelectric memory cell in Figure 4. Referring to Figures 4 and 5, taking writing "1" and reading "1" as examples,

[0064] During the write phase: the potential on the word line WL is high (e.g., 1.5V), and transistor T is turned on. The potential on the board line PL is high (e.g., 1V), and the potential on the bit line BL is low (e.g., 0V), allowing "0" to be written to the ferroelectric capacitor in the ferroelectric memory cell. Afterwards, the potential on the board line PL is low, and the potential on the bit line BL is high, allowing "1" to be written to the ferroelectric capacitor in the ferroelectric memory cell.

[0065] During the read phase: the potential on word line WL is high, and transistor T is turned on. The potential on board line PL is high, bit line BL is floating, the charge in ferroelectric functional layer 13 flips, and the flipped charge is released as a read signal. The flipped charge is released through bit line capacitor C, which is electrically connected to bit line BL. BL The signal is input as a voltage to a multiplexer, which then inputs it to a comparator (sense amplifier, SA). The comparator SA compares the read signal with a reference voltage Vref to identify the read signal as "1", and also amplifies the read signal.

[0066] Referring to Figures 4 and 5, let's take writing "0" and reading "0" as examples.

[0067] During the write phase: the potential on the word line WL is high (e.g., 1.5V), and the transistor T is turned on. The potential on the board line PL is high (e.g., 1V), and the potential on the bit line BL is low (e.g., 0V), allowing "0" to be written to the ferroelectric memory cell.

[0068] During the read phase: the potential on word line WL is high, and transistor T is turned on. The potential on board line PL is high, and bit line BL is floating. Since the direction of the electric field applied to the first electrode 11 and the second electrode 12 does not change during the write and read phases, the charge in the ferroelectric functional layer 13 does not flip and is not released. Bit line BL transmits the unreleased read signal to a multiplexer, which then inputs it to comparator SA. Comparator SA compares the read signal with the reference voltage Vref to identify the read signal as "0".

[0069] For example, when the ferroelectric storage cell is working properly, the comparator SA can determine that the read signal is "1" based on the comparison result that "the read signal is greater than the reference voltage Vref"; conversely, the comparator SA can determine that the read signal is "0" based on the comparison result that "the read signal is less than the reference voltage Vref".

[0070] Figure 6 illustrates an exemplary circuit diagram of a 2T2C ferroelectric memory cell. Referring to Figure 6, two 1T1C ferroelectric memory cells are combined into one memory cell. During operation, in the write phase: the potential on the word line WL is high, and both transistors T are turned on. The potential on the board line PL is high, and the potential on the bit line BL is low, allowing "0" to be written to these two ferroelectric memory cells first. Afterward, the potential on the board line PL is low, and the potential on the bit line BL1 is high, allowing "1" to be written to the ferroelectric memory cell connected to bit line BL1, while the ferroelectric memory cell connected to bit line BL2 remains "0". In the read phase: the potential on the word line WL is high, and transistor T is turned on. The potential on the board line PL is high, and the bit line BL is floating. The charge in the ferroelectric functional layer 13 of the ferroelectric memory cell connected to bit line BL1 flips, releasing the flipped charge as the first read signal. The charge in the ferroelectric functional layer 13 of the ferroelectric memory cell connected to bit line BL2 does not flip, and no charge is released. Bit line BL1 transmits the first read signal to the multiplexer, and bit line BL2 transmits the second read signal (without released charge) to the multiplexer. The signals are then input to the two input terminals of comparator SA through the multiplexer. The first and second read signals can be compared with each other to determine that the first read signal is "1" and the second read signal is "0".

[0071] Compared to a 1T1C ferroelectric memory, a 2T2C ferroelectric memory can determine that the first read signal is "1" and the second read signal is "0" without the need for a reference voltage Vref. Furthermore, the difference between the first and second read signals is twice the difference between the first and second read signals and the reference voltage Vref, respectively, allowing for a more accurate determination of "1" for the first read signal and "0" for the second read signal. However, compared to a 2T2C ferroelectric memory, the layout area of ​​each memory cell in a 1T1C ferroelectric memory is smaller, about half that of a 2T2C ferroelectric memory.

[0072] Because bit lines need to be floated during the read process, the bit line signal is affected by ambient voltage fluctuations due to coupling, resulting in a reduction in the sense margin. One strong type of disturbance is coupling between adjacent bit lines. For example, the potential of surrounding bit lines during the read of a given bit line depends on the type of information stored. Referring to Figure 7, which exemplarily illustrates a schematic diagram of four bit lines, for bit line BL1, when the surrounding bit lines BL2-BL4 are all at high potentials, the surrounding bit lines BL2-BL4 increase the potential of bit line BL1 (strengthening "1" and weakening "0"). When the surrounding bit lines BL2-BL4 are all at low potentials, the surrounding bit lines BL2-BL4 decrease the potential of bit line BL1 (strengthening "0" and weakening "1"). Furthermore, as device miniaturization progresses, the distance between bit lines is getting closer, thus exacerbating the coupling problem between bit lines.

[0073] To address this, this application provides a ferroelectric memory, which may include multiple word lines, multiple bit lines, and multiple ferroelectric memory cells. Each ferroelectric memory cell is connected to one word line and one bit line from the multiple word lines. Furthermore, each word line connects to multiple ferroelectric memory cells, and any word line connects to multiple cell groups. Each cell group includes two ferroelectric memory cells, each consisting of a first ferroelectric memory cell and a second ferroelectric memory cell arranged sequentially. In any cell group, at least one bit line separates the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. This configuration allows the bit line between the first and second ferroelectric memory cells to act as a shield when reading signals from any cell group, thereby reducing the mutual coupling problem during bit line readout and improving signal readout accuracy.

[0074] Figure 8 illustrates a circuit diagram of a ferroelectric memory according to an embodiment of this application. Referring to Figure 8, the ferroelectric memory provided in this embodiment may include: a substrate and multiple word lines WL1 to WL6, multiple bit lines BL1 to BL8, and multiple ferroelectric memory cells A disposed on the substrate. 11 ~A 67 Among them, ferroelectric memory cell A 11 ~A 18 Connected to word line WL1, ferroelectric memory cell A 22 ~A 28 Connected to word line WL2, ferroelectric memory cell A 31 ~A 37 Connected to word line WL3, ferroelectric memory cell A 41~A 48 Connected to word line WL4, ferroelectric memory cell A 52 ~A 58 Connected to word line WL5, ferroelectric memory cell A 61 ~A 67 Connected to word line WL6. Furthermore, ferroelectric memory cell A 11 ~A 61 Connected to bit line BL1, ferroelectric memory cell A 12 ~A 52 Connected to bit line BL2, ferroelectric memory cell A 23 ~A 63 Connected to bit line BL3, ferroelectric memory cell A 14 ~A 64 Connected to bit line BL4, ferroelectric memory cell A 15 ~A 55 Connected to bit line BL5, ferroelectric memory cell A 26 ~A 66 Connected to bit line BL6, ferroelectric memory cell A 17 ~A 67 Connected to bit line BL7, ferroelectric memory cell A 18 ~A 58 Connect to bit line BL8.

[0075] Figure 9 illustrates a schematic diagram of a cell group composed of ferroelectric storage voltages as shown in Figure 8. Referring to Figures 8 and 9, for ferroelectric storage cell A connected by word line WL1... 11 ~A 18 Ferroelectric memory cell A 11 A 14 A 17 This is the second ferroelectric memory cell, ferroelectric memory cell A. 12 A 15 A 18 Let A be the first ferroelectric memory cell, and let ferroelectric memory cell A be... 12 With ferroelectric memory cell A 14 Forming a unit group Z1, ferroelectric storage unit A 12 The bit line BL2 is connected to the ferroelectric memory cell A 14 Bit lines BL3 are spaced apart from each other on the connected bit lines BL4. Based on this, when reading ferroelectric memory cell A... 12 and A 14 At this time, bit lines BL2 and BL4 are used to transmit signals, while bit line BL3 is not used. Therefore, a fixed potential can be input to bit line BL3 through an external driving circuit, using bit line BL3 as a shield for bit lines BL2 and BL4 to reduce coupling interference between bit lines BL2 and BL4. Also, ferroelectric memory cell A... 15 With ferroelectric memory cell A17 Forming a unit group Z2, ferroelectric storage unit A 15 The bit line BL5 is connected to the ferroelectric memory cell A 17 Bit lines BL6 are spaced apart from each other on the connected bit lines BL7. Based on this, when reading ferroelectric memory cell A... 15 and A 17 At this time, bit lines BL5 and BL7 are used to transmit signals, while bit line BL6 is not used. Therefore, a fixed potential can be input to bit line BL6 through an external driving circuit, using bit line BL6 as the shielding line for bit lines BL5 and BL7 to reduce coupling interference between bit lines BL5 and BL7. Furthermore, cell group Z1 and cell group Z2 are arranged adjacent to each other, and ferroelectric memory cell A... 14 The bit line BL4 is connected to the ferroelectric memory cell A 15 The connected bit lines BL5 are arranged adjacently to increase the density of ferroelectric memory cells.

[0076] For the ferroelectric memory cell A connected by word line WL2 22 ~A 28 Ferroelectric memory cell A 22 A 25 A 28 This is the second ferroelectric memory cell, ferroelectric memory cell A. 23 A 26 Let A be the first ferroelectric memory cell, and let ferroelectric memory cell A be... 23 With ferroelectric memory cell A 25 Comprising unit group Z3, ferroelectric storage unit A 26 With ferroelectric memory cell A 28 Composition unit group Z4.

[0077] For the ferroelectric memory cell A connected by word line WL3 31 ~A 37 Ferroelectric memory cell A 31 A 34 A 37 This is the first ferroelectric memory cell, ferroelectric memory cell A. 33 A 36 This is the second ferroelectric memory cell, and ferroelectric memory cell A 31 With ferroelectric memory cell A 33 Composition unit group Z5, ferroelectric storage unit A 34 With ferroelectric memory cell A 36 Composition unit group Z6.

[0078] For ferroelectric memory cell A connected by word line WL4 41 ~A 48 Ferroelectric memory cell A 41 A 44 A47 This is the second ferroelectric memory cell, ferroelectric memory cell A. 42 A 45 A 48 This is the first ferroelectric memory cell, ferroelectric memory cell A. 42 With ferroelectric memory cell A 44 Composition unit group Z7, ferroelectric storage unit A 45 With ferroelectric memory cell A 47 Form a unit group Z8.

[0079] For the ferroelectric storage unit A connected by word line WL5 52 ~A 58 Ferroelectric memory cell A 52 A 55 A 58 This is the second ferroelectric memory cell, ferroelectric memory cell A. 53 A 56 Let A be the first ferroelectric memory cell, and let ferroelectric memory cell A be... 53 With ferroelectric memory cell A 55 Composition unit group Z9, ferroelectric storage unit A 56 With ferroelectric memory cell A 58 Composition unit group Z 10 .

[0080] For the ferroelectric memory cell A connected by word line WL6 61 ~A 67 Ferroelectric memory cell A 61 A 64 A 67 This is the first ferroelectric memory cell, ferroelectric memory cell A. 63 A 66 This is the second ferroelectric memory cell, and ferroelectric memory cell A 61 With ferroelectric memory cell A 63 Composition unit group Z 10 Ferroelectric memory cell A 64 With ferroelectric memory cell A 66 Composition unit group Z 12 .

[0081] For unit group Z3~Z 12 The implementation of the bit lines connecting the ferroelectric memory cells can be derived from the implementation of the bit lines connecting the ferroelectric memory cells in cell groups Z1 to Z2, and so on. Details will not be elaborated here. Furthermore, Figure 8 only illustrates a portion of the ferroelectric memory cell region in the ferroelectric memory. Therefore, some cell groups of ferroelectric memory cells in Figure 8 are not shown; however, their implementation can also be derived from the implementation of the bit lines connecting the ferroelectric memory cells in cell groups Z1 to Z2, and so on. Details will not be elaborated here.

[0082] It is worth mentioning that, in any cell group, there can be two, three, or more bit lines between the bit lines connecting the first ferroelectric memory cell and the bit lines connecting the second ferroelectric memory cell. Specifically, to increase the density of ferroelectric memory cells and reduce the number of bit lines, there can be one bit line between the bit lines connecting the first ferroelectric memory cell and the bit lines connecting the second ferroelectric memory cell in any cell group.

[0083] To further reduce the number of bit lines used, multiple word lines can include adjacent first word lines and second word lines. The first word line connects to a one-to-one correspondence between the first ferroelectric memory cell and the second word line connects to a second ferroelectric memory cell. Furthermore, the corresponding first and second ferroelectric memory cells are connected to the same bit line, so that the corresponding first and second ferroelectric memory cells share the same bit line. For example, referring to Figure 8, word line WL1 can be used as the first word line, word line WL2 can be used as the second word line, and ferroelectric memory cell A... 12 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 22 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL2, ferroelectric memory cell A 15 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 25 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL5, ferroelectric memory cell A 18 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 28 (i.e., the second ferroelectric memory cells) correspond to each other and are connected to the same bit line BL8.

[0084] Furthermore, word line WL2 can also be used as the first word line, and word line WL3 can also be used as the second word line, ferroelectric memory cell A 23 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 33 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL3, ferroelectric memory cell A 26 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 36 (i.e., the second ferroelectric memory cells) correspond to each other and are connected to the same bit line BL6.

[0085] Word line WL3 can also be used as the first word line, and word line WL4 can also be used as the second word line. Ferroelectric memory cell A 31 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 41 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL1, ferroelectric memory cell A 34 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 44(i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL4, ferroelectric memory cell A 37 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 47 (i.e., the second ferroelectric memory cells) correspond to each other and are connected to the same bit line BL7.

[0086] Word line WL4 can also be used as the first word line, and word line WL5 can also be used as the second word line. Ferroelectric memory cell A 42 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 52 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL2, ferroelectric memory cell A 45 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 55 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL5, ferroelectric memory cell A 48 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 58 (i.e., the second ferroelectric memory cells) correspond to each other and are connected to the same bit line BL8.

[0087] Word line WL5 can also be used as the first word line, and word line WL6 can also be used as the second word line. Ferroelectric memory cell A 53 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 63 (i.e., the second ferroelectric memory cell) corresponds to each other and is connected to the same bit line BL3, ferroelectric memory cell A 56 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A 66 (i.e., the second ferroelectric memory cells) correspond to each other and are connected to the same bit line BL6.

[0088] Referring to Figure 8, each ferroelectric memory cell A 11 ~A 67 This can include a transistor T and a ferroelectric capacitor C. The gate of transistor T is connected to the corresponding word line, the first electrode of transistor T is connected to the corresponding bit line, and the second electrode of transistor T is connected to the first electrode of ferroelectric capacitor C. Exemplarily, the transistor can be a horizontal transport transistor (e.g., a FinFET or Gate all around Field Effect Transistor, GAAFET) or a vertical transport field effect transistor (VTFET). The following explanation uses a FinFET as an example.

[0089] To increase the density of ferroelectric memory cells, word lines, transistor channels, and bit lines can be arranged accordingly. For example, Figure 10 is a layout diagram corresponding to the circuit diagram shown in Figure 8, and Figure 11 is a cross-sectional view along the AA' direction in the layout diagram shown in Figure 10. Referring to Figures 10 and 11, and in conjunction with Figure 8, multiple word lines WL1 to WL6 can extend along the first direction F1 and be spaced apart along the second direction F2, and multiple bit lines BL1 to BL8 can extend along the second direction F2 and be spaced apart along the first direction F1. The first direction F1 and the second direction F2 are perpendicular, thus allowing the word lines and bit lines to be arranged orthogonally. Based on this, the channels ch of the transistors in each ferroelectric memory cell can also be extended along the second direction F2, eliminating the need for additional tilting of the channels for each transistor and reducing process complexity. Furthermore, F3 in Figure 11 represents the vertical direction perpendicular to the substrate 10.

[0090] The ferroelectric capacitor in this embodiment may have a first electrode 11, a second electrode 12, and a ferroelectric functional layer 13 disposed between the first electrode 11 and the second electrode 12. In some embodiments, the ferroelectric capacitor may be a stacked structure as shown in Figures 2a and 2b. In other embodiments, the ferroelectric capacitor may also be a columnar electrode. For example, the second electrode may be a columnar electrode, with the ferroelectric functional layer surrounding the bottom and sidewalls of the second electrode, and the first electrode surrounding the ferroelectric functional layer. Furthermore, the channel typically has a channel region and a first source / drain region and a second source / drain region located on both sides of the channel region. The first source / drain region is connected to the corresponding bit line, and the second source / drain region is connected to the first electrode of the ferroelectric capacitor. The corresponding word line covers the channel across the gate dielectric layer to form the gate. This configuration allows the gate to be formed using the word line, eliminating the need for additional structures and reducing the gate's area. It is understood that the first and second source / drain regions may be heavily doped regions for signal transmission.

[0091] In practical implementation, the first source / drain region can be connected to the corresponding bit line through the first conductive portion. For example, referring to Figures 10 and 11, sd A12 Represents ferroelectric memory cell A 12 The first source / drain region of the T-channel in the middle transistor, sd A22 Represents ferroelectric memory cell A 22 The first source / drain region of the T-channel transistor, the first source / drain region sd A12 (or the first source / drain region sd) A22 ) through the first conductive part CK 1a Connect to bit line BL2, sd A42 Represents ferroelectric memory cell A 42 The first source / drain region of the T-channel in the middle transistor, sd A52 Represents ferroelectric memory cell A52 The first source / drain region of the T-channel transistor, the first source / drain region sd A42 (or the first source / drain region sd) A52 ) through the first conductive part CK 1b Connect to bit line BL2. The rest are similar and can be deduced sequentially, so they will not be elaborated upon here. It is worth mentioning that the material of the first conductive part can be a metallic material, for example, one or more of copper, molybdenum, and ruthenium.

[0092] Furthermore, the second source / drain region can be connected to the first electrode of the corresponding ferroelectric capacitor via the second conductive portion. For example, referring to Figures 10 and 11, sd B12 Represents ferroelectric memory cell A 12 The second source / drain region of the T-channel transistor, the second source / drain region sd B12 Through the second conductive part CK 2a Connected to the first electrode 11 of the corresponding ferroelectric capacitor C. B22 Represents ferroelectric memory cell A 22 The second source / drain region of the T-channel transistor, the second source / drain region sd B22 Through the second conductive part CK 2b Connected to the first electrode 11 of the corresponding ferroelectric capacitor C. B42 Represents ferroelectric memory cell A 42 The second source / drain region of the T-channel transistor, the second source / drain region sd B42 Through the second conductive part CK 2c Connected to the first electrode 11 of the corresponding ferroelectric capacitor C. B52 Represents ferroelectric memory cell A 52 The second source / drain region of the transistor channel, the second source / drain region sd B52 Through the second conductive part CK 2d The first electrode 11 is connected to the corresponding ferroelectric capacitor C. The rest are similar and can be deduced sequentially, so they will not be elaborated further here. It is worth mentioning that the material of the second conductive part can be a metallic material, for example, one or more of copper, molybdenum, and ruthenium.

[0093] In some embodiments of this application, the channels of all transistors connected to the same bit line can be arranged sequentially along the second direction F2, thereby allowing the channels to be tightly packed and reducing the occupied area of ​​the channels. For example, referring to Figures 10 and 11, a ferroelectric memory cell A connected to bit line BL1... 11 Ferroelectric storage unit A 31 Ferroelectric storage unit A 41 and ferroelectric memory unit A 61 Taking transistor T as an example, ferroelectric memory cell A 11 Ferroelectric storage unit A 31 Ferroelectric storage unit A41 and ferroelectric memory unit A 61 The channels ch of the transistors T are arranged sequentially along the second direction F2, and the orthogonal projections of the channels ch of these transistors T onto the substrate 10 and the orthogonal projections of the bit line BL1 onto the substrate 10 all have overlapping regions. The implementation of the channels of the other bit line-connected transistors can be deduced by analogy, and will not be described in detail here.

[0094] To further increase the density of ferroelectric memory cells, when multiple word lines include adjacent first and second word lines, the first source / drain regions of the transistors in corresponding first and second ferroelectric memory cells can be set to the same region. This allows the first source / drain regions of the transistors in corresponding first and second ferroelectric memory cells to be shared, further reducing the channel area occupied. Furthermore, the channels of transistors connected by adjacent bit lines can be staggered. For example, referring to Figures 8, 10, and 11, when word line WL1 is the first word line and word line WL2 is the second word line, the ferroelectric memory cell A... 12 transistor T in A12 ditch A12 First source leak region sd A12 With ferroelectric memory cell A 22 transistor T in A22 ditch A22 First source leak region sd A22 For the same region. When word line WL2 is the first word line and word line WL3 is the second word line, the ferroelectric memory cell A... 23 The first source / drain region of the transistor channel and the ferroelectric memory cell 33 The first source and drain regions of the transistor channel are in the same area. When word line WL3 is used as the first word line and word line WL4 is used as the second word line, the ferroelectric memory cell A... 34 The first source / drain region of the transistor channel and the ferroelectric memory cell A 44 The first source and drain regions of the transistor channel are in the same area. When word line WL4 is used as the first word line and word line WL5 is used as the second word line, the ferroelectric memory cell A... 42 transistor T in A42 ditch A42 First source leak region sd A42 With ferroelectric memory cell A 52 transistor T in A52 ditch A52 First source leak region sd A52 This is the same region. The implementation methods for the first source-drain regions of the transistors connected to the other bit lines can be deduced similarly, and will not be elaborated here.

[0095] Based on this, referring to Figure 10, in this embodiment, by extending the channels of each transistor along the second direction F2 without tilting, and arranging the word lines and bit lines in orthogonal directions, each ferroelectric memory cell requires an average of 1.5 word lines along the bit line extension direction (i.e., the second direction F2), thus requiring at least 3 critical dimensions (CD) for each ferroelectric memory cell. Furthermore, along the word line extension direction (i.e., the first direction F1), each ferroelectric memory cell requires an average of one channel (ch), thus requiring at least 2 CDs for each ferroelectric memory cell. Therefore, the layout area of ​​the ferroelectric memory cell in this embodiment can be 6F. 2 This allows for at least partial shielding of adjacent bit lines during the read phase, while also achieving a higher layout density.

[0096] Referring again to Figures 8, 10, and 11, for the ferroelectric memory cell A connected to bit line BL1 11 Ferroelectric storage unit A 31 Ferroelectric storage unit A 41 and ferroelectric memory unit A 61 The transistors in the memory are connected to ferroelectric capacitors C, which are arranged sequentially along the second direction F2. The orthogonal projections of these ferroelectric capacitors C onto the substrate 10 and the orthogonal projections of the bit line BL1 onto the substrate 10 overlap. Furthermore, the orthogonal projections of these ferroelectric capacitors C onto the substrate 10 and the orthogonal projections of the connected second source / drain regions onto the substrate 10 also overlap. For the ferroelectric memory cell A connected to the bit line BL2... 12 Ferroelectric storage unit A 22 Ferroelectric storage unit A 42 and ferroelectric memory unit A 52 The transistors in the memory are connected to ferroelectric capacitors C, which are arranged sequentially along the second direction F2. The orthogonal projections of these ferroelectric capacitors C onto the substrate 10 and the orthogonal projections of the bit line BL2 onto the substrate 10 overlap. Furthermore, the orthogonal projections of these ferroelectric capacitors C onto the substrate 10 and the orthogonal projections of the connected second source / drain regions onto the substrate 10 also overlap. For the ferroelectric memory cell A connected to the bit line BL3... 23 Ferroelectric storage unit A 33 Ferroelectric storage unit A 53 and ferroelectric memory unit A 63The transistors in the memory cell are connected to ferroelectric capacitors C, which are arranged sequentially along the second direction F2. The orthographic projections of these ferroelectric capacitors C onto the substrate 10 overlap with the orthographic projections of the bit line BL3 onto the substrate 10. Furthermore, the orthographic projections of these ferroelectric capacitors C onto the substrate 10 overlap with the orthographic projections of their connected second source / drain regions onto the substrate 10. The implementation of the remaining ferroelectric capacitors can be deduced similarly and will not be elaborated here. This arrangement allows all ferroelectric capacitors connected to the same bit line to be arranged sequentially along the second direction F2, and also allows the ferroelectric capacitors in each ferroelectric memory cell to be correspondingly arranged with their connected second source / drain regions, thus uniformly arranging the ferroelectric capacitors. Further, to prevent short circuits in the first conductive portion, the orthographic projections of any ferroelectric capacitor onto the substrate and any first conductive portion onto the substrate can be designed to have no overlapping regions.

[0097] [Correction 17.02.2025 based on Rule 91] Referring again to Figures 8, 10, and 11, the ferroelectric memory further includes multiple board lines PL1 to PL5. The layer containing board lines PL1 to PL5 is located between the layer containing word lines WL1 to WL6 and the layer containing bit lines BL1 to BL8. Furthermore, the second electrode 12 of the ferroelectric capacitor C in each ferroelectric memory cell is connected to one of the multiple board lines PL1 to PL5. With this configuration, the board line can be used as the second electrode 12 of the ferroelectric capacitor C to transmit signals.

[0098] [Correction 17.02.2025 based on Rule 91] In some embodiments, the ferroelectric capacitors of the first and second ferroelectric memory cells in any unit group can be connected to the same board line, so that some memory cells share the same board line, reducing the number of board lines. For example, referring to Figures 8, 10, and 11, unit groups Z1, Z2, Z5, and Z... 11 For example, for cell group Z1, ferroelectric memory cell A 12 The second electrode 12 of the ferroelectric capacitor C and the ferroelectric storage cell A 14 The second electrode 12 of the ferroelectric capacitor C is connected to the plate line PL3. For cell group Z2, ferroelectric storage cell A 15 The second electrode 12 of the ferroelectric capacitor C and the ferroelectric storage cell A 17 The second electrode 12 of the ferroelectric capacitor C is connected to the plate line PL4. For cell group Z5, ferroelectric storage cell A 31 The second electrode of the ferroelectric capacitor and the ferroelectric storage cell A 33 The second electrode of the ferroelectric capacitor in the circuit is connected to plate line PL2. For unit group Z 11 Ferroelectric memory cell A 61 The second electrode of the ferroelectric capacitor and the ferroelectric storage cell A 63The second electrode of the ferroelectric capacitor in the circuit is connected to the board line PL1. The connection method of the ferroelectric capacitors in the other unit groups to the board lines can be deduced in the same way, and will not be described in detail here.

[0099] Furthermore, the ferroelectric capacitors C in different cell groups connected to the same word line can be connected to different board lines. This configuration allows different board lines to transmit signals to adjacent cell groups, enabling the ferroelectric memory cells to be read in whole or in part when any word line is selected, thus increasing the flexibility of the read operation. For example, referring to Figures 8, 10, and 11, taking cell groups Z1 and Z2 as examples, the second electrode of the ferroelectric capacitor in cell group Z1 is connected to board line PL3, and the second electrode of the ferroelectric capacitor in cell group Z2 is connected to board line PL4.

[0100] To further reduce the number of board lines, when multiple word lines include adjacent first and second word lines, the multiple unit groups connected by the first word line can be considered as first unit groups, and the multiple unit groups connected by the second word line can be considered as second unit groups. Furthermore, the bit line connected to the first ferroelectric memory cell in the second unit group is located between the bit lines connected to the first and second ferroelectric memory cells in the first unit group. This allows the first unit group connected to different word lines and the ferroelectric capacitors in the second unit group to share the same board line, thereby reducing the number of board lines. For example, referring to Figures 8, 9, and 10, when word line WL1 is the first word line and word line WL2 is the second word line, unit group Z1 can be the first unit group connected to word line WL1, and unit group Z3 can be the second unit group connected to word line WL2. In this case, the board line connected to unit groups Z1 and Z3 is the same board line PL3. When word line WL2 is the first word line and word line WL3 is the second word line, Z3 can be the first unit group connected by word line WL2, and Z6 can be the second unit group connected by word line WL3. In this case, the board lines connected to unit groups Z3 and Z6 are the same board line PL3. When word line WL3 is the first word line and word line WL4 is the second word line, Z6 can be the first unit group connected by word line WL3, and Z8 can be the second unit group connected by word line WL4. In this case, the board lines connected to unit groups Z6 and Z8 are the same board line PL3. When word line WL4 is the first word line and word line WL5 is the second word line, Z8 can be the first unit group connected by word line WL4, and Z... 10 If it can be used as the second unit group connected by word line WL5, then unit groups Z8 and Z 10 The connected board line is the same board line PL3. The rest are similar and can be deduced sequentially, so they will not be elaborated further here. Based on this, in the ferroelectric memory provided in this embodiment, there can be multiple board lines (e.g., PL1 to PL5) that are spaced apart from each other.

[0101] Furthermore, when connecting multiple ferroelectric capacitors, the staggered arrangement of transistor channels allows for ample space for inclined zigzag lines during wiring. For example, referring to Figure 11, based on the staggered arrangement of channels, the ferroelectric capacitors in different ferroelectric memory cells can form a unique stepped arrangement from the upper left to the lower right, thus allowing the board lines (e.g., PL2, PL3) to be set as stepped zigzag lines. Alternatively, based on the stepped arrangement of ferroelectric capacitors, the board lines can also be set as straight lines extending in an inclined direction. In addition, the stepped arrangement of ferroelectric capacitors can also prevent the board lines from blocking the contact holes where the first conductive part is located, and prevent short circuits between the board lines and bit lines.

[0102] The ferroelectric memory of this application embodiment can be used as a ferroelectric memory in a 1T1C array. Furthermore, based on the stepped arrangement of ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be written, increasing the flexibility of the write operation. The writing process of the ferroelectric memory of this application embodiment as a 1T1C ferroelectric memory is described below with reference to an embodiment. Taking word line WL1 as an example, during the writing phase, the potential on word line WL1 is high, and the ferroelectric memory cell A... 11 ~A 18 All transistors T in the circuit are turned on. Furthermore, firstly, the potential on each board line PL1-PL5 is set to a high level, and the potential on bit lines BL1-BL8 (or bit lines BL1, BL2, BL4, BL5, BL7, BL8) is set to a low level, causing the ferroelectric memory cell A to... 11 ~A 18 All ferroelectric capacitors in the circuit are written with "0". Afterwards, the potential on each board line PL1-PL5 is set to low, and the potential on bit lines BL2 and BL5 is set to high, sending a signal to the ferroelectric memory cell A. 12 A 15 The ferroelectric capacitors in the memory are each written with a "1", while the ferroelectric memory cell A... 11 A 14 A 17 A 18 The ferroelectric capacitances in each remain at "0". The rest follow the same principle, and the specifics will not be elaborated here.

[0103] In this embodiment, based on the stepped arrangement of ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be read, increasing the degree of freedom in the read operation. The following describes the read process of the ferroelectric memory in this embodiment as a 1T1C ferroelectric memory, in conjunction with specific examples.

[0104] Example 1

[0105] During the read phase, when a word line is selected, each board line is invoked, and only the bit lines connected to the transistors connected to that word line are invoked. The remaining bit lines are input with a fixed potential as shielding lines to reduce coupling interference between bit lines. Furthermore, based on this process, all ferroelectric memory cells connected to the same word line can be read, realizing the operation of reading all bits corresponding to the same word line.

[0106] For example, referring to Figure 8, taking the selected word line WL1 as an example, and the ferroelectric memory cell A 12 A 15 The ferroelectric capacitors in the memory are each written with a "1", while the ferroelectric memory cell A... 11 A 14 A 17 A 18 The ferroelectric capacitors in the memory are written with "0". During the read phase, word line WL1 is selected, and the potential on word line WL1 is high, indicating that the ferroelectric memory cell A... 11 ~A 18 All transistors T in the circuit are turned on. First, board lines PL1 to PL5 are activated, and the potentials on board lines PL1 to PL5 are all set to high level. Bit lines BL1, BL2, BL4, BL5, BL7, and BL8 are all activated while floating. Bit lines BL3 and BL6 have fixed input potentials. Therefore, bit line BL3 can be used as the shield between bit lines BL2 and BL4, and bit line BL6 can be used as the shield between bit lines BL5 and BL7. Combined with the comparator, the ferroelectric memory cell A can be read through bit line BL1. 11 The "0" stored in the memory can be read from the ferroelectric memory cell A via bit line BL2. 12 The "1" stored in the memory can be read from the ferroelectric memory cell A via bit line BL4. 14 The "0" stored in the memory can be read from the ferroelectric memory cell A via bit line BL5. 15 The "1" stored in the memory can be read from the ferroelectric memory cell A via bit line BL7. 17 The "0" stored in the memory can be read from the ferroelectric memory cell A via bit line BL8. 18 The "0" is stored in the middle. The rest can be deduced in the same way, and the details will not be elaborated here.

[0107] Example 2

[0108] During the read phase, a specific word line can be selected from multiple word lines, and multiple (e.g., multiple) board lines can be invoked. Only the bit lines connected to the transistors of the selected word line and the invoked board lines are invoked, while the remaining bit lines are input with a fixed potential as shielding lines to reduce coupling interference between bit lines. Furthermore, based on this process, ferroelectric memory cells in multiple cell groups connected to the same word line can be read, realizing the operation of reading multiple bits corresponding to the same word line. A detailed description is provided below with reference to specific implementation methods.

[0109] The first implementation: During the read phase, when a word line is selected, the odd-numbered or even-numbered board line is invoked. Only the bit lines connected to the transistors of the selected word line and the invoked board line are invoked. The remaining bit lines are input with a fixed potential as shielding lines. This allows each invoked bit line to have one or more shielding lines, achieving 100% shielding. Furthermore, based on this process, ferroelectric memory cells in the odd-numbered or even-numbered cell groups connected to the same word line can be read, enabling the reading of multiple bits corresponding to the same word line.

[0110] For example, referring to Figure 8, taking the selection of the word line WL1 and the invocation of the even-numbered plate line as an example, and the ferroelectric storage unit A 12 A 15 The ferroelectric capacitors in the memory are each written with a "1", while the ferroelectric memory cell A... 11 A 14 A 17 A 18 The ferroelectric capacitors in the memory are written with "0". During the read phase, word line WL1 is selected, and the potential on word line WL1 is high, indicating that the ferroelectric memory cell A... 11 ~A 18 All transistors T in the circuit are turned on. Board lines PL2 and PL4 are activated, and their potentials are set to high. Board lines PL1, PL3, and PL5 are not activated and are all floating. Bit lines BL1, BL5, and BL7 are activated while still floating, and bit lines BL2, BL3, BL4, BL6, and BL8 are input with fixed potentials to act as shielding lines. Bit lines BL2, BL3, and BL4 can serve as shielding lines between bit lines BL1 and BL5, and bit line BL6 can serve as shielding line between bit lines BL5 and BL7. The functions of the remaining bit lines and their shielding lines can be deduced similarly and will not be elaborated further. Based on this, combined with a comparator, the ferroelectric memory cell A can be read through bit line BL1. 11 The "0" stored in the memory is read out through bit line BL5 to retrieve the ferroelectric memory cell A. 15 The "1" stored in the memory is read out through bit line BL7 to retrieve the ferroelectric memory cell A.17 The "0" is stored in the middle. The rest can be deduced in the same way, and the details will not be elaborated here.

[0111] Understandably, in practical applications, when word line WL1 is selected, the even-numbered board line (e.g., PL2, PL4) can be called first to read the ferroelectric memory cell A. 11 The "0" stored in the middle, ferroelectric memory cell A 15 The "1" stored in the middle, ferroelectric memory cell A 17 The ferroelectric memory cell A is stored in the memory. Then, the odd-numbered board lines (e.g., PL1, PL3, PL5) are called to read the ferroelectric memory cell A. 12 The "1" stored in the middle, ferroelectric memory cell A 14 The "0" stored in the middle, ferroelectric memory cell A 18 The system stores a "0". This setting allows selecting any character line to prioritize the even-numbered line, followed by the odd-numbered line. Furthermore, when selecting character lines one by one, the even-numbered line can always be prioritized before the odd-numbered line. Alternatively, when selecting a specific character line from multiple lines, the even-numbered line can be prioritized before the odd-numbered line.

[0112] Alternatively, when word line WL1 is selected, the odd-numbered board lines (e.g., PL1, PL3, PL5) can be called first to read the ferroelectric memory cell A. 12 The "1" stored in the middle, ferroelectric memory cell A 14 The "0" stored in the middle, ferroelectric memory cell A 18 The ferroelectric memory cell A is stored in the memory. Then, the even-numbered board line (e.g., PL2, PL4) is called to read the ferroelectric memory cell A. 11 The "0" stored in the middle, ferroelectric memory cell A 15 The "1" stored in the middle, ferroelectric memory cell A 17 The system stores a "0". This setting allows you to select any character line, first calling the odd-numbered line, then the even-numbered line. Furthermore, when selecting character lines one by one, you can always call the odd-numbered line first, then the even-numbered line. Alternatively, when selecting a specific character line from multiple lines, you can call the odd-numbered line first, then the even-numbered line.

[0113] Alternatively, when any character line is selected, only the even-numbered line can be invoked. Furthermore, when selecting character lines one by one, only the even-numbered line can be invoked. Or, when selecting a specific character line from multiple character lines, only the even-numbered line can be invoked.

[0114] Alternatively, when any character line is selected, only the odd-numbered line can be invoked. Furthermore, when selecting character lines one by one, the odd-numbered line can be invoked for each selection. Or, when selecting a specific character line from multiple character lines, only the odd-numbered line can be invoked.

[0115] Alternatively, you can select the odd-numbered line when selecting each line individually, and then select the even-numbered line when selecting each line individually again. Or, you can select the even-numbered line when selecting each line individually, and then select the odd-numbered line when selecting each line individually again.

[0116] The second implementation: During the read phase, when a word line is selected, a specific portion of the board lines (e.g., multiple board lines) from multiple board lines are invoked. This portion of board lines can be 2, 3, 4, or more board lines. For example, this portion of board lines may be adjacent, or it may include some adjacent board lines and some non-adjacent board lines. Based on this process, ferroelectric memory cells in multiple cell groups connected by the same word line can be read, realizing the operation of reading multiple bits corresponding to the same word line.

[0117] For example, referring to Figure 8, taking the selected word line WL1 and the call board lines PL2, PL3, and PL4 as examples, and the ferroelectric storage unit A 12 A 15 The ferroelectric capacitors in the memory are each written with a "1", while the ferroelectric memory cell A... 11 A 14 A 17 A 18 The ferroelectric capacitors in the memory are written with "0". During the read phase, word line WL1 is selected, and the potential on word line WL1 is high, indicating that the ferroelectric memory cell A... 11 ~A 18 All transistors T in the circuit are turned on. Board lines PL2, PL3, and PL4 are activated, and their potentials are all set to high level. Board lines PL1 and PL5 are not activated and are both floating. Furthermore, bit lines BL1, BL2, BL4, BL5, and BL7 are activated while still floating, and bit lines BL3, BL6, and BL8 are input with fixed potentials as shielding lines. Based on this, combined with a comparator, the ferroelectric memory cell A can be read through bit line BL1. 11 The "0" stored in the memory is read out through bit line BL2 to retrieve the ferroelectric memory cell A. 12 The "1" stored in the memory is read out through bit line BL4 to retrieve the ferroelectric memory cell A. 14 The "0" stored in the memory is read out through bit line BL5 to retrieve the ferroelectric memory cell A. 15 The "1" stored in the memory is read out through bit line BL7 to retrieve the ferroelectric memory cell A. 17The "0" is stored in the middle. The rest can be deduced in the same way, and the details will not be elaborated here.

[0118] Example 3

[0119] During the read phase, a specific word line can be selected from multiple word lines, and a board line can be invoked to read two ferroelectric memory cells in a cell group, thus realizing the operation of reading at least 2 bits corresponding to the same word line. For example, referring to Figure 8, taking the selection of word line WL1 and the invocation of board line PL4 as an example, and ferroelectric memory cell A... 12 A 15 The ferroelectric capacitors in the memory are each written with a "1", while the ferroelectric memory cell A... 11 A 14 A 17 A 18 The ferroelectric capacitors in the memory are written with "0". During the read phase, word line WL1 is selected, and the potential on word line WL1 is high, indicating that the ferroelectric memory cell A... 11 ~A 18 All transistors T in the circuit are turned on. Board line PL3 is activated, and its potential is set to high. Board lines PL1, PL2, PL4, and PL5 are not activated and are all floating. Furthermore, bit lines BL2 and BL4 are activated while still floating, and bit lines BL1, BL3, BL5, BL6, BL7, and BL8 are input with fixed potentials as shielding lines. Based on this, combined with a comparator, the ferroelectric memory cell A can be read through bit line BL2. 12 The "1" stored in the memory is read out through bit line BL4 to retrieve the ferroelectric memory cell A. 14 The "0" is stored in the middle. The rest can be deduced in the same way, and the details will not be elaborated here.

[0120] Example 4

[0121] During the read phase, a specific subset of word lines (e.g., multiple word lines) can be selected from multiple word lines, and a specific subset of board lines (e.g., multiple board lines) can be invoked. This subset of word lines can consist of 2, 3, 4, or more word lines, and the subset of board lines can also consist of 2, 3, 4, or more board lines. Based on this process, ferroelectric memory cells in multiple cell groups connected by multiple word lines can be read, realizing the operation of reading multiple bits corresponding to multiple word lines. It is worth noting that only one ferroelectric memory cell can access a single bit line at a time; therefore, different ferroelectric memory cells connected to the same bit line cannot simultaneously occupy that bit line in a single read operation.

[0122] Besides 1T1C, the ferroelectric memory in this embodiment can also be used as a ferroelectric memory in a 2T2C array. As mentioned above, when accessing a 2T2C array, two 1T1C cells are combined into one storage cell, and the information stored in them is opposite. Since in this embodiment, at least two 1T1C ferroelectric memory cells can be read at a time, each cell group can exactly form a 2T2C memory cell, and the bit lines around the formed 2T2C memory cell are set as uncalled bit lines for use as shielding lines. For example, during the read phase, when a word line is selected, the odd-numbered or even-numbered board line is called, and only the bit lines connected to the transistors connected to the selected word line and the called board line are called. The remaining bit lines are input with a fixed potential as shielding lines, so that one or more shielding lines can be set between each called bit line to achieve 100% shielding effect. Furthermore, based on this process, ferroelectric memory cells in the odd-numbered or even-numbered cell groups connected by the same word line can be read, realizing the operation of reading multiple bits corresponding to the same word line. For example, referring to Figure 8, taking the selection of word line WL1 and the calling of the even-numbered plate line as an example, and ferroelectric memory cell A... 12 A 15 A 18 The ferroelectric capacitors in the memory are each written with a "1", while the ferroelectric memory cell A... 11 A 14 A 17 The ferroelectric capacitors in the memory are written with "0". During the read phase, word line WL1 is selected, and the potential on word line WL1 is high, indicating that the ferroelectric memory cell A... 11 ~A 18 All transistors T in the circuit are turned on. Board lines PL2 and PL4 are activated, and their potentials are set to high. Board lines PL1, PL3, and PL5 are not activated and are all floating. Bit lines BL1, BL5, and BL7 are activated while still floating, and bit lines BL2, BL3, BL4, BL6, and BL8 are input with fixed potentials to act as shielding lines. Bit lines BL2, BL3, and BL4 can serve as shielding lines between bit lines BL1 and BL5, and bit line BL6 can serve as shielding line between bit lines BL5 and BL7. The functions of the remaining bit lines and their shielding lines can be deduced similarly and will not be elaborated further. Based on this, combined with a comparator, the ferroelectric memory cell A can be read through bit lines BL5 and BL7. 15 The stored "1" or the ferroelectric memory cell A can be read. 17 The "0" is stored in the middle. The rest can be deduced in the same way, and the details will not be elaborated here.

[0123] Therefore, when the ferroelectric memory of this embodiment is used as a ferroelectric memory in a 2T2C array, the smallest read unit is 1 bit (i.e., a 2T2C memory cell). Furthermore, not only can there be shielding lines between bit lines of different 2T2C memory cells, but shielding lines are also provided between two bit lines within the same 2T2C memory cell, thereby reducing coupling interference to nearly 100%. Also, when the ferroelectric memory of this embodiment is used as a ferroelectric memory in a 2T2C array, the layout area of ​​the 2T2C memory cell is 2*6F. 2 This design, without reducing storage density, can improve the mutual coupling problem when reading signals from bit lines and increase the accuracy of signal reading compared to the existing 2T2C storage cell scheme.

[0124] It is worth mentioning that, in the ferroelectric memory of this application embodiment, by introducing the function of reading specific cell groups, the number of times the ferroelectric memory can be used and its lifespan can be increased, and power consumption can also be reduced.

[0125] Figure 12 exemplarily illustrates a circuit diagram of another ferroelectric memory according to an embodiment of this application. Figure 13 exemplarily illustrates a layout structure diagram corresponding to the circuit diagram shown in Figure 12. Figure 14 exemplarily illustrates a cross-sectional view along the AA' direction in the layout structure diagram shown in Figure 13. The ferroelectric memory in this embodiment is a modification of the ferroelectric memory in the embodiment shown in Figure 8 above. The similarities are not repeated here, but the difference lies in the connection method of the board wires. A detailed description is provided below with reference to the accompanying drawings and examples.

[0126] Referring to Figures 9 and 12, taking board lines PL1 to PL9 as an example, for cell group Z1, ferroelectric storage cell A 12 The second electrode of the ferroelectric capacitor C in (i.e., the first ferroelectric memory cell) is connected to the board line PL5. Ferroelectric memory cell A 14 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the plate line PL6. For cell group Z2, ferroelectric memory cell A 15 The second electrode of the ferroelectric capacitor C in (i.e., the first ferroelectric memory cell) is connected to the board line PL7. Ferroelectric memory cell A 17 The second electrode of the ferroelectric capacitor C in the second ferroelectric memory cell is connected to board line PL8. The rest can be deduced similarly, and will not be elaborated further here. With this configuration, for any given cell group, the ferroelectric capacitors in the first and second ferroelectric memory cells within the same cell group can be connected to different board lines, allowing the first and second ferroelectric memory cells in the same cell group to transmit signals using different board lines.

[0127] Furthermore, the ferroelectric capacitors in the first and second ferroelectric memory cells connected to the same word line are connected to different board lines, so that these ferroelectric memory cells do not share board lines, further improving the freedom of data reading. For example, referring to Figures 12 to 14, ferroelectric memory cell A... 11 ~A 18 For example, ferroelectric memory cell A 11 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the board line PL4. Ferroelectric memory cell A 12 The second electrode of the ferroelectric capacitor C in (i.e., the first ferroelectric memory cell) is connected to the board line PL5. Ferroelectric memory cell A 14 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the board line PL6. Ferroelectric memory cell A 15 The second electrode of the ferroelectric capacitor C in (i.e., the first ferroelectric memory cell) is connected to the board line PL7. Ferroelectric memory cell A 17 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the board line PL8. Ferroelectric memory cell A 18 The second electrode of the ferroelectric capacitor C in the first ferroelectric storage unit is connected to the board line PL9.

[0128] To reduce the number of board lines, when multiple word lines include adjacent first and second word lines, multiple cell groups connected by the first word line can be included as first cell groups, and multiple cell groups connected by the second word line can be included as second cell groups. Furthermore, the bit line connected to the first ferroelectric memory cell in the second cell group is located between the bit lines connecting the first and second ferroelectric memory cells in the first cell group. This allows the ferroelectric capacitors in the first ferroelectric memory cells in the first cell group and the first ferroelectric memory cells in the second cell group to be connected to the same board line, thereby reducing the number of board lines. For example, referring to Figures 9, 12, and 13, when word line WL1 is the first word line and word line WL2 is the second word line, cell group Z1 can be the first cell group connected by word line WL1, and cell group Z3 can be the second cell group connected by word line WL2. Then, the ferroelectric memory cell A in cell group Z1... 12 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A in cell group Z3 23 The board line connected to the first ferroelectric memory cell is the same board line PL5. When word line WL2 is the first word line and word line WL3 is the second word line, Z3 can be the first unit group connected by word line WL2, and Z6 can be the second unit group connected by word line WL3. Then, the ferroelectric memory cell A in unit group Z3... 23 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A in cell group Z6 34The board line connected to the first ferroelectric memory cell is the same board line PL5. When word line WL3 is the first word line and word line WL4 is the second word line, Z6 can be the first unit group connected by word line WL3, and Z8 can be the second unit group connected by word line WL4. Then, the ferroelectric memory cell A in unit group Z6... 34 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A in cell group Z8 45 The board line connected to the first ferroelectric memory unit (i.e., the first ferroelectric memory unit) is the same board line PL5. When word line WL4 is the first word line and word line WL5 is the second word line, Z8 can be used as the first unit group connected to word line WL4. 10 If it can be used as the second unit group connected by word line WL5, then the ferroelectric storage unit A in unit group Z8 45 (i.e., the first ferroelectric memory cell) and cell group Z 10 Ferroelectric memory cell A in 56 The board line connected to the first ferroelectric memory cell is the same board line PL5. The others are similar and can be deduced sequentially, so they will not be elaborated further here. Based on this, in the ferroelectric memory provided in this embodiment, there can be multiple board lines (e.g., PL1 to PL5) that are spaced apart from each other.

[0129] Furthermore, when connecting multiple ferroelectric capacitors, the staggered arrangement of the transistor channels allows for ample space for the board lines to be routed along a sloping straight line. For example, referring to Figure 13, based on the staggered arrangement of the channels, the ferroelectric capacitors in different ferroelectric memory cells can form unique straight lines extending in a sloping direction (this sloping direction intersects both the first direction F1 and the second direction F2) from the upper left to the lower right. In addition, the stepped arrangement of the ferroelectric capacitors can also prevent the board lines from blocking the contact holes where the first conductive part is located, and prevent short circuits between the board lines and the bit lines.

[0130] The ferroelectric memory of this embodiment can be used as a 1T1C array or a 2T2C array. Furthermore, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be written, increasing the flexibility of the write operation. The write phase process in this embodiment can be referred to the process in the above embodiments, and will not be elaborated here.

[0131] Furthermore, based on the stepped arrangement of ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be read, increasing the degree of freedom in the read operation. The process of the read phase in this embodiment can be referred to the process in the above embodiments, and will not be elaborated here.

[0132] Figure 15 exemplarily illustrates a circuit diagram of another ferroelectric memory according to an embodiment of this application, and Figure 16 exemplarily illustrates a layout structure diagram corresponding to the circuit diagram shown in Figure 15. The ferroelectric memory in this embodiment is a modification of the ferroelectric memory in the embodiment shown in Figure 12 above. The similarities are not repeated here, but the difference lies in the connection relationship of the board lines. Specifically, multiple board lines are divided into multiple board line groups, wherein each board line group includes two adjacent board lines. Furthermore, the two board lines in each board line group are electrically connected to each other, and the board lines in different board line groups are insulated from each other. Exemplarily, the two board lines in each board line group can be electrically connected to each other through connecting lines. For example, referring to Figures 15 and 16, board lines PL2 and PL3 are divided into a board line group, and board lines PL2 and PL3 are electrically connected to each other through one or more connecting lines XL. Board lines PL4 and PL5 are divided into a board line group, and board lines PL4 and PL5 are electrically connected to each other through one or more connecting lines XL. Board wires PL6 and PL7 are grouped into one board wire group, and board wires PL6 and PL7 are electrically connected to each other through one or more connecting wires XL. Board wires PL8 and PL9 are grouped into one board wire group, and board wires PL8 and PL9 are electrically connected to each other through one or more connecting wires XL.

[0133] Furthermore, referring to Figure 16, the stepped arrangement of ferroelectric capacitors and the staggered arrangement of transistor channels allow for sufficient space to be reserved for wiring. Moreover, the stepped arrangement of ferroelectric capacitors also prevents wiring from obstructing the contact holes where the first conductive part is located, thus avoiding short circuits between board lines and bit lines.

[0134] The ferroelectric memory of this embodiment can be used as a 1T1C array or a 2T2C array. Furthermore, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be written, increasing the flexibility of the write operation. The write phase process in this embodiment can be referred to the process in the above embodiments, and will not be elaborated here.

[0135] Furthermore, based on the stepped arrangement of ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be read, increasing the degree of freedom in the read operation. The process of the read phase in this embodiment can be referred to the process in the above embodiments, and will not be elaborated here.

[0136] Figure 17 exemplarily illustrates a circuit diagram of another ferroelectric memory according to an embodiment of this application, and Figure 18 exemplarily illustrates a layout structure diagram corresponding to the circuit diagram shown in Figure 17. The ferroelectric memory in this embodiment is a modification of the ferroelectric memory in the embodiment shown in Figure 8 above. The similarities are not repeated here, but the difference lies in the connection relationship of the board lines. Specifically, the ferroelectric capacitors in the ferroelectric memory cells corresponding to the same word line can be connected to the same board line, while the ferroelectric capacitors in the ferroelectric memory cells corresponding to different word lines are connected to different board lines. For example, referring to Figures 17 and 18, ferroelectric memory cell A... 11 ~A 18 The second electrode of the ferroelectric capacitor is connected to the plate line PL1, and the ferroelectric storage unit A is... 22 ~A 28 The second electrode of the ferroelectric capacitor is connected to plate line PL2, and the ferroelectric storage unit A is... 31 ~A 37 The second electrode of the ferroelectric capacitor is connected to plate line PL3, and the ferroelectric storage unit A is... 41 ~A 48 The second electrode of the ferroelectric capacitor is connected to plate line PL4, and the ferroelectric storage unit A is... 52 ~A 58 The second electrode of the ferroelectric capacitor is connected to plate line PL5, and the ferroelectric storage cell A is... 61 ~A 67 The second electrode of the ferroelectric capacitor is connected to plate line PL6, and plate lines PL1 to PL6 can be arranged alternately along the second direction F2.

[0137] Furthermore, referring to Figure 17, based on the stepped arrangement of ferroelectric capacitors and the staggered arrangement of transistor channels, sufficient space can be reserved for board wiring, so that the board lines extend in a zigzag pattern along the first direction F1. Moreover, the stepped arrangement of ferroelectric capacitors also avoids the board lines obstructing the contact holes where the first conductive part is located, and prevents short circuits between the board lines and bit lines.

[0138] The ferroelectric memory of this embodiment can be used as a 1T1C array or a 2T2C array. Furthermore, based on the stepped arrangement of the ferroelectric capacitors, all ferroelectric memory cells can be written when any word line is selected. The writing process in this embodiment can be referred to the process in the above embodiments, and will not be elaborated here.

[0139] Furthermore, based on the stepped arrangement of ferroelectric capacitors, all ferroelectric memory cells can be read when any word line is selected. The reading process in this embodiment can be referred to the process in the above embodiments, and will not be elaborated upon here.

[0140] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A ferroelectric memory, characterized in that, include: Multiple word lines, multiple bit lines, and multiple ferroelectric memory cells, each of the multiple ferroelectric memory cells being connected to one word line and one bit line among the multiple word lines; The plurality of ferroelectric memory cells connected by any word line include alternating first ferroelectric memory cells and second ferroelectric memory cells. A first ferroelectric memory cell and a second ferroelectric memory cell connected by the same word line form a cell group. In any cell group, there is at least one bit line between the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. In two adjacent cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group.

2. The ferroelectric memory as described in claim 1, characterized in that, In any of the unit groups, there is a bit line between the bit line connected to the first ferroelectric memory unit and the bit line connected to the second ferroelectric memory unit.

3. The ferroelectric memory as described in claim 2, characterized in that, The multiple word lines include adjacent first word lines and second word lines. The first ferroelectric memory cells connected by the first word line correspond one-to-one with the second ferroelectric memory cells connected by the second word line. The corresponding first ferroelectric memory cells and second ferroelectric memory cells are connected to the same bit line.

4. The ferroelectric memory as described in any one of claims 1-3, characterized in that, Each of the ferroelectric memory cells includes a transistor and a ferroelectric capacitor, wherein the gate of the transistor is connected to the corresponding word line, the first terminal of the transistor is connected to the corresponding bit line, and the second terminal of the transistor is connected to the ferroelectric capacitor; The plurality of word lines extend along a first direction and are spaced apart along a second direction, the plurality of bit lines extend along the second direction and are spaced apart along the first direction, and the channel of the transistor in each ferroelectric memory cell extends along the second direction.

5. The ferroelectric memory as described in claim 4, characterized in that, The channels of transistors connected to the same bit line are arranged sequentially along the second direction; or, The ferroelectric capacitors connected to the transistors on the same bit line are arranged sequentially along the second direction.

6. The ferroelectric memory as described in claim 5, characterized in that, The channel of the transistor includes a first source-drain region and a second source-drain region, the first source-drain region being connected to a corresponding bit line, and the second source-drain region being connected to the first electrode of the ferroelectric capacitor. The multiple word lines include adjacent first word lines and second word lines. The first ferroelectric memory cell connected by the first word line corresponds to the second ferroelectric memory cell connected by the second word line. The first source-drain regions of the transistors in the corresponding first ferroelectric memory cells and second ferroelectric memory cells are in the same region.

7. The ferroelectric memory as described in any one of claims 4-6, characterized in that, The multiple word lines, the multiple bit lines, and the multiple ferroelectric memory cells are disposed on the substrate, and the orthographic projection of any of the ferroelectric capacitors on the substrate and the second source / drain region connected to any of the ferroelectric capacitors on the orthographic projection of the substrate have an overlapping region.

8. The ferroelectric memory as described in any one of claims 4-7, characterized in that, It also includes multiple plate lines, with the second electrode of the ferroelectric capacitor in each of the ferroelectric memory cells connected to one of the multiple plate lines.

9. The ferroelectric memory as described in claim 8, characterized in that, In any of the unit groups, the ferroelectric capacitors in the first ferroelectric storage unit and the second ferroelectric storage unit are connected to the same board line.

10. The ferroelectric memory as described in claim 9, characterized in that, Ferroelectric capacitors in different unit groups connected to the same word line are connected to different board lines.

11. The ferroelectric memory according to any one of claims 8-10, characterized in that, The multiple word lines include adjacent first word lines and second word lines. The multiple unit groups connected by the first word lines include a first unit group. The multiple unit groups connected by the second word lines include a second unit group. The bit line connected to the first ferroelectric memory cell in the second unit group is located between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first unit group. The ferroelectric capacitors in the first unit group and the second unit group are connected to the same board line.

12. The ferroelectric memory as described in any one of claims 8-11, characterized in that, Each of the aforementioned plate lines is a stepped, zigzag line.

13. The ferroelectric memory as described in claim 8, characterized in that, In any of the unit groups, the ferroelectric capacitors in the first ferroelectric storage unit and the second ferroelectric storage unit are connected to different board lines.

14. The ferroelectric memory as described in claim 13, characterized in that, The ferroelectric capacitors in the first and second ferroelectric memory cells, which are connected to the same word line, are connected to different board lines.

15. The ferroelectric memory as described in claim 14, characterized in that, The multiple word lines include adjacent first word lines and second word lines. The multiple unit groups connected by the first word lines include a first unit group. The multiple unit groups connected by the second word lines include a second unit group. The bit line connected to the first ferroelectric memory cell in the second unit group is located between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first unit group. The ferroelectric capacitor in the first ferroelectric memory cell in the first unit group and the first ferroelectric memory cell in the second unit group are connected to the same board line.

16. The ferroelectric memory as described in claim 15, characterized in that, Each of the plate lines is a straight line extending in a direction that intersects both the first and second directions.

17. The ferroelectric memory as described in claim 15 or 16, characterized in that, The plurality of board wires includes a plurality of board wire groups, each board wire group includes two adjacent board wires, and the two board wires in each board wire group are electrically connected to each other.

18. The ferroelectric memory as described in claim 8, characterized in that, Ferroelectric capacitors in ferroelectric memory cells corresponding to the same word line are connected to the same board line, while ferroelectric capacitors in ferroelectric memory cells corresponding to different word lines are connected to different board lines.

19. The ferroelectric memory as described in claim 18, characterized in that, Each of the aforementioned plate lines is a broken line extending along a first direction.

20. An electronic device, characterized in that, include: The circuit board and the ferroelectric memory as described in any one of claims 1-19, wherein the ferroelectric memory is disposed on the circuit board.

21. A method for reading a ferroelectric memory, characterized in that, The ferroelectric memory includes: multiple word lines, multiple bit lines, and multiple ferroelectric memory cells. Each of the multiple ferroelectric memory cells is connected to one word line and one bit line among the multiple word lines. Any word line connecting multiple ferroelectric memory cells includes alternating first and second ferroelectric memory cells. A first ferroelectric memory cell and a second ferroelectric memory cell connected to the same word line form a cell group. In any cell group, at least one bit line separates the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. In two adjacent cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group. The method includes: Select any one of the multiple word lines, control at least a portion of the bit lines connected to the ferroelectric memory cells to be in a floating state, and control the unconnected bit lines of the ferroelectric memory cells to input a fixed potential.

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