Storage chip, storage system, and electronic device

Abstract

A storage chip, a storage system, and an electronic device. The storage chip comprises a control circuit and N storage arrays, each storage array comprises a first area and a second area, and a storage unit in the first area and a storage unit in the second area have different failure rates. The control circuit acquires first addresses on the basis of an operation request, and when the first addresses are addresses of the storage units in the first areas, converts the first addresses of M storage units in M storage arrays among the N storage arrays to second addresses, wherein the second addresses correspond to the second storage units in the second areas in the M storage arrays. M second storage units in the M storage arrays are determined on the basis of the second addresses, and an operation is performed on the second storage units. The read-write performance of the storage chip can be improved.

Description

Storage chip, storage system and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410681265.6, filed on May 28, 2024, and entitled "Storage chip, storage system and electronic device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of storage, in particular to a storage chip, a storage system and an electronic device. BACKGROUND

[0003] With the development of storage technology, the number of storage arrays included in the internal arrangement of the storage chip is increasing, and the storage performance of the storage chip is also increasing.

[0004] The storage chip is externally connected with a storage controller, and the storage controller can send a read-write instruction to the storage chip. After receiving the read-write instruction, the storage chip can select the storage unit in each storage array according to the address of the storage unit carried in the read-write instruction, and then apply a read-write voltage to each selected storage unit through the driving circuit corresponding to each storage array, thereby realizing the read-write operation of the storage unit.

[0005] Since the distances between each storage unit in the storage array and the driving circuit are different, in the case that the driving circuit applies the same read-write voltage, the voltage of the storage unit reaching the relatively far area of the storage array becomes smaller due to the voltage division effect of the line in the storage chip, which may not be able to enable the storage unit, i.e., the storage unit is invalid, thereby causing the read-write operation to fail, i.e., the invalid rate is high. For a storage chip including multiple storage arrays, each time a read-write operation is performed, the storage units with the same row and column addresses in each storage array are enabled, i.e., the distances between these storage units and the driving circuit are the same, and therefore, for the storage units corresponding to the read-write operation, they are the storage units in the storage array that are relatively far away. Due to the high invalid rate, the probability that the number of invalid storage units in the read-write operation exceeds the threshold value that can be repaired increases, thereby affecting the performance of the storage chip. SUMMARY

[0006] The present application provides a storage chip, a storage system and an electronic device, which can improve the read-write performance of the storage chip, and the corresponding technical solutions are as follows:

[0007] In a first aspect, a memory chip is provided, which includes a control circuit and N memory arrays. In the N memory arrays of the memory chip, the memory cells of each memory array are arranged in rows and columns, and each memory array has the same number of rows and the same number of columns. Each memory array includes a first region and a second region according to different row addresses and column addresses, and the memory cells in the first region and the second region have different failure rates.

[0008] The control circuit of the memory chip is configured to: obtain a first address, which is an address of N first memory cells that need to perform an operation corresponding to an operation request according to the operation request, including the row addresses and column addresses of the N first memory cells in the N memory arrays. When the first address is an address of a memory cell in the first region, the control circuit converts the first address of M memory cells in M memory arrays of the N memory arrays into a second address corresponding to a second memory cell in the second region of the M memory arrays, where M is less than N. The control circuit determines M second memory cells in the M memory arrays according to the converted second address, and performs the operation on the M second memory cells.

[0009] The memory cells in the first region and the memory cells in the second region have different failure rates, which can be different failure characteristics of the memory cells in the first region and the memory cells in the second region. The difference in the failure characteristics can be determined by the distance between the memory cells in the memory array and the driving circuit corresponding to the memory array. For example, the distance between the memory cells in the first region and the driving circuit is greater than the distance between the memory cells in the second region and the driving circuit, or the distance between the memory cells in the first region and the driving circuit is less than the distance between the memory cells in the second region and the driving circuit.

[0010] In the scheme provided in the present application, the control circuit can convert the first address corresponding to the first region into a second address corresponding to the second region after receiving an operation request for performing an operation on the first address, and determine the second memory cell corresponding to the second address in part of the memory array. In this way, when performing an operation on the memory cells in the plurality of memory arrays according to the operation request, the operation is performed on part of the memory cells in the first region and part of the memory cells in the second region. Since the failure characteristics of the memory cells in the first region and the memory cells in the second region are different, the failure rates of the memory cells corresponding to the operation are not in a high state at the same time. Therefore, when performing read and write operations on the memory cells, the read and write operations will not fail due to the high failure rates of the memory cells corresponding to the operation, thereby improving the read and write performance of the memory chip.

[0011] In an implementable manner, the X storage units in the X storage arrays in the N storage arrays are determined according to the first address, where M+X is less than or equal to N. In this way, the first storage unit in the first region and the second storage unit in the second region can be determined in different storage arrays, and by selecting the first storage unit and the second storage unit, it is possible to avoid simultaneously performing operations on storage units with high failure rates, and to reduce the probability of read / write failure.

[0012] In an implementable manner, each storage array further includes a third region, and the storage units in the third region have different failure rates from the storage units in the first region and the second region. For example, the distance between the storage units in the third region and the driving circuit is different from the distance between the storage units in the first region and the driving circuit and the distance between the storage units in the second region and the driving circuit.

[0013] The control circuit is further configured to: when the first address is an address of a storage unit in the first region, convert the first address of the Y storage units in the Y storage arrays in the N storage arrays into a third address, the third address corresponding to a third storage unit in a third region in the Y storage arrays, and determine the Y storage units in the Y storage arrays in the N storage arrays according to the third address, where M+X+Y is less than or equal to N.

[0014] In the scheme provided in the present application, the storage array can also be divided into a third region, and the control circuit can convert the first address into a second address corresponding to the second region and a third address after receiving an operation request for performing an operation on the first address corresponding to the first region. In this way, the first storage unit corresponding to the first address can be determined in the first region of part of the storage arrays, the second storage unit corresponding to the second address can be determined in the second region of part of the storage arrays, and the third storage unit corresponding to the third address can be determined in the third region of part of the storage arrays. In this way, when performing an operation on the storage units in the multiple storage arrays according to the operation request, the operation is performed not only on the first storage unit located in the first region, but also on the second storage unit located in the second region, and on the third storage unit located in the third region. Since the failure characteristics of the storage units in the first region, the second region and the third region are different, the failure rates of the storage units corresponding to the operation are not simultaneously in a high state. In this way, when performing a read operation on the storage units, the probability of read error can be reduced, and the problem of read / write failure due to the high failure rates of the storage units corresponding to the read operation can be avoided.

[0015] In an example, the control circuit includes a row address determination unit, a row address conversion unit, a column address determination unit, and a column address conversion unit, and the M storage arrays correspond to one row address conversion unit and one column address conversion unit.

[0016] The row address conversion unit corresponding to the M storage arrays is configured to convert the first row address included in the first address into a second row address included in the second address, and the column address conversion unit corresponding to the M storage arrays is configured to convert the first column address included in the first address into a second column address included in the second address. The row address determination unit corresponding to each of the M storage arrays is configured to determine the row in which the second storage unit is located according to the second row address, and the column address determination unit corresponding to each of the M storage arrays is configured to determine the column in which the second storage unit is located according to the second column address.

[0017] In the scheme provided in the application, by adding the row address conversion unit and the column address conversion unit, the first address can be converted into the second address by the row address conversion unit and the column address conversion unit corresponding to part of the storage arrays before the first storage unit of each storage array is operated according to the first address. Thus, when the storage unit is operated, the first storage unit in the first region in part of the storage arrays can be selected according to the first address, and the second storage unit in the second region in part of the storage arrays can be selected according to the second address.

[0018] In an implementable manner, the storage chip further includes a bypass circuit, which is configured to: in response to receiving an address conversion instruction, turn on a first path and a second path corresponding to the row address conversion unit, and a third path and a fourth path corresponding to the column address conversion unit, wherein the row address conversion unit obtains the first row address through the first path and sends the second row address to the row address determination unit through the second path, and the column address conversion unit obtains the first column address through the third path and sends the second column address to the column address determination unit through the fourth path.

[0019] In the scheme provided in the application, by setting the bypass circuit, it can be determined whether the first address is converted into the address corresponding to the different regions by the row address conversion unit and the column address conversion unit. Thus, according to the wear state of the storage unit in the storage chip and the like, it can be determined whether the operation is performed on the storage unit in the different regions, so as to reduce the probability of data error in the storage unit, and further improve the flexibility of performing the operation on the storage chip.

[0020] In an implementable manner, the control circuit includes the row address determination unit and the column address determination unit corresponding to each of the M storage arrays. The row address determination unit corresponding to each of the M storage arrays is configured to convert the first row address included in the first address into a second row address included in the second address, and determine the row in which the second storage unit is located according to the second row address. The column address determination unit corresponding to each of the M storage arrays is configured to convert the first column address included in the first address into a second column address included in the second address, and determine the column in which the second storage unit is located according to the second column address.

[0021] In the scheme provided in the application, the first address is converted into the second address by the row address determination unit and the column address determination unit of the partial storage array, and the second storage unit in the second region is determined according to the second address. In this way, the selected storage units in different regions can be reduced without increasing hardware, and the probability of data error in the storage unit can be reduced.

[0022] In an implementable manner, the storage chip further includes a driving circuit corresponding to each storage array, and in each storage array, the distance between the first storage unit in the first region and the driving circuit is different from the distance between the second storage unit in the second region and the driving circuit. In this way, when the write operation is performed on the storage units corresponding to the first address and the second address, the write voltage applied to the storage units will not be too large or too small. Furthermore, when the read operation is performed on the storage units corresponding to the first address and the second address, the storage units with low threshold voltage and high failure rate that are refreshed will not be selected at the same time, or the storage units with long drift time and high failure rate will not be selected at the same time. In this way, the error probability of the storage units read according to the first address is relatively high, and the accuracy of reading and writing data in the storage unit can be improved.

[0023] In an implementable manner, the distances between the M storage units of the M storage arrays and the X storage units of the X storage arrays and the corresponding driving circuit are all different. In this way, the distance between each storage unit to be operated and the driving circuit is different, so that the storage units far or close to the driving circuit can be avoided at the same time, and the accuracy of reading and writing data in the storage unit can be improved.

[0024] In an implementable manner, the ranks of the M storage units of the M storage arrays in the first sequence are the same as the ranks of the X storage units of the X storage arrays in the second sequence, the first sequence is the sequence of the distances from the driving circuit to the first storage units in the first region from far to near, and the second sequence is the sequence of the distances from the driving circuit to the second storage units in the second region from near to far.

[0025] In the scheme provided in the application, for any selected first storage unit, there is a selected second storage unit that satisfies the matching condition with the first storage unit, and the rank of the first storage unit from the driving circuit in the first region is equal to the rank of the second storage unit from the driving circuit in the second region. The distance between the first storage unit and the second storage unit that satisfies the matching condition and the driving circuit is large, and the probability of data error at the same time is low, so that the accuracy of reading and writing data in the storage unit can be improved.

[0026] In a second aspect, a storage system is provided, which includes one or more storage chips as described in the second aspect above, and a storage controller connected to the storage chips.

[0027] In a third aspect, an electronic device is provided, which includes a processor and a storage system as described in the third aspect above; the processor is configured to send read-write instructions to the storage system to enable the storage system to perform read-write operations. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a structural schematic diagram of a storage chip according to an embodiment of the present application;

[0029] FIG. 2 is a structural schematic diagram of a control circuit according to an embodiment of the present application;

[0030] FIG. 3 is a structural schematic diagram of a storage system according to an embodiment of the present application;

[0031] FIG. 4 is a position schematic diagram of a driving circuit and a storage array according to an embodiment of the present application;

[0032] FIG. 5 is a threshold voltage distribution diagram of a storage unit according to an embodiment of the present application;

[0033] FIG. 6 is a position schematic diagram of a storage unit according to an embodiment of the present application;

[0034] FIG. 7 is a schematic diagram of a storage array region division according to an embodiment of the present application;

[0035] FIG. 8 is a schematic diagram of a storage array region division according to an embodiment of the present application;

[0036] FIG. 9 is a flowchart of a control method of a storage chip according to an embodiment of the present application;

[0037] FIG. 10 is a schematic diagram of selecting multiple storage units according to an embodiment of the present application;

[0038] FIG. 11 is a structural schematic diagram of a control circuit according to an embodiment of the present application;

[0039] FIG. 12 is a structural schematic diagram of a control circuit according to an embodiment of the present application;

[0040] FIG. 13 is a position schematic diagram of a storage unit according to an embodiment of the present application;

[0041] FIG. 14 is a position schematic diagram of a storage unit according to an embodiment of the present application;

[0042] FIG. 15 is a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0044] Some terms involved in the embodiments of the present application are explained as follows:

[0045] Resistive memory: using the change of resistance to store or read data, for example, resistive memory can realize the storage of "0" in high configuration, and realize the storage of "1" in low configuration.

[0046] Phase change memory (PCM): a new type of non-volatile semiconductor memory based on chalcogenide compounds, which belongs to a kind of resistive memory, and can realize the storage of "0" and "1" by using the different resistances of the crystalline and amorphous states of the phase change material constituting the phase change memory. When the phase change material is in the amorphous state, the phase change material is in the high resistance state, that is, it has a high resistance value, which is defined as the RESET (0) state; when the phase change material is in the crystalline state, the phase change material is in the low resistance state, that is, it has a low resistance value, which is defined as the SET (1) state.

[0047] Ovonic threshold switch (OTS): a new type of bidirectional gating device based on chalcogenide compounds. When an electric pulse of any positive or negative direction and lower than the threshold voltage corresponding to the ovonic threshold switch is applied to the ovonic threshold switch, the response current on the ovonic threshold switch is small, and the ovonic threshold switch presents a high resistance non-conducting state. When an electric pulse of any positive or negative direction and higher than the threshold voltage corresponding to the ovonic threshold switch is applied to the ovonic threshold switch, the response current on the ovonic threshold switch is large, and the ovonic threshold switch presents a low resistance conducting state.

[0048] 1S1R memory cell: a memory cell composed of one OTS and one PCM. In an implementable manner, when the PCM in the 1S1R memory cell is in the RESET (0) state, "0" is stored in the 1S1R memory cell, at this time, the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET (1) state, "1" is stored in the 1S1R memory cell, at this time, the 1S1R memory cell has a lower threshold voltage Vths. Wherein, Vthr is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET (0) state, and Vths is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET (1) state.

[0049] Based on the above characteristics, when the 1S1R storage unit stores "0", the 1S1R device unit has a small response current under a specific read voltage Vread (greater than Vths and less than Vthr); when the 1S1R storage unit stores "1", the 1S1R device unit has a large response current under the specific read voltage Vread. In this way, the data stored in the 1S1R storage unit can be read by applying the read voltage Vread.

[0050] Erase operation: achieved by applying a high-amplitude narrow-width electrical pulse to the 1S1R storage unit. The amplitude of the electrical pulse is higher than the threshold voltage of the OTS, and under the action of the electrical pulse, the temperature of the PCM in the 1S1R storage unit is rapidly raised above the melting temperature and then quenched. Since the micro atoms do not have sufficient time to crystallize, they remain in a high-resistance amorphous state, i.e., "0" is stored.

[0051] Write operation: achieved by applying an electrical pulse with a relatively low amplitude but a relatively long duration to the 1S1R storage unit. The amplitude of the electrical pulse is higher than the threshold voltage of the OTS, and under the action of the electrical pulse, the temperature of the PCM in the 1S1R storage unit is raised above the crystallization temperature and below the melting temperature. The PCM can be converted into a low-resistance state through a thermal crystallization process, i.e., "1" is stored.

[0052] Read operation: the stored data in the 1S1R storage unit can be read by applying a fixed read voltage Vread across the 1S1R storage unit according to the response current of the 1S1R storage unit.

[0053] Word line: a signal line required for selecting a row of 1S1R storage units in the storage array, which can select a 1S1R storage unit together with the bit line.

[0054] Bit line: a signal line required for selecting a column in the storage array, which can select a 1S1R storage unit together with the word line. By applying corresponding electrical pulses to the word line and the bit line, the above write operation, erase operation or read operation can be performed on the selected 1S1R storage unit.

[0055] Threshold voltage drift of OTS: the threshold voltage of the OTS changes due to the voltage applied to the OTS within the time from the last opening to the current opening, the ambient temperature, etc., which is called the threshold voltage drift of the OTS.

[0056] OTS has a large current conduction capacity under the action of a voltage greater than the threshold voltage, which is caused by the transition of the originally balanced non-conductive electrons in the low energy state to the unbalanced conductive state in the high energy state under the action of high voltage. When the voltage applied to the OTS is removed, the high energy unbalanced carriers in the OTS will not all return to the balanced state at once, but will gradually return to the low energy balanced non-conductive state according to a certain probability. Therefore, after each operation on the 1S1R storage unit, the threshold voltage of the OTS in the 1S1R storage unit will suddenly decrease and then gradually increase over time. Among them, the greater the voltage applied to the OTS, the more the threshold voltage of the OTS will decrease, and then the higher the ambient temperature of the OTS, the faster the threshold voltage will drift upward. In addition, when the OTS is placed for a long time, its threshold voltage will also drift to a higher state.

[0057] Figure 1 is a structural schematic diagram of a storage chip provided by an embodiment of the present application. As shown in Figure 1, the storage chip 100 includes a control circuit 110 and at least one storage bank 120 (Bank 120), and each Bank 120 includes a plurality of storage arrays 121. The plurality of storage arrays 121 included in the plurality of Banks 120 can generally be tiled on the same plane, or can be stacked in three-dimensional space. Each storage array 121 includes storage cells arranged in rows and columns, and when performing read, write and other operations on the storage cells of the storage chip 100, a storage cell can be selected in each storage array 121 to perform read, write and other operations on the selected storage cells. In this way, the storage capacity and storage performance of the storage chip can be improved without increasing the area occupied by the storage chip.

[0058] Figure 2 is a schematic diagram of a control circuit provided by an embodiment of the present application. As shown in Figure 2, the control circuit 110 includes a logic control circuit 1101, an address register 1102, a Bank selection circuit 1103, a row address multiplexing circuit 1104, a column address multiplexing circuit 1105, and a row decoder 1106, a column decoder 1107, a driving circuit 1108 and a sensing circuit (SA) 1109 corresponding to each storage array, wherein:

[0059] The logic control circuit 1101 can be used to receive read, write and other operation requests sent by the outside, control the timing of performing read, write and other operations, etc. For example, sending the address of the storage cell to be executed read, write operation to the address register 1102, and sending the operation type of the operation performed, such as write operation, read operation, etc. to the driving circuit.

[0060] The address register 1102 can receive and store the address corresponding to the storage cell to be executed read, write and other operations sent by the logic control circuit 1101. The address includes the row address, column address and Bank address of the storage cell.

[0061] The bank selection circuit 1103 can select a bank in which the memory cell to be operated is located, according to the bank address corresponding to the memory cell to be operated.

[0062] The row address multiplexing circuit 1104 can send the row address corresponding to the memory cell to be operated to the row decoder 1106 corresponding to each memory array 121 included in the selected bank. The column address multiplexing circuit 1105 can send the column address corresponding to the memory cell to be operated to the column decoder 1107 corresponding to each memory array 121 included in the selected bank.

[0063] For each row decoder 1106 receiving the row address, the row decoder 1106 can decode the row address to select the row in which the memory cell to be operated is located. For each column decoder 1107 receiving the column address, the column decoder 1107 can decode the column address to select the column in which the memory cell to be operated is located. The memory cell selected by the row decoder 1106 and the column decoder 1107 simultaneously is the memory cell to be operated.

[0064] For each drive circuit 1108 included in the selected bank, the drive circuit 1108 can apply an operation voltage to the selected memory cell in the corresponding memory array 121 according to the received operation type, to complete the corresponding operation.

[0065] For each sensing circuit 1109 included in the selected bank, the sensing circuit 1109 can determine the data stored in the memory cell by detecting the current or voltage after the drive circuit 1108 completes the read operation voltage applied to the memory cell.

[0066] FIG. 3 is a schematic diagram of a storage system according to an embodiment of the present application. As shown in FIG. 3, the storage system 300 includes a storage controller 200 and one or more storage chips 100 as shown in FIG. 1. Wherein:

[0067] The storage controller 200 is a hardware device for controlling the storage chip 100 to perform read / write and other operations. The storage controller 200 can send a read operation, a write operation, or an erase operation corresponding operation request to the storage chip 100, so that the control circuit 120 in the storage chip 100 selects the storage unit through the word line and the bit line, and applies a read voltage, a write voltage, or an erase voltage to the selected storage unit, thereby realizing the execution of the read operation, the write operation, or the erase operation. In order to cope with the read error of the storage unit, the storage controller 200 is also provided with an error correction algorithm. The error correction algorithm can check and correct the read result of the storage chip, so as to avoid or reduce the read error data.

[0068] FIG. 4 is a schematic diagram of the positional relationship between an exemplary drive circuit and each storage unit in a storage array according to an embodiment of the present application. As shown in FIG. 4, the drive circuit can be located in the middle position of each storage unit in the storage array. The drive circuit and each storage unit can be connected through a word line and a bit line (not shown in FIG. 4). The drive circuit can realize the operation of the storage unit by applying an operating voltage to the word line and the bit line. As can be seen from FIG. 4, the distance between the drive circuit and the storage units at different positions in the same storage array can be different. For example, the distance a between the drive circuit and the storage unit a is different from the distance b between the drive circuit and the storage unit b.

[0069] For the storage unit close to the drive circuit, the length of the word line and the bit line between the storage unit and the drive circuit is short, and when the drive circuit applies an operating voltage to the storage unit, the word line and the bit line have less voltage division of the operating voltage. For the storage unit far away from the drive circuit, the length of the word line and the bit line between the storage unit and the drive circuit is long, and when the drive circuit applies an operating voltage to the storage unit, the word line and the bit line have more voltage division of the operating voltage. It can be seen that when the drive circuit applies an operating voltage to the storage unit, the operating voltage applied to the storage unit is different due to the voltage division of the word line and the bit line, so the voltage value of the operating voltage applied to the storage unit close to the drive circuit is higher than that applied to the storage unit far away from the drive circuit.

[0070] FIG. 5 is a schematic diagram of the threshold voltage distribution of a storage unit according to an embodiment of the present application. As shown in FIG. 5:

[0071] In an ideal state, the threshold voltage distribution of the storage unit storing "1" and "0" respectively. That is, the threshold voltage distribution of the 1S1R storage unit storing "1" and the threshold voltage distribution of the 1S1R storage unit storing "0" have a clear window. In this case, by applying a read voltage Vread to the storage unit, it can be accurately determined whether the 1S1R storage unit stores "0" or "1". Referring to Figure 5, in combination with the above-mentioned voltage division of the word line and the bit line, the threshold voltage distribution of part of the storage unit may also appear as follows:

[0072] Case one, for the storage unit close to the driving circuit, because the operating voltage applied to the storage unit is high, so when reading the operation of this part of the storage unit, the read voltage applied to this part of the storage unit is also larger. In this case, the read voltage Vread may be greater than the threshold voltage of the storage unit storing "0", thereby causing the failure rate of this part of the storage unit to be higher. And because the threshold voltage of the storage unit after being operated will be refreshed, resulting in the threshold voltage being lowered. Therefore, the threshold voltage of the storage unit storing "0" just after being operated is more likely to be exceeded by the read voltage Vread. That is, in the storage unit close to the driving circuit, the storage unit storing "0" just after being operated has a higher failure rate.

[0073] Case two, for the storage unit far from the driving circuit, because the operating voltage applied to the storage unit is low, so when reading the operation of this part of the storage unit, the read voltage applied to this part of the storage unit is also smaller. In this case, the read voltage may be less than the threshold voltage of the storage unit storing "1", thereby causing the failure rate of this part of the storage unit to be higher. And because the operating voltage applied to the storage unit is low, the threshold voltage of the storage unit storing "1" in this part is also lower, and because the threshold voltage of the gating device in the storage unit will also increase with time (△t), the threshold voltage of the storage unit will also be higher and higher. Therefore, the threshold voltage of the storage unit storing "1" after being operated for a certain period of time is more likely to be greater than the read voltage Vread. That is, in the storage unit far from the driving circuit, the storage unit storing "1" after being operated for a certain period of time has a higher failure rate.

[0074] In combination with the above-mentioned case one and case two, it can be known that the closer the storage unit is to the driving circuit, the closer the time when the corresponding failure rate is highest to the time when the read / write operation is recently performed, and the farther the storage unit is from the driving circuit, the farther the time when the corresponding failure rate is highest to the time when the read / write operation is recently performed.

[0075] Figure 6 is a schematic diagram of a conventional operation on a memory cell in a memory array. In a memory chip, each time an operation is performed on a memory cell, the memory cell corresponding to the address of the memory cell to be operated can be selected from a plurality of memory arrays according to the address of the memory cell to be operated, where the plurality of memory arrays can be memory arrays included in the selected bank. The memory cells corresponding to the same address are located at the same position in the memory arrays, that is, the distance of the memory cells to be operated from the driving circuit is the same. As shown in Figure 6, if the address of the memory cell to be operated corresponds to a row address of 1 and a column address of 2, the operation can be performed on the memory cell in the second row and the third column of each memory array. In this way, the positions of the memory cells selected in each memory array are the same, and the distance of the memory cells from the driving circuit is the same, and thus it is easy for the selected memory cells to be close to or far from the driving circuit.

[0076] If the distance of the selected memory cells from the driving circuit is close, and the selected memory cells have just performed a write operation or a read operation, the failure rate of each selected memory cell is relatively high. Alternatively, if the distance of the selected memory cells from the driving circuit is far, and the selected memory cells have not performed a write operation or a read operation for a long time, the failure rate of each selected memory cell is also relatively high. In this way, if the failure rates of the selected memory cells are all relatively high, the number of memory cells with data read errors after a read operation on the plurality of memory cells is relatively high, which can exceed the error correction capability of the error correction algorithm, resulting in a situation where the error correction algorithm cannot correct errors.

[0077] Embodiments of the present application provide a memory chip. The control circuit of the memory chip can select memory cells having different positions in each memory array before performing an operation on the memory cells each time. In this way, a plurality of memory cells with a high failure rate (i.e., memory cells far from the driving circuit or memory cells close to the driving circuit) can be avoided, and thus the number of memory cells with data read errors can be reduced, and a situation where the error correction algorithm cannot correct errors can be avoided.

[0078] In embodiments of the present application, the memory arrays included in the memory chip can be divided into regions, and the division can be based on the distance of the memory cells in the memory arrays from the driving circuit. The control circuit of the memory chip can select memory cells located in different regions when selecting memory cells in the plurality of memory arrays, and thus memory cells having different positions in each memory array can be selected, the number of memory cells with data read errors can be reduced, and a situation where the error correction algorithm cannot correct errors can be avoided.

[0079] In an example, a memory array can be divided into at least two regions, including a first region and a second region. In which, the distance between the memory cells in the first region and the connected drive circuit is greater than the distance between the memory cells in the second region and the connected drive circuit. FIG. 7 and 8 are schematic diagrams of a memory array provided by an embodiment of the present application.

[0080] As shown in FIG. 7, the memory array can be divided into a first region and a second region. The first region can also be referred to as a Far region, that is, the distance between the memory cells in the region and the drive circuit is far. The second region can also be referred to as a Near region, that is, the distance between the memory cells in the region and the drive circuit is close. In which, for the Far region and the Near region, the distance threshold value set by the technician can be used for division. That is, the memory cells with a distance greater than the distance threshold value from the drive circuit are divided into the first region, and the memory cells with a distance less than the distance threshold value from the drive circuit are divided into the second region. The specific value of the distance threshold value can be set by the technician according to experience, which is not limited in the embodiment of the present application.

[0081] As shown in FIG. 8, on the basis of FIG. 7, the memory array can be further divided into a third region. The third region can be referred to as a middle region, the distance between the memory cells in the third region and the drive circuit is less than the distance between the memory cells in the first region and the drive circuit and greater than the distance between the memory cells in the second region and the drive circuit. The above FIG. 7 and 8 are only two exemplary division modes of the memory array shown in the embodiment of the present application, and in actual application, more regions can be divided according to the distance between the memory cells and the drive circuit, which will not be enumerated one by one in the embodiment of the present application.

[0082] FIG. 9 is a memory chip provided by an embodiment of the present application. In the memory chip, the memory array includes at least a first region and a second region, and the memory cells in the first region and the memory cells in the second region have different failure rates. Referring to FIG. 9, the method includes:

[0083] In step 901, the control circuit obtains a first address. The first address is determined according to the address of N first memory cells which need to perform the operation corresponding to the operation request, including the row address and the column address of the N first memory cells in the N memory arrays.

[0084] In implementation, the control circuit can receive an operation request. The operation request includes the first address corresponding to the memory cell to be operated. In which, the operation request can be sent by the storage controller connected outside the memory chip. In addition to carrying the first address of the memory cell to be operated, the operation request can also include the operation type of the memory cell, which can include write operation, read operation or erase operation, etc.

[0085] The control circuit can send the first address included in the operation request to the address register after receiving the operation request. In an example, the first address can include the address of the bank corresponding to the bank in which the storage unit to be operated is located, the first row address and the first column address corresponding to the storage unit to be operated in each storage array. The bank selection circuit included in the control circuit can select the bank to be operated according to the bank address included in the first address. The bank can include N storage arrays, the first row address can indicate the row of the storage unit to be operated in each storage array, and the first column address can indicate the column of the storage unit to be operated in each storage array.

[0086] Step 902, when the first address is the address of the storage unit in the first region, converting the first address of the M storage units in the M storage arrays in the N storage arrays into a second address, the second address corresponding to the second storage unit in the second region in the M storage arrays, wherein M is less than N.

[0087] An address correspondence relationship can be provided in the control circuit, in which the address corresponding to the storage unit in the first region can correspond to the address corresponding to the storage unit in the second region. The address corresponding to the storage unit in the second region can correspond to the address corresponding to the storage unit in the first region. In implementation, the control circuit can convert the first address into the second address corresponding to the storage unit in the second region according to the address correspondence relationship after obtaining the first address for the M storage arrays in the N storage arrays. For the remaining N-M storage arrays, no conversion can be performed. In this way, the first storage unit in the first region can be selected in the N-M storage arrays according to the first address, and the second storage unit in the second region can be selected in the M storage arrays according to the second address. The positions of the M storage arrays in the N storage arrays can be pre-set by the technician, which is not limited in the embodiments of the present application.

[0088] Step 903, determining X first storage units in X storage arrays according to the first address, and determining M second storage units in M storage arrays according to the second address, and performing the operation on the determined first storage units and second storage units, wherein M+X is less than or equal to N.

[0089] After converting the first address corresponding to the M storage arrays into the second address corresponding to the N storage arrays, the X first storage units selected in the X storage arrays according to the first address and the M second storage units selected in the M storage arrays according to the second address can be selected, and the operation corresponding to the operation request can be performed on the selected first storage units and second storage units.

[0090] In one example, M+X can equal N. The aforementioned X storage arrays can form the first storage array group in the Bank, and the M storage arrays can form the second storage array group in the Bank. After receiving an operation request corresponding to the first address, the control circuit can convert the first address into a second address, and then, based on the first address, select the first storage cell located in the first region among the storage arrays in the first storage array group, and select the second storage cell located in the second region among the storage arrays in the second storage array group.

[0091] Because the distances between the first storage cell in the first region and the second storage cell in the second region and the driving circuit are different, their failure rates are different. Therefore, the situation where the failure rates of the storage cells in both the first and second regions are relatively high after read / write operations will not occur. This avoids the situation where too many storage cells are read incorrectly during read operations on the storage cells of each storage array, exceeding the error correction capability of the error correction algorithm, thereby improving the read / write performance of the storage chip.

[0092] Figure 10 is a schematic diagram of selecting multiple memory cells according to an embodiment of this application. As shown in Figure 10, at the first moment after a write operation is performed on the selected multiple memory cells, the failure rate of the memory cells closer to the driving circuit (the second memory cell in the second region) is higher, while the failure rate of the memory cells farther from the driving circuit (the first memory cell in the first region) is lower. As time increases, the failure rate of the memory cells closer to the driving circuit gradually decreases, while the failure rate of the memory cells farther from the driving circuit gradually increases. For example, at the second moment after a certain period of threshold voltage drift, the failure rate of the memory cells closer to the driving circuit is lower, while the failure rate of the memory cells farther from the driving circuit is higher. Therefore, when operating on memory cells different from the driving circuit simultaneously, no matter when a read operation is performed on the multiple memory cells again, there is no situation where the failure rate of the multiple memory cells is high. Therefore, the problem of error correction algorithms being unable to correct errors due to a large number of memory cells with data reading errors can be avoided.

[0093] In one feasible implementation, each Bank of the three-dimensional storage array is further divided into a third storage array group, which may include Y storage arrays. Each storage array also includes a third region, where M+X+Y is less than or equal to N. In one example, the distance between a storage cell in the third region and its connected driving circuit is less than the distance between a storage cell in the first region and its connected driving circuit, but greater than the distance between a storage cell in the second region and its connected driving circuit. As shown in Figure 8, the third region can be a middle region.

[0094] In step 902, for each storage array in the third storage array group, the first address can be converted into a third address based on the first address and address correspondence, and a third storage cell located in the third region is selected based on the third address. Combining the first storage cell selected in the first storage array group and the second storage cell selected in the second storage array group, the selected storage cell in each step includes storage cells in the Far region, the middle region, and the near region. Since the distance between the storage cells in the middle region and the driving circuit is moderate, meaning the operating voltage applied to the storage cells in the middle region is neither too high nor too low, the failure rate of the storage cells in the middle region is relatively low. Therefore, by selecting a third storage cell located in the middle region from some storage arrays based on the third address, the probability of overall data errors in each storage cell can be reduced, which means the number of storage cells with data errors can be reduced. This further avoids the problem of error correction algorithms being unable to correct errors due to a large number of storage cells with data read errors.

[0095] In some embodiments, step 902 may involve receiving the second address of the second region and then converting the second address into the first address of the corresponding first region for each of the X memory arrays; the corresponding processing will not be elaborated further. In this embodiment, there is no limitation on the number of regions that each memory array can be divided into, nor on the number of memory array groups included in each Bank. The distance between the memory cells located in different regions and the driving circuit can be different, and the number of regions and the number of memory array groups can be the same. Thus, for each operation request sent by the memory controller, the control circuit can convert the address of the operation request into the address corresponding to the memory cell located in different regions, thereby selecting the memory cell located in different regions. This prevents the write voltage applied to each memory cell from being too high or too low during read / write operations, reducing the probability of data errors in the memory cells.

[0096] The following is a detailed description of the processing for controlling the selected memory cell provided in the embodiments of this application:

[0097] Method 1: Convert the first address of the memory cell to another address by adding an address translation circuit.

[0098] In this embodiment, the control circuit includes an address translation circuit for each memory array group and an address determination circuit for each memory array. The address translation circuit includes a row address translation unit and a column address translation unit, and the address determination circuit also includes a row address translation unit and a column address translation unit. The address translation circuits for different memory array groups use different address mapping relationships. In this way, the address translation circuits for different memory array groups can translate the address in the operation request to the address corresponding to the memory cell in different regions, thereby enabling the selection of memory cells at different locations.

[0099] Figure 11 is a schematic diagram of a control circuit provided in an embodiment of this application. Referring to Figure 11, the row address translation unit can be disposed between the row address register and the row decoder (row address determination module), and the column address translation unit can be disposed between the column address register and the column decoder column address determination module. The row address translation unit and the column address translation unit respectively store address correspondences.

[0100] In one example, in the first memory array group, the row address translation unit can convert the first row address in the row address register to the fourth row address based on the stored address correspondence, and the column address translation unit can convert the first column address in the column address register to the fourth column address based on the stored address correspondence. The row address translation unit can send the converted fourth row address to the row decoder, and the column address translation unit can send the converted fourth column address to the row decoder. Then, the row decoder can select the row corresponding to the fourth row address in the memory array by decoding the fourth row address, and the column decoder can select the column corresponding to the fourth column address in the memory array by decoding the fourth column address, thereby selecting the first memory cell in the first region corresponding to the fourth address after the first address translation. The fourth address can be the same as or different from the first address.

[0101] In one example, in the second memory array group, the row address translation unit can convert the first row address in the row address register to the second row address based on the stored address mapping, and the column address translation unit can convert the first column address in the column address register to the second column address based on the stored address mapping. The row address translation unit can send the converted second row address to the row decoder, and the column address translation unit can send the converted second column address to the column decoder. Then, the row decoder can decode the second row address to select the row corresponding to the second row address in the memory array, and the column decoder can decode the second column address to select the column corresponding to the second column address in the memory array, thereby selecting the second memory cell in the second region corresponding to the second address after the first address translation.

[0102] For the third or other memory array groups, the processing of the first address translation and the processing of determining the memory cell are similar to those of the second memory array group in the above example, and will not be repeated in the embodiments of this application.

[0103] Referring again to Figure 11, in one implementation, the control circuit also includes a bypass circuit. The bypass circuit has a first operating state and a second operating state. In the first operating state, the bypass circuit can be used to connect the address register, the address translation circuit, and the address determination circuit, allowing the address translation circuit to convert the first address into another address before sending it to the address determination circuit for decoding. In the second operating state, the bypass circuit can be used to short-circuit the address translation circuit, allowing the address determination circuit to directly receive the first address stored in the address register, decode the first address, and select the memory cell at the same location in the memory array.

[0104] In implementation, the bypass circuit, responding to an address translation command, can enter a first operating state, which means it can establish a first path between the row address multiplexing circuit and the row address translation unit, a second path between the row address translation unit and the row decoder, a third path between the column address multiplexing circuit and the column address translation unit, and a fourth path between the column address translation unit and the column decoder. Thus, the row address multiplexing circuit sends the first row address of the first address to the row address translation unit through the first path, and the row address translation unit can send the translated second row address to the row decoder through the second path. Similarly, the column address multiplexing circuit sends the first column address of the first address to the column address translation unit through the third path, and the column address translation unit can send the translated second column address to the column decoder through the fourth path. This enables the translation of the first address, thereby selecting memory cells located in different regions within different memory array groups.

[0105] When no address translation instruction is received, the bypass circuit can be in a second operating state, which allows the fifth path between the row address multiplexing circuit and the row decoder, and the sixth path between the column address multiplexing circuit and the column decoder, to be activated. In this way, the row address multiplexing circuit sends the first row address of the first address to the row decoder via the fifth path, and sends the first column address of the first address to the column decoder via the sixth path. This allows for the selection of memory cells located at the same position in each memory array group.

[0106] As shown in Figure 11, the bypass circuit can be controlled by the mode register set (MRS). For example, when the MRS is set to "1", the bypass is in the first working state, and when the MRS is set to "0", the bypass is in the second working state. Since the data error rate of the memory cell is related to the usage time and wear status (cycle count) of the memory cell, in this embodiment, in the early stage of the use of the memory chip, such as when the cycle count of the memory cell in the memory chip is lower than the set threshold, the bypass circuit can be configured so that the address decoding circuit directly selects the memory cell at the same location through the first address, thereby improving the operation efficiency of the memory cell. In the later stage of the use of the memory chip, such as when the cycle count of the memory cell in the memory chip is greater than the set threshold, the bypass circuit can be configured so that the address translation circuit first translates the first address to a different address, and then selects the memory cell at a different location according to the different translated addresses, thereby reducing the probability of data error in the memory cell. It can be seen that in this embodiment, the flexibility of controlling the memory chip is improved by setting the bypass circuit.

[0107] Method 2: Select different memory units by using different decoding methods through the address decoding circuit.

[0108] In this embodiment, the control circuit includes an address determination circuit for each memory array. The address determination circuit includes a row decoder and a column decoder. Each memory array's row decoder and column decoder have an address mapping relationship, and different memory array groups use different address mapping relationships. In this way, the row decoders and column decoders for different memory array groups can translate the same address to addresses in different regions, thereby enabling the selection of memory cells in different regions.

[0109] Unlike Method 1, Method 2 does not require an additional address translation circuit. Instead, the address mapping can be directly set in the address determination circuit. After translating the first address to other addresses, memory cells in different locations are selected based on these other addresses. Similar to Method 1, row decoders and column decoders corresponding to the same memory array group can use the same address mapping, while row decoders and column decoders corresponding to different memory array groups can use different address mappings to select memory cells located in different regions within different memory array groups.

[0110] Figure 12 is a schematic diagram of a control circuit structure provided in an embodiment of this application. Referring to Figure 12, each storage array has a row decoder and a column decoder. The address correspondence used by the row decoder in the same storage array group can be the same, while the address correspondence used by the row decoder in different storage array groups is different. The address correspondence used by the column decoder in the same storage array group can be the same, while the address correspondence used by the column decoder in different storage array groups is different.

[0111] In the first memory array group, the row decoder can convert the first row address in the row address register to the fourth row address based on the stored address correspondence, and then decode the fourth row address to select the row corresponding to the fourth row address in the memory array. Similarly, the column decoder can convert the first column address in the row address register to the fourth column address based on the stored address correspondence, and then decode the fourth column address to select the column corresponding to the fourth column address in the memory array. Thus, the memory cell corresponding to the fourth address in the first region can be selected using the first address. The fourth address can be the same as or different from the first address.

[0112] In the second memory array group, the row decoder can convert the first row address in the row address register to the second row address based on the stored address correspondence, and then decode the second row address to select the row corresponding to the second row address in the memory array. Similarly, the column decoder can convert the first column address in the row address register to the second column address based on the stored address correspondence, and then decode the second column address to select the column corresponding to the second column address in the memory array. Thus, the memory cell corresponding to the second address in the second region can be selected using the first address.

[0113] Figures 13 and 14 are schematic diagrams showing the location of selected storage cells in different storage arrays using either method one or method two described above.

[0114] In one example, in the selected memory cells of the first and second memory array groups, the distance between each memory cell and the connected drive circuit is different.

[0115] As shown in Figure 13, for example, a Bank includes m storage arrays, each of which can include m columns and m rows, for a total of m... 2There are several memory cells. As shown in Figure 13, taking an example where the row address and column address in the first address are both 0, the memory cells with row number 0 and column number 0 selected by the first address are located on the diagonal of the memory array. Memory cells with the same row and column numbers in different memory arrays can be selected by other addresses after the first address has been converted. In this way, the distance between the selected memory cells and the driving circuit is different, and the time corresponding to the data error rate of each memory cell is different. This avoids selecting memory cells with high data error rates in batches, reducing the number of memory cell read errors and preventing uncorrectable errors.

[0116] In another example, for each first memory cell selected in the first memory array group, there exists a selected second memory cell in the second memory array group that satisfies a matching condition with the first memory cell. The matching condition means that the first memory cell's position in a first sequence is the same as the second memory cell's position in a second sequence. The first sequence is the order of distance between each first memory cell and the driving circuit from farthest to closest, and the second sequence is the order of distance between each second memory cell and the driving circuit from closest to farthest.

[0117] As shown in Figure 14, the storage array is divided into a first region and a second region. The storage cells in the first region can correspond to a first order, that is, the storage cells in the first region are sorted according to the order in which each storage cell is closest to the driving circuit, and a first sequence number is assigned to each storage cell in the first region. The storage cells in the second region can correspond to a second order, that is, the storage cells in the second region are sorted according to the order in which each storage cell is closest to the driving circuit, and a second sequence number is assigned to each storage cell in the second region.

[0118] In implementation, after selecting storage cells in the first and second regions based on the first storage cell, the first serial number corresponding to the multiple selected storage cells in the first region is the same as the second serial number corresponding to the multiple selected storage cells in the second region. As shown in Figure 14, the first serial number of the two storage cells selected in the Far region is the same as the second serial number of the two storage cells selected in the Near region. Thus, the farther the selected storage cells in the first region are from the driving circuit, the closer the selected storage cells in the first region are to the driving circuit. This results in a greater difference in the timing of high data error rates for storage cells in the first and second regions, thereby avoiding the simultaneous selection of multiple storage cells with high data error rates in both regions. Conversely, the closer the selected storage cells in the first region are to the driving circuit, the farther the selected storage cells in the first region are from the driving circuit. This results in a moderate distance between the storage cells in the first and second regions and the driving circuit, leading to a lower data error rate. This also reduces the likelihood of selecting multiple storage cells with high data error rates in both regions.

[0119] This application also provides a schematic diagram of an electronic device, as shown in FIG15. The electronic device 1400 includes a processor 1410 and a storage system 300 as described in the above embodiments. The processor 1410 is used to send read / write instructions to the storage system 300 to enable the storage system to perform read / write operations. The electronic device 1400 can be a mobile phone, tablet computer, desktop computer, personal laptop computer, or smart wearable device, etc.

[0120] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and purpose. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of various examples, a first region can be referred to as a second region, and similarly, a second region can be referred to as a first region. Both the first and second regions can be collectively referred to as regions, and in some cases, they can refer to different regions respectively.

[0121] In this application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory chip, characterized in that, The memory chip includes a control circuit and N memory arrays. In the N memory arrays, the memory cells of each memory array are arranged in rows and columns, and each memory array has the same number of rows and the same number of columns. Each memory array is divided according to different row addresses and column addresses, so that each memory array includes a first region and a second region. The memory cells in the first region and the memory cells in the second region have different failure rates. The control circuit is used for: Obtain the first address, which is the address of N first storage units that need to perform the operation corresponding to the operation request, as determined according to the operation request, including the row address and column address of the N first storage units in the N storage arrays; When the first address is the address of a storage cell in the first region, the first address of the M storage cells in the M storage arrays of the N storage arrays is converted into a second address, and the second address corresponds to the second storage cell in the second region of the M storage arrays, where M is less than N; The M second storage cells in the M storage arrays are determined based on the second address, and the operation is performed on the M second storage cells.

2. The memory chip according to claim 1, characterized in that, The control circuit is also used for: Based on the first address, determine X storage cells in X of the N storage arrays, where M+X is less than or equal to N.

3. The memory chip according to claim 2, characterized in that, Each storage array further includes a third region, wherein the storage cells in the third region have a different failure rate than the storage cells in the first region and the second region; The control circuit is further configured to: when the first address is the address of a storage cell in the first region, convert the first address of the Y storage cells in the Y storage arrays of the N storage arrays into a third address, wherein the third address corresponds to the third storage cell in the third region of the Y storage arrays, and M+X+Y is less than or equal to N.

4. The memory chip according to any one of claims 1 to 3, characterized in that, The control circuit includes a row address determination unit, a row address conversion unit, a column address determination unit, and a column address conversion unit. Each of the M storage arrays corresponds to one row address conversion unit and one column address conversion unit. The row address translation unit corresponding to the M storage arrays is used to convert the first row address included in the first address into the second row address included in the second address, and the column address translation unit corresponding to the M storage arrays is used to convert the first column address included in the first address into the second column address included in the second address; The row address determination unit corresponding to each of the M storage arrays is used to determine the row where the second storage unit is located based on the second row address, and the column address determination unit corresponding to each of the M storage arrays is used to determine the column where the second storage unit is located based on the second column address.

5. The memory chip according to claim 4, characterized in that, The memory chip also includes a bypass circuit, which is used for: In response to receiving an address translation instruction, the first and second paths corresponding to the row address translation unit, and the third and fourth paths corresponding to the column address translation unit are activated. The row address translation unit obtains the first row address through the first path and sends the second row address to the row address determination unit through the second path. The column address translation unit obtains the first column address through the third path and sends the second column address to the column address determination unit through the fourth path.

6. The memory chip according to any one of claims 1 to 3, characterized in that, The control circuit includes a row address determination unit and a column address determination unit for each storage array; The row address determination unit corresponding to each of the M storage arrays is used to convert the first row address included in the first address into the second row address included in the second address, and determine the row where the second storage unit is located based on the second row address; The column address determination unit corresponding to each of the M storage arrays is used to convert the first column address included in the first address into the second column address included in the second address, and determine the column where the second storage unit is located based on the second column address.

7. The memory chip according to any one of claims 2 to 6, characterized in that, The memory chip also includes a driving circuit corresponding to each memory array. In each memory array, the distance between the first memory cell in the first region and the driving circuit is different from the distance between the second memory cell in the second region and the driving circuit.

8. The memory chip according to claim 7, characterized in that, The distances between the M storage cells of the M storage arrays and the X storage cells of the X storage arrays and their corresponding drive circuits are all different.

9. The memory chip according to claim 7, characterized in that, The M storage cells of the M storage arrays are arranged in the first order in the same order as the X storage cells of the X storage arrays are arranged in the second order. The first order is the order in which the storage cells in the first region are farthest from the driving circuit, and the second order is the order in which the storage cells in the second region are farthest from the driving circuit.

10. A storage system, characterized in that, The storage system includes one or more storage chips as described in any one of claims 1 to 9, and a storage controller connected to the storage chips.

11. An electronic device, characterized in that, The electronic device includes a processor and the storage system as described in claim 10; The processor is used to send read and write instructions to the storage system so that the storage system can perform read and write operations.

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