Shift register unit, gate driver, and display device

Abstract

Provided is a shift register unit, comprising: an input circuit, a first output circuit, a first node discharge circuit, a first output discharge circuit, a first node potential control circuit, a first reset circuit, and a first output control circuit. The input circuit is electrically connected to an input end and a first node, and the first output circuit is electrically connected to a clock signal receiving end, the first node, and a first output end; the first node discharge circuit is electrically connected to a second node and the first node; the first output discharge circuit is electrically connected to the second node and the first output end; the first node potential control circuit is electrically connected to a first control signal receiving end, a second control signal receiving end, the second node, and a first reference voltage end; the first reset circuit is electrically connected to a first reset signal receiving end and the first node; the first output control circuit is electrically connected to at least one of the first reset signal receiving end and the input end and is electrically connected to the first output end and the first reference voltage end.

Description

Shift register unit, gate driver, display device Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a shift register unit, a gate driver including the shift register unit, and a display device including the gate driver. Background Technology

[0002] Display devices such as liquid crystal displays and organic light-emitting displays typically include gate drivers located in the non-display area surrounding the display device or between adjacent pixel areas in the display area. The gate drivers include multiple cascaded shift register units, which can obtain scan signals provided to each gate line or scan line based on input signals and clock signals.

[0003] In a gate driver, each shift register unit sequentially outputs a scan signal for each row of pixels. The stability and reliability of the scan signal are crucial factors affecting the image display quality of the display device. However, when using existing gate drivers or gate drive circuits, it often happens that some row shift register units fail to output signals, resulting in interlaced display. Alternatively, even if interlaced display does not occur, other display anomalies may also exist. Summary of the Invention

[0004] This application provides a shift register unit, a gate driver including the shift register unit, and a display device including the gate driver. The shift register unit provided according to this application includes: an input circuit electrically connected to an input terminal and a first node, configured to control the potential of the first node based on an input signal received from the input terminal; a first output circuit electrically connected to a clock signal receiving terminal, the first node, and a first output terminal, configured to provide a first output signal to the first output terminal based on a clock signal received by the clock signal receiving terminal under the control of the potential of the first node; a first node discharge circuit electrically connected to a second node and the first node, configured to discharge the first node under the control of the potential of the second node; a first output discharge circuit electrically connected to the second node and the first output terminal, configured to discharge the first output terminal under the control of the potential of the second node; and a first node potential control circuit electrically connected to a first control signal receiving terminal, a second control signal receiving terminal, the second node, and a first reference voltage terminal, configured to... Under the control of a first control signal received by a first control signal receiving terminal, the potential of the second node becomes a first reference voltage of the first reference voltage terminal before the effective level of the input signal arrives, and under the control of a second control signal received by the second control signal receiving terminal, the potential of the second node becomes the first reference voltage during the period when the first output circuit provides an effective level of the first output signal; a first reset circuit, electrically connected to the first reset signal receiving terminal and the first node, is configured to reset the first node under the control of a first reset signal received by the first reset signal receiving terminal; and a first output control circuit, electrically connected to at least one of the first reset signal receiving terminal and the input terminal, and electrically connected to the first output terminal and the first reference voltage terminal, is configured to, under the control of the first reset signal or the input signal, make the potential of the first output terminal become the first reference voltage during the period when the first node is reset.

[0005] In some embodiments, the shift register unit further includes: a second node discharge circuit electrically connected to the third node and the first node, configured to discharge the first node under the control of the potential of the third node; a second output discharge circuit electrically connected to the third node and the first output terminal, configured to discharge the first output terminal under the control of the potential of the third node; and a second node potential control circuit electrically connected to the first control signal receiving terminal, the second control signal receiving terminal, the third node, and the first reference voltage terminal, configured to, under the control of the first control signal, cause the potential of the third node to become a first reference voltage of the first reference voltage terminal before the arrival of the effective level of the input signal, and under the control of the second control signal, cause the potential of the third node to become the first reference voltage during the period when the first output circuit provides the effective level of the first output signal.

[0006] In some embodiments, the shift register unit further includes: a second output circuit electrically connected to the clock signal receiving terminal, the first node, and the second output terminal, configured to provide a second output signal to the second output terminal based on the clock signal under the control of the potential of the first node; and a third output discharge circuit electrically connected to the second node, the third node, and the second output terminal, configured to discharge the second output terminal under the control of the potentials of the second node and the third node.

[0007] In some embodiments, the shift register unit further includes: a second output control circuit electrically connected to the second output terminal and the first reference voltage terminal, configured to receive at least one of the first reset signal and the input signal, such that, under the control of the first reset signal or the input signal, the potential of the second output terminal becomes the first reference voltage during the reset of the first node.

[0008] In some embodiments, the shift register unit further includes: a second reset circuit electrically connected to a second reset signal receiving terminal, the first node and the first output terminal, configured to reset the first node and the first output terminal under the control of a second reset signal received at the second reset signal receiving terminal.

[0009] In some embodiments, the input circuit includes a first transistor, a first terminal and a control terminal of the first transistor are electrically connected to the input terminal, a second terminal of the first transistor is electrically connected to the first node, and the first reset circuit includes a second transistor, a control terminal of the second transistor is electrically connected to the first reset signal receiving terminal, a first terminal of the second transistor is electrically connected to the first node, and a second terminal of the second transistor is electrically connected to the first reference voltage terminal.

[0010] In some embodiments, the first output circuit includes a third transistor and a capacitor, wherein a first terminal and a second terminal of the capacitor are electrically connected to a control terminal and a second terminal of the third transistor, respectively, and a first terminal of the third transistor is electrically connected to the clock signal receiving terminal.

[0011] In some embodiments, the first node potential control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the fourth transistor is electrically connected to the second node, the second terminal of the fourth transistor is electrically connected to the first reference voltage terminal, the control terminal of the fourth transistor is electrically connected to the first control signal receiving terminal, the control terminal and the first terminal of the fifth transistor are electrically connected to the second reference voltage terminal, the second terminal of the fifth transistor is electrically connected to the second node, the control terminal of the sixth transistor is electrically connected to the second control signal receiving terminal, and the first terminal and the second terminal of the sixth transistor are respectively electrically connected to the second node and the first reference voltage terminal.

[0012] In some embodiments, the first output control circuit includes a seventh transistor, the first terminal and the second terminal of the seventh transistor being electrically connected to the first output terminal and the first reference voltage terminal, respectively, and the control terminal of the seventh transistor being electrically connected to the first reset signal receiving terminal.

[0013] In some embodiments, the first node discharge circuit includes an eighth transistor, the first terminal and the second terminal of the eighth transistor being electrically connected to the first node and the first reference voltage terminal, respectively, and the control terminal of the eighth transistor being electrically connected to the second node. The first output discharge circuit includes a ninth transistor, the first terminal and the second terminal of the ninth transistor being electrically connected to the first output terminal and the first reference voltage terminal, respectively, and the control terminal of the ninth transistor being electrically connected to the second node.

[0014] In some embodiments, the first node potential control circuit further includes a tenth transistor and an eleventh transistor connected in series between the second reference voltage terminal and the first reference voltage terminal. The first terminal and the control terminal of the tenth transistor are respectively electrically connected to the first terminal and the second terminal of the fifth transistor. The first terminal and the second terminal of the eleventh transistor are respectively electrically connected to the second terminal of the tenth transistor and the first reference voltage terminal. The control terminal of the eleventh transistor is electrically connected to the control terminal of the fourth transistor.

[0015] In some embodiments, the second reset circuit includes a twelfth transistor and a thirteenth transistor, wherein the control terminals of the twelfth transistor and the thirteenth transistor are electrically connected to the second reset signal receiving terminal, the first terminals of the twelfth transistor and the thirteenth transistor are electrically connected to the first node and the first output terminal, respectively, and the second terminals of the twelfth transistor and the thirteenth transistor are electrically connected to the first reference voltage terminal.

[0016] In some embodiments, the input circuit includes a first transistor, the control terminal of the first transistor is electrically connected to the input terminal, a first terminal of the first transistor is electrically connected to a third control signal receiving terminal, and a second terminal of the first transistor is electrically connected to the first node. The first reset circuit includes a second transistor, the control terminal of the second transistor is electrically connected to the first reset signal receiving terminal, a first terminal of the second transistor is electrically connected to the first node, and a second terminal of the second transistor is electrically connected to a fourth control signal receiving terminal. The third control signal received by the third control signal receiving terminal is in phase opposite to the fourth control signal received by the fourth control signal receiving terminal.

[0017] In some embodiments, the first output control circuit further includes a fourteenth transistor, the control terminal of which is electrically connected to the input terminal, and the first terminal and the second terminal of which are electrically connected to the first output terminal and the first reference voltage terminal, respectively.

[0018] In some embodiments, the first node potential control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. A first terminal of the fourth transistor is electrically connected to the second node, a second terminal of the fourth transistor is electrically connected to the first reference voltage terminal, and a control terminal of the fourth transistor is electrically connected to the first control signal receiving terminal. The control terminal and the first terminal of the fifth transistor are electrically connected to the second reference voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node. The control terminal of the sixth transistor is electrically connected to the second control signal receiving terminal, and the first terminal and the second terminal of the sixth transistor are respectively electrically connected to the second node and the first reference voltage terminal. The second output discharge circuit includes a fifteenth transistor. The control terminal of the fifteenth transistor is electrically connected to the third node, and the first terminal and the second terminal of the fifteenth transistor are respectively electrically connected to the first output terminal and the first reference voltage terminal. The second node discharges... The circuit includes a sixteenth transistor, the control terminal of which is electrically connected to the third node. The first and second terminals of the sixteenth transistor are electrically connected to the first node and the first reference voltage terminal, respectively. The second node potential control circuit includes a seventeenth, an eighteenth, and a nineteenth transistor. The seventeenth and eighteenth transistors are connected in series between the third reference voltage terminal and the first reference voltage terminal. The first and control terminals of the seventeenth transistor are electrically connected to the third reference voltage terminal. The second terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor. The control and second terminals of the eighteenth transistor are electrically connected to the control terminal of the sixth transistor and the first reference voltage terminal, respectively. The control terminal of the nineteenth transistor is electrically connected to the control terminal of the fourth transistor. The first and second terminals of the nineteenth transistor are electrically connected to the third node and the first reference voltage terminal, respectively.

[0019] In some embodiments, the first node potential control circuit further includes a tenth transistor and an eleventh transistor connected in series between the second reference voltage terminal and the first reference voltage terminal. The first terminal and control terminal of the tenth transistor are electrically connected to the first terminal and the second terminal of the fifth transistor, respectively. The first terminal and the second terminal of the eleventh transistor are electrically connected to the second terminal of the tenth transistor and the first reference voltage terminal, respectively. The control terminal of the eleventh transistor is electrically connected to the control terminal of the fourth transistor. The second node potential control circuit further includes a twentieth transistor and a twenty-first transistor connected in series between the third reference voltage terminal and the first reference voltage terminal. The first terminal and control terminal of the twentieth transistor are electrically connected to the first terminal and the second terminal of the seventeenth transistor, respectively. The first terminal and the second terminal of the twenty-first transistor are electrically connected to the second terminal of the twentieth transistor and the first reference voltage terminal, respectively. The control terminal of the twenty-first transistor is electrically connected to the control terminal of the eighteenth transistor.

[0020] In some embodiments, the second output circuit includes a twenty-second transistor, the control terminal of which is electrically connected to the first node, and the first and second terminals of which are electrically connected to the clock signal receiving terminal and the second output terminal, respectively. The third output discharge circuit includes a twenty-third transistor and a twenty-fourth transistor, the control terminals of which are electrically connected to the second node and the third node, respectively. The first and second terminals of which are electrically connected to the second output terminal and the first reference voltage terminal, respectively, are also electrically connected to the second output terminal and the first reference voltage terminal, respectively.

[0021] In some embodiments, the second output control circuit includes a twenty-fifth transistor, the control terminal of the twenty-fifth transistor is electrically connected to the first reset signal receiving terminal, and the first terminal and the second terminal of the twenty-fifth transistor are respectively electrically connected to the second output terminal and the first reference voltage terminal.

[0022] In some embodiments, the second output control circuit further includes a second sixteenth transistor, the control terminal of which is electrically connected to the input terminal, and the first and second terminals of which are electrically connected to the second output terminal and the first reference voltage terminal, respectively.

[0023] Another embodiment of this application provides a gate driver, including N cascaded shift register units and multiple clock signal transmission lines. Each of the N shift register units is a shift register unit as described in any of the preceding embodiments. The input terminal of each shift register unit is electrically connected to the first output terminal of another shift register unit among the N shift register units. The first reset signal receiving terminal of the shift register unit is electrically connected to the first output terminal of yet another shift register unit among the N shift register units. The first control signal receiving terminal of the shift register unit is electrically connected to the first node in the other shift register unit. The second control signal receiving terminal of the shift register unit is electrically connected to the first node in yet another shift register unit. The clock signal receiving terminals of any one of the other shift register unit and the yet another shift register unit are respectively electrically connected to different clock signal transmission lines among the multiple clock signal transmission lines, where N is an integer greater than or equal to 3.

[0024] According to another embodiment of this application, the gate driver includes N cascaded shift register units and multiple clock signal transmission lines. Each of the N shift register units includes an input terminal, a first output terminal, a first reset signal receiving terminal, a first control signal receiving terminal, a second control signal receiving terminal, a clock signal receiving terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a capacitor, and a first node. The control terminal of the first transistor is electrically connected to the input terminal, and the first terminal of the first transistor is electrically connected to the input terminal or used to receive a third control signal. The second terminal of the first transistor is electrically connected to... The first terminal of the second transistor is connected to the second transistor, the second terminal of the second transistor is electrically connected to the first reference voltage terminal or used to receive a fourth control signal, the control terminal of the second transistor is electrically connected to the first reset signal receiving terminal, the first terminal and the second terminal of the third transistor are respectively electrically connected to the clock signal receiving terminal and the first output terminal of the shift register unit, the first terminal of the capacitor and the control terminal of the third transistor are electrically connected to the first node between the first transistor and the second transistor, the second terminal of the capacitor is electrically connected to the first output terminal, the first terminal and the second terminal of the ninth transistor are respectively electrically connected to the first output terminal and the first reference voltage terminal, the control terminal of the ninth transistor is electrically connected to the second node, the first terminal and the second terminal of the seventh transistor are respectively electrically connected to the first output terminal and the first reference voltage terminal, the control terminal of the seventh transistor is electrically connected to the first reset signal receiving terminal, the fourth transistor and the fifth transistor are connected in series between the second reference voltage terminal and the first reference voltage terminal, the first terminal and the control terminal of the fifth transistor are electrically connected to the second reference voltage terminal, the second terminal of the fifth transistor is electrically connected to the second node, the first terminal and the second terminal of the fourth transistor are respectively electrically connected to the second node and the first reference voltage terminal, the control terminal of the fourth transistor is electrically connected to the first control signal receiving terminal, and the first terminal and the second terminal of the sixth transistor are respectively electrically connected to the first node. The second node and the first reference voltage terminal are connected together. The control terminal of the sixth transistor is electrically connected to the second control signal receiving terminal. The first and second terminals of the eighth transistor are respectively electrically connected to the first node and the first reference voltage receiving terminal. The control terminal of the eighth transistor is electrically connected to the second node. The input terminal of the shift register unit is electrically connected to the first output terminal of another shift register unit among the N shift register units. The first reset signal receiving terminal of the shift register unit is electrically connected to the first output terminal of yet another shift register unit among the N shift register units. The first control signal receiving terminal of the shift register unit is electrically connected to the first node of the other shift register unit.The second control signal receiving terminal of the shift register unit is electrically connected to the first node in the other shift register unit. The clock signal receiving terminals of the other shift register unit and any one of the other shift register units are electrically connected to different clock signal transmission lines among the plurality of clock signal transmission lines, where N is an integer greater than or equal to 3.

[0025] In some embodiments, the phase of the clock signal received by the clock signal receiver of any one of the other shift register units and the yet another shift register unit is opposite to the phase of the clock signal received by the clock signal receiver of the shift register unit.

[0026] In some embodiments, the gate driver further includes a first dummy shift register unit and a second dummy shift register unit, each of the first dummy shift register unit and the second dummy shift register unit having the same circuit structure as each of the N shift register units. The gate driver also includes a frame start signal transmission line. The input terminal and a first control signal receiving terminal of the first dummy shift register unit are electrically connected to the frame start signal transmission line. The second control signal receiving terminal of the first dummy shift register unit is electrically connected to a first node of a first-stage shift register unit among the N shift register units. The first reset signal receiving terminal of the first dummy shift register unit is electrically connected to a first output terminal of the first-stage shift register unit. The first output terminal of the first dummy shift register unit is electrically connected to an input terminal of the first-stage shift register unit. The first node of the first dummy shift register unit is electrically connected to the first control signal receiving terminal of the first-stage shift register unit. The second control signal receiving terminal of the first-stage shift register unit is electrically connected to a second-stage shift register unit among the N shift register units. The first node of the unit, the first reset signal receiving terminal of the first stage shift register unit is electrically connected to the first output terminal of the second stage shift register unit among the N shift register units, the input terminal of the second dummy shift register unit is electrically connected to the first output terminal of the Nth stage shift register unit among the N shift register units, the first control signal receiving terminal of the second dummy shift register unit is electrically connected to the first node of the Nth stage shift register unit, the first output terminal of the second dummy shift register unit is electrically connected to the first reset signal receiving terminal of the Nth stage shift register unit, the first node of the second dummy shift register unit is electrically connected to the second control signal receiving terminal of the Nth stage shift register unit, the second control signal receiving terminal and the first reset signal receiving terminal of the second dummy shift register unit are electrically connected to the frame start signal transmission line, the first control signal receiving terminal of the Nth stage shift register unit is electrically connected to the first node of the (N-1)th stage shift register unit among the N shift register units, and the input terminal of the Nth stage shift register unit is electrically connected to the first output terminal of the (N-1)th stage shift register unit.

[0027] In some embodiments, the gate driver includes two clock signal transmission lines, wherein the input terminal of the Kth stage shift register unit among the N shift register units is electrically connected to the first output terminal of the (K-1)th stage shift register unit among the N shift register units, the first control signal receiving terminal of the Kth stage shift register unit is electrically connected to the first node of the (K-1)th stage shift register unit, the first output terminal of the Kth stage shift register unit is electrically connected to the first reset signal receiving terminal of the (K-1)th stage shift register unit, the second control signal receiving terminal of the Kth stage shift register unit is electrically connected to the first node of the (K+1)th stage shift register unit among the N shift register units, and the first reset signal receiving terminal of the Kth stage shift register unit is electrically connected to the first output terminal of the (K+1)th stage shift register unit, wherein N is an integer greater than or equal to 3, and K is an integer greater than 1 and less than N.

[0028] Another embodiment of this application provides a display device including a gate driver as described in any of the foregoing embodiments.

[0029] These and other advantages of this application will become clear from the embodiments described below, and will be illustrated with reference to the embodiments described below. Attached Figure Description

[0030] Embodiments of this application will now be described in more detail with reference to the accompanying drawings, wherein:

[0031] Figures 1 and 2 illustrate the circuit schematic and corresponding signal timing diagram of a shift register unit provided according to a comparative example of this application, respectively.

[0032] Figures 3 to 7 illustrate the circuit structure block diagrams of shift register units provided according to different embodiments of this application;

[0033] Figures 8 and 9 illustrate the circuit schematic and corresponding signal timing diagram of a shift register unit provided according to an embodiment of this application, respectively.

[0034] Figure 10 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0035] Figure 11 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0036] Figure 12 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0037] Figure 13 illustrates an example of a signal timing diagram for the shift register unit shown in Figure 12;

[0038] Figure 14 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0039] Figure 15 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0040] Figure 16 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0041] Figure 17 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0042] Figure 18 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0043] Figure 19 illustrates a waveform diagram of the signal timing diagram applicable to the shift register unit shown in Figure 18 or Figure 17 within a single cycle;

[0044] Figure 20 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0045] Figure 21 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0046] Figure 22 illustrates a circuit schematic of a shift register unit according to another embodiment of this application;

[0047] Figure 23 illustrates a variant embodiment based on the shift register unit shown in Figure 22;

[0048] Figure 24 illustrates a waveform diagram of the signal timing diagram applicable to the shift register unit shown in Figure 23 or Figure 22 within a single cycle;

[0049] Figure 25 schematically shows four cascaded shift register units GOA1, GOA2, GOA3 and GOA4;

[0050] Figure 26 illustrates N shift register units in a gate driver according to another embodiment of this application;

[0051] Figure 27 illustrates the signal timing of some of the signals received by the gate driver when it is operating in forward scan mode.

[0052] Figure 28 schematically illustrates the signal timing of some of the signals received by the gate driver when it is operating in reverse scan mode;

[0053] Figure 29 schematically illustrates the signal timing of some of the signals received by the gate driver when it is operating in forward scan mode;

[0054] Figure 30 schematically illustrates the signal timing of a portion of the signals received by the gate driver when it is operating in reverse scan mode. Detailed Implementation

[0055] The following description provides specific details of various embodiments of this application to enable those skilled in the art to fully understand and implement the various embodiments of this application. In some cases, this application does not show or describe in detail some structures or functions well known in the art to avoid such unnecessary descriptions that would obscure the description of the embodiments of this application. The technical solutions of this application can be embodied in many different forms and for many different purposes, and should not be limited to the embodiments set forth herein. These embodiments are provided to make the technical solutions of this application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the technical solutions of this application can be practiced without one or more of these details. Detailed steps and structures are set forth in the following description to illustrate the technical solutions proposed by the present invention. The terminology used in this application should be understood in its broadest reasonable sense, even when used in connection with specific embodiments of this application.

[0057] Here, some of the terms used in the embodiments of this application will be explained first, so that those skilled in the art can understand them.

[0058] The term "control terminal" as used herein refers to the gate of a transistor used to receive scan signals. The transistor can be in an on or off state under the control of the signal received at its control terminal. The term "first terminal" as used herein refers to one of the two terminals of the transistor other than the control terminal, and the term "second terminal" refers to the other of the two terminals of the transistor other than the control terminal. That is, the first terminal can be one of the source and drain of the transistor, and the second terminal can be the other of the source and drain of the transistor. The term "display device" as used herein can be an assembled display product with image display function, or a component of a complete display product, but this component includes the shift register unit or gate drive circuit described in the embodiments of this application.

[0059] Figures 1 and 2 schematically illustrate a shift register unit and its corresponding signal timing diagram provided according to a comparative example of this application. As shown in Figure 1, in this comparative example, the shift register unit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The first transistor M1 and the second transistor M2 are connected in series between the first signal receiving terminal FW and the second signal receiving terminal BM. The control terminals of the first transistor M1 and the second transistor M2 receive the input signal IN and the reset signal RE, respectively. The fifth transistor and the sixth transistor M6 are connected in series between the first reference voltage terminal GCL and the second reference voltage terminal GCH. The third transistor M3 and the fourth transistor M4 are connected in series between the clock signal receiving terminal CLK and the first reference voltage terminal GCL. The control terminal of the third transistor M3 is electrically connected to the connection node PU between the first transistor M1 and the second transistor M2. At the same time, the control terminal of the sixth transistor M6 is electrically connected to the connection node PU. The control terminal of the fifth transistor M5 is electrically connected to the second reference voltage terminal GCH. The capacitor C1 is electrically connected between the connection node PU and the output terminal OP of the shift register unit. The output terminal OP also serves as the connection node between the third transistor M3 and the fourth transistor M4. The first and second terminals of the seventh transistor M7 are electrically connected to the connection node PU and the first reference voltage terminal GCL, respectively. The control terminal of the seventh transistor M7 is electrically connected to the connection node PD between the fifth transistor M5 and the sixth transistor M6. In addition, the control terminal of the fourth transistor M4 is also electrically connected to the connection node PD.

[0060] Figure 2 schematically illustrates the signal timing diagram for the shift register unit shown in Figure 1 within a single cycle. In this embodiment, the first signal receiver FW and the second signal receiver BM receive a constant high-level signal and a constant low-level signal, respectively; or, the first signal receiver FW and the second signal receiver BM receive a constant low-level signal and a constant high-level signal, respectively. This enables the gate driver comprising multiple such shift register units cascaded together to sequentially output multiple scan signals in the forward direction or in the reverse direction, i.e., to perform forward or reverse scanning of each gate line or scan line. As shown in Figures 2 and 1, when the shift register unit receives an effective level (e.g., a high level) of the input signal IN, the first transistor M1 is turned on. Therefore, the first signal receiving terminal FW can charge the connection node PU (i.e., one end of capacitor C1). Correspondingly, the potential of the connection node PU rises from a low level to a higher first level, thus turning on the third transistor M3 and the sixth transistor M6. The potential of the connection node PD becomes the first reference voltage (e.g., a negative voltage) of the first reference voltage terminal GCL, thereby turning on the seventh transistor M7 and the fourth transistor M4. At this time, the clock signal CK received by the clock signal receiving terminal is at a low level. When the clock signal CK changes from a low level to a high level, the potential of the connection node PU jumps from the aforementioned first level to a higher second level due to the bootstrap effect of capacitor C1. Therefore, the output terminal OP of the shift register unit also outputs a high-level signal of the clock signal CK. Next, when the shift register unit receives the effective level (high level) of the reset signal RE, the second transistor M2 turns on, causing the potential of the connection node PU to become low. The third transistor M3 and the sixth transistor M6 turn off, and correspondingly, the potential of the second connection node PD becomes high. The output signal of the output terminal OP of the shift register unit is a low level signal.

[0061] Figure 2 is a signal timing diagram of the shift register unit shown in Figure 1 under ideal conditions. However, the inventors of this application realized that during the actual operation of the gate driver or display device, the potential changes of the aforementioned connection node PU and connection node PD may compete. For example, when connection node PU is first charged or in the early stage of charging, the potential of connection node PU has not yet risen to a high level, thus the potential of connection node PD is high, and correspondingly, the seventh transistor M7 is in the conducting state. That is to say, at some time, connection node PU is charged, and connection node PU is simultaneously discharged through the seventh transistor M7; that is, the charging and discharging of connection node PU may coexist, as shown by the dashed arrow in Figure 1. If the potential of connection node PU cannot be charged to a normal high level, the shift register unit will not be able to output a normal scanning signal, resulting in interlaced display in the display device.

[0062] Embodiments of this application provide a shift register unit, including: an input circuit, a first output circuit, a first node discharge circuit, a first output discharge circuit, a first node potential control circuit, a first reset circuit, and a first output control circuit. Figure 3 illustrates the structural block diagram of the shift register unit. As shown in Figure 3, the input circuit 101 is electrically connected to the input terminal IN and the first node PU, and is configured to control the potential of the first node PU based on the input signal received from the input terminal; the first output circuit 102 is electrically connected to the clock signal receiving terminal CLK, the first node PU, and the first output terminal OP1, and is configured to provide a first output signal to the first output terminal OP1 based on the clock signal received by the clock signal receiving terminal CLK under the control of the potential of the first node PU; the first node discharge circuit 103 is electrically connected to the second node PD and the first node PU, and is configured to discharge the first node PU under the control of the potential of the second node PD; the first output discharge circuit 104 is electrically connected to the second node PD and the first output terminal OP1, and is configured to discharge the first output terminal OP1 under the control of the potential of the second node PD; the first node potential control circuit 105 is electrically connected to the first control signal receiving terminal CT1, the second control signal receiving terminal CT2, the second node PD, and the first reference voltage terminal VR1, and is configured to... Under the control of the first control signal received by the control signal receiving terminal CT1, the potential of the second node PD becomes the first reference voltage of the first reference voltage terminal VR1 before the effective level of the input signal IN arrives. Under the control of the second control signal received by the second control signal receiving terminal CT2, the potential of the second node PD becomes the first reference voltage during the effective level of the first output signal provided by the first output circuit 102. The first reset circuit 106 is electrically connected to the first reset signal receiving terminal RE1 and the first node PU, and is configured to reset the first node PU under the control of the first reset signal received by the first reset signal receiving terminal RE1. The first output control circuit 107 is electrically connected to at least one of the first reset signal receiving terminal RE1 and the input terminal IN, and is electrically connected to the first output terminal OP1 and the first reference voltage terminal VR1. It is configured to make the potential of the first output terminal OP1 become the first reference voltage during the reset of the first node PU under the control of the first reset signal or the input signal. In the example of Figure 3, the first output control circuit 107 is electrically connected to one of the first reset signal receiving terminal RE1 and the input terminal IN. In other embodiments, the first output control circuit 107 may be electrically connected to both the first reset signal receiving terminal RE1 and the input terminal IN.

[0063] In the shift register unit provided in this application embodiment, the first node potential control circuit can, under the control of a first control signal, make the potential of the second node become the first reference voltage of the first reference voltage terminal before the effective level of the input signal arrives, and under the control of a second control signal, make the potential of the second node become the first reference voltage during the effective level of the first output signal provided by the first output circuit. When the input terminal of the shift register unit receives the effective level of the input signal, the first node can begin to be charged. However, before the effective level of the input signal arrives, the potential of the second node is controlled by the first node potential control circuit to be the first reference voltage. This ensures that the potential of the second node is at a stable first reference voltage (e.g., low level) during the charging period of the first node, thereby avoiding the simultaneous charging and discharging of the first node and promoting the normal output of the first output signal of the shift register unit. In addition, the first node potential control circuit can use a second control signal to make the potential of the second node become the first reference voltage during the effective level of the first output signal provided by the first output circuit. This can further facilitate the effective level of the first output signal of the first output circuit to follow the clock signal and be free from interference from other signals. Furthermore, the first output control circuit can receive at least one of the first reset signal and the input signal and is electrically connected to the first output terminal and the first reference voltage terminal. Under the control of the first reset signal or the input signal, the potential of the first output terminal becomes the first reference voltage during the period when the first node is reset. In other words, during the time period when the first node is reset using the effective level of the first reset signal, the potential of the first output terminal can be effectively fixed to the first reference voltage, avoiding the possibility that the first output terminal is in a floating state during the time period when the first node is reset, thereby preventing the display device from displaying abnormally.

[0064] According to another embodiment of this application, the shift register unit further includes a second node discharge circuit, a second output discharge circuit, and a second node potential control circuit. Figure 4 illustrates a structural block diagram of the shift register unit provided in this embodiment. As shown in Figure 4, in order to distinguish the different nodes in the shift register unit, the first node mentioned above is still represented by PU, the second node mentioned above is represented by PD1 in Figure 4, and PD2 in Figure 4 represents the third node. The shift register unit includes: a second node discharge circuit 108 electrically connected to a third node PD2 and a first node PU, configured to discharge the first node PU under the control of the potential of the third node PD2; a second output discharge circuit 109 electrically connected to the third node PD2 and the first output terminal OP1, configured to discharge the first output terminal OP1 under the control of the potential of the third node PD2; and a second node potential control circuit 110 electrically connected to the first control signal receiving terminal CT1, the second control signal receiving terminal CT2, the third node PD2, and the first reference voltage terminal VR1, configured to, under the control of the first control signal, make the potential of the third node PD2 become the first reference voltage of the first reference voltage terminal VR1 before the effective level of the input signal arrives, and under the control of the second control signal, make the potential of the third node PD2 become the first reference voltage during the period when the first output circuit 102 provides the effective level of the first output signal. Compared to the embodiment shown in Figure 3, the shift register unit shown in Figure 4 adds a second node discharge circuit, a second output discharge circuit, and a second node potential control circuit, and forms an additional third node PD2. The third node PD2 can affect the potential changes of the first node PU and the first output terminal OP1 in a similar manner to the second node PD1. Therefore, the embodiment shown in Figure 4 can further ensure the stability of the output signal of the first output terminal OP1 of the shift register unit.

[0065] Figure 5 illustrates a structural block diagram of a shift register unit according to another embodiment of this application. As shown in Figure 5, in addition to the various circuit modules in the shift register unit shown in Figure 4, the shift register unit further includes: a second output circuit 111 electrically connected to the first node PU and the second output terminal OP2, configured to receive the clock signal to provide a second output signal to the second output terminal OP2 based on the clock signal under the control of the potential of the first node PU; and a third output discharge circuit 112 electrically connected to the second node PD1, the third node PD2, and the second output terminal OP2, configured to discharge the second output terminal under the control of the potentials of the second node PD1 and the third node PD2. In this embodiment, since the second output circuit 111 is also electrically connected to the first node PU and provides the second output signal to the second output terminal OP2 based on the clock signal under the control of the potential of the first node PU, the second output signal output by the second output terminal OP2 can be the same as the first output signal output by the first output terminal. In some embodiments, when multiple shift register units are cascaded together to form a gate drive circuit, the first control signal received by the first control signal receiving terminal of each shift register unit, the second control signal received by the second control signal receiving terminal, and the first reset signal received by the first reset signal receiving terminal can be the first output signal output by the first output terminal of the preceding or following shift register unit. In the embodiment shown in FIG5, the first control signal received by the first control signal receiving terminal of each shift register unit, the second control signal received by the second control signal receiving terminal, and the first reset signal received by the first reset signal receiving terminal can be the second output signal output by the second output terminal of the preceding or following shift register unit. The first output signal output by the first output terminal of each shift register unit is normally used to scan the gate line or scan line, thereby avoiding the situation where the first output signal of the shift register unit is used as both a scan signal for scanning the gate line or scan line and a control signal or reset signal provided to other shift register units. This is beneficial for improving the driving capability of the first output signal for the gate line or scan line.

[0066] Figure 6 illustrates a structural block diagram of a shift register unit according to another embodiment of this application. Based on the shift register unit shown in Figure 5, the shift register unit shown in Figure 6 further includes: a second output control circuit 113 electrically connected to the second output terminal OP2 and the first reference voltage terminal VR1, configured to receive at least one of the first reset signal and the input signal, so that, under the control of the first reset signal or the input signal, the potential of the second output terminal OP2 becomes the first reference voltage during the reset of the first node. The second output control circuit 113 can use the first reset signal or the input signal to stabilize the potential of the second output terminal OP2 at the first reference voltage during the reset of the first node, thereby avoiding the possibility that the second output terminal OP2 may be in a floating state.

[0067] According to some embodiments of this application, the shift register unit further includes a second reset circuit electrically connected to a second reset signal receiving terminal, the first node, and the first output terminal. This circuit receives at least one of the first reset signal and the input signal and resets the first node and the first output terminal under the control of the second reset signal received at the second reset signal receiving terminal. The second reset circuit mentioned herein can be incorporated into the shift register unit described in any of the foregoing embodiments. Figure 7 illustrates a structural block diagram of a shift register unit provided according to another embodiment of this application. Compared to the shift register unit shown in Figure 3, the shift register unit shown in Figure 7 further includes a second reset circuit 114 electrically connected to a second reset signal receiving terminal RE2, the first node PU, and the first output terminal OP1. This circuit is configured to reset the first node PU and the first output terminal OP1 under the control of the second reset signal received at the second reset signal receiving terminal RE2. In some embodiments, multiple such shift register units can be cascaded to form a gate driver. Each shift register unit can receive the same second reset signal, thereby enabling a unified reset of the first node and first output terminal of all shift register units using the second reset signal.

[0068] The above describes structural block diagrams of different embodiments of shift register units. These shift register units can be applied to gate drivers or gate drive circuits of display devices to achieve scanning of each gate line or scan line of the display device. Based on these shift register units, gate drivers for forward scanning (e.g., scanning sequentially from the first row of gate lines to the last row of gate lines) or reverse scanning (e.g., scanning sequentially from the last row of gate lines to the first row of gate lines), as well as gate drivers for both forward and reverse scanning, can be implemented. Using the shift register units provided in the embodiments herein, the simultaneous charging and discharging of the first node can be avoided, promoting the output of a normal first output signal from the first output circuit of the shift register unit. Furthermore, the first node potential control circuit in the shift register unit can make the potential of the second node a first reference voltage during the effective level of the first output signal provided by the first output circuit. This further facilitates the effective level of the first output signal of the first output circuit following the clock signal, free from interference from other signals. Moreover, the first output control circuit can effectively fix the potential of the first output terminal to the first reference voltage during the period when the first node is reset, avoiding the possibility that the first output terminal is in a floating state during the period when the first node is reset, thereby preventing the display device from displaying abnormally.

[0069] The following examples further illustrate the more detailed circuit implementation of the shift register unit. In each example below, the specific circuit of the shift register unit is explained using the assumption that all transistors in the shift register unit are N-type transistors (e.g., N-type MOSFETs).

[0070] In some embodiments, the input circuit of the shift register unit includes a first transistor, a first terminal and a control terminal of the first transistor electrically connected to the input terminal, and a second terminal of the first transistor electrically connected to the first node. The first reset circuit includes a second transistor, a control terminal of the second transistor electrically connected to the first reset signal receiving terminal, a first terminal of the second transistor electrically connected to the first node, and a second terminal of the second transistor electrically connected to the first reference voltage terminal. As shown in Figures 8 to 10, the input circuit includes a first transistor M1, a first terminal and a control terminal of the first transistor M1 electrically connected to the input terminal G(N-1), and a second terminal of the first transistor M1 electrically connected to the first node PU(N). The first reset circuit includes a second transistor M2, a control terminal of the second transistor M2 electrically connected to the first reset signal receiving terminal G(N+1), a first terminal of the second transistor M2 electrically connected to the first node PU(N), and a second terminal of the second transistor electrically connected to the first reference voltage terminal VR1. Figures 8 through 10 and subsequent figures show specific circuit diagrams of the shift register unit in the Nth stage of the gate driver. In these examples, the first node is denoted by PU(N). The first reset signal received by the first reset signal receiver and the input signal received by the input terminal come from the first output terminal of the shift register unit in other stages. Therefore, G(N+1) or G(N-1) is used to represent the first reset signal receiver or input terminal. However, G(N+1) or G(N-1) does not necessarily mean that the first reset signal or input signal comes from the shift register unit in the adjacent stage of the Nth stage shift register unit, which will be further described in the embodiments for the gate driver later. The embodiments in Figures 8 through 10 implement a shift register unit with unidirectional scanning function using a simpler circuit.

[0071] Referring again to Figure 8, the first output circuit includes a third transistor M3 and a capacitor C1. The first and second terminals of the capacitor C1 are electrically connected to the control terminal and the second terminal of the third transistor M3, respectively. The first terminal of the third transistor M3 is electrically connected to the clock signal receiving terminal CLK. The first node potential control circuit includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first terminal of the fourth transistor M4 is electrically connected to the second node PD, and the second terminal of the fourth transistor M4 is electrically connected to the first reference voltage terminal VR1. The control terminal of the fourth transistor M4 is electrically connected to the first control signal receiving terminal PU(N-1). The control terminal and the first terminal of the fifth transistor M5 are electrically connected to the second reference voltage terminal VR2 (the second reference voltage of the second reference voltage terminal is, for example, a constant high level). The second terminal of the fifth transistor M5 is electrically connected to the second node PD. The control terminal of the sixth transistor M6 is electrically connected to the second control signal receiving terminal PU(N+1), and the first and second terminals of the sixth transistor M6 are electrically connected to the second node PD and the first reference voltage terminal VR1, respectively. In this example and subsequent related examples, the first control signal and the second control signal received by the first control signal receiver and the second control signal receiver respectively come from the first node of the shift register unit of other stages. However, PU(N+1) or PU(N-1) does not mean that the second control signal or the first control signal necessarily comes from the shift register unit of the adjacent stage of the shift register unit of the Nth stage, which will be further described in the embodiments for the gate driver later.

[0072] As shown in Figure 8, the first output control circuit of the shift register unit includes a seventh transistor M7. The first and second terminals of the seventh transistor M7 are electrically connected to the first output terminal G(N) and the first reference voltage terminal VR1, respectively. The control terminal of the seventh transistor M7 is electrically connected to the first reset signal receiving terminal G(N+1). In Figure 8 and subsequent figures, G(N) represents the first output terminal of the Nth stage shift register unit. The first node discharge circuit includes an eighth transistor M8. The first and second terminals of the eighth transistor are electrically connected to the first node PU(N) and the first reference voltage terminal VR1, respectively. The control terminal of the eighth transistor is electrically connected to the second node PD. The first output discharge circuit includes a ninth transistor M9. The first and second terminals of the ninth transistor are electrically connected to the first output terminal G(N) and the first reference voltage terminal VR1, respectively. The control terminal of the ninth transistor is electrically connected to the second node PD.

[0073] Figure 9 illustrates an exemplary schematic diagram of the signal timing within a single cycle for the shift register unit shown in Figure 8. As shown in Figure 9, during time period t1 to time period t2, the potential of the first node from another shift register unit undergoes a change from a higher first level to a higher second level, and the first output terminal G(N-1) of this other shift register unit becomes high during time period t2. Similarly, during time period t3 to t4, the potential of the first node of another shift register unit undergoes a change from a higher first level to a higher second level, and the first output terminal G(N+1) of this other shift register unit becomes high during time period t4. It can be understood that the potential change of the first node of each shift register unit and the change of the first output signal at the first output terminal are similar to the comparative examples described with respect to Figures 2 and 1. Referring to Figures 8 and 9, during time period t1, the input terminal of the shift register unit shown in Figure 8 has not yet received a valid level of the input signal, the first transistor M1 is in the off state, and the first node PU(N) has not yet been charged. However, the first control signal received by the first control signal receiver PU(N-1) is high, causing the fourth transistor M4 to turn on. Therefore, the potential of the second node PD is pulled down to the first reference voltage (e.g., a negative potential) of the first reference voltage terminal, thus ensuring that the eighth transistor M8 and the ninth transistor M9 are in the off state at this time. Since the second control signal received by the second control signal receiver PU(N+1) is low at this time, the sixth transistor M6 is in the off state at this time. That is to say, the potential of the second node PD has become the first reference voltage of the first reference voltage terminal VR1 before the effective level of the input signal arrives. In time period t2, the input terminal G(N-1) of the shift register unit receives the effective level (high level) of the input signal, the first transistor M1 turns on, the first node PU(N) is charged, and the potential of the first node PU(N) is raised from the low level to a higher first level. The first control signal received by the first control signal receiver PU(N-1) changes from the higher first level to a higher second level. The fourth transistor M4 maintains its previous on state, and the eighth transistor M8 and the ninth transistor M9 maintain their previous off state. The third transistor M3 is in the on state. Since the clock signal of the clock signal receiver CLK is low at this time, the first output signal output by the first output terminal G(N) is low at this time.It can be understood that during the time period t1 before the first node PU(N) is charged and during the time period t2 when the first node PU(N) begins charging, the potential of the second node PD is stably maintained at the first reference voltage. This ensures that the first node PU(N) is not simultaneously discharged during the charging process, promotes the normal rise of the potential of the first node PU(N) in the shift register unit, and ensures that the first output circuit of the shift register unit outputs a normal first output signal. During the time period t3, the clock signal received by the clock signal receiver CLK changes from low level to high level. Due to the bootstrap effect of capacitor C1, the potential of the first node PU(N) jumps from the first level to a higher second level. The third transistor M3 is in the conducting state, and the first output terminal G(N) can output the high-level clock signal as the first output signal. During time period t3, the second control signal received by the second control signal receiver PU(N+1) changes from a previous low level to a higher first level. Correspondingly, the sixth transistor M6 is turned on, so that the potential of the second node PD remains at the previous low level. That is, the potential of the second node PD becomes the first reference voltage during the effective level of the first output signal provided by the first output circuit 102, keeping the ninth transistor M9 in the off state. At the same time, the first reset signal received by the first reset signal receiver G(N+1) is at a low level, and the seventh transistor M7 and the second transistor M2 are in the off state. This ensures that the first output circuit stably outputs the first output signal during time period t3. During time period t4, the first reset signal received by the first reset signal receiver G(N+1) becomes high, thereby turning on the second transistor M2 and the seventh transistor M7. Correspondingly, the potential of the first node PU(N) is pulled down from the previous second level to the first reference voltage (low level). That is, the first node PU(N) is reset during time period t4. The third transistor M3 is in the off state. The second control signal received by the second control signal receiver PU(N+1) changes from the previous first level to a higher second level. The sixth transistor M6 maintains the previous on state. The potential of the second node PD remains at the low level of the first reference voltage. The eighth transistor M8 and the ninth transistor M9 are in the off state. In addition, since the control terminal of the seventh transistor M7 in the first output control circuit is turned on by receiving a high-level second control signal, the potential of the first output terminal G(N) of the shift register unit can be stabilized at the first reference voltage (low level) during the reset of the first node PU(N), thereby effectively preventing the first output terminal G(N) of the shift register unit from being in a floating state during the reset period and preventing the display device from displaying abnormally.

[0074] According to another embodiment of this application, the first node potential control circuit in the shift register unit further includes a tenth transistor and an eleventh transistor connected in series between the second reference voltage terminal and the first reference voltage terminal. The first terminal and the control terminal of the tenth transistor are respectively electrically connected to the first terminal and the second terminal of the fifth transistor. The first terminal and the second terminal of the eleventh transistor are respectively electrically connected to the second terminal of the tenth transistor and the first reference voltage terminal. The control terminal of the eleventh transistor is electrically connected to the control terminal of the fourth transistor. Figure 10 illustrates the circuit schematic of the shift register unit provided in this embodiment. As shown in Figure 10, the shift register unit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, similar to those shown in Figure 8. The first node potential control circuit also includes a tenth transistor M10 and an eleventh transistor M11 connected in series between the second reference voltage terminal VR2 and the first reference voltage terminal VR1. The first terminal and control terminal of the tenth transistor M10 are electrically connected to the first terminal and the second terminal of the fifth transistor M5, respectively. The first terminal and the second terminal of the eleventh transistor M11 are electrically connected to the second terminal of the tenth transistor M10 and the first reference voltage terminal VR1, respectively. The control terminal of the eleventh transistor M11 is electrically connected to the control terminal of the fourth transistor M4. The working principle and process of the shift register unit shown in Figure 10 are roughly the same as those of the shift register unit shown in Figure 8. However, compared to the shift register unit shown in Figure 8, the amplitude of the current in the internal branch of the first node potential control circuit can be suppressed, thus avoiding excessive instantaneous inrush current. For example, when the first control signal received by the first control signal receiving terminal PU(N-1) changes from a low level to a higher first level, the eleventh transistor M11 and the fourth transistor M4 are turned on simultaneously. Correspondingly, the control terminal of the tenth transistor M10 receives the first reference voltage, thereby turning the tenth transistor M10 off, thus suppressing the instantaneous large current that may flow from the second reference voltage terminal to the first reference voltage terminal via the second node PD.

[0075] The shift register unit shown in Figure 10 also includes the aforementioned second reset circuit. As shown in Figure 10, the second reset circuit includes a twelfth transistor M12 and a thirteenth transistor M13. The control terminals of the twelfth transistor M12 and the thirteenth transistor M13 are electrically connected to the second reset signal receiving terminal RE2. The first terminals of the twelfth and thirteenth transistors are electrically connected to the first node PU(N) and the first output terminal G(N), respectively. The second terminals of the twelfth and thirteenth transistors are electrically connected to the first reference voltage terminal VR1. When the second reset signal receiving terminal of the second reset circuit receives an effective level (high level) of the second reset signal, the twelfth and thirteenth transistors are turned on, thereby pulling down the potentials of the first node PU(N) and the first output terminal G(N) of the shift register unit to the first reference voltage, thus resetting the first node PU(N) and the first output terminal G(N). In some embodiments, the second reset signal receiving terminals of each shift register unit in the gate drive circuit can be connected together to receive the same second reset signal, thereby enabling unified reset of the first node and first output terminal of all shift register units.

[0076] Figure 11 illustrates a circuit diagram of a shift register unit according to another embodiment of this application. In this embodiment, the first node potential control circuit is in the same form as the embodiment shown in Figure 8, and the shift register unit includes the second reset circuit shown in Figure 10.

[0077] According to another embodiment of this application, the input circuit of the shift register unit includes a first transistor, the control terminal of the first transistor is electrically connected to the input terminal, a first terminal of the first transistor is electrically connected to a third control signal receiving terminal, and a second terminal of the first transistor is electrically connected to the first node. The first reset circuit includes a second transistor, the control terminal of the second transistor is electrically connected to the first reset signal receiving terminal, a first terminal of the second transistor is electrically connected to the first node, and a second terminal of the second transistor is electrically connected to a fourth control signal receiving terminal. The third control signal received by the third control signal receiving terminal is out of phase with the fourth control signal received by the fourth control signal receiving terminal. Compared with the various embodiments discussed previously with reference to Figures 3 to 11, the gate drive circuit of the shift register unit provided by this embodiment can realize a dual scanning mode of forward scanning and reverse scanning. For example, Figure 12 illustrates an example of a shift register unit. As shown in Figure 12, the input circuit includes a first transistor M1, the control terminal of which is electrically connected to the input terminal G(N-1), the first terminal of which is electrically connected to a third control signal receiving terminal VDS, and the second terminal of which is electrically connected to the first node PU(N). The first reset circuit includes a second transistor M2, the control terminal of which is electrically connected to the first reset signal receiving terminal G(N+1), the first terminal of which is electrically connected to the first node PU(N), and the second terminal of which is electrically connected to a fourth control signal receiving terminal VSD. The third control signal received by the third control signal receiving terminal VDS is out of phase with the fourth control signal received by the fourth control signal receiving terminal VSD. In some embodiments, the first output control circuit may further include a fourteenth transistor, the control terminal of which is electrically connected to the input terminal, and the first and second terminals of which are electrically connected to the first output terminal and the first reference voltage terminal, respectively. As shown in Figure 12, the first output control circuit includes a seventh transistor M7 and a fourteenth transistor M14. The control terminal of the fourteenth transistor is electrically connected to the input terminal G(N-1), and the first terminal and the second terminal of the fourteenth transistor are electrically connected to the first output terminal G(N) and the first reference voltage terminal VR1, respectively.

[0078] Figure 13 illustrates an example of a signal timing diagram for the shift register unit shown in Figure 12. The left side of Figure 13 shows the signal timing of a single shift register unit in a single cycle when the gate drivers of multiple cascaded shift register units as shown in Figure 12 are operating in forward scan mode. The right side of Figure 13 shows the signal timing of a single shift register unit in a single cycle when the gate drivers of multiple cascaded shift register units as shown in Figure 12 are operating in reverse scan mode. When the gate driver is operating in forward scan mode, the third control signal received by the third control signal receiver VDS is high, and the fourth control signal received by the fourth control signal receiver VSD is low. When the gate driver is operating in reverse scan mode, the third control signal received by the third control signal receiver VDS is low, and the fourth control signal received by the fourth control signal receiver VSD is high. The operation of the shift register unit in forward scan mode is substantially similar to the operation described previously with reference to Figure 9. As shown in the left figure of Figure 13, before the high-level signal of the input signal received at input terminal G(N-1) arrives, the first control signal received at the first control signal receiving terminal PU(N-1) is at a higher first level, causing the fourth transistor M4 to turn on. Correspondingly, the potential of the second node PD is controlled at the first reference voltage (e.g., low level), causing the eighth transistor M8 and the ninth transistor M9 to be in the off state. When the input signal received at input terminal G(N-1) becomes high, the first transistor M1 turns on, the first node PU(N) is charged, and the potential of the first node PU(N) changes from the previous low level to a higher first level. The third transistor M3 turns on, and the first control signal received at the first control signal receiving terminal PU(N-1) becomes a higher second level. Therefore, the eighth transistor M8 remains in the previous off state. Therefore, during the charging process of the first node PU(N), there is no discharge path for the first node PU(N). When the input signal received at input terminal G(N-1) changes from high to low, the signal received at clock signal receiver CLK changes from low to high. Due to the bootstrap effect of capacitor C1, the potential of the first node PU(N) jumps from the previously higher first level to a higher second level. The third transistor M3 remains on. Therefore, the first output terminal G(N) of the shift register unit outputs a high-level first output signal. Meanwhile, the second control signal received at the second control signal receiver PU(N+1) changes from low to a higher first level, and the first reset signal received at the first reset signal receiver G(N+1) is at a low level. The sixth transistor M6 is on, the potential of the second node PD is maintained at the first reference voltage, and the ninth transistor M9 and the seventh transistor M7 are off, ensuring the normal output of the first output signal at the first output terminal G(N).Next, the first reset signal received by the first reset signal receiver G(N+1) becomes high, which turns on the second transistor M2 and the seventh transistor M7. Therefore, during the time when the first node PU(N) is reset, the output signal of the first output terminal G(N) is stabilized at the first reference voltage, thus avoiding abnormal output of the first output terminal of the shift register unit.

[0079] In reverse scan mode, the third control signal received by the third control signal receiver VDS is at a low level, and the fourth control signal received by the fourth control signal receiver VSD is at a high level. The first reset signal received by the first reset signal receiver G(N+1) of the shift register unit is equivalent to the input signal in forward scan mode, and the input signal received by the input terminal G(N-1) is equivalent to the first reset signal in forward scan mode. As shown in the right figure of Figure 13, during time period t1, the second control signal received by the second control signal receiver PU(N+1) changes from a low level to a higher first level, the sixth transistor M6 is turned on, and the potential of the second node PD is controlled to the first reference voltage (low level). During time period t2, the first reset signal received by the first reset signal receiver G(N+1) changes from a low level to a high level, the second transistor M2 is turned on, the first node PU(N) is charged through the second transistor M2, the second control signal changes from the previous first level to a higher second level, the sixth transistor M6 remains turned on, and the potential of the second node PD remains low. Therefore, during the charging period of the first node PU(N), there is no discharge path for discharging the first node PU(N), ensuring the normal output of the shift register unit. In time period t3, the first control signal received by the first control signal receiver PU(N-1) becomes a higher first level, and the clock signal received by the clock signal receiver CLK changes from a low level to a high level. Due to the bootstrap effect of capacitor C1, the potential of the first node PU(N) further increases to a higher second level, and the third transistor M3 turns on, causing the first output terminal G(N) to output a high-level clock signal. In time period t4, the input terminal G(N-1) receives a high-level signal, causing the first transistor M1 to turn on, and the first node PU(N) is reset. Simultaneously, the control terminal of the fourteenth transistor M14 in the first output control circuit receives a high-level input signal and turns on. The potential of the first output terminal G(N) is effectively controlled to the first reference voltage, avoiding the possibility that the potential of the first output terminal might be in an uncertain state during the reset period of the first node PU(N), thereby preventing abnormal display of the display device. It can be seen that the seventh transistor M7 and the fourteenth transistor M14 in the first output control circuit can stabilize the potential of the first output terminal G(N) in both forward and reverse scan modes, respectively, thus preventing possible abnormal outputs from the shift register unit in both modes. Furthermore, the waveform of the clock signal received by the clock signal receiver CLK is not shown in Figure 13, but it can be the same as the waveform of the clock signal shown in Figure 9.

[0080] Figure 14 illustrates a variant embodiment based on the shift register unit shown in Figure 12. The first node potential control circuit differs from that shown in Figure 12. As shown in Figure 14, the first node potential control circuit further includes a tenth transistor M10 and an eleventh transistor M11 connected in series between the second reference voltage terminal VR2 and the first reference voltage terminal VR1. The first terminal and control terminal of the tenth transistor M10 are electrically connected to the first and second terminals of the fifth transistor M5, respectively. The first and second terminals of the eleventh transistor M11 are electrically connected to the second terminal of the tenth transistor M10 and the first reference voltage terminal VR1, respectively. The control terminal of the eleventh transistor M11 is electrically connected to the control terminal of the fourth transistor M4. The second reference voltage terminal VR2 can receive a fixed-level second reference voltage; when the first reference voltage is negative, the second reference voltage is a fixed positive level. The working principle and process of the shift register unit shown in Figure 14 are largely the same as those of the shift register unit shown in Figure 12, and will not be described in detail here.

[0081] As previously described, in some embodiments, the shift register unit may further include a second node discharge circuit, a second output discharge circuit, and a second node potential control circuit. According to one embodiment of this application, the second output discharge circuit includes a fifteenth transistor, the control terminal of which is electrically connected to the third node, and the first and second terminals of which are respectively electrically connected to the first output terminal and the first reference voltage terminal. The second node discharge circuit includes a sixteenth transistor, the control terminal of which is electrically connected to the third node, and the first and second terminals of which are respectively electrically connected to the first node and the first reference voltage terminal. The second node potential control circuit includes a seventeenth, eighteenth, and nineteenth transistors, the seventeenth and eighteenth transistors being connected in series between the third reference voltage terminal and the first reference voltage terminal. The first terminal and control terminal of the seventeenth transistor are electrically connected to the third reference voltage terminal, the second terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor, the control terminal and second terminal of the eighteenth transistor are respectively electrically connected to the control terminal of the sixth transistor and the first reference voltage terminal, and the control terminal of the nineteenth transistor is electrically connected to the control terminal of the fourth transistor. The first and second terminals of the nineteenth transistor are respectively electrically connected to the third node and the first reference voltage terminal. Figure 15 illustrates the circuit schematic of the shift register unit provided according to this embodiment. In Figure 15, the second node and the third node are represented by PD1 and PD2, respectively, to distinguish them.As shown in Figure 15, the second output discharge circuit of the shift register unit includes a fifteenth transistor M15. The control terminal of the fifteenth transistor M15 is electrically connected to the third node PD2. The first and second terminals of the fifteenth transistor M15 are respectively electrically connected to the first output terminal G(N) and the first reference voltage terminal VR1. The second node discharge circuit includes a sixteenth transistor M16. The control terminal of the sixteenth transistor M16 is electrically connected to the third node PD2. The first and second terminals of the sixteenth transistor are respectively electrically connected to the first node PU(N) and the first reference voltage terminal VR1. The second node potential control circuit includes a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19. Transistor M19, the seventeenth transistor, and the eighteenth transistor are connected in series between the third reference voltage terminal VR3 and the first reference voltage terminal VR1. The first terminal and control terminal of the seventeenth transistor M17 are electrically connected to the third reference voltage terminal VR3, and the second terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor M18. The control terminal and the second terminal of the eighteenth transistor M18 are respectively electrically connected to the control terminal of the sixth transistor M6 and the first reference voltage terminal VR1. The control terminal of the nineteenth transistor M19 is electrically connected to the control terminal of the fourth transistor M4, and the first terminal and the second terminal of the nineteenth transistor are respectively electrically connected to the third node PD2 and the first reference voltage terminal VR1.

[0082] Figure 16 illustrates a variant embodiment based on the shift register unit shown in Figure 15. As shown in Figure 16, in addition to the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6, the first node potential control circuit also includes a tenth transistor M10 and an eleventh transistor M11 connected in series between the second reference voltage terminal VR2 and the first reference voltage terminal VR1. The first terminal and control terminal of the tenth transistor M10 are electrically connected to the first terminal and the second terminal of the fifth transistor, respectively. The first terminal and the second terminal of the eleventh transistor M11 are electrically connected to the second terminal of the tenth transistor and the first reference voltage terminal, respectively. The control terminal of the eleventh transistor... The second node potential control circuit also includes a twentieth transistor M20 and a twenty-first transistor M21 connected in series between the third reference voltage terminal VR3 and the first reference voltage terminal VR1. The first terminal and control terminal of the twentieth transistor M20 are electrically connected to the first terminal and the second terminal of the seventeenth transistor M17, respectively. The first terminal and the second terminal of the twenty-first transistor M21 are electrically connected to the second terminal of the twentieth transistor M20 and the first reference voltage terminal VR1, respectively. The control terminal of the twenty-first transistor M21 is electrically connected to the control terminal of the eighteenth transistor M18. Compared to the shift register unit shown in Figure 15, the amplitude of the current in the internal branches of the first node potential control circuit and the second node potential control circuit in the shift register unit shown in Figure 16 can be suppressed, thus avoiding excessive instantaneous inrush current. For example, when the first control signal received at the first control signal receiving terminal PU(N-1) changes from a low level to a higher first level, the eleventh transistor M11 and the fourth transistor M4 are simultaneously turned on. Correspondingly, the control terminal of the tenth transistor M10 receives the first reference voltage, thereby turning the tenth transistor M10 off and suppressing a potentially large instantaneous current that might flow from the second reference voltage terminal through the second node PD1 to the first reference voltage terminal. Similarly, a potentially large instantaneous current that might flow from the third reference voltage terminal VR3 through the third node PD2 to the first reference voltage terminal can also be suppressed.

[0083] Figure 17 illustrates another variant embodiment based on the shift register unit shown in Figure 15. The gate driver using the shift register unit shown in Figure 17 can operate in both forward and reverse scan modes. As shown in Figure 17, the shift register unit includes a third control signal receiver VDS and a fourth control signal receiver VSD. The third control signal received by the third control signal receiver and the fourth control signal received by the fourth control signal receiver can be complementary signals. For example, the third control signal can be a constant high-level signal, while the fourth control signal is a constant low-level signal, or the third control signal can be a constant low-level signal, while the fourth control signal is a constant high-level signal. As shown in Figure 17, the first terminal of the first transistor M1 is electrically connected to the third control signal receiver VDS, and the second terminal of the second transistor M2 is electrically connected to the fourth control signal receiver VSD. The first output control circuit includes a seventh transistor M7 and a fourteenth transistor M14. The control terminal of the fourteenth transistor is electrically connected to the input terminal G(N-1), and the first and second terminals of the fourteenth transistor are respectively electrically connected to the first output terminal G(N) and the first reference voltage terminal VR1. In some embodiments, when the third control signal is a constant high-level signal and the fourth control signal is a constant low-level signal, the shift register unit shown in FIG17 operates in forward scanning mode. At this time, the seventh transistor M7 in the first output control circuit can stabilize the potential of the first output terminal G(N) to the first reference voltage during the reset of the first node PU(N). When the third control signal is a constant low-level signal and the fourth control signal is a constant high-level signal, the shift register unit shown in FIG17 operates in reverse scanning mode. At this time, the fourteenth transistor M14 in the first output control circuit can stabilize the potential of the first output terminal G(N) to the first reference voltage during the reset of the first node PU(N).

[0084] Figure 18 illustrates a variant embodiment based on the shift register unit shown in Figure 17. The gate driver using the shift register unit shown in Figure 18 can operate in both forward and reverse scan modes. As shown in Figure 18, in addition to the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6, the first node potential control circuit also includes a tenth transistor M10 and an eleventh transistor M11 connected in series between the second reference voltage terminal VR2 and the first reference voltage terminal VR1. The first terminal and control terminal of the tenth transistor M10 are electrically connected to the first terminal and the second terminal of the fifth transistor, respectively. The first terminal and the second terminal of the eleventh transistor M11 are electrically connected to the second terminal of the tenth transistor and the first reference voltage terminal, respectively. The control terminal of the eleventh transistor is electrically connected to the control terminal of the fourth transistor M4. In addition to the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19, the second node potential control circuit also includes a twentieth transistor M20 and a twenty-first transistor M21 connected in series between the third reference voltage terminal VR3 and the first reference voltage terminal VR1. The first terminal and the control terminal of the twentieth transistor M20 are electrically connected to the first terminal and the second terminal of the seventeenth transistor M17, respectively. The first terminal and the second terminal of the twenty-first transistor M21 are electrically connected to the second terminal of the twentieth transistor M20 and the first reference voltage terminal VR1, respectively. The control terminal of the twenty-first transistor M21 is electrically connected to the control terminal of the eighteenth transistor M18.

[0085] Figure 19 illustrates a waveform diagram of the signal timing diagram applicable to the shift register unit shown in Figure 18 or Figure 17 within a single cycle. The left diagram in Figure 19 is the signal timing diagram for forward scan mode, and the right diagram in Figure 19 is the signal timing diagram for reverse scan mode. In some embodiments, the second reference voltage of the second reference voltage terminal VR2 and the third reference voltage of the third reference voltage terminal VR3 can be pulse signals with opposite phases. However, within a single operating cycle of the shift register unit, the second reference voltage and the third reference voltage can each maintain a constant level. For example, within a single cycle, the second reference voltage and the third reference voltage can be a high-level signal and a low-level signal, respectively. In some embodiments, the second reset signal received by the second reset signal receiving terminal RE2 is a pulse signal alternating between high and low levels. However, the effective level of the second reset signal only exists during the interval between switching between different frames of image display by the display device. During the time of displaying a single frame image, the second reset signal remains at an ineffective level (e.g., low level). Therefore, Figure 19 does not illustrate the second reset signal at the second reset signal receiver RE2, the second reference voltage at the second reference voltage receiver VR2, or the third reference voltage at the third reference voltage receiver VR3. By referring to Figure 19 and Figure 17 or 18, it can be understood that the signal change processes of the shift register unit shown in Figure 17 or 18 at the input G(N-1), first reset signal receiver G(N+1), first node PU(N), second node PD1, first output G(N), first control signal receiver PU(N-1), and second control signal receiver PU(N+1) are similar to those described with reference to Figure 9. Furthermore, the potential change of the third node PD2 is approximately the same as the potential change of the second node PD1.

[0086] As previously described, in some embodiments, the shift register unit may further include a second output circuit and a third output discharge circuit. The second output circuit is electrically connected to the clock signal receiving terminal, the first node, and the second output terminal to provide a second output signal to the second output terminal based on the clock signal under the control of the potential of the first node. The third output discharge circuit is electrically connected to the second node, the third node, and the second output terminal to discharge the second output terminal under the control of the potentials of the second node and the third node. The arrangement of the second output circuit can prevent the first output signal of the shift register unit from being used both as a scan signal for scanning the gate line or scan line and as a control signal or reset signal provided to other shift register units. Figure 20 illustrates a circuit schematic of a shift register unit according to another embodiment of this application. As shown in Figure 20, the shift register unit includes a first output circuit and a second output circuit. The first output circuit includes a third transistor M3 and a capacitor C1. The second output circuit includes a twenty-second transistor M22. The control terminal of the twenty-second transistor is electrically connected to the first node PU(N). The first and second terminals of the twenty-second transistor are respectively electrically connected to the clock signal receiving terminal CLK and the second output terminal G_C(N). The third output discharge circuit includes a twenty-third transistor M23 and a twenty-fourth transistor M24. The control terminals of the twenty-third and twenty-fourth transistors are respectively electrically connected to the second node PD1 and the third node PD2. The first and second terminals of the twenty-third transistor M23 are respectively electrically connected to the second output terminal G_C(N) and the first reference voltage terminal VR1. The first and second terminals of the twenty-fourth transistor M24 are respectively electrically connected to the second output terminal G_C(N) and the first reference voltage terminal VR1. It is understood that the connection method of the twentieth transistor M23 is the same as that of the ninth transistor M9, and the connection method of the twenty-fourth transistor M24 is the same as that of the fifteenth transistor M15. Therefore, the operating modes of the twenty-third transistor M23 and the twenty-fourth transistor M24 are the same as those of the ninth and fifteenth transistors, respectively. The twenty-second transistor is also controlled by the potential of the first node PU(N). Therefore, the second output circuit can output a second output signal from the second output terminal G_C(N) that is approximately the same as the first output signal provided by the first output circuit. Therefore, in a gate driver that includes multiple shift register units, the second output signal provided by the second output terminal G_C(N) of the shift register unit can be used as an input signal, reset signal, or reset signal provided to other shift register units. Therefore, in Figure 20 and Figures 21 to 23 discussed below, the first reset signal receiving terminal of the shift register unit is represented by G_C(N+1), and the input terminal is represented by G_C(N-1).Referring again to Figure 20, the shift register unit may further include a second output control circuit. This second output control circuit includes a twenty-fifth transistor M25. The control terminal of the twenty-fifth transistor M25 is electrically connected to the first reset signal receiving terminal G_C(N+1). The first and second terminals of the twenty-fifth transistor are respectively electrically connected to the second output terminal G_C(N) and the first reference voltage terminal VR1. By configuring the second output control circuit, the second output circuit can output a stable second output signal during the reset of the first node PU(N), that is, the second output signal is maintained at the first reference voltage during the reset of the first node PU(N), preventing the second output terminal G_C(N) from being in a floating displacement state.

[0087] Figure 21 illustrates a circuit diagram of a shift register unit according to another embodiment of this application. In this embodiment, the shift register unit also includes a second output circuit (including a twenty-second transistor M22), a third output discharge circuit (including a twenty-third transistor M23 and a twenty-fourth transistor M24), and a second output control circuit (including a twenty-fifth transistor M25). The main difference between the shift register unit shown in Figure 21 and the shift register unit shown in Figure 20 lies in the first node potential control circuit and the second node potential control circuit. Compared to the shift register unit shown in Figure 20, the first node potential control circuit in the shift register unit shown in Figure 21 further includes a tenth transistor M10 and an eleventh transistor M11 connected in series between the second reference voltage terminal VR2 and the first reference voltage terminal VR1. The first terminal and control terminal of the tenth transistor M10 are electrically connected to the first terminal and the second terminal of the fifth transistor M5, respectively. The first terminal and the second terminal of the eleventh transistor M11 are electrically connected to the second terminal of the tenth transistor M10 and the first reference voltage terminal VR1, respectively. The control terminal of the eleventh transistor M11 is electrically connected to the control terminal of the fourth transistor M4. Furthermore, the second node potential control circuit in the shift register unit shown in Figure 21 also includes a twentieth transistor M20 and a eleventh transistor M21 connected in series between the third reference voltage terminal VR3 and the first reference voltage terminal VR1. The first terminal and control terminal of the twentieth transistor M20 are electrically connected to the first terminal and the second terminal of the seventeenth transistor M17, respectively. The first terminal and the second terminal of the eleventh transistor M21 are electrically connected to the second terminal of the twentieth transistor M20 and the first reference voltage terminal VR1, respectively. The control terminal of the eleventh transistor M21 is electrically connected to the control terminal of the eighteenth transistor M18.

[0088] In some embodiments, the second output control circuit in the shift register unit further includes a twenty-sixth transistor. The control terminal of the twenty-sixth transistor is electrically connected to the input terminal, and the first and second terminals of the twenty-sixth transistor are electrically connected to the second output terminal and the first reference voltage terminal, respectively. As shown in FIG22, the control terminal of the twenty-sixth transistor M26 is electrically connected to the input terminal G_C(N-1), and the first and second terminals of the twenty-sixth transistor are electrically connected to the second output terminal G_C(N) and the first reference voltage terminal VR1, respectively. In particular, the first terminal of the first transistor M1 is electrically connected to the third control signal receiving terminal, and the second terminal of the second transistor M2 is electrically connected to the fourth control signal receiving terminal. Therefore, the gate driver of the shift register unit shown in FIG22 can operate in forward scan mode or reverse scan mode under the control of the third and fourth control signals. In forward scanning mode, the seventh transistor M7 in the first output control circuit and the twenty-fifth transistor M25 in the second output circuit can stabilize the potentials of the first output terminal G(N) and the second output terminal G_C(N) to the first reference voltage during the reset of the first node PU(N). In reverse scanning mode, the fourteenth transistor M14 in the first output control circuit and the twenty-sixth transistor M26 in the second output circuit can stabilize the potentials of the first output terminal G(N) and the second output terminal G_C(N) to the first reference voltage during the reset of the first node PU(N), preventing the first output terminal G(N) and the second output terminal G_C(N) from being in a floating state.

[0089] Figure 23 illustrates a variant embodiment based on the shift register unit shown in Figure 22. The gate driver of the shift register unit using the embodiment shown in Figure 2 can also operate in both forward scan mode and reverse scan mode. The main difference between the shift register unit shown in Figure 23 and the shift register unit shown in Figure 22 lies in the first node potential control circuit and the second node potential control circuit. Compared to the shift register unit shown in Figure 22, the first node potential control circuit in the shift register unit shown in Figure 23 further includes a tenth transistor M10 and an eleventh transistor M11 connected in series between the second reference voltage terminal VR2 and the first reference voltage terminal VR1. The first terminal and control terminal of the tenth transistor M10 are electrically connected to the first terminal and the second terminal of the fifth transistor M5, respectively. The first terminal and the second terminal of the eleventh transistor M11 are electrically connected to the second terminal of the tenth transistor M10 and the first reference voltage terminal VR1, respectively. The control terminal of the eleventh transistor M11 is electrically connected to the control terminal of the fourth transistor M4. Furthermore, the second node potential control circuit in the shift register unit of Figure 23 also includes a twentieth transistor M20 and a eleventh transistor M21 connected in series between the third reference voltage terminal VR3 and the first reference voltage terminal VR1. The first terminal and control terminal of the twentieth transistor M20 are electrically connected to the first terminal and the second terminal of the seventeenth transistor M17, respectively. The first terminal and the second terminal of the eleventh transistor M21 are electrically connected to the second terminal of the twentieth transistor M20 and the first reference voltage terminal VR1, respectively. The control terminal of the eleventh transistor M21 is electrically connected to the control terminal of the eighteenth transistor M18.

[0090] Figure 24 illustrates a waveform diagram of the signal timing diagram applicable to the shift register unit shown in Figure 23 or Figure 22 within a single cycle. The left diagram in Figure 24 is the signal timing diagram for forward scan mode, and the right diagram in Figure 24 is the signal timing diagram for reverse scan mode. In some embodiments, the second reference voltage of the second reference voltage terminal VR2 and the third reference voltage of the third reference voltage terminal VR3 can be pulse signals with opposite phases. However, within a single operating cycle of the shift register unit, the second reference voltage and the third reference voltage can each maintain a constant level. For example, within a single cycle, the second reference voltage and the third reference voltage can be a high-level signal and a low-level signal, respectively. In some embodiments, the second reset signal received by the second reset signal receiving terminal RE2 is a pulse signal alternating between high and low levels. However, the effective level of the second reset signal only exists during the interval between switching between different frames of image display by the display device. During the time of displaying a single frame image, the second reset signal remains at an ineffective level (e.g., low level). Figure 24 does not illustrate the second reset signal at the second reset signal receiver RE2, the second reference voltage at the second reference voltage receiver VR2, and the third reference voltage at the third reference voltage receiver VR3. By referring to Figure 24 and Figure 22 or 23, it can be understood that the signal change processes of the shift register unit shown in Figure 22 or 23 at the input G_C(N-1), the first reset signal receiver G_C(N+1), the first node PU(N), the second node PD1, the first output G(N), the first control signal receiver PU(N-1), and the second control signal receiver PU(N+1) are similar to those described with reference to Figure 9. The signal at the second output G_C(N) is approximately the same as the signal at the first output G(N), and the potential change of the third node PD2 is approximately the same as the potential change of the second node PD1.

[0091] Another embodiment of this application provides a gate driver that may include a plurality of shift register units as described in any of the foregoing embodiments and a plurality of clock signal transmission lines.

[0092] In some embodiments, the gate driver includes N cascaded shift register units and multiple clock signal transmission lines. Each of the N shift register units has the same circuit structure as the shift register unit described in any of the foregoing embodiments. That is, each of the N shift register units includes the same number of transistors, capacitors, and various terminals as the shift register unit described in any of the foregoing embodiments, and the electrical connections between these transistors, capacitors, and corresponding terminals are also substantially the same. The input terminal of each shift register unit is electrically connected to the first output terminal of another shift register unit among the N shift register units. The first reset signal receiving terminal of the shift register unit is electrically connected to the first output terminal of yet another shift register unit among the N shift register units. The first control signal receiving terminal of the shift register unit is electrically connected to the first node in the other shift register unit. The second control signal receiving terminal of the shift register unit is electrically connected to the first node in the yet another shift register unit. The clock signal receiving terminals of any one of the other shift register unit and the yet another shift register unit are respectively electrically connected to different clock signal transmission lines among the multiple clock signal transmission lines, where N is an integer greater than or equal to 3.

[0093] Figure 25 schematically illustrates four cascaded shift register units GOA1, GOA2, GOA3, and GOA4. Each shift register unit includes a clock signal receiver CLK, a first reference voltage terminal VR1, a second reference voltage terminal VR2, a third reference voltage terminal VR3, an input terminal IN, a first control signal receiver PU(N-1), a first output terminal G(N), a first node PU(N), a second control signal receiver PU(N+1), and a first reset signal receiver RE1. The shift register unit shown in Figure 25 may include the circuitry of the shift register units shown in Figures 15, 16, 17, or 18. In Figure 25, the shift register unit also includes a fixed voltage receiver GCH, which can be electrically connected to a voltage transmission line providing a constant voltage (e.g., a positive voltage). This allows the shift register unit to implement the circuitry of the shift register units shown in Figures 8, 10, 11, 12, or 14, in which case the fixed voltage receiver GCH can replace the second reference voltage terminal VR2. Of course, in other embodiments, the shift register unit may not include a fixed voltage receiver GCH. As shown in FIG25, the input IN of each shift register unit (e.g., shift register unit GOA3) is electrically connected to the first output G(N) of another shift register unit GOA1 among the N shift register units. The first reset signal receiver RE1 of shift register unit GOA3 is electrically connected to the first output of yet another shift register unit among the N shift register units (e.g., shift register unit GOA5, the next level after shift register unit GOA4, not shown in FIG25). The first control signal receiver PU(N-1) of shift register unit GOA3 is electrically connected to... The first node PU(N) of the other shift register unit GOA1 and the second control signal receiving terminal PU(N+1) of the shift register unit GOA3 are electrically connected to the first node of the other shift register unit (e.g., shift register unit GOA5). The first output terminal G(N) of the shift register unit GOA3 is electrically connected to the first reset signal receiving terminal RE1 of the other shift register unit GOA1. The first node PU(N) of the shift register unit GOA3 is electrically connected to the second control signal receiving terminal PU(N+1) of the other shift register unit GOA1. The clock signal receiving terminal of any one of the other shift register unit and the other shift register unit is electrically connected to different clock signal transmission lines among the multiple clock signal transmission lines. In other words, the clock signal received by the clock signal receiving terminal of the shift register unit is different from the clock signal received by the clock signal receiving terminal of the other shift register unit or the other shift register unit.For example, the clock signal receiving terminals of shift register units GOA1 and GOA3 are connected to clock signal transmission lines CLK1 and CLK3, respectively. The clock signal receiving terminal of shift register unit GOA5, which is the next level of shift register unit GOA4 (not shown in Figure 25), is electrically connected to clock signal transmission line CLK1.

[0094] In some embodiments, the phase of the clock signal received by the clock signal receiving terminal of any one of the other shift register units and the yet another shift register unit is opposite to the phase of the clock signal received by the clock signal receiving terminal of the shift register unit. For example, the clock signals transmitted by clock signal transmission lines CLK1 and CLK3 are in opposite phases, that is, the first clock signal transmitted by clock signal transmission line CLK1 and the third clock signal transmitted by clock signal line CLK3 are complementary. Further, the second clock signal transmitted by clock signal transmission line CLK2 and the fourth clock signal transmitted by clock signal line CLK4 are complementary, while the pulse waveforms of the first clock signal and the second clock signal may be different from each other, and the pulse waveforms of the third clock signal and the fourth clock signal may be different from each other.

[0095] According to another embodiment of this application, the gate driver includes N cascaded shift register units and multiple clock signal transmission lines. Each of the N shift register units includes an input terminal IN, a first output terminal G(N), a first reset signal receiver G(N+1), a first control signal receiver PU(N-1), a second control signal receiver PU(N+1), a clock signal receiver CLK, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a capacitor C1, and a first node PU. (N), the control terminal of the first transistor M1 is electrically connected to the input terminal IN, the first terminal of the first transistor is electrically connected to the input terminal IN or used to receive a third control signal, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the second terminal of the second transistor is electrically connected to the first reference voltage terminal VR1 or used to receive a fourth control signal, the control terminal of the second transistor is electrically connected to the first reset signal receiving terminal G(N+1), the first terminal and the second terminal of the third transistor are respectively electrically connected to the clock signal receiving terminal and the first output terminal of the shift register unit, and the first terminal of the capacitor C1 is electrically connected to the control terminal of the third transistor. A first node is connected between the first transistor and the second transistor. The second terminal of the capacitor is electrically connected to the first output terminal. The first and second terminals of the ninth transistor are electrically connected to the first output terminal and the first reference voltage terminal, respectively. The control terminal of the ninth transistor is electrically connected to the second node. The first and second terminals of the seventh transistor are electrically connected to the first output terminal G(N) and the first reference voltage terminal VR1, respectively. The control terminal of the seventh transistor is electrically connected to the first reset signal receiving terminal. The fourth and fifth transistors are connected in series between the second reference voltage terminal and the first reference voltage terminal. The first terminal and control terminal of the fifth transistor are electrically connected to the second reference voltage terminal. The second terminal of the fifth transistor is electrically connected to the second node. The first and second terminals of the fourth transistor are electrically connected to the second node and the first reference voltage terminal, respectively. The control terminal of the fourth transistor is electrically connected to the first control signal receiving terminal. The first and second terminals of the sixth transistor are electrically connected to the second node and the first reference voltage terminal, respectively. The control terminal of the sixth transistor is electrically connected to the second control signal receiving terminal. The first and second terminals of the eighth transistor are electrically connected to the first node and the first reference voltage receiving terminal, respectively. The control terminal of the eighth transistor is electrically connected to the second node. In other words, in this embodiment, each of the N shift register units can be a shift register unit as shown in FIG8 or include the first transistor M1 to the ninth transistor M9 as shown in FIG12 and the capacitor C1.The input terminal of the shift register unit is electrically connected to the first output terminal of another shift register unit among the N shift register units. The first reset signal receiving terminal of the shift register unit is electrically connected to the first output terminal of yet another shift register unit among the N shift register units. The first control signal receiving terminal of the shift register unit is electrically connected to the first node in the other shift register unit. The second control signal receiving terminal of the shift register unit is electrically connected to the first node in yet another shift register unit. The clock signal receiving terminals of any one of the other shift register unit and the yet another shift register unit are respectively electrically connected to different clock signal transmission lines among the plurality of clock signal transmission lines, where N is an integer greater than or equal to 3. An example of the connection method of the cascaded N shift register units included in the gate driver in this embodiment can be shown in Figure 25. Figure 26 illustrates N shift register units in a gate driver provided according to another embodiment of this application. In this embodiment, the gate driver includes two clock signal transmission lines, and N shift register units can output N first output signals G(1), G(2)...G(N-1) and G(N) respectively. These N first output signals can be used to drive or scan N gate lines or scan lines in the N-row display device.

[0096] According to some embodiments of this application, as shown in FIG26, the gate driver includes two clock signal transmission lines CLKA and CLKB. The input terminal of the Kth-level shift register unit in the N shift register units is electrically connected to the first output terminal of the (K-1)th-level shift register unit in the N shift register units. The first control signal receiving terminal of the Kth-level shift register unit is electrically connected to the first node of the (K-1)th-level shift register unit. The first output terminal of the Kth-level shift register unit is electrically connected to the first reset signal receiving terminal of the (K-1)th-level shift register unit. The second control signal receiving terminal of the Kth-level shift register unit is electrically connected to the first node of the (K+1)th-level shift register unit in the N shift register units. The first reset signal receiving terminal of the Kth-level shift register unit is electrically connected to the first output terminal of the (K+1)th-level shift register unit. Where N is an integer greater than or equal to 3, and K is an integer greater than 1 and less than N. For example, the input terminal IN of the second-stage shift register unit GOA(2) is electrically connected to the first output terminal G(N) of the first-stage shift register unit GOA(1), the first control signal receiving terminal PU(N-1) of the second-stage shift register unit is electrically connected to the first node PU(N) of the first-stage shift register unit, the first output terminal G(N) of the second-stage shift register unit GOA(2) is electrically connected to the first reset signal receiving terminal RE1 of the first-stage shift register unit, the second control signal receiving terminal PU(N+1) of the second-stage shift register unit GOA(2) is electrically connected to the first node PU(N) of the third-stage shift register unit, and the first reset signal receiving terminal of the second-stage shift register unit GOA(2) is electrically connected to the first output terminal G(N) of the third-stage shift register unit.

[0097] According to another embodiment of this application, the gate driver further includes a first dummy shift register unit and a second dummy shift register unit, each of which has the same circuit structure as each of the N shift register units. The gate driver also includes a frame start signal transmission line. Although both the first dummy shift register unit and the second dummy shift register unit have the same circuit structure as each of the aforementioned N shift register units, the first output signal output from the first output terminal of the first dummy shift register unit and the second dummy shift register unit is not used to drive the gate lines or scan lines in the display device. Therefore, these two shift register units are referred to as the first dummy shift register unit and the second dummy shift register unit. Continuing to refer to FIG26, the gate driver includes a first dummy shift register unit DGOA1, a second dummy shift register unit DGOA2, and a frame start signal transmission line STV for transmitting an image frame start signal. The input terminal IN and the first control signal receiving terminal PU(N-1) of the first dummy shift register unit DGOA1 are electrically connected to the frame start signal transmission line STV. The second control signal receiving terminal PU(N+1) of the first dummy shift register unit DGOA1 is electrically connected to the first node PU(N) of the first-stage shift register unit GOA(1) among the N shift register units. The first reset signal receiving terminal RE1 of the first dummy shift register unit DGOA1 is electrically connected to the first output terminal G(N) of the first-stage shift register unit GOA(1). The first output terminal G(N) of the first dummy shift register unit DGOA1 is electrically connected to the first-stage shift register. The input terminal IN of the shift register unit GOA(1) is connected to the first node PU(N) of the first dummy shift register unit DGOA1. The first control signal receiving terminal PU(N-1) of the first-stage shift register unit GOA(1) is connected to the second control signal receiving terminal PU(N+1) of the first-stage shift register unit GOA(1). The first node PU(N) of the second-stage shift register unit GOA(2) among the N shift register units is connected to the first reset signal receiving terminal RE1 of the first-stage shift register unit GOA(1). The first output terminal G(N) of the second-stage shift register unit GOA(2) among the N shift register units is connected to the first output terminal G(N).The input terminal IN of the second dummy shift register unit DGOA2 is electrically connected to the first output terminal G(N) of the Nth-stage shift register unit GOA(N) among the N shift register units. The first control signal receiving terminal PU(N-1) of the second dummy shift register unit DGOA2 is electrically connected to the first node PU(N) of the Nth-stage shift register unit GOA(N). The first output terminal G(N) of the second dummy shift register unit DGOA2 is electrically connected to the first reset signal receiving terminal RE1 of the Nth-stage shift register unit GOA(N). The first node PU(N) of the second dummy shift register unit DGOA2 is electrically connected to the Nth-stage shift register. The second control signal receiving terminal PU(N+1) of the shift register unit GOA(N), the second control signal receiving terminal PU(N+1) of the second dummy shift register unit DGOA2, and the first reset signal receiving terminal RE1 are electrically connected to the frame start signal transmission line STV. The first control signal receiving terminal PU(N-1) of the Nth stage shift register unit GOA(N) is electrically connected to the first node PU(N) of the (N-1)th stage shift register unit GOA(N-1) among the N shift register units. The input terminal IN of the Nth stage shift register unit GOA(N) is electrically connected to the first output terminal G(N) of the (N-1)th stage shift register unit GOA(N-1). In this embodiment, the first dummy shift register unit and the second dummy shift register unit can provide relevant input signals or control signals to the first stage shift register unit and the last stage shift register unit among the N shift register units, respectively.

[0098] The timing of the input or control signals during the operation of the gate driver shown in Figure 26 is briefly illustrated below using examples. Assume that each shift register unit in the gate driver shown in Figure 26 includes the circuit structure shown in Figure 17 or Figure 18, i.e., the gate driver can operate in forward scan mode and reverse scan mode. Figure 27 illustrates the signal timing of some signals received by the gate driver when it operates in forward scan mode. As shown in Figure 27, when the display device displays an image, there is a display time Ta for the Nth frame, a display time Tc for the N+1th frame, and a blank time or frame switching time Tb between the time periods Ta and Tc. During the frame switching time Tb, the second reset signal receiver of each shift register unit receives a valid second reset signal, causing the first node and first output of the shift register unit to be reset during the frame switching time. The frame start signal transmitted by the frame start signal transmission line has a valid level signal at the beginning of each frame. The clock signals transmitted by the two clock signal lines CLKA and CLKB are out of phase, or in other words, the first clock signal transmitted by clock signal line CLKA and the second clock signal transmitted by clock signal line CLKB are complementary. During the display time Ta or Tc of each frame, the levels of the second reference voltage and the third reference voltage received by the second reference voltage terminal VR2 and the third reference voltage terminal VR3 are constant but opposite to each other. During the display time Ta of the Nth frame, the third reference voltage is a positive voltage VGH and the second reference voltage is a negative voltage VGL. During the display time Tc of the N+1th frame, the third reference voltage is a positive voltage VGL and the second reference voltage is a negative voltage VGH. The levels of the second and third reference voltages switch during the frame switching time Tb. As shown in Figure 27, in the forward scanning mode, the third control signal received by the third control signal receiving terminal VDS is a high level VGH, and the fourth control signal received by the fourth control signal receiving terminal VSD is a low level VGL. In forward scan mode, the waveforms of the input signal of a single shift register unit, the potential of the first node, the first output signal of the first output terminal, and the first reset signal of the first reset signal receiver terminal can be seen in the left figure of Figure 19, and will not be described again here. Figure 28 schematically shows the signal timing of some signals received by the gate driver when it is operating in reverse scan mode. The signal timing shown in Figure 28 is roughly similar to that shown in Figure 27, except that the third control signal received by the third control signal receiver terminal VDS is at a low level VGL, and the fourth control signal received by the fourth control signal receiver terminal VSD is at a high level VGH. In the embodiments shown in Figures 27 and 28, although not illustrated, the first reference voltage of the first reference voltage terminal VR1 can be kept at a constant low level VGL.In reverse scan mode, the waveforms of the input signal of a single shift register unit, the potential of the first node, the first output signal of the first output terminal, and the first reset signal of the first reset signal receiver terminal can be seen in the right figure of Figure 19, and will not be described again here.

[0099] In the case where each shift register unit in the gate driver shown in Figure 26 includes the circuit structure of the shift register unit shown in Figure 12 or Figure 14, the gate driver can also operate in forward scan mode and reverse scan mode. The signal timing of some signals received by the gate driver when operating in forward scan mode and reverse scan mode are shown in Figures 29 and 30, respectively. In this embodiment, the second reference voltage received by the second reference voltage terminal VR2 can be a constant high-level voltage VGH, and the first reference voltage received by the first reference voltage terminal VR1 can be a constant low-level voltage VGL. As shown in Figure 29, when the display device displays an image, there is a display time for the Nth frame image, a display time for the N+1th frame image, and a frame switching time Tb. During the frame switching time Tb, the second reset signal receiving terminal RE2 of each shift register unit receives a valid second reset signal, so that the first node and the first output terminal of the shift register unit are reset during the frame switching time. The frame start signal transmitted by the frame start signal transmission line STV has a valid level signal at the beginning of each frame, and the first clock signal transmitted by the clock signal line CLKA and the second clock signal transmitted by the clock signal line CLKB are complementary. As shown in Figure 29, in the forward scan mode, the third control signal received by the third control signal receiver VDS is at a high level (VGH), and the fourth control signal received by the fourth control signal receiver VSD is at a low level (VGL). The waveforms of the input signal of a single shift register unit, the potential of the first node, the first output signal of the first output terminal, and the first reset signal of the first reset signal receiver can be seen in the left figure of Figure 13, and will not be described again here. Figure 30 schematically shows the signal timing of some signals received by the gate driver when it is operating in the reverse scan mode. The signal timing shown in Figure 30 is roughly similar to that shown in Figure 29, except that the third control signal received by the third control signal receiver VDS is at a low level (VGL), and the fourth control signal received by the fourth control signal receiver VSD is at a high level (VGH). In the reverse scan mode, the waveforms of the input signal of a single shift register unit, the potential of the first node, the first output signal of the first output terminal, and the first reset signal of the first reset signal receiver can be seen in the right figure of Figure 13, and will not be described again here.

[0100] Another embodiment of this application provides a display device including a gate driver as described in any of the foregoing gate driver embodiments. The gate driver may be arranged in a non-display area or a non-pixel area of ​​the display device; for example, the gate driver may be distributed in the peripheral area of ​​the display device or in a non-pixel area between adjacent pixel areas.

[0101] It will be understood that although the terms first, second, third, etc., may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms, but only indicate a distinction in name. Furthermore, the term "electrical connection" as used herein includes both "direct connection" and "indirect connection." Although the technical solutions of this application have been described in conjunction with some embodiments, the scope of protection of this application is not limited to the specific forms set forth herein, and the scope of this application is defined by the appended claims.

Claims

1. A shift register unit, comprising: an input circuit electrically connected to an input terminal and a first node, configured to control a potential of the first node based on an input signal received from the input terminal; a first output circuit electrically connected to a clock signal receiving terminal, the first node and a first output terminal, configured to provide a first output signal to the first output terminal based on a clock signal received by the clock signal receiving terminal under the control of the potential of the first node; a first node discharging circuit electrically connected to a second node and the first node, configured to discharge the first node under the control of a potential of the second node; a first output discharging circuit electrically connected to the second node and the first output terminal, configured to discharge the first output terminal under the control of the potential of the second node; a first node potential control circuit electrically connected to a first control signal receiving terminal, a second control signal receiving terminal, the second node and a first reference voltage terminal, configured to cause the potential of the second node to be a first reference voltage of the first reference voltage terminal before a valid level of the input signal arrives under the control of a first control signal received by the first control signal receiving terminal, and to cause the potential of the second node to be the first reference voltage during a period in which the first output circuit provides a valid level of the first output signal under the control of a second control signal received by the second control signal receiving terminal; a first reset circuit electrically connected to a first reset signal receiving terminal and the first node, configured to reset the first node under the control of a first reset signal received by the first reset signal receiving terminal; and a first output control circuit electrically connected to at least one of the first reset signal receiving terminal and the input terminal, and electrically connected to the first output terminal and a first reference voltage terminal, configured to cause the potential of the first output terminal to be the first reference voltage during a period in which the first node is reset under the control of the first reset signal or the input signal. 2.The shift register unit of claim 1, further comprising: a second node discharging circuit electrically connected to a third node and the first node, configured to discharge the first node under the control of a potential of the third node; a second output discharging circuit electrically connected to the third node and the first output terminal, configured to discharge the first output terminal under the control of the potential of the third node; and a second node potential control circuit electrically connected to the first control signal receiving terminal, the second control signal receiving terminal, the third node and the first reference voltage terminal, configured to cause the potential of the third node to be the first reference voltage of the first reference voltage terminal before the valid level of the input signal arrives under the control of the first control signal, and to cause the potential of the third node to be the first reference voltage during the period in which the first output circuit provides the valid level of the first output signal under the control of the second control signal. ​ ​ 3.The shift register unit of claim 2, wherein the shift register unit further comprises: a second output circuit electrically connected to the clock signal receiving terminal, the first node and a second output terminal, configured to provide a second output signal to the second output terminal based on the clock signal under the control of the potential of the first node; a third output discharge circuit electrically connected to the second node, a third node and the second output terminal, configured to discharge the second output terminal under the control of the potentials of the second node and the third node. 4.The shift register unit of claim 3, wherein the shift register unit further comprises: a second output control circuit electrically connected to the second output terminal and a first reference voltage terminal, configured to receive at least one of the first reset signal and the input signal to cause the potential of the second output terminal to be the first reference voltage during the first node is reset under the control of the first reset signal or the input signal. 5.The shift register unit of any one of claims 1-4, wherein the shift register unit further comprises: a second reset circuit electrically connected to a second reset signal receiving terminal, the first node and the first output terminal, configured to reset the first node and the first output terminal under the control of a second reset signal received by the second reset signal receiving terminal. 6.The shift register unit of claim 1, wherein the input circuit comprises a first transistor, a first end of the first transistor and a control terminal of the first transistor are electrically connected to the input terminal, a second end of the first transistor is electrically connected to the first node, the first reset circuit comprises a second transistor, a control terminal of the second transistor is electrically connected to the first reset signal receiving terminal, a first end of the second transistor is electrically connected to the first node, a second end of the second transistor is electrically connected to the first reference voltage terminal. 7.The shift register unit of claim 1, wherein the first output circuit comprises a third transistor and a capacitor, a first end and a second end of the capacitor are electrically connected to a control terminal and a second end of the third transistor respectively, a first end of the third transistor is electrically connected to the clock signal receiving terminal. 8.The shift register unit of claim 1, wherein the first node potential control circuit comprises a fourth transistor, a fifth transistor and a sixth transistor, a first end of the fourth transistor is electrically connected to the second node, a second end of the fourth transistor is electrically connected to the first reference voltage terminal, a control terminal of the fourth transistor is electrically connected to the first control signal receiving terminal, a control terminal and a first end of the fifth transistor are electrically connected to a second reference voltage terminal, a second end of the fifth transistor is electrically connected to the second node, a control terminal of the sixth transistor is electrically connected to the second control signal receiving terminal, a first end and a second end of the sixth transistor are electrically connected to the second node and the first reference voltage terminal respectively. 9.The shift register unit of claim 1, wherein the first output control circuit comprises a seventh transistor, a first end and a second end of the seventh transistor are electrically connected to the first output end and the first reference voltage end respectively, and a control end of the seventh transistor is electrically connected to the first reset signal receiving end. 10.The shift register unit of claim 1 or 2, wherein the first node discharge circuit comprises an eighth transistor, a first end and a second end of the eighth transistor are electrically connected to the first node and the first reference voltage end respectively, and a control end of the eighth transistor is electrically connected to the second node, the first output discharge circuit comprises a ninth transistor, a first end and a second end of the ninth transistor are electrically connected to the first output end and the first reference voltage end respectively, and a control end of the ninth transistor is electrically connected to the second node. 11.The shift register unit of claim 8, wherein the first node potential control circuit further comprises a tenth transistor and an eleventh transistor connected in series with each other between the second reference voltage end and the first reference voltage end, a first end and a control end of the tenth transistor are electrically connected to the first end and the second end of the fifth transistor respectively, a first end and a second end of the eleventh transistor are electrically connected to the second end of the tenth transistor and the first reference voltage end respectively, and a control end of the eleventh transistor is electrically connected to the control end of the fourth transistor. 12.The shift register unit of claim 5, wherein the second reset circuit comprises a twelfth transistor and a thirteenth transistor, a control end of the twelfth transistor and a control end of the thirteenth transistor are electrically connected to the second reset signal receiving end, a first end of the twelfth transistor and a first end of the thirteenth transistor are electrically connected to the first node and the first output end respectively, and a second end of the twelfth transistor and a second end of the thirteenth transistor are electrically connected to the first reference voltage end. 13.The shift register unit of claim 1, wherein the input circuit comprises a first transistor, a control end of the first transistor is electrically connected to the input end, a first end of the first transistor is electrically connected to a third control signal receiving end, and a second end of the first transistor is electrically connected to the first node, the first reset circuit comprises a second transistor, a control end of the second transistor is electrically connected to the first reset signal receiving end, a first end of the second transistor is electrically connected to the first node, and a second end of the second transistor is electrically connected to a fourth control signal receiving end, a third control signal received by the third control signal receiving end and a fourth control signal received by the fourth control signal receiving end are opposite in phase. 14.The shift register unit of claim 9, wherein the first output control circuit further comprises a fourteenth transistor, a control end of the fourteenth transistor is electrically connected to the input end, and a first end and a second end of the fourteenth transistor are electrically connected to the first output end and the first reference voltage end respectively. ​ ​ 15. The shift register unit of claim 2, wherein the first node potential control circuit comprises a fourth transistor, a fifth transistor and a sixth transistor, a first end of the fourth transistor is electrically connected to the second node, a second end of the fourth transistor is electrically connected to the first reference voltage terminal, a control end of the fourth transistor is electrically connected to the first control signal receiving terminal, a control end and a first end of the fifth transistor are electrically connected to a second reference voltage terminal, a second end of the fifth transistor is electrically connected to the second node, a control end of the sixth transistor is electrically connected to the second control signal receiving terminal, a first end and a second end of the sixth transistor are electrically connected to the second node and the first reference voltage terminal respectively, wherein the second output discharge circuit comprises a fifteenth transistor, a control end of the fifteenth transistor is electrically connected to the third node, a first end and a second end of the fifteenth transistor are electrically connected to the first output terminal and the first reference voltage terminal respectively, the second node discharge circuit comprises a sixteenth transistor, a control end of the sixteenth transistor is electrically connected to the third node, a first end and a second end of the sixteenth transistor are electrically connected to the first node and the first reference voltage terminal respectively, wherein the second node potential control circuit comprises a seventeenth transistor, an eighteenth transistor and a nineteenth transistor, the seventeenth transistor and the eighteenth transistor are connected in series between a third reference voltage terminal and the first reference voltage terminal, a first end and a control end of the seventeenth transistor are electrically connected to the third reference voltage terminal, a second end of the seventeenth transistor is electrically connected to a first end of the eighteenth transistor, a control end and a second end of the eighteenth transistor are electrically connected to the control end of the sixth transistor and the first reference voltage terminal respectively, a control end of the nineteenth transistor is electrically connected to the control end of the fourth transistor, a first end and a second end of the nineteenth transistor are electrically connected to the third node and the first reference voltage terminal respectively.

16. The shift register unit of claim 15, wherein the first node potential control circuit further comprises a tenth transistor and an eleventh transistor connected in series to each other between the second reference voltage terminal and the first reference voltage terminal, a first end and a control end of the tenth transistor are electrically connected to the first end and the second end of the fifth transistor respectively, a first end and a second end of the eleventh transistor are electrically connected to the second end of the tenth transistor and the first reference voltage terminal respectively, a control end of the eleventh transistor is electrically connected to the control end of the fourth transistor, The second node potential control circuit further comprises a twentieth transistor and a twenty-first transistor connected in series with each other between the third reference voltage terminal and the first reference voltage terminal, a first terminal and a control terminal of the twentieth transistor are electrically connected to a first terminal and a second terminal of the seventeenth transistor respectively, a first terminal and a second terminal of the twenty-first transistor are electrically connected to a second terminal of the twentieth transistor and the first reference voltage terminal respectively, and a control terminal of the twenty-first transistor is electrically connected to a control terminal of the eighteenth transistor.

17. The shift register unit of claim 4, wherein the second output circuit comprises a twenty-second transistor, a control terminal of the twenty-second transistor is electrically connected to the first node, and a first terminal and a second terminal of the twenty-second transistor are electrically connected to the clock signal receiving terminal and a second output terminal respectively, wherein the third output discharge circuit comprises a twenty-third transistor and a twenty-fourth transistor, a control terminal of the twenty-third transistor and a control terminal of the twenty-fourth transistor are electrically connected to the second node and the third node respectively, a first terminal and a second terminal of the twenty-third transistor are electrically connected to the second output terminal and the first reference voltage terminal respectively, and a first terminal and a second terminal of the twenty-fourth transistor are electrically connected to the second output terminal and the first reference voltage terminal respectively.

18. The shift register unit of claim 17, wherein the second output control circuit comprises a twenty-fifth transistor, a control terminal of the twenty-fifth transistor is electrically connected to the first reset signal receiving terminal, and a first terminal and a second terminal of the twenty-fifth transistor are electrically connected to the second output terminal and the first reference voltage terminal respectively.

19. The shift register unit of claim 18, wherein the second output control circuit further comprises a twenty-sixth transistor, a control terminal of the twenty-sixth transistor is electrically connected to the input terminal, and a first terminal and a second terminal of the twenty-sixth transistor are electrically connected to the second output terminal and the first reference voltage terminal respectively.

20. A gate driver comprising N shift register units connected in cascade and a plurality of clock signal transmission lines, each of the N shift register units being the shift register unit of any one of claims 1-19. The input end of each shift register unit is electrically connected to the first output end of another shift register unit of the N shift register units, the first reset signal receiving end of the shift register unit is electrically connected to the first output end of still another shift register unit of the N shift register units, the first control signal receiving end of the shift register unit is electrically connected to the first node in the another shift register unit, the second control signal receiving end of the shift register unit is electrically connected to the first node in the still another shift register unit, and the clock signal receiving end of any one of the another shift register unit and the still another shift register unit is electrically connected to a different clock signal transmission line of the plurality of clock signal transmission lines, respectively.

21. A gate driver comprising a cascade of N shift register units and a plurality of clock signal transmission lines, each shift register unit of the N shift register units comprising an input end, a first output end, a first reset signal receiving end, a first control signal receiving end, a second control signal receiving end, a clock signal receiving end, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a capacitor, and a first node, The first end of the first transistor is electrically connected to the input end or is configured to receive a third control signal, the second end of the first transistor is electrically connected to the first end of the second transistor, the second end of the second transistor is electrically connected to the first reference voltage end or is configured to receive a fourth control signal, the control end of the second transistor is electrically connected to the first reset signal receiving end, the first end and the second end of the third transistor are electrically connected to the clock signal receiving end and the first output end of the shift register unit respectively, the first end of the capacitor and the control end of the third transistor are electrically connected to the first node between the first transistor and the second transistor, the second end of the capacitor is electrically connected to the first output end, the first end and the second end of the ninth transistor are electrically connected to the first output end and the first reference voltage end respectively, the control end of the ninth transistor is electrically connected to the second node, the first end and the second end of the seventh transistor are electrically connected to the first output end and the first reference voltage end respectively, the control end of the seventh transistor is electrically connected to the first reset signal receiving end, the fourth transistor and the fifth transistor are connected in series between the second reference voltage end and the first reference voltage end, the first end and the control end of the fifth transistor are electrically connected to the second reference voltage end, the second end of the fifth transistor is electrically connected to the second node, the first end and the second end of the fourth transistor are electrically connected to the second node and the first reference voltage end respectively, the control end of the fourth transistor is electrically connected to the first control signal receiving end, the first end and the second end of the sixth transistor are electrically connected to the second node and the first reference voltage end respectively, the control end of the sixth transistor is electrically connected to the second control signal receiving end, the first end and the second end of the eighth transistor are electrically connected to the first node and the first reference voltage receiving end respectively, the control end of the eighth transistor is electrically connected to the second node, The input end of the shift register unit is electrically connected to the first output end of another shift register unit in the N shift register units, the first reset signal receiving end of the shift register unit is electrically connected to the first output end of still another shift register unit in the N shift register units, the first control signal receiving end of the shift register unit is electrically connected to the first node in the another shift register unit, the second control signal receiving end of the shift register unit is electrically connected to the first node in the still another shift register unit, the clock signal receiving end of any one of the another shift register unit and the still another shift register unit is electrically connected to a different clock signal transmission line in the plurality of clock signal transmission lines respectively, wherein N is an integer greater than or equal to 3. 22.The gate driver of claim 20 or 21, wherein a phase of a clock signal received by the clock signal receiving end of any one of the another shift register unit and the yet another shift register unit is opposite to a phase of a clock signal received by the clock signal receiving end of the shift register unit. 23.The gate driver of claim 20 or 21, wherein the gate driver further comprises a first dummy shift register unit and a second dummy shift register unit, each of the first dummy shift register unit and the second dummy shift register unit has a same circuit structure as each of the N shift register units, wherein the gate driver further comprises a frame start signal transmission line, wherein an input end and a first control signal receiving end of the first dummy shift register unit are electrically connected to the frame start signal transmission line, a second control signal receiving end of the first dummy shift register unit is electrically connected to a first node of a first stage shift register unit of the N shift register units, a first reset signal receiving end of the first dummy shift register unit is electrically connected to a first output end of the first stage shift register unit, a first output end of the first dummy shift register unit is electrically connected to an input end of the first stage shift register unit, a first node of the first dummy shift register unit is electrically connected to a first control signal receiving end of the first stage shift register unit, a second control signal receiving end of the first stage shift register unit is electrically connected to a first node of a second stage shift register unit of the N shift register units, a first reset signal receiving end of the first stage shift register unit is electrically connected to a first output end of the second stage shift register unit of the N shift register units, wherein an input end of the second dummy shift register unit is electrically connected to a first output end of an Nth stage shift register unit of the N shift register units, a first control signal receiving end of the second dummy shift register unit is electrically connected to a first node of the Nth stage shift register unit, a first output end of the second dummy shift register unit is electrically connected to a first reset signal receiving end of the Nth stage shift register unit, a first node of the second dummy shift register unit is electrically connected to a second control signal receiving end of the Nth stage shift register unit, a second control signal receiving end and a first reset signal receiving end of the second dummy shift register unit are electrically connected to the frame start signal transmission line, a first control signal receiving end of the Nth stage shift register unit is electrically connected to a first node of an (N-1) th stage shift register unit of the N shift register units, an input end of the Nth stage shift register unit is electrically connected to a first output end of the (N-1) th stage shift register unit. 24.The gate driver of claim 20 or 21, wherein the gate driver comprises two clock signal transmission lines, wherein an input terminal of a Kth stage shift register unit in the N shift register units is electrically connected to a first output terminal of a (K-1) th stage shift register unit in the N shift register units, a first control signal receiving terminal of the Kth stage shift register unit is electrically connected to a first node of the (K-1) th stage shift register unit, a first output terminal of the Kth stage shift register unit is electrically connected to a first reset signal receiving terminal of the (K-1) th stage shift register unit, a second control signal receiving terminal of the Kth stage shift register unit is electrically connected to a first node of a (K+1) th stage shift register unit in the N shift register units, and a first reset signal receiving terminal of the Kth stage shift register unit is electrically connected to a first output terminal of the (K+1) th stage shift register unit, wherein N is an integer greater than or equal to 3, and K is an integer greater than 1 and less than N. 25.A display device comprising the gate driver of any one of claims 20-24.

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