Array substrate and touch display apparatus

Abstract

An array substrate and a touch display apparatus, relating to the technical field of display. The array substrate comprises: a first base substrate; a first conductive layer disposed at one side of the first base substrate, the first conductive layer comprising touch signal lines extending along a first direction; an insulating layer group disposed at a side of the first conductive layer facing away from the first base substrate, the insulating layer group comprising a first insulating layer group and a second insulating layer which are stacked, multiple first via holes and multiple second via holes being provided in the first insulating layer group, and multiple third via holes being provided in the second insulating layer; and a second conductive layer disposed at at least one layer in the first insulating layer group and a side of the second insulating layer facing away from the first base substrate, the second conductive layer comprising touch electrodes, and each touch electrode being connected to a touch signal line by means of a first via hole and a third via hole which are in communication, and a second via hole and a third via hole which are in communication. At least one first via hole and at least one second via hole are in communication with a same touch signal line. Each third via hole is provided with a first hole wall and a second hole wall which are oppositely disposed in the first direction. A first via hole is disposed close to the first hole wall, and a second via hole is disposed close to the second hole wall. The array substrate can prevent low-frequency flickering.

Description

Array substrate and touch display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410693900.2, filed May 30, 2024, entitled “Array substrate and touch display device,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to an array substrate and a touch display device. BACKGROUND

[0004] The existing touch and display driver integration (TDDI) product is a touch display device in which touch electrodes are arranged inside a display panel, also known as an in-cell touch display device. The touch display device has high integration, is more lightweight, and thus has a wide application prospect.

[0005] However, some touch display devices currently have a low-frequency flicker defect.

[0006] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and thus can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0007] The present disclosure aims to overcome the deficiencies of the prior art, and provides an array substrate and a touch display device.

[0008] According to one aspect of the present disclosure, an array substrate is provided, comprising:

[0009] a first substrate substrate;

[0010] a first conductive layer disposed on one side of the first substrate substrate, the first conductive layer comprising a touch signal line, the touch signal line extending in a first direction;

[0011] an insulating layer group disposed on a side of the first conductive layer away from the first substrate substrate, the insulating layer group comprising a first insulating layer group and a second insulating layer stacked and arranged, the first insulating layer group being provided with a plurality of first vias and a plurality of second vias, the second insulating layer being provided with a plurality of third vias;

[0012] A second conductive layer is disposed on a side of at least one of the first insulating layer group and the second insulating layer away from the first substrate, and includes a touch electrode connected to the touch signal line through the first via, the third via, the second via, and the third via.

[0013] At least one of the first via and the second via is connected to the same touch signal line, and the third via has a first hole wall and a second hole wall oppositely arranged in the first direction, wherein the first via is arranged closer to the first hole wall relative to the second hole wall in the first direction, and the second via is arranged closer to the second hole wall relative to the first hole wall in the first direction.

[0014] In an example embodiment of the present disclosure, the first insulating layer group includes:

[0015] A first insulating layer is disposed on a side of the first conductive layer away from the first substrate, and has a plurality of first sub-vias and a plurality of second sub-vias disposed thereon, and the second insulating layer is disposed on a side of the first insulating layer away from the first substrate.

[0016] And / or, a third insulating layer is disposed on a side of the second insulating layer away from the first substrate, and has a plurality of third sub-vias and a plurality of fourth sub-vias disposed thereon.

[0017] The first via includes the first sub-via and / or the third sub-via, and the first sub-via and the third sub-via are in communication with each other; and the second via includes the second sub-via and / or the fourth sub-via, and the second sub-via and the fourth sub-via are in communication with each other.

[0018] In an example embodiment of the present disclosure, a normal projection of the first sub-via on the first substrate is located within a normal projection of the third via on the first substrate, and a normal projection of the third sub-via on the first substrate at least partially overlaps with the normal projection of the third via on the first substrate.

[0019] In an example embodiment of the present disclosure, at the first via and the third via, the third insulating layer covers the hole wall of the third via; or the third insulating layer does not cover the first hole wall, and the third insulating layer covers the second hole wall; or the third insulating layer does not cover the first hole wall and does not cover a portion of the side of the second insulating layer away from the first substrate close to the first hole wall, and the third insulating layer covers the second hole wall.

[0020] In an example embodiment of the present disclosure, the second sub-via hole has a projection on the first substrate within a projection of the third via hole on the first substrate, and the fourth sub-via hole has at least partial overlap with the projection of the third via hole on the first substrate.

[0021] In an example embodiment of the present disclosure, at the second via hole and the third via hole, the third insulating layer covers the hole wall of the third via hole; or, the third insulating layer does not cover the second hole wall, and the third insulating layer covers the first hole wall; or, the third insulating layer does not cover the second hole wall and does not cover a portion of the second insulating layer close to the second hole wall on a side of the second insulating layer facing away from the first substrate, and the third insulating layer covers the first hole wall.

[0022] In an example embodiment of the present disclosure, the first insulating layer and the third insulating layer are made of inorganic material, and the second insulating layer is made of organic material.

[0023] In an example embodiment of the present disclosure, the second conductive layer is arranged between the second insulating layer and the third insulating layer, the touch control electrode extends to an end portion in a second direction within the third via hole, the second direction intersects the first direction and is parallel to a side of the first substrate on which the first conductive layer is arranged, and the array substrate further comprises:

[0024] a third conductive layer arranged on a side of the third insulating layer facing away from the first substrate, the third conductive layer comprising a pixel electrode, a first connecting portion and a second connecting portion, the pixel electrode being arranged separately from the first connecting portion and the second connecting portion, the first connecting portion connecting the touch control electrode and the touch control signal line through the third via hole and the first via hole, and the second connecting portion connecting the touch control electrode and the touch control signal line through the third via hole and the second via hole;

[0025] Alternatively, the second conductive layer is arranged on a side of the third insulating layer facing away from the first substrate, and the array substrate further comprises:

[0026] a third conductive layer arranged between the second insulating layer and the third insulating layer, the third conductive layer comprising a pixel electrode.

[0027] In an example embodiment of the present disclosure, the array substrate further comprises:

[0028] a gate layer arranged on a side of the first substrate, the gate layer comprising a gate and a gate line, the gate being connected to the gate line.

[0029] a gate insulating layer disposed on a side of the gate layer away from the first substrate;

[0030] an active layer disposed on a side of the gate insulating layer away from the first substrate, the active layer comprising a channel portion and a source connection portion and a drain connection portion disposed at two ends of the channel portion;

[0031] The first conductive layer is disposed on a side of the active layer away from the first substrate, and the first conductive layer further comprises a data line, a source electrode and a drain electrode. The data line extends along the first direction and is disposed apart from the touch signal line. The source electrode is connected to the data line and to the source connection portion. The drain electrode is connected to the pixel electrode and to the drain connection portion.

[0032] In an exemplary embodiment of the present disclosure, the first conductive layer further comprises a gate electrode and a gate line. The gate electrode is connected to the gate line. The gate line extends along the first direction and is disposed apart from the touch signal line. The first insulating layer group further comprises:

[0033] a gate insulating layer disposed on a side of the first conductive layer away from the first substrate, the gate insulating layer being provided with a plurality of fifth sub-vias and a plurality of sixth sub-vias;

[0034] The first via comprises the first sub-via, the third sub-via and the fifth sub-via that are in communication with each other. The second via comprises the second sub-via, the fourth sub-via and the sixth sub-via that are in communication with each other.

[0035] In an exemplary embodiment of the present disclosure, in a second direction, a distance between an edge line of a projection of the third sub-via on the first substrate and an edge line of a projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0036] In the second direction, a distance between an edge line of a projection of the fourth sub-via on the first substrate and an edge line of a projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. The second direction intersects the first direction and is parallel to a side of the first substrate on which the first conductive layer is disposed.

[0037] In an example embodiment of the present disclosure, in the first direction, the distance between the first via and the orthographic projection of the hole wall of the first hole wall on the first substrate is less than or equal to 0.5 microns; the distance between the first via and the orthographic projection of the hole wall of the second hole wall on the first substrate is greater than or equal to 1 micron and less than or equal to 2.5 microns.

[0038] In an example embodiment of the present disclosure, in the first direction, the distance between the second via and the orthographic projection of the hole wall of the second hole wall on the first substrate is less than or equal to 0.5 microns; the distance between the second via and the orthographic projection of the hole wall of the first hole wall on the first substrate is greater than or equal to 1 micron and less than or equal to 2.5 microns.

[0039] In an example embodiment of the present disclosure, the touch electrodes are multiplexed as common electrodes.

[0040] In an example embodiment of the present disclosure, the array substrate comprises:

[0041] The first connection structure comprises the first via and the third via.

[0042] The second connection structure comprises the second via and the third via.

[0043] In an example embodiment of the present disclosure, one of the touch electrodes is connected to one of the touch signal lines through the first connection structure and the second connection structure arranged alternately.

[0044] Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to one of the touch signal lines through the first connection group and the second connection group arranged alternately.

[0045] In an example embodiment of the present disclosure, one of the touch electrodes is connected to at least two of the touch signal lines, and each of the touch signal lines is connected to the touch electrode through the first connection structure and the second connection structure arranged alternately.

[0046] Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to at least two of the touch signal lines, each of the touch signal lines being connected to the touch electrode through the first connection group and the second connection group alternately arranged.

[0047] In an exemplary embodiment of the present disclosure, the first connection structure and the second connection structure connected to two adjacent touch signal lines are arranged alternately.

[0048] In an exemplary embodiment of the present disclosure, the first insulating layer group further has a fourth via hole, a projection of the fourth via hole on the first substrate being located in a middle region of a projection of the third via hole on the first substrate; and the third via hole and the fourth via hole are included in a third connection structure.

[0049] In an exemplary embodiment of the present disclosure, the first connection structure, the second connection structure and the third connection structure are included in a third connection group; one of the touch electrodes is connected to one of the touch signal lines through the third connection group; or one of the touch electrodes is connected to at least two of the touch signal lines, each of the touch signal lines being connected to the touch electrode through the third connection structure.

[0050] In an exemplary embodiment of the present disclosure, one of the touch electrodes is connected to one of the touch signal lines through a plurality of connection structures; the third connection structure is located at both ends of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure; or the third connection structure is located in a middle of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure.

[0051] In an exemplary embodiment of the present disclosure, one of the touch electrodes is connected to at least two of the touch signal lines, each of the touch signal lines being connected to the touch electrode through a plurality of connection structures; the third connection structure is located at both ends of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure; or the third connection structure is located in a middle of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure.

[0052] In an exemplary embodiment of the present disclosure, one of the touch electrodes is connected to at least two of the touch signal lines, the at least two of the touch signal lines connected to the same touch electrode forming a group of touch signal line groups, and the array substrate further includes:

[0053] The touch control lead is connected to one end of the at least two touch control signal lines to make the at least two touch control signal lines in parallel. Data lines are arranged between adjacent two touch control signal lines belonging to the same group, and data lines are also arranged between adjacent two groups of touch control signal lines.

[0054] According to another aspect of the present disclosure, there is provided a touch display device, comprising the array substrate as described in any one of the above.

[0055] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0056] The drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is expressly understood that the drawings are only exemplary and are limiting of the present disclosure as long as the drawings do not depict the essential characteristics of the present disclosure and, therefore, should not be taken to limit the scope of the present disclosure, which is defined solely by the claims. It will be readily apparent to those skilled in the art that certain aspects of the present disclosure can be put into effect without departing from the scope of the present disclosure.

[0057] FIG. 1 is a structural schematic diagram of an in-cell touch display device.

[0058] FIG. 2 is a schematic diagram of the position relationship between the touch control signal lines and the sub-pixel regions in the in-cell touch display device shown in FIG. 1.

[0059] FIG. 3 is a structural schematic diagram of a sub-pixel in the in-cell touch display device shown in FIG. 1.

[0060] FIG. 4 is a structural schematic diagram of the cooperation between the touch control electrodes and the touch control signal lines in the array substrate of the present disclosure.

[0061] FIG. 5 is a top structural schematic diagram of an example embodiment of the array substrate of the present disclosure.

[0062] FIG. 6 is a structural schematic diagram of the touch control electrodes in FIG. 5.

[0063] FIG. 7 is a structural schematic diagram of the pixel electrodes in FIG. 5.

[0064] FIG. 8 is a partial enlarged schematic diagram of the portion indicated by H in FIG. 5.

[0065] FIG. 9 is a sectional schematic diagram according to the section A-A in FIG. 8.

[0066] FIG. 10 is a sectional schematic diagram according to the section B-B in FIG. 8.

[0067] FIG. 11 is a sectional schematic diagram according to the section C-C in FIG. 8.

[0068] FIG. 12 is a sectional schematic diagram according to the section C-C in FIG. 8 of another example embodiment.

[0069] Fig. 13 is a cross-sectional view of another example embodiment taken along line C-C in Fig. 8.

[0070] Fig. 14 is a plan view of a second via and a third via in an array substrate of the present disclosure.

[0071] Fig. 15 is a cross-sectional view taken along line D-D in Fig. 13.

[0072] Fig. 16 is a cross-sectional view taken along line E-E in Fig. 13.

[0073] Fig. 17 is a cross-sectional view of another example embodiment of an array substrate of the present disclosure.

[0074] Fig. 18 is a cross-sectional view of a first via and a third via in a further example embodiment of an array substrate of the present disclosure.

[0075] Fig. 19 is a cross-sectional view of a second via and a third via in a further example embodiment of an array substrate of the present disclosure.

[0076] Fig. 20 is a structural view of a first example embodiment of a connection structure between a touch electrode and a touch signal line.

[0077] Fig. 21 is a structural view of a second example embodiment of a connection structure between a touch electrode and a touch signal line.

[0078] Fig. 22 is a structural view of a third example embodiment of a connection structure between a touch electrode and a touch signal line.

[0079] Fig. 23 is a structural view of a fourth example embodiment of a connection structure between a touch electrode and a touch signal line.

[0080] Fig. 24 is a structural view of a fifth example embodiment of a connection structure between a touch electrode and a touch signal line.

[0081] Fig. 25 is a plan view of a fourth via and a third via in an array substrate of the present disclosure.

[0082] Fig. 26 is a cross-sectional view taken along line F-F in Fig. 25.

[0083] Fig. 27 is a cross-sectional view taken along line G-G in Fig. 25.

[0084] Fig. 28 is a structural view of a sixth example embodiment of a connection structure between a touch electrode and a touch signal line.

[0085] Fig. 29 is a structural view of a seventh example embodiment of a connection structure between a touch electrode and a touch signal line.

[0086] Fig. 30 is a structural schematic diagram of a connection structure between a touch electrode and a touch signal line in an eighth example embodiment.

[0087] Fig. 31 is a structural schematic diagram of a connection structure between a touch electrode and a touch signal line in a ninth example embodiment.

[0088] Fig. 32 is a structural schematic diagram of a connection structure between a touch electrode and a touch signal line in a tenth example embodiment.

[0089] Fig. 33 is a structural schematic diagram of a connection structure between a touch electrode and a touch signal line in an eleventh example embodiment.

[0090] Fig. 34 is a structural schematic diagram of a connection structure between a touch electrode and a touch signal line in a twelfth example embodiment.

[0091] Fig. 35 is a structural schematic diagram of an array of the present disclosure in which a touch signal line and a data line are matched in a non-display area.

[0092] Fig. 36 is a structural schematic diagram of a touch display device of an example embodiment of the present disclosure.

[0093] BRIEF DESCRIPTION OF THE DRAWINGS: 100, array substrate; 200, color filter substrate; 300, liquid crystal layer; 400, frame; 1, first substrate; 2, gate layer; 21, gate; 22, gate line; 23, data lead; 3, gate insulating layer; 31, fifth sub-via; 32, sixth sub-via; 33, data via; 4, active layer; 41, channel portion; 42, source connection portion; 43, drain connection portion; 5, first conductive layer; 51, touch signal line; 51a, touch signal line group; 52, data line; 53, source; 54, drain; 55, touch lead; 6, insulating layer group; 601, via; 6a, first insulating layer group; 6a1, first via; 6a2, second via; 6a3, fourth via; 61, first insulating layer; 611, first sub-via; 612, second sub-via; 613, seventh sub-via; 62, second insulating layer; 621, third via; 6211, first hole wall; 6212, second hole wall; 63, third insulating layer; 631, third sub-via; 632, fourth sub-via; 633, eighth sub-via; 7, second conductive layer; 71, touch electrode; 8, third conductive layer; 81, first connection portion; 82, second connection portion; 83, third connection portion; 84, pixel electrode; 9, touch control circuit; 11, first connection structure; 12, second connection structure; 13, third connection structure; 14, first connection group; 15, second connection group; 16, third connection group; X, first direction; Y, second direction. DETAILED DESCRIPTION

[0094] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any number of manners, and are not limited to the example implementations described herein; rather, examples implementations should be understood as illustrative in nature. Like reference numerals refer to like elements throughout the drawings, and detailed descriptions of the drawings are omitted for brevity. Further, the drawings are diagrammatic and schematic and are not necessarily to scale.

[0095] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not necessarily limiting. It will be further understood that if the icon is turned over, such that the "upper" component becomes the "lower" component, the aforementioned orientation will be reversed. When a structure is "on" or "over" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is placed directly on the other structure or that the structure is placed "indirectly" on the other structure via another structure.

[0096] The terms "one", "a", "an", "the", and "at least one" are used to mean one or more elements / components / etc.; the term "includes" and the term "comprising", and variations thereof, mean the inclusion of a recited element, component, etc. and the possibility of other elements being present in addition to the recited element, component, etc; and the term "first", "second", and "third", and the like, are used merely as labels, and are not meant to impose numerical requirements on their objects.

[0097] In the present application, unless specifically stated and limited otherwise, the term "connected" is used broadly and encompasses direct and indirect connections, fixed and removable connections, and the like. The term "and / or" includes combinations thereof, i.e., items "A" and / or "B" include any or all of the following alternatives: A alone, B alone, or A and B together. In addition, the term "and / or" as used in the context of the present application is intended to mean "and / or", both "and" and "or".

[0098] The inventors found that the main cause of the poor low-frequency flicker is that, as shown in FIGS. 1 and 2, a via hole 601 needs to be arranged in a part of the sub-pixels of the array substrate 100, and the touch electrode 71 and the touch signal line 51 are connected through the via hole 601. The via hole 601 needs to occupy a certain space. For a product with a relatively high PPI (Pixels Per Inch) and small sub-pixels, the sub-pixel in which the via hole 601 is arranged is designed differently from the normal sub-pixel, and the common electrode and the pixel electrode 84 need to be cut to a certain extent to place the via hole 601 or the connecting part, so that the Cst (storage capacitance) of the sub-pixel in which the via hole 601 is arranged is smaller than that of the normal sub-pixel, and the voltage retention capability of the sub-pixel in which the via hole 601 is arranged is poorer than that of the normal sub-pixel, especially in the case of low frequency, low-frequency flicker is prone to occur.

[0099] The example embodiments of the present disclosure provide an array substrate 100, as shown in FIGS. 1-35, which can include a first substrate 1, a first conductive layer 5, an insulating layer group 6, and a second conductive layer 7; the first conductive layer 5 is arranged on one side of the first substrate 1, and the first conductive layer 5 includes a touch signal line 51 extending along a first direction X; the insulating layer group 6 is arranged on the side of the first conductive layer 5 away from the first substrate 1, and the insulating layer group 6 includes a first insulating layer group 6a and a second insulating layer 62 arranged in layers, a plurality of first via holes 6a1 and a plurality of second via holes 6a2 are arranged on the first insulating layer group 6a, and a plurality of third via holes 621 are arranged on the second insulating layer 62; the second conductive layer 7 is arranged on the side of at least one layer of the first insulating layer group 6a and the second insulating layer 62 away from the first substrate 1, and the second conductive layer 7 includes a touch electrode 71 connected to the touch signal line 51 through the first via hole 6a1 and the third via hole 621 in communication and the second via hole 6a2 and the third via hole 621 in communication; wherein at least one first via hole 6a1 and at least one second via hole 6a2 are in communication with the same touch signal line 51, and the third via hole 621 has a first hole wall 6211 and a second hole wall 6212 arranged opposite in the first direction X, and in the first direction X, the first via hole 6a1 is arranged closer to the first hole wall 6211 relative to the second hole wall 6212, and the second via hole 6a2 is arranged closer to the second hole wall 6212 relative to the first hole wall 6211.

[0100] The array substrate 100 of the present disclosure, on the one hand, for the first via hole 6a1, the overlapping edge margin of the first via hole 6a1 near the first hole wall 6211 side and the third via hole 621 can not be considered, so that the first via hole 6a1 and the third via hole 621 can be set smaller; for the second via hole 6a2, the overlapping edge margin of the second via hole 6a2 near the second hole wall 6212 side and the third via hole 621 can not be considered, so that the second via hole 6a2 and the third via hole 621 can be set smaller, that is, the occupied area of the first via hole 6a1, the second via hole 6a2 and the third via hole 621 can be reduced, thereby increasing the setting space of the capacitance of the sub-pixel, to ensure the voltage holding ability of the sub-pixel, and avoid the occurrence of low-frequency flicker.

[0101] On the other hand, even if the alignment process of the mask plate deviates during the patterning process, when the first hole wall 6211 is offset, although the first via hole 6a1 and the third via hole 621 may be connected, the second via hole 6a2 is offset to the center position of the third via hole 621, thereby ensuring the connection between the second via hole 6a2 and the third via hole 621, thereby ensuring the connection between the touch electrode 71 and the touch signal line 51; similarly, when the second hole wall 6212 is offset, although the second via hole 6a2 and the third via hole 621 may be connected, the first via hole 6a1 is offset to the center position of the third via hole 621, thereby ensuring the connection between the first via hole 6a1 and the third via hole 621, thereby ensuring the connection between the touch electrode 71 and the touch signal line 51; moreover, they are all offset in the first direction X, and the touch signal line 51 extends along the first direction X, so no matter how the offset is, it will not deviate from the touch signal line 51.

[0102] Referring to FIG. 1, FIG. 5 and FIG. 6, the structure of each layer cannot be seen due to the multilayer stacking of FIG. 5, and the touch electrode 71 is not shown in FIG. 5. The touch electrode 71 is basically set in the whole layer, and the touch electrode 71 is not set at the thin film transistor T. The array substrate 100 can include a plurality of touch electrodes 71 arranged in an array and a plurality of touch signal lines 51. Each touch electrode 71 is electrically connected to the corresponding touch signal line 51 through the via hole 601, thereby being electrically connected to the touch control circuit 9 through the touch signal line 51.

[0103] Referring to FIG. 2, the array substrate 100 can include a plurality of pixel regions P (four pixel regions P1, P2, P3 and P4 are shown in FIG. 2 for illustration), each pixel region P includes three sub-pixel regions (see SP1, SP2, SP3), and each sub-pixel region is defined by the intersection of adjacent gate lines 22 (two gate lines 22, 221 and 222 are shown in FIG. 2 for illustration) and adjacent data lines 52 (521 to 526 are shown in FIG. 2 for illustration).

[0104] The array substrate 100 also includes multiple touch signal lines 51 located on the first substrate 1 (Figure 2 shows 511 to 512 as examples). These multiple touch signal lines 51 extend along a first direction X and are arranged sequentially along a second direction Y. Each touch signal line 51 passes through an opening area of ​​the sub-pixel region SP that is not blocked by the black matrix layer in the display device. A via 601 is provided at the sub-pixel region SP3 of the pixel region P1. The touch electrode 71 and the touch signal line 51 are connected through the via 601. As a result, the Cst (storage capacitance) of the sub-pixel region SP3 is smaller than that of the normal sub-pixel regions SP1 and SP2. This results in the voltage retention capability of the sub-pixel region SP3 being worse than that of the normal sub-pixels, especially at low frequencies, which can easily cause low-frequency flicker.

[0105] In this example embodiment, the first substrate 1 may be a glass substrate; of course, in some other example embodiments of this disclosure, the first substrate 1 may also be quartz, etc.; the first substrate 1 may also include an insulating material layer, which may be disposed on one side of the glass substrate, and the insulating material layer may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.

[0106] In this example embodiment, referring to FIG3, a gate layer 2 may be disposed on one side of the first substrate 1. The gate layer 2 may include multiple gate lines 22 and multiple gates 21. The gate lines 22 may extend along the second direction Y, and the multiple gates 21 arranged along the second direction Y may be connected to the same gate line 22, or a portion of the gate line 22 may serve as a gate 21.

[0107] In this exemplary embodiment, referring to FIG3, a gate insulating layer 3 is provided on the side of the gate layer 2 away from the first substrate 1. An active layer 4 is provided on the side of the gate insulating layer 3 away from the first substrate 1. The active layer may include a channel portion 41 and conductor portions disposed at both ends of the channel portion 41. One of the two conductor portions is a source connection portion 42, and the other is a drain connection portion 43. The channel portion 41 is disposed on the side of the gate line 22 away from the first substrate 1, that is, a portion of the gate line 22 opposite to the channel portion 41 serves as the gate 21.

[0108] In this example embodiment, referring to FIG3, a first conductive layer 5 is disposed on the side of the active layer 4 away from the first substrate 1. The first conductive layer 5 may include a source electrode 53, a drain electrode 54, a data line 52, and a touch signal line 51. The touch signal line 51 extends along a first direction X, and the data line 52 extends along the first direction X. The first direction X intersects with the second direction Y, for example, the first direction X may be perpendicular to the second direction Y.

[0109] The source 53 is connected to the data line 52 and to the source connection portion 42, thereby connecting the source connection portion 42 and the data line 52 through the source 53; the drain 54 is connected to the subsequently formed pixel electrode and to the drain connection portion 43, thereby connecting the drain connection portion 43 and the pixel electrode through the drain 54. The gate 21, the channel portion 41, the source 53, the drain 54, and the source connection portion 42 and the drain connection portion 43 form a switching unit, which is a thin-film transistor.

[0110] It should be noted that the thin-film transistor described in this specification is a bottom-gate thin-film transistor. In other exemplary embodiments of this disclosure, the thin-film transistor may also be a top-gate or dual-gate type, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 53" and "drain 54" are sometimes interchanged. Therefore, in this specification, the "source 53" and "drain 54" can be interchanged.

[0111] In this exemplary embodiment, referring to FIG3, an insulating layer group 6 is provided on the side of the first conductive layer 5 away from the first substrate 1. The insulating layer group 6 may include a first insulating layer group 6a and a second insulating layer 62. The material of the first insulating layer group 6a may include inorganic materials, such as silicon nitride, silicon oxide, etc. The material of the second insulating layer 62 may include organic materials, such as polyimide, polycarbonate, polyacrylate, etc. The material of the second insulating layer 62 may be photoresist. When forming the second sub-via 612 on the second insulating layer 62, only exposure and development are required, saving process steps; while when forming the second sub-via 612 on other film layers, after exposure and development, it is necessary to etch the other film layers using photoresist as a mask.

[0112] Of course, in some other exemplary embodiments of this disclosure, the first insulating layer group 6a may also include organic materials, and the second insulating layer 62 may also include inorganic materials.

[0113] Referring to Figure 4, the first insulating layer group 6a and the second insulating layer 62 are not shown; only the first via 6a1, the second via 6a2, and the third via 621 are shown. The first insulating layer group 6a has multiple first vias 6a1 and multiple second vias 6a2. At least one first via 6a1 and at least one second via 6a2 are connected to the same touch signal line 51. That is, the orthographic projection of at least one first via 6a1 and at least one second via 6a2 on the substrate overlaps with the orthographic projection of the same touch signal line 51 on the substrate. Alternatively, at least two portions of the same touch signal line 51 are not covered by the first insulating layer group 6a. For example, one first via 6a1 and one second via 6a2 can be connected to the same touch signal line 51, or two or more first vias 6a1 and two or more second vias 6a2 can be connected to the same touch signal line 51.

[0114] Specifically, referring to FIG3, the first insulating layer group 6a may include a first insulating layer 61, which is disposed on the side of the first conductive layer 5 away from the first substrate 1. The material of the first insulating layer 61 may be an inorganic material, such as silicon nitride, silicon oxide, etc. The first insulating layer 61 is provided with a plurality of first sub-vias 611 and a plurality of second sub-vias 612.

[0115] In this example embodiment, referring to FIG3, a second insulating layer 62 is provided on the side of the first insulating layer 61 facing away from the first substrate 1. A plurality of third vias 621 are provided on the second insulating layer 62. The third vias 621 have a first hole wall 6211 and a second hole wall 6212 disposed opposite to each other in the first direction X.

[0116] The second conductive layer 7 is disposed on at least one layer of the first insulating layer group 6a and on the side of the second insulating layer 62 away from the first substrate 1. Specifically, the second conductive layer 7 is disposed on the side of the second insulating layer 62 away from the first substrate 1. The second conductive layer 7 may include a touch electrode 71. Referring to FIG4, the touch electrode 71 is connected to the touch signal line 51 through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621.

[0117] The second conductive layer 7 can be made of a transparent conductive material. Specifically, the first conductive layer 5 can be made of ITO (indium tin oxide), IZO (indium zinc oxide), etc.

[0118] Referring to Figures 8, 9, and 14, the touch electrode 71 extends to one end of the third via 621 in the second direction Y. That is, the touch electrode 71 does not occupy the entire third via 621, but only one end in the second direction Y. The other part of the third via 621 in the second direction Y is for exposing the touch signal line 51. The first via 6a1 and the second via 6a2 are offset in the first direction X. Regardless of the offset, as long as the first via 6a1 is connected to the third via 621 or the second via 6a2 is connected to the third via 621, the connection between the touch electrode 71 and the touch signal line 51 can be guaranteed.

[0119] The touch electrode 71 can be reused as a common electrode. Specifically, the touch electrode 71 can be time-division multiplexed as a common electrode. That is, during the first time period, a touch signal is applied to the touch signal line 51, and the touch electrode 71 is used as a touch electrode to realize the touch function; during the second time period, a common voltage is applied to the touch signal line 51, and the touch electrode 71 is used as a common electrode to realize the display function.

[0120] Referring to FIG3, the first insulating layer group 6a may further include a third insulating layer 63. Specifically, the third insulating layer 63 is disposed on the side of the second conductive layer 7 away from the first substrate 1, that is, the second conductive layer 7 is disposed between the second insulating layer 62 and the third insulating layer 63. The material of the third insulating layer 63 can be an inorganic material, such as silicon nitride, silicon oxide, etc. The third insulating layer 63 is provided with a plurality of third sub-vias 631 and a plurality of fourth sub-vias 632.

[0121] The first via 6a1 may include a first sub-via 611 and a third sub-via 631, which are interconnected, i.e., the third sub-via 631 is connected to the first sub-via 611. The second via 6a2 may include a second sub-via 612 and a fourth sub-via 632, which are interconnected, i.e., the fourth sub-via 632 is connected to the second sub-via 612, thereby enabling at least one third sub-via 631 and at least one fourth sub-via 632 to be connected to the same touch signal line 51. Moreover, at least one third sub-via 631 and at least one fourth sub-via 632 are connected to the same touch electrode 71, i.e., the same touch electrode 71 is exposed at the locations of at least one third sub-via 631 and at least one fourth sub-via 632 where it is not covered by the third insulating layer 63.

[0122] Of course, in some other exemplary embodiments of this disclosure, the first insulating layer group 6a may include only the first insulating layer 61. In this case, the second conductive layer 7 is disposed on the side of the second insulating layer 62 away from the first substrate 1, the first via 6a1 may include only the first sub-via 611, and the second via 6a2 may include only the second sub-via 612; the first insulating layer group 6a may include only the third insulating layer 63. In this case, the first via 6a1 may include only the third sub-via 631, and the second via 6a2 may include only the fourth sub-via 632.

[0123] Since the first via 6a1 and the second via 6a2 on the first insulating layer group 6a and the third via 621 on the second insulating layer 62 are formed through two different patterning processes, due to the deviation of the mask alignment process during the two patterning processes, the deviation range is between -2 micrometers and +2 micrometers (positive and negative indicate direction). Therefore, the third via 621 formed first needs to be set larger so that the periphery of the third via 621 forms an overlay margin with the periphery of the first via 6a1 and the periphery of the second via 6a2. This ensures that the first via 6a1 and the second via 6a2 formed later can be connected to the third via 621 to realize the electrical connection between the touch electrode 71 and the touch signal line 51.

[0124] In this example embodiment, in the first direction, the first via 6a1 is disposed closer to the second hole wall 6211 than the second hole wall 6212, such that the first via 6a1 is located on one side of the third via 621 in the first direction X; the second via 6a2 is disposed closer to the second hole wall 6212 than the first hole wall 6211, such that the second via 6a2 is located on the opposite side of the third via 621 in the first direction X; that is, the first via 6a1 and the second via 6a2 are disposed off-center from the third via 621 relative to the center of the third via 621.

[0125] With this configuration, for the first via 6a1, the overlap distance between the side of the first via 6a1 closest to the first hole wall 6211 and the third via 621 can be disregarded, thus allowing the first via 6a1 and the third via 621 to be set smaller; for the second via 6a2, the overlap distance between the side of the second via 6a2 closest to the second hole wall 6212 and the third via 621 can be disregarded, thus allowing the second via 6a2 and the third via 621 to be set smaller, thereby increasing the setting space for the capacitance of the sub-pixel to ensure the voltage holding capability of the sub-pixel and avoid the defect of low-frequency flicker.

[0126] Furthermore, since the first via 6a1 and the second via 6a2 are located at opposite ends of the third via 621, even if the alignment process of the mask plate deviates during the patterning process, and the second via 6a2 shifts towards the center of the third via 6211 when it shifts towards the first hole wall 6211, although the first via 6a1 and the third via 621 may have poor communication, this causes the second via 6a2 to shift towards the center of the third via 621, thereby ensuring the communication between the second via 6a2 and the third via 621, and thus ensuring the connection between the touch electrode 71 and the touch signal line 51. Similarly, when shifting towards the second hole wall 6212, although the second via 6a2 and the third via 621 may have poor communication, this causes the first via 6a1 to shift towards the center of the third via 621, thereby ensuring the communication between the first via 6a1 and the third via 621, and thus ensuring the connection between the touch electrode 71 and the touch signal line 51.

[0127] In this example embodiment, a third conductive layer 8 is provided on the side of the third insulating layer 63 facing away from the first substrate 1. The material of the third conductive layer 8 can be a transparent conductive material. Specifically, the material of the first conductive layer 5 can be ITO (indium tin oxide), IZO (indium zinc oxide), etc. Referring to Figures 7, 8, and 14, the third conductive layer 8 may include a pixel electrode 84, a first connecting portion 81, and a second connecting portion 82. Moreover, the pixel electrode 84, the first connecting portion 81, and the second connecting portion 82 are spaced apart, that is, there is no connection between the pixel electrode 84, the first connecting portion 81, and the second connecting portion 82.

[0128] The first connecting part 81 connects the touch control electrode 71 and the touch signal line 51 through the third via 621 and the first via 6a1, and the second connecting part 82 connects the touch control electrode 71 and the touch signal line 51 through the third via 621 and the second via 6a2. Thus, the touch control electrode 71 and the touch signal line 51 are connected as a single unit through the first connecting part 81 and the second connecting part 82, and touch signals can be transmitted to the touch electrode 71 through the touch signal line 51.

[0129] This configuration reduces the opening area of ​​the first via 6a1, the second via 6a2, and the third via 621, thereby reducing the area of ​​the first connecting portion 81 and the second connecting portion 82. This increases the area of ​​the pixel electrode 84 and the Cst of the sub-pixel with the via, ensuring the voltage retention capability of the sub-pixel with the via and preventing low-frequency flicker.

[0130] Referring to Figures 8-13, since the second insulating layer 62 and the touch electrode 71 can block the first insulating layer 61 when the first sub-via 611 is formed, the orthogonal projection of the first sub-via 611 on the first substrate 1 is located within the orthogonal projection of the third via 621 on the first substrate 1. Specifically, the area of ​​the orthogonal projection of the first sub-via 611 on the first substrate 1 is smaller than the area of ​​the orthogonal projection of the third via 621 on the first substrate 1, and the orthogonal projection of the third via 621 on the first substrate 1 completely covers the orthogonal projection of the first sub-via 611 on the first substrate 1.

[0131] The orthographic projection of the third via 631 on the first substrate 1 at least partially overlaps with the orthographic projection of the third via 621 on the first substrate 1.

[0132] For example, referring to Figures 10 and 11, the orthographic projection of the third sub-via 631 on the first substrate 1 may be located within the orthographic projection of the third via 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via 631 on the first substrate 1 may coincide with the orthographic projection of the first hole wall 6211 of the third via 621 on the first substrate 1, such that at the first via 6a1 and the third via 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.

[0133] Referring to FIG12, when the mask plate is offset more towards the first hole wall 6211 when forming the first via 6a1, a portion of the orthographic projection of the third sub-via 631 on the first substrate 1 may overlap with a portion of the orthographic projection of the third via 621 on the first substrate 1, such that at the first via 6a1 and the third via 621, the third insulating layer 63 does not cover the first hole wall 6211 and does not cover the portion of the side of the second insulating layer away from the first substrate 1 near the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.

[0134] Referring to FIG13, when the mask plate is offset to the side of the second hole wall 6212 when forming the first via 6a1, the orthogonal projection of the third sub-via 631 on the first substrate 1 may be located within the orthogonal projection of the third via 621 on the first substrate 1, so that at the first via 6a1 and the third via 621, the third insulating layer 63 covers the hole wall of the third via 621, that is, the third insulating layer 63 almost completely covers the surrounding hole walls of the third via 621.

[0135] Additionally, referring to FIG9, in the above example embodiment, at the first via 6a1 and the third via 621, the third insulating layer 63 covers the two sidewalls of the third via 621 that are disposed opposite to each other in the second direction Y.

[0136] Referring to Figures 9 and 14-16, since the second insulating layer 62 and the touch electrode 71 can block the first insulating layer 61 when the second sub-via 612 is formed, the orthogonal projection of the second sub-via 612 on the first substrate 1 is located within the orthogonal projection of the third via 621 on the first substrate 1. Specifically, the area of ​​the orthogonal projection of the second sub-via 612 on the first substrate 1 is smaller than the area of ​​the orthogonal projection of the third via 621 on the first substrate 1, and the orthogonal projection of the third via 621 on the first substrate 1 completely covers the orthogonal projection of the second sub-via 612 on the first substrate 1.

[0137] The orthographic projection of the fourth sub-via 632 on the first substrate 1 at least partially overlaps with the orthographic projection of the third via 621 on the first substrate 1.

[0138] For example, referring to Figures 15 and 16, the orthographic projection of the fourth sub-via 632 on the first substrate 1 may be located within the orthographic projection of the third via 621 on the first substrate 1, and one side edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 may coincide with the orthographic projection of the second hole wall 6212 of the third via 621 on the first substrate 1, such that at the second via 6a12 and the third via 621, the third insulating layer 63 does not cover the second hole wall 6212, and the third insulating layer 63 covers the first hole wall 6211.

[0139] When forming the second via 6a2, if the mask plate is offset more towards the first hole wall 6211, the orthogonal projection of the fourth sub-via 632 on the first substrate 1 may be located within the orthogonal projection of the third via 621 on the first substrate 1, so that at the second via 6a12 and the third via 621, the third insulating layer 63 covers the hole wall of the third via 621, that is, the third insulating layer 63 almost completely covers the surrounding hole walls of the third via 621.

[0140] When forming the second via 6a2, if the mask plate is offset more towards the second hole wall 6212, a portion of the orthographic projection of the fourth sub-via 632 on the first substrate 1 may overlap with a portion of the orthographic projection of the third via 621 on the first substrate 1. This results in the third insulating layer 63 not covering the second hole wall 6212 and not covering a portion of the side of the second insulating layer facing away from the first substrate 1 near the second hole wall 6212 at the second via 6a12 and the third via 621, and the third insulating layer 63 covering the first hole wall 6211.

[0141] Additionally, referring to FIG9, in the above example embodiment, at the second via 6a12 and the third via 621, the third insulating layer 63 covers the two sidewalls of the third via 621 that are disposed opposite to each other in the second direction Y.

[0142] In other example embodiments of this disclosure, referring to FIG17, the second conductive layer 7 is disposed on the side of the third insulating layer 63 facing away from the first substrate 1; the touch electrode 71 can be directly connected to the touch signal line 51 through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621, without the need for the first connection portion 81 and the second connection portion 82. In this case, the array substrate may also include a third conductive layer 8, which is disposed between the second insulating layer 62 and the third insulating layer 63, and includes a pixel electrode 84. Since the connection between the touch electrode 71 and the touch signal line 51 also requires the connection through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621, the above-mentioned arrangement of the first via 6a1, second via 6a2 and third via 621 is also applicable to this example embodiment, and the specific structure will not be described here.

[0143] In some other exemplary embodiments of this disclosure, referring to Figures 18 and 19, the first conductive layer 5 may further include a gate 21 and a gate line 22, that is, the first conductive layer 5 is the gate layer 2. The touch signal line 51 and the gate line 22 are disposed on the same layer to avoid the touch signal line 51 and the gate line 22 from crossing. The gate line 22 also extends along the first direction X and is spaced apart from the touch signal line 51. The gate 21 is connected to the gate line 22, and its specific structure will not be described in detail here.

[0144] In this case, the first insulating layer group 6a may further include a gate insulating layer 3. The gate insulating layer 3 is disposed on the side of the first conductive layer 5 away from the first substrate 1. The gate insulating layer 3 is provided with a plurality of fifth sub-vias 31 and a plurality of sixth sub-vias 32. The plurality of fifth sub-vias 31 and the plurality of sixth sub-vias 32 are formed in the same patterning process as the first sub-vias 611 and the second sub-vias 612 on the first insulating layer 61 and the third sub-vias 631 and the fourth sub-vias 632 on the third insulating layer 63. This allows the first via 6a1 to include the interconnected first sub-vias 611, the third sub-vias 631 and the fifth sub-vias 31, and the second via 6a2 to include the interconnected second sub-vias 612, the fourth sub-vias 632 and the sixth sub-vias 32.

[0145] The orthographic projection of the fifth sub-via 31 on the first substrate 1 is located within the orthographic projection of the third via 621 on the first substrate 1. Specifically, the area of ​​the orthographic projection of the fifth sub-via 31 on the first substrate 1 is smaller than the area of ​​the orthographic projection of the third via 621 on the first substrate 1, and the orthographic projection of the third via 621 on the first substrate 1 completely covers the orthographic projection of the fifth sub-via 31 on the first substrate 1.

[0146] The orthographic projection of the sixth sub-via 32 on the first substrate 1 is located within the orthographic projection of the third via 621 on the first substrate 1. Specifically, the area of ​​the orthographic projection of the sixth sub-via 32 on the first substrate 1 is smaller than the area of ​​the orthographic projection of the third via 621 on the first substrate 1, and the orthographic projection of the third via 621 on the first substrate 1 completely covers the orthographic projection of the sixth sub-via 32 on the first substrate 1.

[0147] Additionally, it should be noted that this example embodiment limits the touch signal line 51 to be located in the gate layer 2. Therefore, other structures in the above example embodiment can be combined as long as they do not conflict with this example embodiment, and will not be described one by one here.

[0148] In this example embodiment, in the second direction Y, the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. For example, the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.

[0149] If the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too small, it will increase the difficulty of the alignment process and thus increase the manufacturing cost.

[0150] If the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too large, the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100. Alternatively, the third sub-via 631 needs to be reduced, which may easily lead to the third sub-via 631 and the third via 621 being unable to communicate.

[0151] The above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the third sub-via 631 and the third via 621 are connected.

[0152] It should be noted that, referring to Figure 9, since the first sub-via 611 and the third sub-via 631 are formed through the same patterning process, and one end of the first sub-via 611 in the second direction Y is blocked by the touch electrode 71 while the other end is not blocked; therefore, in the second direction Y, the distance between the corresponding edge lines of the orthographic projection of the first sub-via 611 near the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is the length of the touch electrode 71 extending into the third sub-via 621, and the distance between the corresponding edge lines of the orthographic projection of the first sub-via 611 away from the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is also greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0153] In this example embodiment, in the second direction Y, the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. For example, the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.

[0154] If the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too small, it will increase the difficulty of the alignment process and thus increase the manufacturing cost.

[0155] If the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too large, the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100. Alternatively, the fourth sub-via 632 needs to be reduced, which may result in the fourth sub-via 632 and the third via 621 being unable to communicate.

[0156] The above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the fourth sub-via 632 and the third via 621 are connected.

[0157] It should be noted that, referring to Figure 9, since the second sub-via 612 and the third sub-via 631 are formed through the same patterning process, and one end of the second sub-via 612 in the second direction Y is blocked by the touch electrode 71 while the other end is not blocked; therefore, in the second direction Y, the distance between the corresponding edge lines of the orthographic projection of the second sub-via 612 near the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is the length of the touch electrode 71 extending into the third sub-via 621, and the distance between the corresponding edge lines of the orthographic projection of the second sub-via 612 away from the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is also greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0158] In this example embodiment, in the first direction X, the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is less than or equal to 0.5 micrometers. For example, the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 can be 0.05 micrometers, 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, etc.

[0159] If the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is too large, the first via 6a1 will deviate too far from the center of the third via 621, or the first via 6a1 will not deviate much from the center of the third via 621. This will result in the first via 6a1 being set too large, failing to achieve the purpose of reducing the first via 6a1 to reduce the first connection portion 81 and increase the pixel electrode 84, and low-frequency flickering will still occur.

[0160] It should be noted that, referring to FIG12, since the first via 6a1 may include a first sub-via 611 and a third sub-via 631, when a part of the first via 6a1 is offset to the outside of the third via 621, the first sub-via 611 will not be offset to the outside of the third via 621 due to the shielding of the second insulating layer 62. In this case, the hole wall of the first sub-via 611 near the first hole wall 6211 is basically flush with the first hole wall 6211. The above-mentioned numerical range may refer to the distance between the orthographic projection of the hole wall of the third sub-via 631 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1.

[0161] The distance between the orthographic projection of the first via 6a1 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. For example, the distance between the orthographic projection of the first via 6a1 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.

[0162] The first via 6a1 and the second via 6a2 on the first insulating layer group 6a and the third via 621 on the second insulating layer 62 are formed by two different patterning processes. Due to the deviation of the mask alignment process during the two patterning processes, the deviation range is between -2 micrometers and +2 micrometers (positive and negative indicate direction). The third via 621 formed first needs to be set to a larger value to ensure that the first via 6a1 and the second via 6a2 formed later can be connected to the third via 621.

[0163] If the distance between the orthographic projection of the first via 6a1 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 is too small, it will increase the difficulty of the alignment process and thus increase the manufacturing cost.

[0164] If the distance between the orthographic projection of the first via 6a1 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 is too large, the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100, or the first via 6a1 needs to be reduced, which may easily lead to the first via 6a1 and the third via 621 being unable to communicate.

[0165] The above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the first via 6a1 and the third via 621 are connected.

[0166] It should be noted that since the walls of the first sub-via 611, the third sub-via 631, the first hole wall 6211, and the second hole wall 6212 are generally all inclined, the orthogonal projections of the walls of the third sub-via 631, the first hole wall 6211, and the second hole wall 6212 on the first substrate 1 have a certain width. Therefore, the wall of the third sub-via 631 near the first hole wall 6211 needs to be in a corresponding position, and the wall of the third sub-via 631 near the second hole wall 6212 also needs to be in a corresponding position. For example, they can all be away from the edge of the first substrate 1, or they can all be close to the edge of the first substrate 1.

[0167] In this example embodiment, in the first direction X, the distance between the orthographic projection of the second via 6a2 near the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1 is less than or equal to 0.5 micrometers. For example, the distance between the orthographic projection of the second via 6a2 near the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1 can be 0.05 micrometers, 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, etc.

[0168] If the distance between the orthographic projection of the second via 6a2 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 is too large, the second via 6a2 will deviate too far from the center of the third via 621, or the second via 6a2 will not deviate much from the center of the third via 621. This will result in the second via 6a2 being set too large, failing to achieve the purpose of reducing the second via 6a2 to reduce the second connection portion 82 and increase the pixel electrode 84, and low-frequency flickering will still occur.

[0169] It should be noted that, since the second via 6a2 may include the second sub-via 612 and the fourth sub-via 632, when a part of the second via 6a2 is offset to the outside of the third via 621, the second sub-via 612 will not be offset to the outside of the third via 621 due to the shielding of the second insulating layer 62. In this case, the hole wall of the second sub-via 612 near the second hole wall 6212 is basically flush with the second hole wall 6212. The above-mentioned numerical range may refer to the distance between the orthographic projection of the hole wall of the fourth sub-via 632 near the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1.

[0170] The distance between the orthographic projection of the second via 6a2 near the first via wall 6211 on the first substrate 1 and the orthographic projection of the first via wall 6211 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. For example, the distance between the orthographic projection of the second via 6a2 near the first via wall 6211 on the first substrate 1 and the orthographic projection of the first via wall 6211 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.

[0171] If the distance between the orthographic projection of the second via 6a2 near the first via wall 6211 on the first substrate 1 and the orthographic projection of the first via wall 6211 on the first substrate 1 is too small, it will increase the difficulty of the alignment process and thus increase the manufacturing cost.

[0172] If the distance between the orthographic projection of the second via 6a2 near the first via wall 6211 on the first substrate 1 and the orthographic projection of the first via wall 6211 on the first substrate 1 is too large, the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100, or the second via 6a2 needs to be reduced, which may easily lead to the second via 6a2 and the third via 621 being unable to communicate.

[0173] The above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the second via 6a2 and the third via 621 are connected.

[0174] It should be noted that since the walls of the second sub-via 612, the fourth sub-via 632, the first hole wall 6211, and the second hole wall 6212 are generally all inclined, the orthogonal projections of the walls of the fourth sub-via 632, the first hole wall 6211, and the second hole wall 6212 on the first substrate 1 have a certain width. Therefore, the wall of the fourth sub-via 632 near the first hole wall 6211 needs to be in a corresponding position, and the wall of the fourth sub-via 632 near the second hole wall 6212 also needs to be in a corresponding position. For example, they can all be away from the edge of the first substrate 1, or they can all be close to the edge of the first substrate 1.

[0175] Specifically, the first sub-via 611 has a size greater than or equal to 2 micrometers and less than or equal to 15 micrometers in the first direction X. For example, the size of the first sub-via 611 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, etc. The second sub-via 612 has a size greater than or equal to 2 micrometers and less than or equal to 15 micrometers in the first direction X. For example, the size of the second sub-via 612 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, etc.; this reduces the size by 15%-35% compared to the structure in the prior art.

[0176] The size of the third via 621 in the first direction X is greater than or equal to 2 micrometers and less than or equal to 20 micrometers. For example, the size of the third via 621 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, 15 micrometers, 18 micrometers, etc.; which is 15%-35% smaller than the structure in the prior art.

[0177] The third sub-via 631 has a dimension in the first direction X that is greater than or equal to 2 micrometers and less than or equal to 20 micrometers. For example, the dimension of the third sub-via 631 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, 15 micrometers, 18 micrometers, etc. The fourth sub-via 632 has a dimension in the first direction X that is greater than or equal to 2 micrometers and less than or equal to 20 micrometers. For example, the dimension of the fourth sub-via 632 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, 15 micrometers, 18 micrometers, etc. This reduces the size by 15%-35% compared to the structure in the prior art.

[0178] The array substrate may include a first connection structure 11 and a second connection structure 12; the first connection structure may include a first via 6a1 and a third via 621; the second connection structure may include a second via 6a2 and a third via 621. In this example embodiment, the first connection portion 81, the third via 621, and the first via 6a1 are included in the first connection structure 11, that is, the first connection structure 11 may include the first connection portion 81 and the interconnected third via 621 and the first via 6a1; the second connection portion 82, the third via 621, and the second via 6a2 are included in the second connection structure 12, that is, the second connection structure 12 may include the second connection portion 82, the interconnected third via 621, and the second via 6a2.

[0179] Referring to Figures 20 and 21, a touch electrode 71 is connected to a touch signal line 51 through alternating first connection structures 11 and second connection structures 12, such that a second connection structure 12 is provided between two adjacent first connection structures 11, and a first connection structure 11 is provided between two adjacent second connection structures 12; for example, both the first connection structure 11 and the second connection structure 12 can be set to ten; referring to Figure 20, the first one can be a first connection structure 11; referring to Figure 21, the first one can be a second connection structure 12.

[0180] In some exemplary embodiments of this disclosure, referring to FIG22, at least two first connection structures 11 are included in the first connection group 14, that is, the first connection group 14 may include at least two first connection structures 11. For example, the first connection group 14 may include two first connection structures 11, or the first connection group 14 may include three or more first connection structures 11. At least two second connection structures 12 are included in the second connection group 15, that is, the second connection group 15 may include at least two second connection structures 12. For example, the second connection group 15 may include two second connection structures 12, or the second connection group 15 may include three or more second connection structures 12.

[0181] A touch electrode 71 is connected to a touch signal line 51 through alternating first connection group 14 and second connection group 15, such that a second connection group 15 is provided between two adjacent first connection groups 14, and a first connection group 14 is provided between two adjacent second connection groups 15; the initial group can be a first connection group 14; the initial group can also be a second connection group 15.

[0182] In some exemplary embodiments of this disclosure, referring to FIG23, a touch electrode 71 is connected to at least two touch signal lines 51. The at least two touch signal lines 51 can be connected in parallel. For example, a touch electrode 71 can be connected to two touch signal lines 51, or a touch electrode 71 can be connected to three or more touch signal lines 51.

[0183] Each touch signal line 51 is connected to the touch electrode 71 via an alternately arranged first connection structure 11 and second connection structure 12. For example, when two touch signal lines 51 are connected to one touch electrode 71, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512. The first touch signal line 511 is connected to the touch electrode 71 via an alternately arranged first connection structure 11 and second connection structure 12, and the second touch signal line 512 is also connected to the touch electrode 71 via an alternately arranged first connection structure 11 and second connection structure 12. A second connection structure 12 is provided between two adjacent first connection structures 11, and a first connection structure 11 is provided between two adjacent second connection structures 12. There can be ten first connection structures 11 and ten second connection structures 12 connected to each touch signal line 51; the first connection structure can be a first connection structure 11, and the first connection structure can be a second connection structure 12. Furthermore, the initial connection structures of two adjacent touch signal lines 51 can be the same or different.

[0184] In some exemplary embodiments of this disclosure, referring to FIG24, at least two first connection structures 11 are included in the first connection group 14, that is, the first connection group 14 may include at least two first connection structures 11. For example, the first connection group 14 may include two first connection structures 11, or the first connection group 14 may include three or more first connection structures 11. At least two second connection structures 12 are included in the second connection group 15, that is, the second connection group 15 may include at least two second connection structures 12. For example, the second connection group 15 may include two second connection structures 12, or the second connection group 15 may include three or more second connection structures 12.

[0185] A touch electrode 71 is connected to at least two touch signal lines 51. The at least two touch signal lines 51 can be connected in parallel. For example, a touch electrode 71 can be connected to two touch signal lines 51, or a touch electrode 71 can be connected to three or more touch signal lines 51.

[0186] Each touch signal line 51 is connected to the touch electrode 71 via an alternately arranged first connection group 14 and second connection group 15. For example, when two touch signal lines 51 are connected to one touch electrode 71, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512. The first touch signal line 511 is connected to the touch electrode 71 via an alternately arranged first connection group 14 and second connection group 15, and the second touch signal line 512 is also connected to the touch electrode 71 via an alternately arranged first connection group 14 and second connection group 15. A second connection group 15 is provided between two adjacent first connection groups 14, and a first connection group 14 is provided between two adjacent second connection groups 15. The number of first connection groups 14 and second connection groups 15 connected to each touch signal line 51 can be ten; the first group can be a first connection group 14; the first group can be a second connection group 15. Furthermore, the initial connection structures of two adjacent touch signal lines 51 can be the same or different.

[0187] Optionally, the first connection structure 11 and the second connection structure 12 connected to two adjacent touch signal lines 51 are staggered, that is, the first connection structure 11 and the second connection structure 12 connected to two adjacent touch signal lines 51 are not arranged opposite each other, so as to avoid mutual interference between the first connection structure 11 and the second connection structure 12.

[0188] In some exemplary embodiments of this disclosure, referring to Figures 25-27, a fourth via 6a3 is further provided on the first insulating layer group 6a. The fourth via 6a3 may include a seventh sub-via 613 provided on the first insulating layer 61 and an eighth sub-via 633 provided on the third insulating layer 63. The orthographic projection of the fourth via 6a3 on the first substrate 1 is located in the middle region of the orthographic projection of the third via 621 on the first substrate 1. That is, the entire orthographic projection of the fourth via 6a3 on the first substrate 1 overlaps with the middle region of the orthographic projection of the third via 621 on the first substrate 1. In other words, the distance between each hole wall of the fourth via 6a3 and each hole wall of the third via 621 is substantially the same.

[0189] In this case, the third conductive layer 8 may also include a third connection portion 83. The third connection portion 83 is spaced apart from the pixel electrode 84, the first connection portion 81, and the second connection portion 82, that is, there is no connection between the third connection portion 83 and the pixel electrode 84, the first connection portion 81, and the second connection portion 82. The third connection portion 83 is connected to the touch electrode 71 and the touch signal line 51 through the fourth via 6a3 and the third via 621. The touch signal line 51 can transmit touch signals to the touch electrode 71.

[0190] The third via 621 and the fourth via 6a3 are included in the third connecting structure 13. Specifically, the third connecting part 83, the fourth via 6a3 and the third via 621 are included in the third connecting structure 13, that is, the third connecting structure 13 may include the third connecting part 83, the fourth via 6a3 and the third via 621.

[0191] Referring to Figure 28, the first connecting structure 11, the second connecting structure 12, and the third connecting structure 13 are included in the third connecting group 16. That is, the third connecting group 16 may include one first connecting structure 11, one second connecting structure 12, and one third connecting structure 13. The first connecting structure 11, the third connecting structure 13, and the second connecting structure 12 can be arranged in sequence, or the first connecting structure 11, the second connecting structure 12, and the third connecting structure 13 can be arranged in sequence. Of course, other arrangements are also possible, which will not be described in detail here.

[0192] Referring to FIG28, a touch electrode 71 is connected to a touch signal line 51 through a third connection group 16. For example, a touch electrode 71 is connected to a touch signal line 51 through a third connection group 16, or a touch electrode 71 is connected to a touch signal line 51 through two or more third connection groups 16.

[0193] Alternatively, as shown in FIG29, a touch electrode 71 is connected to at least two touch signal lines 51. For example, a touch electrode 71 may be connected to two touch signal lines 51, or a touch electrode 71 may be connected to three or more touch signal lines 51.

[0194] Each touch signal line 51 is connected to the touch electrode 71 through the third connection structure 13; for example, when two touch signal lines 51 are connected to one touch electrode 71, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512. The first touch signal line 511 is connected to the touch electrode 71 through the third connection structure 13; the second touch signal line 512 is also connected to the touch electrode 71 through the third connection structure 13.

[0195] In some exemplary embodiments of this disclosure, referring to FIG30, a touch electrode 71 is connected to a touch signal line 51 through multiple connection structures; among the multiple connection structures, the third connection structure 13 is located at both ends, and the remaining connection structures include a first connection structure 11 and a second connection structure 12; the first connection structure 11 and the second connection structure 12 can be arranged in an overlapping manner.

[0196] Alternatively, as shown in FIG31, the third connection structure 13 is located in the middle of the multiple connection structures, and the remaining connection structures include the first connection structure 11 and the second connection structure 12; the first connection structure 11 and the second connection structure 12 can be arranged in an overlapping manner.

[0197] In some exemplary embodiments of this disclosure, referring to Figures 32 and 33, a touch electrode 71 is connected to at least two touch signal lines 51. For example, a touch electrode 71 may be connected to two touch signal lines 51, or a touch electrode 71 may be connected to three or more touch signal lines 51.

[0198] Each touch signal line 51 is connected to the touch electrode 71 through multiple connection structures; for example, when two touch signal lines 51 are connected to one touch electrode 71, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512. The first touch signal line 511 is connected to the touch electrode 71 through multiple connection structures; the second touch signal line 512 is also connected to the touch electrode 71 through multiple connection structures.

[0199] Referring to FIG32, the third connection structure 13 is located in the middle of the multiple connection structures, and the remaining connection structures may include the first connection structure 11 or the second connection structure 12. The first connection structure 11 and the second connection structure 12 may be arranged in an overlapping manner.

[0200] Alternatively, as shown in FIG33, the third connection structure 13 is located at both ends of the multiple connection structures, and the remaining connection structures may include the first connection structure 11 and the second connection structure 12; the first connection structure 11 and the second connection structure 12 may be arranged in an overlapping manner.

[0201] It should be noted that the middle part of multiple connection structures is not only the one located in the exact middle of multiple connection structures. For example, the middle part of nine connection structures can be the fifth one, that is, the fifth one of the nine connection structures is the third connection structure 13. The middle part of multiple connection structures can also be a middle region. For example, the middle part of nine connection structures can be the fourth, fifth and sixth, and the middle part of ten connection structures can be the fourth, fifth, sixth and seventh.

[0202] In addition, in some other example embodiments of this disclosure, as shown in FIG34, a first connection structure 11 or a second connection structure 12 may be provided between two adjacent third connection structures 13, and the first connection structure 11 and the second connection structure 12 may be alternately provided between two adjacent third connection structures 13.

[0203] Referring to FIG35, a touch electrode 71 is connected to at least two touch signal lines 51, and the at least two touch signal lines 51 connected to the same touch electrode 71 form a group of touch signal lines 51a. The array substrate may also include touch leads 55, which may be located in the non-display area where the touch control circuit 9 is disposed. The touch leads 55 are connected to one end of at least two touch signal lines 51 so that at least two touch signal lines 51 are connected in parallel. A data line 52 is provided between two adjacent touch signal lines 51 belonging to the same group. Specifically, a data line 52 is provided between two adjacent touch signal lines 51 belonging to the same group. A data line 52 is provided between two adjacent groups of touch signal lines 51a. Specifically, a data line 52 is provided between two adjacent groups of touch signal lines 51a. The touch signal line 51, data line 52 and touch lead 55 can be disposed on the same layer, that is, the touch signal line 51, data line 52 and touch lead 55 can be disposed on the first conductive layer 5.

[0204] The array substrate may also include data leads 23, which may be located in the non-display area where the touch control circuit 9 is located. The data leads 23 may be located in the gate layer 2. The data leads 23 may be connected to the data line 52 through the data via 33 located in the gate insulating layer 3, thereby avoiding the intersection of the data leads 23 and the touch leads 55 in the same layer.

[0205] Based on the same inventive concept, the present disclosure provides a touch display device. Referring to FIG36, the touch display device may include the array substrate 100 described in any of the above-mentioned claims. The specific structure of the array substrate 100 has been described in detail above, and therefore will not be repeated here.

[0206] The touch display device may be a liquid crystal touch display device. Specifically, the touch display device may not include a color filter substrate 200, a frame 400, or a liquid crystal layer 300. The color filter substrate 200 is disposed on the side of the array substrate 100 away from the first substrate 1. The frame 400 is disposed between the array substrate 100 and the color filter substrate 200. The liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200 and is located within the frame 400.

[0207] The specific type of the touch display device is not particularly limited; any type of touch display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated here.

[0208] It should be noted that, in addition to the array substrate 100, the touch display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the touch display device, and will not elaborate further here.

[0209] Compared with the prior art, the beneficial effects of the touch display device provided by the example embodiments of the present invention are the same as the beneficial effects of the array substrate 100 provided by the example embodiments described above, and will not be repeated here.

[0210] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: First substrate; A first conductive layer is disposed on one side of the first substrate, and the first conductive layer includes a touch signal line extending along a first direction; An insulating layer group is disposed on the side of the first conductive layer away from the first substrate. The insulating layer group includes a first insulating layer group and a second insulating layer stacked together. The first insulating layer group has a plurality of first vias and a plurality of second vias, and the second insulating layer has a plurality of third vias. A second conductive layer is disposed on at least one layer of the first insulating layer group and on the side of the second insulating layer opposite to the first substrate. The second conductive layer includes a touch electrode, which is connected to the touch signal line through a first via and a third via, as well as a second via and a third via. Wherein, at least one first via and at least one second via are connected to the same touch signal line, and the third via has a first hole wall and a second hole wall disposed opposite to each other in the first direction. In the first direction, the first via is disposed closer to the first hole wall than the second hole wall, and the second via is disposed closer to the second hole wall than the first hole wall.

2. The array substrate according to claim 1, wherein, The first insulating layer group includes: A first insulating layer is disposed on the side of the first conductive layer away from the first substrate. The first insulating layer has a plurality of first sub-vias and a plurality of second sub-vias. The second insulating layer is disposed on the side of the first insulating layer away from the first substrate. And / or, a third insulating layer is disposed on the side of the second insulating layer opposite to the first substrate, and the third insulating layer is provided with a plurality of third sub-vias and a plurality of fourth sub-vias; Wherein, the first via includes the first sub-via and / or the third sub-via, and the first sub-via and the third sub-via are interconnected; the second via includes the second sub-via and / or the fourth sub-via, and the second sub-via and the fourth sub-via are interconnected.

3. The array substrate according to claim 2, wherein, The orthographic projection of the first sub-via on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the third sub-via on the first substrate at least partially overlaps with the orthographic projection of the third via on the first substrate.

4. The array substrate according to claim 3, wherein, At the first via and the third via, the third insulating layer covers the wall of the third via; or, the third insulating layer does not cover the first via wall and covers the second via wall; or, the third insulating layer does not cover the first via wall and does not cover a portion of the side of the second insulating layer facing away from the first substrate near the first via wall, and the third insulating layer covers the second via wall.

5. The array substrate according to claim 2, wherein, The orthographic projection of the second sub-via on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the fourth sub-via on the first substrate at least partially overlaps with the orthographic projection of the third via on the first substrate.

6. The array substrate according to claim 5, wherein, At the second via and the third via, the third insulating layer covers the wall of the third via; or, the third insulating layer does not cover the second via wall, and the third insulating layer covers the first via wall; or, the third insulating layer does not cover the second via wall and does not cover a portion of the side of the second insulating layer facing away from the first substrate near the second via wall, and the third insulating layer covers the first via wall.

7. The array substrate according to claim 2, wherein, The first insulating layer and the third insulating layer are made of inorganic materials; the second insulating layer is made of organic materials.

8. The array substrate according to claim 2, wherein, The second conductive layer is disposed between the second insulating layer and the third insulating layer. The touch electrode extends to one end of the third via in a second direction, the second direction intersecting the first direction and being parallel to the side of the first substrate where the first conductive layer is disposed. The array substrate further includes: A third conductive layer is disposed on the side of the third insulating layer opposite to the first substrate. The third conductive layer includes a pixel electrode, a first connection portion, and a second connection portion. The pixel electrode, the first connection portion, and the second connection portion are spaced apart. The first connection portion connects the touch electrode and the touch signal line through the third via and the first via. The second connection portion connects the touch electrode and the touch signal line through the third via and the second via. Alternatively, the second conductive layer is disposed on the side of the third insulating layer opposite to the first substrate; the array substrate further includes: A third conductive layer is disposed between the second insulating layer and the third insulating layer, and the third conductive layer includes a pixel electrode.

9. The array substrate according to claim 8, wherein, The array substrate further includes: A gate layer is disposed on one side of the first substrate, the gate layer including a gate and a gate line, the gate being connected to the gate line; A gate insulating layer is disposed on the side of the gate layer opposite to the first substrate. An active layer is disposed on the side of the gate insulating layer away from the first substrate. The active layer includes a channel portion and a source connection portion and a drain connection portion disposed at both ends of the channel portion. The first conductive layer is disposed on the side of the active layer away from the first substrate. The first conductive layer also includes a data line, a source electrode, and a drain electrode. The data line extends along the first direction and is spaced apart from the touch signal line. The source electrode is connected to the data line and to the source electrode connection portion. The drain electrode is connected to the pixel electrode and to the drain electrode connection portion.

10. The array substrate according to claim 8, wherein, The first conductive layer further includes a gate and a gate line, the gate being connected to the gate line, the gate line extending along the first direction and spaced apart from the touch signal line; the first insulating layer group further includes: A gate insulating layer is disposed on the side of the first conductive layer opposite to the first substrate, and a plurality of fifth sub-vias and a plurality of sixth sub-vias are disposed on the gate insulating layer; The first via includes a first sub-via, a third sub-via, and a fifth sub-via that are interconnected, and the second via includes a second sub-via, a fourth sub-via, and a sixth sub-via that are interconnected.

11. The array substrate according to claim 8, wherein, In the second direction, the distance between the edge of the orthographic projection of the third sub-via on the first substrate and the edge of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. In the second direction, the distance between the edge of the orthographic projection of the fourth sub-via on the first substrate and the edge of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. The second direction intersects the first direction and is parallel to the side of the first substrate on which the first conductive layer is disposed.

12. The array substrate according to claim 1, wherein, In the first direction, the distance between the orthographic projection of the first via wall near the first via wall on the first substrate and the orthographic projection of the first via wall on the first substrate is less than or equal to 0.5 micrometers; The distance between the orthographic projection of the first via wall near the second via wall on the first substrate and the orthographic projection of the second via wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

13. The array substrate according to claim 1, wherein, In the first direction, the distance between the orthographic projection of the second via wall near the second via wall on the first substrate and the orthographic projection of the second via wall on the first substrate is less than or equal to 0.5 micrometers; The distance between the orthographic projection of the second via wall near the first via wall on the first substrate and the orthographic projection of the first via wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

14. The array substrate according to claim 1, wherein, The touch electrodes are reused as common electrodes.

15. The array substrate according to any one of claims 1 to 14, wherein, The array substrate includes: The first connection structure includes the first via and the third via; The second connection structure includes the second via and the third via.

16. The array substrate according to claim 15, wherein, One of the touch electrodes is connected to a touch signal line via alternating first and second connection structures; Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to a touch signal line through alternating first and second connection groups.

17. The array substrate according to claim 15, wherein, Each of the touch electrodes is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through an alternately arranged first connection structure and a second connection structure; Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to at least two of the touch signal lines, with each of the touch signal lines connected to the touch electrode via alternating first and second connection groups.

18. The array substrate according to claim 17, wherein, The first connection structure and the second connection structure connected to the two adjacent touch signal lines are staggered.

19. The array substrate according to claim 15, wherein, The first insulating layer group is further provided with a fourth via, and the orthographic projection of the fourth via on the first substrate is located in the middle region of the orthographic projection of the third via on the first substrate. The third via and the fourth via are included in the third connection structure.

20. The array substrate according to claim 19, wherein, The first connection structure, the second connection structure, and the third connection structure are included in a third connection group; one of the touch electrodes is connected to one of the touch signal lines through the third connection group; or, one touch electrode is connected to at least two of the touch signal lines, and each of the touch signal lines is connected to the touch electrode through the third connection structure.

21. The array substrate according to claim 19, wherein, One of the touch electrodes is connected to a touch signal line through multiple connection structures; among the multiple connection structures, the third connection structure is located at both ends, and the remaining connection structures include the first connection structure and the second connection structure; or, among the multiple connection structures, the third connection structure is located in the middle, and the remaining connection structures include the first connection structure and the second connection structure.

22. The array substrate according to claim 19, wherein, Each of the touch electrodes is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through multiple connection structures; Of the plurality of connection structures, the third connection structure is located at both ends, and the remaining connection structures include the first connection structure and the second connection structure; or, of the plurality of connection structures, the third connection structure is located in the middle, and the remaining connection structures include the first connection structure and the second connection structure.

23. The array substrate according to any one of claims 1 to 14, wherein, One of the touch electrodes is connected to at least two touch signal lines, and the at least two touch signal lines connected to the same touch electrode form a group of touch signal lines. The array substrate further includes: A touch lead is connected to one end of at least two touch signal lines to make at least two touch signal lines connected in parallel. A data line is provided between two adjacent touch signal lines belonging to the same group, and a data line is also provided between two adjacent groups of touch signal lines.

24. A touch display device, wherein, include: The array substrate according to any one of claims 1 to 23.

Images