Power module and semiconductor device

Abstract

A semiconductor device, comprising a power module, the power module comprising a power chip, a first substrate, and a second substrate. A first metal layer is provided on the first substrate, a second metal layer is provided on the second substrate, and the first metal layer and the second metal layer are provided on adjacent sides of the first substrate and the second substrate, respectively, in the thickness direction of the power chip. The power chip is provided between the first metal layer and the second metal layer, and the power chip is electrically connected to the first metal layer and the second metal layer.

Description

Power module and semiconductor device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202421246205.3, filed on May 31, 2024, entitled “Power module and semiconductor device”, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor technology, and in particular to a power module and a semiconductor device. BACKGROUND

[0004] In the prior art, a power module includes a substrate and a power chip. When the power chip is electrically connected with a metal layer on the substrate, the electrical connection between the metal layer on the substrate and the power chip is generally realized by a wire. However, the connection by the wire makes the structure inside the power module more complex, which affects the assembly efficiency of the power module and is not conducive to the optimization of the volume of the power module.

[0005] DISCLOSURE

[0006] The present disclosure aims to at least solve one of the technical problems existing in the prior art. To this end, one object of the present disclosure is to provide a power module which can simplify the structure of the power module.

[0007] Another object of the present disclosure is to provide a semiconductor device comprising the power module described above.

[0008] According to the power module of the first aspect of the present disclosure, the power module comprises a power chip, a first substrate and a second substrate, the first substrate is provided with a first metal layer, the second substrate is provided with a second metal layer, the first metal layer and the second metal layer are respectively arranged on one side of the first substrate and the second substrate adjacent to each other along the thickness direction of the power chip, the power chip is arranged between the first metal layer and the second metal layer, and the power chip is electrically connected with the first metal layer and the second metal layer.

[0009] According to the power module of the present disclosure, by electrically connecting the power module with the metal layer on the adjacent substrate, the structure of the power module can be optimized, the thickness of the power module can be significantly reduced, which is helpful to realize the miniaturization design of the power module and increase the utilization rate of space.

[0010] In some embodiments, the power chip comprises a first chip and a second chip, one side of the first chip is directly electrically connected with the first metal layer, the other side of the first chip away from the first metal layer is directly electrically connected with the second metal layer; one side of the second chip is directly electrically connected with the second metal layer, the other side of the second chip away from the second metal layer is directly electrically connected with the first metal layer.

[0011] In some embodiments, the first chip and the second chip each comprise a power source, a power drain and a power gate, the power source and the power gate are arranged on one side in the thickness direction of the power chip, the power drain is arranged on the other side in the thickness direction of the power chip, the power source and the power gate of the first chip are electrically connected with the first metal layer, the power drain of the first chip is electrically connected with the second metal layer; the power source and the power gate of the second chip are electrically connected with the second metal layer, the power drain of the second chip is electrically connected with the first metal layer.

[0012] In some embodiments, the first metal layer and the second metal layer each comprise a source connection part, a gate connection part and a drain connection part, the source connection part of the first metal layer is electrically connected with the power source of the second chip, the source connection part of the second metal layer is electrically connected with the power source of the first chip; the gate connection part of the first metal layer is electrically connected with the power gate of the second chip, the gate connection part of the second metal layer is electrically connected with the power gate of the first chip; the drain connection part of the first metal layer is electrically connected with the power drain of the first chip, the drain connection part of the second metal layer is electrically connected with the power drain of the second chip; the source connection part, the gate connection part and the drain connection part comprised by the first metal layer and the second metal layer are arranged in isolation from each other.

[0013] In some embodiments, at least one insulating groove is formed on the first metal layer and the second metal layer respectively, the insulating groove is arranged between the source connection part, the gate connection part and the drain connection part.

[0014] In some embodiments, the first metal layer comprises a first sub-metal layer, a second sub-metal layer and a third sub-metal layer, the power drain of the first chip is electrically connected with the first sub-metal layer; the second sub-metal layer is electrically connected with the power source of the second chip; the third sub-metal layer is electrically connected with the power gate of the second chip, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer are arranged in isolation along a first direction, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer extend along a second direction, the first direction and the second direction are perpendicular.

[0015] In some embodiments, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer are at least one, and the at least one first sub-metal layer, the at least one second sub-metal layer and the at least one third sub-metal layer are arranged alternately along the first direction.

[0016] In some embodiments, the plurality of third sub-metal layers are connected to each other.

[0017] In some embodiments, the power module further comprises a plurality of positive direct current terminals and a plurality of negative direct current terminals, the plurality of positive direct current terminals are respectively electrically connected to the plurality of first sub-metal layers, and the plurality of negative direct current terminals are respectively electrically connected to the plurality of second sub-metal layers, and the plurality of positive direct current terminals and the plurality of negative direct current terminals are arranged alternately along the first direction.

[0018] In some embodiments, a first control terminal is further included, the first control terminal is electrically connected to the third sub-metal layer, and the first control terminal is arranged at the same end of the power module as the positive direct current terminals and the negative direct current terminals along the second direction.

[0019] In some embodiments, the second metal layer comprises a fourth sub-metal layer, the fourth sub-metal layer comprises a first connecting portion and a second connecting portion, one end of the first connecting portion and the second connecting portion along the second direction is connected, the other end of the first connecting portion and the second connecting portion along the second direction is spaced apart from each other, and the plurality of second chips are arranged spaced apart along the second direction on the first connecting portion and the second connecting portion, and the fourth sub-metal layer is respectively electrically connected to the power drain of the second chip and the power source of the first chip.

[0020] In some embodiments, the second metal layer further comprises a fifth sub-metal layer, the fifth sub-metal layer is arranged spaced apart from the fourth sub-metal layer along the first direction, one end of the fifth sub-metal layer is arranged between the first connecting portion and the second connecting portion, and the other end of the fifth sub-metal layer is arranged at one side of the fourth sub-metal layer along the first direction, and the fifth sub-metal layer is electrically connected to the power gate of the first chip.

[0021] In some embodiments, the power module further comprises an alternating current terminal and a second control terminal, the alternating current terminal is electrically connected to the fourth sub-metal layer along the second direction, and the second control terminal is connected to the fifth sub-metal layer, and the second control terminal and the alternating current terminal are arranged at the same end of the power module along the second direction.

[0022] In some embodiments, a first control terminal is further included, the first metal layer is formed with a first avoiding part opposite to the second control terminal, and the second metal layer is formed with a second avoiding part opposite to the first control terminal.

[0023] In some embodiments, the first substrate is further provided with a third metal layer on a side of the first substrate away from the first metal layer, and the second substrate is further provided with a fourth metal layer on a side of the second substrate away from the second metal layer.

[0024] In some embodiments, the first substrate and the second substrate are insulating members.

[0025] In some embodiments, the power module further includes a mounting plate on a side of the third metal layer and the fourth metal layer away from each other, and the mounting plate is connected to the third metal layer and the fourth metal layer respectively.

[0026] In some embodiments, the mounting plate is a heat dissipation plate.

[0027] In some embodiments, the power module further includes a plastic sealing member between the first metal layer and the second metal layer.

[0028] According to the semiconductor device of the second aspect of the embodiments of the present disclosure, the power module of any one of the above embodiments is included.

[0029] Additional aspects and advantages of the present disclosure will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily appreciated from the following description, including the appended drawings.

[0031] FIG. 1 is a schematic diagram of a plurality of power modules assembled together according to an embodiment of the present disclosure;

[0032] FIG. 2 is a schematic diagram of a power module according to an embodiment of the present disclosure;

[0033] FIG. 3 is a schematic diagram of a partial cross-section of a power module according to an embodiment of the present disclosure;

[0034] FIG. 4 is a schematic diagram of a first substrate according to an embodiment of the present disclosure;

[0035] FIG. 5 is a schematic diagram of a second substrate according to an embodiment of the present disclosure;

[0036] Fig. 6 is a partially exploded schematic view of a power module according to an embodiment of the present disclosure;

[0037] Fig. 7 is a schematic view of a plastic package according to an embodiment of the present disclosure;

[0038] [Corrected according to Rule 91 on 25.06.2025] Fig. 8 is a schematic view of a semiconductor device according to an embodiment of the present disclosure.

[0039] Reference signs: 100, power module; 10, power chip; 11, power source; 12, power gate; 13, power drain; 14, first chip; 15, second chip; 30, second substrate; 21, first metal layer; 211, first sub-metal layer; 212, second sub-metal layer; 213, third sub-metal layer; 22, third metal layer; 20, first substrate; 31, second metal layer; 311, fourth sub-metal layer; 3111, first connecting portion; 3112, second connecting portion; 312, fifth sub-metal layer; 32, fourth metal layer; 41, positive DC terminal; 42, negative DC terminal; 43, AC terminal; 44, insulating groove; 51, first control terminal; 52, second control terminal; 61, mounting plate; 62, plastic package; 70, semiconductor device; 71, first avoiding portion; 72, second avoiding portion; 81, source connecting portion; 82, gate connecting portion; 83, drain connecting portion. DETAILED DESCRIPTION

[0040] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The embodiments described with reference to the accompanying drawings are exemplary, and a power module 100 according to a first aspect embodiment of the present disclosure is described below with reference to Figs. 1-7, which includes a power chip 10, a first substrate 20, and a second substrate 30.

[0041] Specifically, as shown in Figs. 1-3, the first substrate 20 is provided with a first metal layer 21, and the second substrate 30 is provided with a second metal layer 31. The first metal layer 21 and the second metal layer 31 are respectively arranged on a side of the first substrate 20 and the second substrate 30 adjacent to each other along a thickness direction of the power chip 10. The power chip 10 is arranged between the first metal layer 21 and the second metal layer 31, and the power chip 10 is electrically connected to the first metal layer 21 and the second metal layer 31.

[0042] In the embodiment, the power module 100 comprises a first substrate 20 and a second substrate 30 opposite in the thickness direction, the first substrate 20 and the second substrate 30 are respectively provided with a first metal layer 21 and a second metal layer 31 on the side adjacent to each other, the power chip 10 is arranged between the first metal layer 21 and the second metal layer 31, and the two sides of the power chip 10 in the thickness direction are respectively electrically connected with the first metal layer 21 and the second metal layer 31. Among them, the power chip 10 is welded or sintered to at least one of the first substrate 20 and the second substrate 30, that is, the power chip 10 and one of the first substrate 20 and the second substrate 30 are electrically connected by welding or sintering; in the embodiment, the two sides of the power chip 10 in the thickness direction are respectively sintered to the first substrate 20 and the second substrate 30, so that the power chip 10 is electrically connected with the adjacent metal layer to realize the conduction of the circuit.

[0043] According to the power module 100 of the present disclosure, by electrically connecting the power module 100 with the metal layer on the adjacent substrate, the structure of the power module 100 can be optimized, the thickness of the power module 100 can be significantly reduced, the miniaturization design of the power module 100 can be facilitated, the utilization rate of space can be increased, and the heat dissipation capacity of the power module 100 can be improved due to the simpler structure, and the use demand of larger current can be met.

[0044] In some embodiments, as shown in FIGS. 4 and 5, the power chip 10 comprises a first chip 14 and a second chip 15, one side of the first chip 14 is directly electrically connected with the first metal layer 21, and the other side of the first chip 14 away from the first metal layer 21 is directly electrically connected with the second metal layer 31; one side of the second chip 15 is directly electrically connected with the second metal layer 31, and the other side of the second chip 15 away from the second metal layer 31 is directly electrically connected with the first metal layer 21.

[0045] That is, in the embodiment, when the first chip 14 and the second chip 15 are electrically connected with the first metal layer 21 and the second metal layer 31, the conventional wire is cancelled, and the power chip 10 is directly electrically connected with the corresponding metal layer of the first substrate 20 and the second substrate 30 by welding or sintering, so that the internal structure of the power module 100 is optimized, the height of the power module 100 is reduced, and the flow of current between the metal layer on the first substrate 20 and the metal layer on the second substrate 30 is facilitated.

[0046] In some embodiments, as shown in Figures 3-5, both the first chip 14 and the second chip 15 include a power source 11, a power drain 13, and a power gate 12. The power source 11 and the power gate 12 are disposed on one side of the thickness direction of the power chip 10, and the power drain 13 is disposed on the other side of the thickness direction of the power chip 10, so as to facilitate the connection between the first chip 14 and the second chip 15 and the first metal layer 21 and the second metal layer 31. The power source 11 and the power gate 12 of the first chip 14 are electrically connected to the first metal layer 21, and the power drain 13 of the first chip 14 is electrically connected to the second metal layer 31. The power source 11 and the power gate 12 of the second chip 15 are electrically connected to the second metal layer 31, and the power drain 13 of the second chip 15 is electrically connected to the first metal layer 21. That is, the power chip 10 includes a power source 11 and a power gate 12 located on one side of the thickness direction, and a power drain 13 located on the other side of the thickness direction, wherein the power source 11, the power gate 12, and the power drain 13 are spaced apart.

[0047] When the power chip 10 is electrically connected to the first metal layer 21 and the second metal layer 31, the power source 11 and power gate 12 on the first chip 14 of the power chip 10 can be electrically connected to the second metal layer 31 first, and the power source 11 and power gate 12 on the second chip 15 of the power chip 10 can be electrically connected to the first metal layer 21. Then, the power drain 13 of the first chip 14 is electrically connected to the first metal layer 21, and the power drain 13 of the second chip 15 is electrically connected to the second metal layer 31.

[0048] Therefore, when welding the power chip 10 to the first metal layer 21 and the second metal layer 31, since the power source 11 and the power gate 12 are smaller than the power drain 13, the power source 11 and the power gate 12 can be welded to the corresponding metal layers first, which can maximize the accuracy and tolerance requirements of the electrical connection. Welding the power drain 13 to the corresponding metal layer later can reduce the requirements for welding precision and tolerance, and improve the convenience and efficiency of welding the power chip 10 to the first metal layer 21 and the second metal layer 31.

[0049] In some embodiments, as shown in FIG3, the first metal layer 21 and the second metal layer 31 include a source connection portion 81, a gate connection portion 82, and a drain connection portion 83. The source connection portion 81 of the first metal layer 21 is electrically connected to the power source 11 of the second chip 15; the source connection portion 81 of the second metal layer 31 is electrically connected to the power source 11 of the first chip 14; the gate connection portion 82 of the first metal layer 21 is electrically connected to the power gate 12 of the second chip 15, and the gate connection portion 82 of the second metal layer 31 is electrically connected to the power gate 12 of the first chip 14; the drain connection portion 83 of the first metal layer 21 is electrically connected to the power drain 13 of the first chip 14, and the drain connection portion 83 of the second metal layer 31 is electrically connected to the power drain 13 of the second chip 15. The source connection portion 81, the gate connection portion 82, and the drain connection portion 83 of the first metal layer 21 and the second metal layer 31 are insulated from each other.

[0050] Therefore, the first metal layer 21 and the second metal layer 31 are respectively provided with source connection portion 81, gate connection portion 82 and drain connection portion 83 corresponding to power source 11, power gate 12 and power drain, which can facilitate the accurate connection of power chip 10 with the first metal layer 21 and the second metal layer 31, avoid short circuits caused by power source 11 and power gate 12 being connected to the same position on the same metal layer, and avoid mutual interference between power source 11, power gate 12 and power drain 13, thus improving safety in use.

[0051] In some embodiments, as shown in FIG3, at least one insulating trench 44 is formed on the first metal layer 21 and the second metal layer 31, respectively. The insulating trench 44 is disposed between the source connection portion 81, the gate connection portion 82, and the drain connection portion 83. The first metal layer 21 and the second metal layer 31 serve both current conduction and heat conduction functions. Insulation trenches 44 are formed between metal regions of different functional areas by etching to achieve insulation between each functional region. Here, when the power chip 10 is disposed on the first metal layer 21, an insulating trench 44 is provided between the source connection portion 81, the gate connection portion 82, and the drain connection portion 83 electrically connected to the power chip 10 to achieve insulation. When the power chip 10 is disposed on the second metal layer 31, an insulating trench 44 is also provided between the source connection portion 81, the gate connection portion 82, and the drain connection portion 83 electrically connected to the power chip 10 to achieve insulation. Therefore, the design of the insulating trench 44 can isolate the possibility of electrical connection between the source connection portion 81, the gate connection portion 82, and the drain connection portion 83 through the metal layer, thereby achieving insulation between the source connection portion 81, the gate connection portion 82, and the drain connection portion 83.

[0052] In some embodiments, referring to Figure 3, the thickness of the power module 100 is H, where H satisfies: 1.5mm ≤ H ≤ 10mm. That is, compared to the prior art where the power chip 10 is connected to the metal layer via wires, this embodiment eliminates the wire bonding structure, allowing direct electrical connection between the power chip 10 and the metal layer, thus reducing the thickness of the power chip 10; for example, H = 3mm. If the thickness of the power chip 10 is less than 1.5mm, the manufacturing process requires higher precision and is more costly. If the thickness of the power module 100 is greater than 10mm, it may result in a thicker module, affecting its miniaturization and integration design, leading to higher space requirements, greater material consumption, and increased costs. Therefore, controlling the thickness of the power module 100 between 1.5mm and 10mm allows for a miniaturized and thinner design, reducing costs, minimizing space utilization, and providing good assembly precision.

[0053] In some embodiments, as shown in FIG4, the first metal layer 21 includes a first sub-metal layer 211, a second sub-metal layer 212, and a third sub-metal layer 213. The power drain 13 of the first chip 14 is electrically connected to the first sub-metal layer 211, the second sub-metal layer 212 is electrically connected to the power source 11 of the second chip 15, and the third sub-metal layer 213 is electrically connected to the power gate 12 of the second chip 15. The first sub-metal layer 211, the second sub-metal layer 212, and the third sub-metal layer 213 are spaced apart along a first direction A, and all three extend along a second direction B. The first direction A and the second direction B are perpendicular.

[0054] In this embodiment, the power source 11 and power gate 12 of the second chip 15 are electrically connected to the second sub-metal layer 212 and the third sub-metal layer 213, respectively. A clearance groove and a protrusion at the edge of the clearance groove are formed on the third sub-metal layer 213. When the second chip 15 is electrically connected to the second metal layer 31, the power drain 13 of the second chip 15 is also electrically connected to the second metal layer 31. When the second chip 15 is electrically connected to the first metal layer 21, in order to avoid the power source 11 and power gate 12 on the second chip 15 being electrically connected to the same metal layer, a clearance groove for avoiding the power source 11 and a protrusion for facilitating the electrical connection between the third sub-metal layer 213 and the power gate 12 are provided on the third sub-metal layer 213, which is electrically connected to the power gate 12.

[0055] Therefore, the arrangement of the second sub-metal layer 212 and the third sub-metal layer 213 facilitates the arrangement of the power source 11 and the power gate 12 of the same power chip 10, effectively avoiding the phenomenon of short circuit caused by the power source 11 and the power gate 12 being electrically connected to the same metal layer.

[0056] Along the first direction A, the third sub-metal layer 213, the first sub-metal layer 211, and the second sub-metal layer 212 are sequentially spaced apart. Multiple first chips 14 are arranged along the second direction B on the first sub-metal layer 211, and the power drain 13 of each first chip 14 is electrically connected to the first sub-metal layer 211. Therefore, the arrangement of the first sub-metal layer 211 facilitates current conduction with the second metal layer 31 and the first chips 14, allowing current to flow through the first sub-metal layer 211 to the first chip 14 and then from the power source 11 of the first chip 14 to the second metal layer 31.

[0057] In some embodiments, as shown in FIG4, the first sub-metal layer 211, the second sub-metal layer 212, and the third sub-metal layer 213 are at least one, and at least one first sub-metal layer 211, at least one second sub-metal layer 212, and at least one third sub-metal layer 213 are alternately disposed along the first direction A.

[0058] If multiple third sub-metal layers 213 are provided, the multiple third sub-metal layers 213 are connected to each other. One end of the third sub-metal layer 213 is located between two adjacent first sub-metal layers 211 and second sub-metal layers 212, and the other end of the third sub-metal layer 213 is located at the edge of the first sub-metal layer 211 along the first direction A.

[0059] That is, the third sub-metal layer 213 is spaced apart from the first sub-metal layer 211 and the second sub-metal layer 212 along the first direction A, and the third sub-metal layer 213 has a U-shaped structure. One end of the third sub-metal layer 213 is located between the two adjacent first sub-metal layers 211 and the second sub-metal layer 212 in the middle, and the other end of the third sub-metal layer 213 is located on the side of the first substrate 20 along the first direction A. The other end of the third sub-metal layer 213 is electrically connected to the first control terminal 51 so that the first control terminal 51 controls the second chip 15 through the third sub-metal layer 213.

[0060] As shown in Figures 1 and 4, the power module 100 also includes a plurality of positive DC terminals 41 and a plurality of negative DC terminals 42. The plurality of positive DC terminals 41 are electrically connected to a plurality of first sub-metal layers 211 respectively; the plurality of negative DC terminals 42 are electrically connected to a plurality of second sub-metal layers 212 respectively. The plurality of positive DC terminals 41 and the plurality of negative DC terminals 42 are alternately arranged along the first direction A.

[0061] That is, multiple first sub-metal layers 211 and multiple second sub-metal layers 212 are alternately and spaced apart along the first direction A, and multiple positive DC terminals 41 and multiple negative DC terminals 42 are spaced apart along the first direction A. The first sub-metal layers 211 are electrically connected to the positive DC terminals 41, and the second sub-metal layers 212 are electrically connected to the negative DC terminals 42. Therefore, the spaced arrangement of the positive DC terminals 41 and negative DC terminals 42 along the first direction A can cancel out most of the stray inductance, reduce the parameters of the power module 100, and thus reduce the losses and interference of the power module 100. This results in more uniform heat dissipation of the power chip 10, lowers the temperature of the power chip 10, and improves the overcurrent capability of the power module 100.

[0062] In some embodiments, referring to FIG4, the power module 100 further includes a first control terminal 51, which is electrically connected to the third sub-metal layer 213 and is electrically connected to the third sub-metal layer 213 on one side edge of the power module 100 along the first direction A. The first control terminal 51 is disposed at the same end of the power module 100 along the second direction B as the positive DC terminal 41 and the negative DC terminal 42.

[0063] Therefore, the first control terminal 51 is located at the same end of the second direction B as the positive DC terminal 41 and the negative DC terminal 42, which facilitates the setting of each terminal on the power module 100 and optimizes the structure of the power module 100.

[0064] In some embodiments, as shown in FIG5, the second metal layer 31 includes a fourth sub-metal layer 311, the fourth sub-metal layer 311 includes a first connection portion 3111 and a second connection portion 3112, the first connection portion 3111 and the second connection portion 3112 are connected at one end along the second direction B, and the first connection portion 3111 and the second connection portion 3112 are spaced apart from each other at the other end along the second direction B, a plurality of second chips 15 are spaced apart on the first connection portion 3111 and the second connection portion 3112 along the second direction B, and the fourth sub-metal layer 311 is electrically connected to the power drain 13 of the second chip 15 and the power source 11 of the first chip 14, respectively.

[0065] In this embodiment, the first connecting portion 3111 and the second connecting portion 3112 of the fourth sub-metal layer 311 extend along the second direction B and are connected to each other at one end of the second direction B. That is, the first connecting portion 3111 and the second connecting portion 3112 are connected to each other at the end of the second substrate 30 away from the first control terminal 51. A plurality of second chips 15 are provided on both the first connecting portion 3111 and the second connecting portion 3112. The plurality of second chips 15 are spaced apart on the first connecting portion 3111 and the second connecting portion 3112 along the second direction B.

[0066] When the first substrate 20 and the second substrate 30 are connected, a plurality of first chips 14 electrically connected on the first metal layer 21 and a plurality of second chips 15 electrically connected on the second metal layer 31 are staggered along the first direction A to ensure that the power drain 13 of the second chip 15 is electrically connected to the fourth sub-metal layer 311 disposed on the second metal layer 31, and the power source 11 of the first chip 14 is electrically connected to the fourth sub-metal layer 311. This increases the heat dissipation capacity of the power chip 10 on the second metal layer 31, facilitates the electrical connection between the first chip 14 and the second chip 15 and between the first metal layer 21 and the second metal layer 31, and helps to reduce the thickness of the power module 100.

[0067] In some embodiments, as shown in FIG5, the second metal layer 31 further includes a fifth sub-metal layer 312, which is spaced apart from the fourth sub-metal layer 311 along the first direction A. One end of the fifth sub-metal layer 312 is disposed between the first connecting portion 3111 and the second connecting portion 3112, and the other end of the fifth sub-metal layer 312 is disposed on one side of the fourth sub-metal layer 311 along the first direction A. The fifth sub-metal layer 312 is electrically connected to the power gate 12 of the first chip 14, that is, the fifth sub-metal layer 312 has a U-shaped structure. One end of the fifth sub-metal layer 312 is located between the first connecting portion 3111 and the second connecting portion 3112, and the other end of the fifth sub-metal layer 312 is located along the first direction A on the side of the first connecting portion 3111 away from the second connecting portion 3112 or on the side of the second connecting portion 3112 away from the first connecting portion 3111.

[0068] Furthermore, the power module 100 also includes an AC terminal 43 and a second control terminal 52. The AC terminal 43 is electrically connected to the fourth sub-metal layer 311 along the second direction B; the second control terminal 52 is connected to the fifth sub-metal layer 312, and the second control terminal 52 and the AC terminal 43 are located at the same end of the power module 100 along the second direction B. The end of the AC terminal 43 connected to the first connecting portion 3111 and the second connecting portion 3112 is electrically connected, and the second control terminal 52 is electrically connected to the fifth sub-metal layer 312, thereby realizing the control of the power chip 10.

[0069] Referring to Figures 3-6, current flows into the first sub-metal layer 211 through the positive DC terminal 41, passes through the power drain 13 of the first chip 14, flows through the first chip 14 to the power source 11 of the first chip 14, and then flows out through the fourth sub-metal layer 311 to the AC terminal 43, thus completing the circuit. In addition, if a reverse current is applied, the reverse current flows into the fourth sub-metal layer 311 through the AC terminal 43, passes through the power drain 13 of the second chip 15, enters the power source 11 of the second chip 15, and then enters the first metal layer 21 again through the second sub-metal layer 212 of the first metal layer 21, and finally flows out from the negative DC terminal 42. The current of the second chip 15 disposed on the first connection part 3111 and the second chip 15 disposed on the second connection part 3112 flows into the second sub-metal layer 212 of the corresponding first metal layer 21 and flows out from the corresponding negative DC terminal 42.

[0070] In some embodiments, a first metal layer 21 has a first clearance portion 71, which is opposite to the second control terminal 52; a second metal layer 31 has a second clearance portion 72, which is opposite to the first control terminal 51. That is, when the first substrate 20 and the second substrate 30 are connected, the first clearance portion 71 of the first metal layer 21 on the first substrate 20 is opposite to the second control terminal 52 on the second substrate 30, thus preventing the second control terminal 52 from being electrically connected to the first metal layer 21; the second clearance portion 72 of the second metal layer 31 on the second substrate 30 is opposite to the first control terminal 51 on the first substrate 20, thus preventing the first control terminal 51 from being electrically connected to the second metal layer 31.

[0071] Therefore, the arrangement of the first clearance portion 71 and the second clearance portion 72 can ensure the electrical connection between the first control terminal 51 and the first metal layer 21, and the electrical connection between the second control terminal 52 and the second metal layer 31, thereby increasing the performance of the power terminals when the first substrate 20 and the second substrate 30 are combined, and increasing the safety of use.

[0072] In some embodiments, as shown in FIG3, the first substrate 20 is further provided with a third metal layer 22, which is disposed on the side of the first substrate 20 away from the first metal layer 21; the second substrate 30 is further provided with a fourth metal layer 32, which is disposed on the side of the second substrate 30 away from the second metal layer 31. That is, the first metal layer 21 and the third metal layer 22 are respectively disposed on both sides of the first substrate 20, and the second metal layer 31 and the fourth metal layer 32 are respectively disposed on both sides of the second substrate 30. The first metal layer 21 and the second metal layer 31 are adjacent to each other. After the first substrate 20 and the second substrate 30 are merged, they can be electrically connected to external components by soldering through the third metal layer 22 and the fourth metal layer 32.

[0073] Optionally, the first substrate 20 and the second substrate 30 are insulating components. This avoids short circuits caused by contact between the metal layers on both sides of the substrate, increasing the safety of the power module 100.

[0074] The minimum gap between the first substrate 20 and the second substrate 30 can be 0 to 0.5 mm.

[0075] In some embodiments, as shown in FIG1, the power module 100 further includes a mounting plate 61, which is disposed on the side of the third metal layer 22 and the fourth metal layer 32 that are far apart from each other, and the mounting plate 61 is respectively connected to the third metal layer 22 and the fourth metal layer 32. For example, there can be multiple mounting plates 61, which are respectively connected to the third metal layer 22 and the fourth metal layer 32 for mounting the first substrate 20 and the second substrate 30.

[0076] Optionally, the mounting plate 61 is a heat sink. For example, the mounting plate 61 may have a heat exchange channel, which can be connected to an external heat exchange system to dissipate heat from the power module 100. The mounting plate 61 can be connected to the third metal layer 22 and the fourth metal layer 32 as a single product by welding, sintering, or using thermal grease.

[0077] In some embodiments, referring to FIG7, the power module 100 further includes a molding compound 62 disposed between the first metal layer 21 and the second metal layer 31. That is, after the first substrate 20 and the second substrate 30 are merged, the molding compound 62 is filled between the first substrate 20 and the second substrate 30. The molding compound 62 fills the gap between the first metal layer 21 and the second metal layer 31 of the entire power module 100 to achieve molding, thereby ensuring that the components inside the power module 100 are insulated from each other, which can effectively reduce thermal resistance, reduce the number of processes, and improve production efficiency.

[0078] The semiconductor device 70 according to a second aspect embodiment of the present disclosure, as shown in FIG8, includes a power module 100 of any of the above embodiments.

[0079] The semiconductor device 70 according to the embodiments of this disclosure includes one or more power modules 100 as described above. The current is directly conducted between the power chip 10 and the metal layer without passing through other conductive materials. This can reduce the size of the semiconductor device, making the semiconductor device 70 more miniaturized and thinner, improving the heat dissipation capacity of the semiconductor device, eliminating the wire bonding process, and reducing the structure of the semiconductor device 70, so that the semiconductor device 70 has good production efficiency.

[0080] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0081] In the description of this disclosure, "first feature" and "second feature" may include one or more of the features. In the description of this disclosure, "a plurality of" means two or more. In the description of this disclosure, "above" or "below" the second feature may include direct contact between the first and second features, or contact between the first and second features not in direct contact but through another feature between them. In the description of this disclosure, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0083] Although embodiments of this disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A power module (100), characterized in that, include: Power chip (10); A first substrate (20) is provided with a first metal layer (21); as well as A second substrate (30) is provided with a second metal layer (31). The first metal layer (21) and the second metal layer (31) are respectively disposed on the side of the first substrate (20) and the second substrate (30) adjacent to each other along the thickness direction of the power chip (10). The power chip (10) is disposed between the first metal layer (21) and the second metal layer (31) and is electrically connected to the first metal layer (21) and the second metal layer (31).

2. The power module (100) according to claim 1, characterized in that, The power chip (10) includes: A first chip (14), one side of which is directly electrically connected to the first metal layer (21), and the other side of which is away from the first metal layer (21) is directly electrically connected to the second metal layer (31); and The second chip (15) has one side directly electrically connected to the second metal layer (31), and the other side of the second chip (15) away from the second metal layer (31) is directly electrically connected to the first metal layer (21).

3. The power module (100) according to claim 2, characterized in that, Both the first chip (14) and the second chip (15) include: The power chip (10) has a power source (11), a power drain (13), and a power gate (12). The power source (11) and the power gate (12) are located on one side of the thickness direction of the power chip (10), and the power drain (13) is located on the other side of the thickness direction of the power chip (10). The power source (11) and the power gate (12) of the first chip (14) are electrically connected to the first metal layer (21), and the power drain (13) of the first chip (14) is electrically connected to the second metal layer (31). The power source (11) and power gate (12) of the second chip (15) are electrically connected to the second metal layer (31), and the power drain (13) of the second chip (15) is electrically connected to the first metal layer (21).

4. The power module (100) according to claim 3, characterized in that, Both the first metal layer (21) and the second metal layer (31) include: Source connection portion (81), the source connection portion (81) of the first metal layer (21) is electrically connected to the power source (11) of the second chip (15), and the source connection portion (81) of the second metal layer (31) is electrically connected to the power source (11) of the first chip (14). Gate connection portion (82), the gate connection portion (82) of the first metal layer (21) is electrically connected to the power gate (12) of the second chip (15), and the gate connection portion (82) of the second metal layer (31) is electrically connected to the power gate (12) of the first chip (14). Drain connection portion (83), the drain connection portion (83) of the first metal layer (21) is electrically connected to the power drain (13) of the first chip (14), and the drain connection portion (83) of the second metal layer (31) is electrically connected to the power drain (13) of the second chip (15). The source connection portion, the gate connection portion (82) and the drain connection portion (83) included in the first metal layer (21) and the second metal layer (31) are insulated from each other.

5. The power module (100) according to claim 4, characterized in that, At least one insulating trench (44) is formed on the first metal layer (21) and the second metal layer (31), respectively, and the insulating trench (44) is disposed between the source connection portion (81), the gate connection portion (82) and the drain connection portion (83).

6. The power module (100) according to claim 4 or 5, characterized in that, The first metal layer (21) includes: The first sub-metal layer (211) is electrically connected to the power drain (13) of the first chip (14). The second sub-metal layer (212) is electrically connected to the power source (11) of the second chip (15); The third sub-metal layer (213) is electrically connected to the power gate (12) of the second chip (15). The first sub-metal layer (211), the second sub-metal layer (212) and the third sub-metal layer (213) are spaced apart along a first direction. The first sub-metal layer (211), the second sub-metal layer (212) and the third sub-metal layer (213) extend along a second direction. The first direction and the second direction are perpendicular.

7. The power module (100) according to claim 6, characterized in that, The first sub-metal layer (211), the second sub-metal layer (212), and the third sub-metal layer (213) are at least one, and at least one first sub-metal layer (211), at least one second sub-metal layer (212), and at least one third sub-metal layer (213) are alternately arranged along the first direction.

8. The power module (100) according to claim 7, characterized in that, The plurality of the third sub-metal layers (213) are connected to each other.

9. The power module (100) according to claim 7 or 8, characterized in that, The power module (100) also includes: Multiple positive DC terminals (41), each of which is electrically connected to a plurality of the first sub-metal layers (211); and Multiple negative DC terminals (42) are electrically connected to multiple second sub-metal layers (212) respectively, and multiple positive DC terminals (41) and multiple negative DC terminals (42) are alternately arranged along the first direction.

10. The power module (100) according to claim 9, characterized in that, Also includes: The first control terminal (51) is electrically connected to the third sub-metal layer (213), and the first control terminal (51), the positive DC terminal (41), and the negative DC terminal (42) are disposed at the same end of the power module (100) along the second direction.

11. The power module (100) according to any one of claims 6-10, characterized in that, The second metal layer (31) includes: A fourth sub-metal layer (311) includes a first connection portion (3111) and a second connection portion (3112). The first connection portion (3111) and the second connection portion (3112) are connected at one end along the second direction, and the first connection portion (3111) and the second connection portion (3112) are spaced apart from each other at the other end along the second direction. A plurality of second chips (15) are spaced apart on the first connection portion (3111) and the second connection portion (3112) along the second direction. The fourth sub-metal layer (311) is electrically connected to the power drain (13) of the second chip (15) and the power source (11) of the first chip (14), respectively.

12. The power module (100) according to claim 11, characterized in that, The second metal layer (31) further includes: A fifth sub-metal layer (312) is provided at a distance from the fourth sub-metal layer (311) along the first direction. One end of the fifth sub-metal layer (312) is located between the first connecting portion (3111) and the second connecting portion (3112), and the other end of the fifth sub-metal layer (312) is located on one side of the fourth sub-metal layer (311) along the first direction. The fifth sub-metal layer (312) is electrically connected to the power gate (12) of the first chip (14).

13. The power module (100) according to claim 12, characterized in that, The power module (100) also includes: AC terminal (43), said AC terminal (43) being electrically connected to said fourth sub-metal layer (311) along the second direction; and The second control terminal (52) is connected to the fifth sub-metal layer (312), and the second control terminal (52) and the AC terminal (43) are located at the same end of the power module (100) along the second direction.

14. The power module (100) according to claim 13, characterized in that, Also includes: First control terminal (51), The first metal layer (21) has a first clearance portion (71) which is opposite to the second control terminal (52); The second metal layer (31) has a second clearance portion (72) which is opposite to the first control terminal (51).

15. The power module (100) according to any one of claims 1-14, characterized in that, The first substrate (20) is further provided with a third metal layer (22), which is disposed on the side of the first substrate (20) away from the first metal layer (21); The second substrate (30) is further provided with a fourth metal layer (32), which is disposed on the side of the second substrate (30) away from the second metal layer (31).

16. The power module (100) according to claim 15, characterized in that, The first substrate (20) and the second substrate (30) are insulating materials.

17. The power module (100) according to claim 15 or 16, characterized in that, Also includes: Mounting plate (61) is disposed on the side of the third metal layer (22) and the fourth metal layer (32) that are far apart from each other, and the mounting plate (61) is connected to the third metal layer (22) and the fourth metal layer (32) respectively.

18. The power module (100) according to claim 17, characterized in that, The mounting plate (61) is a heat sink.

19. The power module (100) according to any one of claims 1-18, characterized in that, Also includes: A molding compound (62) is disposed between the first metal layer (21) and the second metal layer (31).

20. A semiconductor device (70), characterized in that, Includes the power module (100) according to any one of claims 1-19.

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