Method for manufacturing semiconductor package and semiconductor package

Abstract

This method for manufacturing a semiconductor package (20) comprises: a step for forming a first insulating layer (32) on a first wiring layer (42); a step for forming a conductor (48) penetrating the first insulating layer and connected to the first wiring layer; a step for forming a second insulating layer (34) constituting a first optical waveguide (44) on the first insulating layer; a step for forming a second wiring layer (46) connected to the conductor on the second insulating layer; and a step for forming a third insulating layer (36) on the second wiring layer.

Description

Semiconductor package manufacturing method and semiconductor package

[0001] The present disclosure relates to a method for manufacturing a semiconductor package and a semiconductor package.

[0002] In recent years, the concept of co-packaged optics, which combines an optical circuit chip and an electronic circuit chip for controlling it into a single package, has become widespread for the purpose of application to high-speed optical communications, HPC (High Performance Computing), etc. (See, for example, U.S. Patent Application Publication No. 2019 / 0317287).

[0003] When an optical circuit chip and an electronic circuit chip are combined into one package, it becomes possible to achieve higher speeds, larger capacities, lower power consumption, and smaller size, compared to when they are packaged separately.

[0004] However, in the specification of U.S. Patent Application Publication No. 2019 / 0317287, the optical interposer for the optical circuit chip and the rewiring layer for the electronic circuit chip are manufactured separately, so there is room for improvement in productivity.

[0005] An object of the present disclosure is to provide a technology for improving the productivity and signal quality of semiconductor packages on which optical circuit chips and electronic circuit chips are mounted.

[0006] <1> A method for manufacturing a semiconductor package, comprising the steps of: forming a first insulating layer on a first wiring layer; forming a conductor that penetrates the first insulating layer and connects to the first wiring layer; forming a second insulating layer that constitutes a first optical waveguide on the first insulating layer; forming a second wiring layer that connects to the conductor on the second insulating layer; and forming the third insulating layer on the second wiring layer. <2> A method for manufacturing a semiconductor package according to <1>, further comprising the step of placing an optical circuit chip on the third insulating layer, wherein the first optical waveguide is provided with an optical coupling portion for optically coupling with a second optical waveguide provided in the optical circuit chip. <3> A method for manufacturing a semiconductor package according to <2>, further comprising the step of placing an electronic circuit chip on the optical circuit chip. <4> A method for manufacturing a semiconductor package, comprising the steps of: forming a first insulating layer on a first wiring layer; forming a second insulating layer constituting a first optical waveguide on the first insulating layer; forming a second wiring layer on the second insulating layer and forming a conductor that penetrates the first insulating layer and the second insulating layer and connects the first wiring layer to the second wiring layer; and forming the third insulating layer on the second wiring layer. <5> The method for manufacturing a semiconductor package according to <4>, further comprising the step of forming the first wiring layer on the optical circuit chip, and the first optical waveguide is provided with an optical coupling portion for optically coupling with a second optical waveguide provided in the optical circuit chip. <6> The method for manufacturing a semiconductor package according to <5>, further comprising the step of placing an electronic circuit chip on the optical circuit chip. <7> A semiconductor package comprising: a first insulating layer including a first wiring layer, a second insulating layer configuring a first optical waveguide and disposed on the first insulating layer, a third insulating layer including the third wiring layer and disposed on the second insulating layer, a conductor penetrating the second insulating layer and connecting the first wiring layer and the second wiring layer, an optical circuit chip disposed on the third insulating layer and connected to the first optical waveguide, and an electronic circuit chip disposed on the optical circuit chip and connected to the second wiring layer. <8> The semiconductor package according to <7>, wherein the first optical waveguide comprises an optical coupling portion for optically coupling to a second optical waveguide provided in the optical circuit chip.

[0007] According to the technology of the present disclosure, it is possible to improve the productivity and signal quality of semiconductor packages on which optical circuit chips and electronic circuit chips are mounted.

[0008] FIG. 1 is a cross-sectional view schematically illustrating an embodiment of a semiconductor package according to the present disclosure. FIG. 2 is a plan view schematically illustrating the semiconductor package shown in FIG. 1. FIG. 3 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 4 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 5 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 6 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 7 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 8 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 9 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 10 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 11 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 12 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 13 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 14 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. FIG. 15 is a cross-sectional view schematically illustrating an embodiment of a method for manufacturing a semiconductor package. Fig. 16 is a cross-sectional view schematically illustrating another embodiment of a semiconductor package according to the present disclosure. Fig. 17 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 18 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 19 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 20 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 21 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 22 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 23 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package. Fig. 24 is a cross-sectional view schematically illustrating another embodiment of a method for manufacturing a semiconductor package.Fig. 25 is a cross-sectional view illustrating another embodiment of the method for manufacturing a semiconductor package. Fig. 26 is a cross-sectional view illustrating another embodiment of the method for manufacturing a semiconductor package. Fig. 27 is a cross-sectional view illustrating another embodiment of the method for manufacturing a semiconductor package. Fig. 28 is a cross-sectional view illustrating another embodiment of the method for manufacturing a semiconductor package.

[0009] Hereinafter, embodiments for carrying out the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments. In the following embodiments, components (including element steps, etc.) are not essential unless otherwise specified. The same applies to numerical values ​​and their ranges, and do not limit the present disclosure.

[0010] In the present disclosure, the term "process" includes not only a process that is independent of other processes, but also a process that cannot be clearly distinguished from other processes as long as the purpose of the process is achieved.

[0011] In the present disclosure, numerical ranges indicated using "to" include the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0012] In the numerical ranges described in stages in this disclosure, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another numerical range described in stages. Furthermore, in the numerical ranges described in this disclosure, the upper or lower limit value of that numerical range may be replaced with a value shown in the examples.

[0013] In the present disclosure, each component may contain multiple substances corresponding to the component. When multiple substances corresponding to each component are present in the composition, the content or amount of each component means the total content or amount of the multiple substances present in the composition, unless otherwise specified.

[0014] In the present disclosure, the term "layer" includes cases where the layer is formed over the entire area when the area in which the layer exists is observed, as well as cases where the layer is formed over only a portion of the area.

[0015] When embodiments are described with reference to the drawings in this disclosure, the configuration of the embodiment is not limited to the configuration shown in the drawings. Furthermore, the sizes of components in each drawing are conceptual, and the relative size relationships between components are not limited to these.

[0016] [Semiconductor Package] The semiconductor package of the present disclosure comprises: a first insulating layer including a first wiring layer; a second insulating layer that constitutes a first optical waveguide and is disposed on the first insulating layer; a third insulating layer that includes a second wiring layer and is disposed on the second insulating layer; a conductor that penetrates the second insulating layer and connects the first wiring layer and the second wiring layer; an optical circuit chip that is disposed on the third insulating layer and connected to the first optical waveguide; and an electronic circuit chip that is disposed on the optical circuit chip and connected to the second wiring layer.

[0017] The first optical waveguide may include an optical coupling portion for optically coupling with a second optical waveguide included in the optical circuit chip.

[0018] 1 is a schematic cross-sectional view showing one embodiment of a semiconductor package according to the present disclosure. The semiconductor package 20 according to the present disclosure includes an optoelectronic composite wiring layer 30, an optical circuit chip 50, and an electronic circuit chip 60. The semiconductor package 20 may also be referred to as an optoelectronic composite package.

[0019] (Optoelectronic Composite Wiring Layer 30) As shown in FIG. 1 , the optoelectronic composite wiring layer 30 includes a resin layer, optical wiring, and electrical wiring. Specifically, the optoelectronic composite wiring layer 30 includes a first insulating layer 32, a second insulating layer 34, and a third insulating layer 36. The first insulating layer 32 includes a first wiring layer 42 as electrical wiring. The second insulating layer 34 constitutes a first optical waveguide 44 as optical wiring. The third insulating layer 36 includes a second wiring layer 46 as electrical wiring. The optoelectronic composite wiring layer 30 also includes a conductor 48 as electrical wiring that electrically connects the first wiring layer 42 and the second wiring layer 46. In this embodiment, the optoelectronic composite wiring layer 30 is configured of three layers, the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36, as an example, but the present disclosure is not limited thereto. The optoelectronic composite wiring layer 30 may be formed by stacking four or more insulating layers.

[0020] The first insulating layer 32 includes a first wiring layer 42. Specifically, the first insulating layer 32 is made of an insulating resin material, and is disposed so as to cover the first wiring layer 42.

[0021] The second insulating layer 34 is made of an insulating resin material and is disposed on the first insulating layer 32. In this embodiment, "disposed on a layer" means being laminated on one surface of the corresponding layer. That is, "disposed on the first insulating layer 32" means being laminated on one surface (the top surface in FIG. 1 ) of the first insulating layer 32. The second insulating layer 34 constitutes a first optical waveguide 44. Specifically, the first optical waveguide 44 is constituted by the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. That is, the portion of the second insulating layer 34 that constitutes the first optical waveguide 44 has a higher refractive index than the portions of the first insulating layer 32, the third insulating layer 36, and the second insulating layer 34 other than the portion that constitutes the first optical waveguide 44. An optical signal is guided by this first optical waveguide 44. This first optical waveguide 44 includes a first optical coupling portion 45 that is optically coupled to a second optical waveguide 52 provided in the optical circuit chip 50. Specifically, the first optical waveguide 44 and the second optical waveguide 52 are optically coupled by the second optical coupling portion 53 provided in the second optical waveguide 52 and the first optical coupling portion 45. Note that in the present embodiment, as an example, the first optical coupling portion 45 is a reflecting mirror and the second optical coupling portion 53 is a grating coupler, but the present disclosure is not limited to this configuration.

[0022] The third insulating layer 36 includes a second wiring layer 46 and is disposed on the second insulating layer 34. Specifically, the third insulating layer 36 is made of an insulating resin material and is disposed on the second insulating layer 34 so as to cover the second wiring layer 46 disposed on the second insulating layer 34.

[0023] Each wiring layer may contain one or more metals. Examples of metals constituting each wiring layer include copper, silver, gold, aluminum, etc. However, the metals constituting each wiring layer are not limited to the above metals.

[0024] The conductor 48 penetrates the second insulating layer 34 and electrically connects the first wiring layer 42 and the second wiring layer 46. When there are multiple wiring layers, adjacent wiring layers in the stacking direction may be electrically connected by another conductor. The metal constituting the conductor 48 may be the same as the metal constituting each wiring layer.

[0025] (Optical Circuit Chip 50) The optical circuit chip 50 is disposed on the optoelectronic composite wiring layer 30. Specifically, the optical circuit chip 50 is disposed on the third insulating layer 36. The optical circuit chip 50 is connected to the first optical waveguide 44. Specifically, the optical circuit chip 50 is connected to the first optical waveguide 44 via the second optical coupling portion 53 of the second optical waveguide 52.

[0026] The optical circuit chip 50 may include, for example, an optical circuit chip substrate (such as a silicon substrate), a laser diode or a photodiode, an optical modulator, a transparent resin layer, a waveguide (second optical waveguide 52), and a grating coupler (second optical coupling section 53) disposed on one surface of the optical circuit chip substrate, and a chip electrode 54 disposed on the other surface of the optical circuit chip substrate. The optical circuit chip 50 is connected to a wiring layer for the optical circuit chip 50 in the optoelectronic composite wiring layer 30 via the chip electrode 54.

[0027] Furthermore, a first sealing material 80 that is transparent to the wavelength used is filled between the third insulating layer 36 and the optical circuit chip 50 .

[0028] The optical circuit chip 50 is not particularly limited, and a conventionally known one may be used.

[0029] (Electronic Circuit Chip 60) The electronic circuit chip 60 is disposed on the optical circuit chip 50. The electronic circuit chip 60 is connected to the second wiring layer 46 via chip electrodes 62. Specifically, the electronic circuit chip 60 is connected to the second wiring layer 46 via a wiring layer 56 provided on the optical circuit chip 50. The chip electrodes 62 of the electronic circuit chip 60 are connected to the wiring layer 56.

[0030] The electronic circuit chip 60 may include, for example, an electronic circuit chip substrate (such as a silicon substrate), a transmitting circuit and a receiving circuit arranged on one surface of the electronic circuit chip substrate, and a chip electrode 62 arranged on the other surface of the electronic circuit chip substrate.

[0031] The third insulating layer 36 , the optical circuit chip 50 , and the electronic circuit chip 60 are sealed with a second sealing material 82 .

[0032] 2 is a schematic plan view of the semiconductor package 20 shown in FIG. 2. In the example of FIG. 2, an optical circuit chip 50 is disposed in the center of the optoelectronic composite wiring layer 30, and an electronic circuit chip 60 is disposed on the optical circuit chip 50. These optical circuit chips 50 are connected to a plurality of first optical waveguides 44 extending from optical connectors 70 provided on the periphery of the optoelectronic composite wiring layer 30. Note that in the example of FIG. 2, the optical connector 70 is provided on one side of the optoelectronic composite wiring layer 30, but the present disclosure is not limited to this configuration. For example, the optical connector 70 may be provided on each of two opposing sides of the optoelectronic composite wiring layer 30, or the optical connector 70 may be provided on each of the four sides of the optoelectronic composite wiring layer 30.

[0033] [Method for manufacturing a semiconductor package] The method for manufacturing a semiconductor package of the present disclosure includes the steps of: forming a first insulating layer on a first wiring layer (hereinafter referred to as the "first insulating layer forming step" as appropriate); forming a conductor that penetrates the first insulating layer and connects to the first wiring layer (hereinafter referred to as the "conductor forming step" as appropriate); forming a second insulating layer that constitutes a first optical waveguide on the first insulating layer (hereinafter referred to as the "second insulating layer forming step" as appropriate); forming a second wiring layer that connects to the conductor on the second insulating layer (hereinafter referred to as the "second wiring layer forming step" as appropriate); and forming a third insulating layer on the second wiring layer (hereinafter referred to as the "third insulating layer forming step" as appropriate).

[0034] The method for manufacturing a semiconductor package according to the present disclosure may further include a step of arranging an optical circuit chip on the third insulating layer (hereinafter referred to as an "optical circuit chip arranging step"), and the first optical waveguide may be provided with an optical coupling portion for optically coupling with a second optical waveguide provided in the optical circuit chip.

[0035] The method for manufacturing a semiconductor package according to the present disclosure may further include a step of placing an electronic circuit chip on the optical circuit chip (hereinafter referred to as an "electronic circuit chip placement step" as appropriate).

[0036] Next, an embodiment of a method for manufacturing a semiconductor package according to the present disclosure will be described. Figures 3 to 15 are schematic cross-sectional views illustrating an embodiment of a method for manufacturing a semiconductor package 20.

[0037] First, a support substrate 100 is prepared as shown in Fig. 3. This support substrate 100 has a temporary fixing layer 102 on its surface (the upper surface in Fig. 3). The support substrate 100 may be one manufactured by a conventionally known method, or a commercially available one. For example, a glass substrate may be used as the support substrate 100.

[0038] Examples of materials constituting the temporary fixing layer 102 include resins containing non-polar components such as acrylic, epoxy, polyimide, polybenzoxazole, silicone, and fluorine, resins containing components that expand in volume or foam when heated or exposed to ultraviolet (UV) light, resins containing components that undergo a crosslinking reaction when heated or exposed to UV light, and resins that generate heat when exposed to light. It is also known that using a layer made of carbon or hydrocarbon as the temporary fixing layer 102 makes it possible to accommodate mechanical peeling, and this may also be used.

[0039] Next, as shown in Fig. 4, a seed layer 104 is provided on the surface (top surface in Fig. 4) of the temporary fixing layer 102. The material constituting the seed layer 104 is not particularly limited, and a conventionally known material may be used. For example, the seed layer 104 may be formed by sputtering or plating copper, titanium, or the like onto a glass substrate serving as the support substrate 100.

[0040] In the manufacturing method of this embodiment, the seed layer 104 is provided on the surface of the temporary fixing layer 102, but the present disclosure is not limited to this configuration. For example, a support substrate 100 in which the seed layer 104 is provided in advance on the surface of the temporary fixing layer 102 may be used.

[0041] 5, a first wiring layer 42 is formed on the surface (top surface in FIG. 5) of the seed layer 104. The first wiring layer 42 of this embodiment is a redistribution layer, and can be formed by a conventionally known method.

[0042] In one embodiment of the present disclosure, the rewiring layer is formed by the following method. First, a positive or negative photosensitive resin composition is applied to the surface of the target object or target layer to form a coating film. Next, the coating film is exposed to light. After exposure, if the coating film is a positive material, the exposed portions are removed with a developer, and if the coating film is a negative material, the unexposed portions are removed. Next, metal wiring is placed in the removed portions by a method such as plating. This forms the rewiring layer. Here, a film-like photosensitive resin composition may be used, and this may be laminated by a method such as lamination.

[0043] The above-mentioned coating film formation, exposure, and wiring arrangement may be repeated. Furthermore, drying may be performed after the application of the photosensitive resin composition. A hot plate, an oven, or the like may be used for drying. A conventionally known mask may be used for exposing the coating film. Furthermore, ultraviolet light, visible light, radiation, or the like may be used for exposure. Examples of the developer that can be used include aqueous solutions containing alkaline components such as sodium hydroxide, potassium hydroxide, sodium carbonate, potassium carbonate, sodium silicate, ammonia, ethylamine, diethylamine, triethylamine, triethanolamine, and tetramethylammonium hydroxide; and organic solvents such as γ-butyrolactone, ethyl lactate, propylene glycol monomethyl ether acetate, benzyl acetate, n-butyl acetate, ethoxyethyl propionate, 3-methylmethoxypropionate, N-methyl-2-pyrrolidone, N,N-dimethylformamide, N,N-dimethylacetamide, dimethyl sulfoxide, hexamethylphosphorylamide, tetramethylene sulfone, diethyl ketone, diisobutyl ketone, methyl amyl ketone, cyclopentanone, cyclohexanone, propylene glycol monomethyl ether, propylene glycol monopropyl ether, propylene glycol monobutyl ether, and dipropylene glycol monomethyl ether. For drying the coating film after development, ovens such as a quartz tube furnace, a hot plate, a convection oven, a rapid thermal annealing oven, a vertical diffusion furnace, an infrared heating furnace, an electron beam heating furnace, a microwave heating furnace, a microwave heating device, a variable frequency microwave heating device, and the like can be used.

[0044] As an example, the first wiring layer 42 is formed by forming a coating film of a positive photosensitive resin composition on the surface of the seed layer 104, which is made of titanium and copper in this order, exposing the coating film to light, removing the exposed portion with a developer after the exposure, and disposing copper wiring in the removed exposed portion by electrolytic plating. Thereafter, the photosensitive resin composition is removed.

[0045] (First Insulating Layer Formation Process) Next, as shown in FIG. 6 , a first insulating layer 32 is formed on the first wiring layer 42. The first insulating layer 32 may be formed by depositing a film-like resin material on the first wiring layer 42, or by applying a liquid resin material to the first wiring layer 42 and curing it. The resin material constituting the first insulating layer 32 is preferably a photosensitive resin composition. The photosensitive resin composition is not particularly limited, and conventionally known materials may be used, specifically, negative-type materials that undergo photopolymerization, or positive-type materials that exhibit solubility in alkaline aqueous solutions upon exposure to light. Specific examples of photopolymerizable materials include nitrone derivatives, norbornadiene derivatives, polyvinyl cinnamate, and maleimide compounds, which contain functional groups that undergo photopolymerization, such as C═C (unsaturated double bonds), maleimide groups, indene groups, cinnamate groups, stilbene groups, and cinnamoyl groups. Epoxy resins are also known to undergo photopolymerization. On the other hand, specific examples of materials that exhibit solubility upon irradiation with light include α-diazoketone compounds and azide compounds having an azide group, which is a functional group that releases nitrogen upon irradiation with light. By including at least one of these, the material exhibits the function of curing or dissolving upon exposure to light. Therefore, as long as it includes at least one of these, it may be used by appropriately selecting from alkali-soluble resins having a phenolic hydroxyl group, acrylic resins, epoxy resins, polyimide resins, polyamideimide resins, polybenzoxazole resins, and the like.

[0046] Next, through holes 32A for conductors 48 that connect the first wiring layer 42 and the second wiring layer 46 are formed in the surface (top surface in FIG. 6 ) of the first insulating layer 32. These through holes 32A may be formed, for example, by drilling, by laser irradiation, or by exposure and development.

[0047] 7, the conductor 48 is formed so as to penetrate the first insulating layer 32 and connect to the first wiring layer 42. The conductor 48 is formed at the position of the through hole 32A. The conductor 48 can be formed by the same method as that for the first wiring layer 42.

[0048] 8, a second insulating layer 34 that constitutes the first optical waveguide 44 is formed on the first insulating layer 32. Similar to the first insulating layer 32, the second insulating layer 34 may be formed by disposing a film-like resin material on the first insulating layer 32, or by applying a liquid resin material onto the first insulating layer 32 and curing it.

[0049] In addition, the first optical waveguide 44 is formed by exposing and developing the second insulating layer 34 and patterning it into a circuit shape, and this is covered with the first insulating layer 32 and the third insulating layer 36, which have a lower refractive index than the second insulating layer 34, so that the second insulating layer 34 functions as the core of the optical waveguide, and the first insulating layer 32 and the third insulating layer 36 function as the cladding of the optical waveguide.

[0050] Next, through holes 34A connecting the conductors 48 and the second wiring layer 46 are formed in the surface (top surface in FIG. 8 ) of the second insulating layer 34. These through holes 34A may be formed, for example, by drilling, by laser irradiation, or by exposure and development. Forming through exposure and development is preferable because it allows the through holes 34A to be produced in the same process as the patterning of the first optical waveguide 44.

[0051] The resin material constituting the second insulating layer 34 is a photosensitive resin composition. This photosensitive resin composition is not particularly limited, and the same photosensitive resin composition as that of the first insulating layer 32 can be used.

[0052] Furthermore, the present disclosure is not limited to the above configuration. For example, the resin material constituting the second insulating layer 34 may contain a substance whose refractive index is modulated by exposure. Specifically, the second insulating layer 34 is a photosensitive layer containing a substance whose refractive index increases when exposed to light with a wavelength of 10 nm to 450 nm, including ultraviolet light. By forming a mask on such second insulating layer 34 and exposing it to light, the refractive index of the exposed portion of the second insulating layer 34 increases. This portion with a higher refractive index becomes the first optical waveguide 44.

[0053] Next, the first optical coupling section 45 is formed in the first optical waveguide 44. Specifically, a reflecting mirror is disposed on the first optical waveguide 44 as the first optical coupling section 45. This reflecting mirror may be a metal mirror disposed inside the first optical waveguide 44, or may be formed by evaporating a metal film onto an end of the first optical waveguide 44.

[0054] 9, a second wiring layer 46 connected to the conductor 48 is formed on the second insulating layer 34. A portion of the second wiring layer 46 is formed at the position of the through hole 34A. The second wiring layer 46 can be formed by the same method as the first wiring layer 42.

[0055] 10, the third insulating layer 36 is formed on the second insulating layer 34. As with the first insulating layer 32, the third insulating layer 36 may be formed by disposing a film-like resin material on the second insulating layer 34, or by applying a liquid resin material onto the second insulating layer 34 and curing it.

[0056] Next, through holes 36A that connect the chip electrodes 54 of the optical circuit chip 50 and the second wiring layer 46 are formed in the surface (top surface in FIG. 10 ) of the third insulating layer 36. These through holes 36A may be formed, for example, by drilling, by laser irradiation, or by exposure and development.

[0057] 11, the optical circuit chip 50 is placed on the third insulating layer 36. Specifically, the optical circuit chip 50 is placed on the third insulating layer 36, and each chip electrode 54 is connected to the second wiring layer 46, i.e., electrically connected.

[0058] Next, as shown in FIG. 12, a first sealing material 80 that is transparent to the wavelength to be used is injected into the gap between the third insulating layer 36 and the optical circuit chip 50 .

[0059] 13, the electronic circuit chip 60 is placed on the optical circuit chip 50. Specifically, the electronic circuit chip 60 is placed on the optical circuit chip 50, and the wiring layer 56 provided on the optical circuit chip 50 and the chip electrodes 54 of the electronic circuit chip 60 are connected, i.e., electrically connected.

[0060] 14, the third insulating layer 36, the optical circuit chip 50, and the electronic circuit chip 60 are sealed with a second sealing material 82. The sealing method using the second sealing material 82 is not particularly limited, and can be performed by a conventionally known method. For example, the sealing can be performed by using transfer molding, injection molding, compression molding, or mold underfill.

[0061] Next, the surface (upper surface in FIG. 14) of the second sealing material 82 is polished. This polishing method is not particularly limited, and can be performed by a conventionally known method.

[0062] (Supporting Substrate Removal Process) Next, as shown in Fig. 15, the supporting substrate 100 is removed. The method for removing the supporting substrate 100 is not particularly limited, and can be performed by a conventionally known method. Note that, when the supporting substrate 100 includes a temporary fixing layer 102, the temporary fixing layer 102 is also removed together with the supporting substrate 100.

[0063] Next, the seed layer 104 is removed from the lower surfaces of the first wiring layer 42 and the first insulating layer 32. For example, the seed layer 104 can be removed by etching using known methods such as spraying or swing immersion, and the seed layer 104 can be removed by polishing using known methods such as brushing or scraping.

[0064] In this manner, the semiconductor package 20 having optical wiring and electrical wiring is manufactured.

[0065] The manufacturing method of the present disclosure is not limited to the above, and may include, for example, a step of providing solder balls on the lower surface of the first wiring layer 42 .

[0066] Next, the effects of this embodiment will be described. In this embodiment, compared to a configuration in which a rewiring layer for the optical circuit chip 50 and a rewiring layer for the electronic circuit chip 60 are separately provided, one optoelectronic composite wiring layer 30 serves as both a rewiring layer for the optical circuit chip 50 and a rewiring layer for the electronic circuit chip 60, i.e., it serves the functions of both optical rewiring and electrical rewiring, thereby improving the productivity of the semiconductor package 20. Furthermore, since the length of electrical and optical wiring can be shortened, it is possible to improve the quality of both electrical and optical signals and reduce loss.

[0067] Furthermore, in this embodiment, the first optical waveguide 44 is provided with a first optical coupling portion 45 for optically coupling with the second optical waveguide 52 provided in the optical circuit chip 50, so that the layout of the first optical waveguide 44 (layout of the optical wiring) can be freely set.

[0068] In addition, in this embodiment, since the electronic circuit chip 60 is disposed on the optical circuit chip 50, the size of the optoelectronic composite wiring layer 30 can be made smaller than when the electronic circuit chip 60 is disposed around the optical circuit chip 50. Furthermore, since the electronic circuit chip 60 is disposed on the optical circuit chip 50, the signal transmission efficiency between them is improved. Also, power saving is achieved.

[0069] Other Embodiments Next, other embodiments of the semiconductor package and the method for manufacturing the semiconductor package according to the present disclosure will be described.

[0070] 16 , a semiconductor package 120 of another embodiment includes an optoelectronic composite wiring layer 130, an optical circuit chip 50, and an electronic circuit chip 60. The optoelectronic composite wiring layer 130 includes a first insulating layer 132, a second insulating layer 134, and a third insulating layer 136 arranged in this order from the optical circuit chip 50 side. The first wiring layer 142 is arranged closer to the optical circuit chip 50 than the second wiring layer 146. The first wiring layer 142 is in direct contact with the wiring layer 56 of the optical circuit chip 50. Therefore, in the semiconductor package 120 of this embodiment, it is possible to omit the sealant that seals the gap between the optical circuit chip 50 and the first wiring layer 142, in other words, the sealant that covers the periphery of the chip electrodes 54.

[0071] Next, a method for manufacturing a semiconductor package according to another embodiment of the present disclosure will be described. The method for manufacturing a semiconductor package according to the present disclosure includes the steps of forming a first insulating layer on a first wiring layer (hereinafter referred to as the "first insulating layer forming step"), forming a second insulating layer constituting a first optical waveguide on the first insulating layer (hereinafter referred to as the "second insulating layer forming step"), forming a second wiring layer on the second insulating layer and forming a conductor that penetrates the first insulating layer and the second insulating layer and connects the first wiring layer to the second wiring layer (hereinafter referred to as the "conductor forming step"), and forming a third insulating layer on the second wiring layer (hereinafter referred to as the "third insulating layer forming step").

[0072] The method for manufacturing a semiconductor package according to the present disclosure may further include a step of forming the first wiring layer on the optical circuit chip (hereinafter referred to as the "first wiring layer forming step" as appropriate), and the first optical waveguide may be provided with an optical coupling portion for optically coupling with a second optical waveguide provided on the optical circuit chip.

[0073] The method for manufacturing a semiconductor package according to the present disclosure may further include a step of placing an electronic circuit chip on the optical circuit chip (hereinafter referred to as an "electronic circuit chip placement step" as appropriate).

[0074] Next, another embodiment of the method for manufacturing a semiconductor package according to the present disclosure will be described. Figures 17 to 28 are schematic cross-sectional views illustrating one embodiment of the method for manufacturing a semiconductor package 20.

[0075] First, as shown in FIG. 17, a support substrate 100 having a temporary fixing layer 102 is prepared.

[0076] Next, as shown in FIG. 18, the optical circuit chip 50 is placed on the surface of the temporary fixing layer 102 of the support substrate 100 .

[0077] 19, the electronic circuit chip 60 is placed on the optical circuit chip 50. Then, the chip electrodes 62 of the electronic circuit chip 60 and the wiring layer 56 of the optical circuit chip 50 are connected, i.e., electrically connected.

[0078] Next, as shown in FIG. 20, the optical circuit chip 50 and the electronic circuit chip 60 are sealed with a first sealing material 182 .

[0079] Next, the surface (upper surface in FIG. 20) of the first sealing material 182 is polished.

[0080] Next, as shown in FIG. 21, the support substrate 100 is removed.

[0081] Next, as shown in FIG. 22, the surface of the first sealing material 182 on the electronic circuit chip 60 side is placed facing the surface of the temporary fixing layer 102 of the support substrate 100 .

[0082] (First Wiring Layer Formation Process) Next, the first wiring layer 142 is formed on the optical circuit chip 50. The formation of the first wiring layer 142 is similar to that of the previously described embodiment. As an example, the first wiring layer 142 is formed by forming titanium and copper, in this order, on the surface of the optical circuit chip 50 (the upper surface in FIG. 23) as a seed layer for electrolytic plating. Next, a coating film of a positive photosensitive resin composition is formed, and the coating film is exposed to light. After exposure, the exposed portion is removed with a developer, and copper wiring is disposed in the removed exposed portion by electrolytic plating. Thereafter, the photosensitive resin composition and then the seed layer are removed.

[0083] The first wiring layer 142 formed in this manner is in direct contact with the wiring layer 56 of the optical circuit chip 50 .

[0084] 24, the first insulating layer 132 is formed on the first wiring layer 142. The first insulating layer 132 may be formed by disposing a film-like resin material on the first wiring layer 142, or by applying a liquid resin material onto the first wiring layer 142 and curing it.

[0085] Next, through holes 132A for conductors 148 that connect the first wiring layer 142 and the second wiring layer 146 are formed on the surface (top surface in FIG. 24 ) of the first insulating layer 132. These through holes 132A may be formed, for example, by drilling, by laser irradiation, or by exposure and development.

[0086] 25 , a second insulating layer 134 that constitutes a first optical waveguide 144 is formed on the first insulating layer 132. Similar to the first insulating layer 132, the second insulating layer 134 may be formed by disposing a film-like resin material on the first insulating layer 132, or may be formed by applying a liquid resin material onto the first insulating layer 132 and curing it.

[0087] In addition, the first optical waveguide 144 is formed by exposing and developing the second insulating layer 134 and patterning it into a circuit shape, and this is covered with the first insulating layer 132 and the third insulating layer 136, which have a lower refractive index than the second insulating layer 134, so that the second insulating layer 134 functions as the core of the optical waveguide, and the first insulating layer 132 and the third insulating layer 136 function as the cladding of the optical waveguide.

[0088] Next, through holes 134A connecting the conductors 148 and the second wiring layer 146 are formed in the surface (top surface in FIG. 25 ) of the second insulating layer 134. These through holes 134A may be formed, for example, by drilling, by laser irradiation, or by exposure to light and development. Forming through holes 134A by exposure to light and development is preferable because it allows the through holes 134A to be produced in the same process as the patterning of the first optical waveguide 144 described above.

[0089] Next, the first optical coupling section 145 is formed on the first optical waveguide 144. Specifically, a reflecting mirror is disposed as the first optical coupling section 145 on the first optical waveguide 144. This reflecting mirror may be a metal mirror disposed on the first optical waveguide 144, or may be formed by evaporating a metal film onto an end of the first optical waveguide 144.

[0090] 26 , a second wiring layer 146 is formed on the second insulating layer 134, and a conductor 148 is formed that penetrates the first insulating layer 132 and the second insulating layer 134 and connects the first wiring layer 142 and the second wiring layer 146. The conductor 148 is formed at the position of the through hole in the second insulating layer 134. The second wiring layer 146 and the conductor 148 can be formed by a method similar to that for the first wiring layer 42.

[0091] In this embodiment, the conductor forming step and the second wiring layer forming step are performed simultaneously, but the present disclosure is not limited to this configuration. The conductor forming step and the second wiring layer forming step may be performed separately. Specifically, the second wiring layer 146 may be formed after the conductor 148 is formed.

[0092] 27, the third insulating layer 136 is formed on the second insulating layer 134. As with the first insulating layer 132, the third insulating layer 136 may be formed by disposing a film-like resin material on the second insulating layer 134, or by applying a liquid resin material onto the second insulating layer 134 and curing it.

[0093] Next, through holes 136A for forming solder balls to be connected to the second wiring layer 46 are formed in the surface (top surface in FIG. 27 ) of the third insulating layer 136. These through holes 136A may be formed, for example, by drilling, by laser irradiation, or by exposure and development.

[0094] (Support Base Removal Process) Next, as shown in FIG. 28, the support base 100 and the temporary fixing layer 102 are removed from the electronic circuit chip 60 and the first sealing material 182.

[0095] In this manner, the semiconductor package 120 having optical wiring and electrical wiring is manufactured.

[0096] The manufacturing method of the present disclosure is not limited to the above, and may include, for example, a step of providing a solder ball on the surface of the second wiring layer 146 exposed from the third insulating layer 136 .

[0097] Next, the effects of other embodiments will be described, with the effects obtained by the same configuration as the semiconductor package 20 and the manufacturing method of the semiconductor package 20 being omitted.

[0098] In other embodiments, the first wiring layer 142 is in direct contact with the wiring layer 56 of the optical circuit chip 50, which allows for fewer components (materials) than when chip electrodes are used for connection, thereby enabling cost reduction. Furthermore, the number of processes using components that can be reduced can be reduced, improving productivity. Furthermore, since the first wiring layer 142 is in direct contact with the wiring layer 56 of the optical circuit chip 50, the height of the semiconductor package 20 can be reduced compared to when chip electrodes 54 are provided.

[0099] In the other embodiment described above, the optical circuit chip 50 and the electronic circuit chip 60 are sealed with the first sealing material 182, and then the first sealing material 182 is reattached to the support substrate 100, but the present disclosure is not limited to this configuration. If sufficient strength can be ensured by the second sealing material 82, it is not necessary to reattach the second sealing material 182 to the support substrate 100. In this case, the step of reattaching the second sealing material 82 can be omitted, and the productivity of the semiconductor package 120 is improved.

[0100] Although the embodiments of the present disclosure have been described above, these embodiments are merely examples and can be modified in various ways without departing from the spirit and scope of the present disclosure. It goes without saying that the scope of the present disclosure is not limited to these embodiments.

[0101] 20 Semiconductor package 30 Optoelectronic composite wiring layer 32 First insulating layer 32A Through hole 34 Second insulating layer 34A Through hole 36 Third insulating layer 36A Through hole 42 First wiring layer 44 First optical waveguide 45 First optical coupling section (an example of an optical coupling section) 46 Second wiring layer 48 Conductor 50 Optical circuit chip 52 Second optical waveguide 53 Second optical coupling section 54 Chip electrode 56 Wiring layer 60 Electronic circuit chip 62 Chip electrode 70 Optical connector 80 First sealing material 82 Second sealing material 100 Support base material 102 Temporary fixing layer 104 Seed layer 120 Semiconductor package 132 First insulating layer 132A Through hole 134 Second insulating layer 134A Through hole 136 Third insulating layer 136A Through hole 142 First wiring layer 144 First optical waveguide 145 First optical coupling section (an example of an optical coupling section) 146 Second wiring layer 148 Conductor 182 First sealing material

Claims

1. A method for manufacturing a semiconductor package, comprising the steps of: forming a first insulating layer on a first wiring layer; forming a conductor that penetrates the first insulating layer and connects to the first wiring layer; forming a second insulating layer on the first insulating layer to form a first optical waveguide; forming a second wiring layer on the second insulating layer that connects to the conductor; and forming a third insulating layer on the second wiring layer.

2. The method for manufacturing a semiconductor package according to claim 1, further comprising the step of placing an optical circuit chip on said third insulating layer, wherein said first optical waveguide is provided with an optical coupling portion for optically coupling with a second optical waveguide provided in said optical circuit chip.

3. The method for manufacturing a semiconductor package according to claim 2, further comprising the step of placing an electronic circuit chip on said optical circuit chip.

4. A method for manufacturing a semiconductor package, comprising the steps of: forming a first insulating layer on a first wiring layer; forming a second insulating layer on the first insulating layer that constitutes a first optical waveguide; forming a second wiring layer on the second insulating layer and forming a conductor that penetrates the first insulating layer and the second insulating layer and connects the first wiring layer to the second wiring layer; and forming a third insulating layer on the second wiring layer.

5. The method for manufacturing a semiconductor package according to claim 4, further comprising the step of forming the first wiring layer on the optical circuit chip, and the first optical waveguide is provided with an optical coupling portion for optically coupling with a second optical waveguide provided in the optical circuit chip.

6. The method for manufacturing a semiconductor package according to claim 5, further comprising the step of placing an electronic circuit chip on said optical circuit chip.

7. A semiconductor package comprising: a first insulating layer including a first wiring layer; a second insulating layer forming a first optical waveguide and disposed on the first insulating layer; a third insulating layer including a second wiring layer and disposed on the second insulating layer; a conductor penetrating the second insulating layer and connecting the first wiring layer and the second wiring layer; an optical circuit chip disposed on the third insulating layer and connected to the first optical waveguide; and an electronic circuit chip disposed on the optical circuit chip and connected to the second wiring layer.

8. The semiconductor package according to claim 7, wherein the first optical waveguide comprises an optical coupling portion for optically coupling to a second optical waveguide included in the optical circuit chip.

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