Solid-state imaging element and electronic device

Abstract

This solid-state imaging element comprises a photoelectric conversion layer and a plurality of on-chip lenses. The photoelectric conversion layer has a plurality of photoelectric conversion parts. The plurality of on-chip lenses are positioned, side by side in a matrix, closer to the light-incident side than the photoelectric conversion layer. In addition, a first boundary part located between diagonally adjacent on-chip lenses is spaced further apart from a first surface, located on the light-incident side of the photoelectric conversion layer, than a second boundary part located between on-chip lenses adjacent to each other in the row direction or column direction.

Description

Solid-state imaging device and electronic device

[0001] The present disclosure relates to a solid-state imaging device and an electronic device.

[0002] Noise generated by solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors can be divided into random noise and fixed pattern noise. Random noise changes over time, while fixed pattern noise occurs in a fixed manner regardless of time.

[0003] Since this fixed pattern noise reduces the quality of captured images, various methods have been proposed for reducing fixed pattern noise in solid-state imaging devices (see, for example, Japanese Patent Application Laid-Open No. 2003-144998).

[0004] Japanese Patent Application Laid-Open No. 2019-140581

[0005] However, the above-described conventional technology does not take any measures against fixed pattern noise caused by the on-chip lens, and therefore has a problem in that the fixed pattern noise caused by the on-chip lens cannot be reduced.

[0006] Therefore, the present disclosure proposes a solid-state imaging device and an electronic device that can reduce fixed pattern noise caused by an on-chip lens.

[0007] According to the present disclosure, there is provided a solid-state imaging element. The solid-state imaging element includes a photoelectric conversion layer and a plurality of on-chip lenses. The photoelectric conversion layer has a plurality of photoelectric conversion units. The plurality of on-chip lenses are arranged in a matrix on the light incident side of the photoelectric conversion layer. Furthermore, first boundaries located between diagonally adjacent on-chip lenses are farther from a first surface located on the light incident side of the photoelectric conversion layer than second boundaries located between diagonally adjacent on-chip lenses in the row direction or the column direction.

[0008] 16 is a system configuration diagram showing a schematic configuration example of a solid-state imaging element according to an embodiment of the present disclosure. FIG. 17 is a circuit diagram showing an example of a circuit configuration of a unit pixel according to an embodiment of the present disclosure. FIG. 18 is a plan view for explaining an example of an arrangement of photodiodes, color filters, and on-chip lenses in a pixel array unit according to an embodiment of the present disclosure. FIG. 19 is a cross-sectional view taken along the arrows A-A shown in FIG. 3. FIG. 19 is a cross-sectional view taken along the arrows B-B shown in FIG. 3. FIG. 19 is a cross-sectional view schematically showing the structure of a pixel array unit in a reference example. FIG. 20 is a diagram showing evaluation results of fixed pattern noise in pixel array units of an embodiment and a reference example. FIG. 21 is a diagram showing an example of a manufacturing process for an on-chip lens according to an embodiment of the present disclosure. FIG. 22 is a diagram showing an example of a manufacturing process for an on-chip lens according to an embodiment of the present disclosure. FIG. 23 is a diagram showing an example of a manufacturing process for an on-chip lens according to an embodiment of the present disclosure. FIG. 24 is a diagram showing an example of a manufacturing process for an on-chip lens according to an embodiment of the present disclosure. FIG. 25 is a diagram showing an example of a manufacturing process for an on-chip lens according to an embodiment of the present disclosure. FIG. 26 is a diagram showing an example of a manufacturing process for an on-chip lens according to an embodiment of the present disclosure. Fig. 10 is a cross-sectional view schematically illustrating a structure of a pixel array unit according to a modified example 2 of the embodiment of the present disclosure. Fig. 11 is a block diagram illustrating an example of the configuration of an imaging device as an electronic device to which the technology according to the present disclosure is applied.

[0009] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0010] Noise generated in solid-state imaging devices such as CMOS image sensors can be divided into random noise and fixed pattern noise. Random noise changes over time, while fixed pattern noise occurs in a fixed manner regardless of time.

[0011] Since this fixed pattern noise reduces the quality of captured images, various methods have been proposed for reducing fixed pattern noise in solid-state imaging devices.

[0012] However, in the above-mentioned conventional technologies, signal processing or the like is performed as a countermeasure against fixed pattern noise, but no countermeasure is taken against fixed pattern noise caused by on-chip lenses, which poses a problem that fixed pattern noise caused by on-chip lenses cannot be reduced.

[0013] Therefore, there is a need to develop a technology that can overcome the above-mentioned problems and reduce fixed pattern noise caused by on-chip lenses.

[0014] 1 is a system configuration diagram showing a schematic configuration example of a solid-state imaging device 1 according to an embodiment of the present disclosure. As shown in FIG. 1, the solid-state imaging device 1, which is a CMOS image sensor, includes a pixel array unit 10, a system control unit 12, a vertical drive unit 13, a column readout circuit unit 14, a column signal processing unit 15, a horizontal drive unit 16, and a signal processing unit 17.

[0015] The pixel array section 10, system control section 12, vertical drive section 13, column readout circuit section 14, column signal processing section 15, horizontal drive section 16 and signal processing section 17 are provided on the same semiconductor substrate or on multiple electrically connected stacked semiconductor substrates.

[0016] The pixel array section 10 has effective unit pixels (hereinafter also referred to as "unit pixels") 11 arranged two-dimensionally in a matrix, each of which has a photoelectric conversion element (such as a photodiode PD (see Figure 2)) that can photoelectrically convert an amount of charge corresponding to the amount of incident light, store it internally, and output it as a signal.

[0017] In addition to the effective unit pixels 11, the pixel array section 10 may also include an area in which dummy unit pixels having a structure that does not have a photodiode PD or the like, and light-shielding unit pixels that block light incident from outside by shading the light-receiving surface, are arranged in rows and / or columns.

[0018] The light-shielded unit pixel may have the same configuration as the effective unit pixel 11, except that the light-receiving surface is structured so as to be light-shielded. In the following description, the photocharge having an amount corresponding to the amount of incident light may also be simply referred to as "charge," and the unit pixel 11 may also be simply referred to as "pixel."

[0019] In the pixel array unit 10, pixel drive lines LD are formed for each row in the matrix-like pixel arrangement along the left-right direction in the drawing (the direction in which pixels in the pixel row are arranged), and vertical pixel wiring LV are formed for each column in the up-down direction in the drawing (the direction in which pixels in the pixel column are arranged). One end of the pixel drive line LD is connected to an output terminal of the vertical drive unit 13 corresponding to each row.

[0020] The column readout circuit unit 14 includes at least a circuit that supplies a constant current to the unit pixels 11 in a selected row in the pixel array unit 10 for each column, a current mirror circuit, and a switch for selecting the unit pixel 11 to be read out.

[0021] The column readout circuit unit 14 forms an amplifier together with the transistors in the selected pixels in the pixel array unit 10, converts the photocharge signal into a voltage signal, and outputs it to the vertical pixel line LV.

[0022] The vertical drive unit 13 includes a shift register, an address decoder, etc., and drives each unit pixel 11 of the pixel array unit 10 all at once or row by row, etc. Although the specific configuration of this vertical drive unit 13 is not shown in the figure, it is configured to have a readout scanning system and a sweep scanning system or a batch sweep and batch transfer system.

[0023] The readout scanning system sequentially selects and scans the unit pixels 11 of the pixel array section 10 row by row in order to read out pixel signals from the unit pixels 11. In the case of row driving (rolling shutter operation), for sweeping, for the readout row on which readout scanning is performed by the readout scanning system, sweeping scanning is performed prior to the readout scanning by the shutter speed.

[0024] In the case of global exposure (global shutter operation), a collective sweep is performed prior to the collective transfer by the time of the shutter speed. By this sweep, unnecessary charges are swept (reset) from the photodiodes PD of the unit pixels 11 of the readout row. Then, the sweep (reset) of unnecessary charges performs a so-called electronic shutter operation.

[0025] Here, the electronic shutter operation refers to an operation of discarding unnecessary photocharges that have been accumulated in the photodiode PD and the like until just before, and starting new exposure (starting accumulation of photocharges).

[0026] The signal read by the readout operation by the readout scanning system corresponds to the amount of light that has entered since the immediately preceding readout operation or electronic shutter operation. In the case of row driving, the period from the readout timing of the immediately preceding readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the accumulation time (exposure time) of the photocharges in the unit pixel 11. In the case of global exposure, the time from the collective sweep to the collective transfer is the accumulation time (exposure time).

[0027] The pixel signals output from each unit pixel 11 in a pixel row selected and scanned by the vertical drive unit 13 are supplied through each vertical pixel wiring LV to the column signal processing unit 15. The column signal processing unit 15 performs predetermined signal processing on the pixel signals output from each unit pixel 11 in the selected row through the vertical pixel wiring LV for each pixel column in the pixel array unit 10, and temporarily holds the pixel signals after signal processing.

[0028] Specifically, the column signal processing unit 15 performs at least noise removal processing, such as correlated double sampling (CDS) processing, as signal processing. The CDS processing by the column signal processing unit 15 removes pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistor AMP.

[0029] In addition to the noise removal processing, the column signal processing unit 15 may also be configured to have, for example, an AD conversion function so as to output pixel signals as digital signals.

[0030] The horizontal drive unit 16 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 15. By selective scanning by this horizontal drive unit 16, pixel signals processed by the column signal processing unit 15 are sequentially output to the signal processing unit 17.

[0031] The system control unit 12 includes a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 13, column signal processing unit 15, horizontal driving unit 16, etc. based on the various timing signals generated by the timing generator.

[0032] The solid-state imaging device 1 further includes a signal processing unit 17 and a data storage unit (not shown). The signal processing unit 17 has at least an addition processing function and performs various signal processing such as addition processing on the pixel signals output from the column signal processing unit 15.

[0033] The data storage unit temporarily stores data necessary for signal processing in the signal processing unit 17. The signal processing unit 17 and the data storage unit may be an external signal processing unit provided on a board separate from the solid-state imaging device 1, such as a DSP (Digital Signal Processor) or software processing, or may be mounted on the same board as the solid-state imaging device 1.

[0034] 2 is a circuit diagram showing an example of a circuit configuration of a unit pixel 11 according to an embodiment of the present disclosure. The unit pixel 11 includes a photodiode PD as a photoelectric conversion unit, a transfer transistor 91, a floating diffusion 92, a reset transistor 93, an amplification transistor 94, and a selection transistor 95.

[0035] The photodiode PD generates and accumulates electric charges (signal charges) according to the amount of light received. The photodiode PD has an anode terminal grounded and a cathode terminal connected to a floating diffusion 92 via a transfer transistor 91.

[0036] When the transfer transistor 91 is turned on by a transfer signal TG, it reads out the charge generated by the photodiode PD and transfers it to the floating diffusion 92 .

[0037] The floating diffusion 92 holds the charge read out from the photodiode PD. When the reset transistor 93 is turned on by a reset signal RST, it discharges the charge accumulated in the floating diffusion 92 to the drain (constant voltage source Vdd), thereby resetting the potential of the floating diffusion 92.

[0038] The amplification transistor 94 outputs a pixel signal according to the potential of the floating diffusion 92. That is, the amplification transistor 94 configures a source follower circuit together with a load (not shown) serving as a constant current source connected via a vertical signal line 96.

[0039] The amplification transistor 94 then outputs a pixel signal indicating a level corresponding to the charge accumulated in the floating diffusion 92 to the column signal processing unit 15 (see FIG. 1) via the selection transistor 95 .

[0040] The selection transistor 95 is turned on when the unit pixel 11 is selected by the selection signal SEL, and outputs a pixel signal generated in the unit pixel 11 to the column signal processing unit 15 via a vertical signal line 96. The signal lines through which the transfer signal TG, the selection signal SEL, and the reset signal RST are transmitted are connected to the vertical drive unit 13 (see FIG. 1).

[0041] The unit pixel 11 can be configured as described above, but is not limited to the configuration shown in Fig. 2 and other configurations can also be adopted. For example, a shared pixel structure can be adopted in which a plurality of unit pixels 11 share the floating diffusion 92, reset transistor 93, amplification transistor 94, and selection transistor 95.

[0042] [Configuration of Pixel Array Section] Next, a detailed configuration of the pixel array section 10 will be described with reference to Figures 3 to 7. Figure 3 is a plan view for explaining an example of the arrangement of the photodiodes PD, color filters 30, and on-chip lenses 40 in the pixel array section 10 according to an embodiment of the present disclosure.

[0043] 3 , the pixel array unit 10 according to the embodiment includes a plurality of photodiodes PD and a plurality of on-chip lenses 40. In a plan view, the plurality of photodiodes PD and the plurality of on-chip lenses 40 are arranged in a matrix. In the embodiment, one photodiode PD is located for one on-chip lens 40.

[0044] The color filter 30 (see FIG. 4) is an optical filter that transmits light in a predetermined wavelength range out of the light L (see FIG. 4) that is incident on the pixel array unit 10. The plurality of color filters 30 includes, for example, a plurality of red filters 30R (see FIG. 4), a plurality of green filters 30G (see FIG. 5), and a plurality of blue filters 30B (see FIG. 4).

[0045] The red filter 30R transmits light in the red wavelength range (hereinafter also referred to as red light) of the light L. The green filter 30G transmits light in the green wavelength range (hereinafter also referred to as green light) of the light L. The blue filter 30B transmits light in the blue wavelength range (hereinafter also referred to as blue light) of the light L.

[0046] In this embodiment, one of a red filter 30R, a green filter 30G, and a blue filter 30B is provided for each on-chip lens 40. The multiple color filters 30 are arranged in a regular color array (for example, a Bayer array).

[0047] In addition, in the drawings of this disclosure, for ease of understanding, the location where the red filter 30R is located may be marked with "R," the location where the green filter 30G is located may be marked with "G," and the location where the blue filter 30B is located may be marked with "B."

[0048] 3 , in the embodiment, the multiple on-chip lenses 40 arranged in a matrix have multiple first boundaries 41 and multiple second boundaries 42. The first boundaries 41 are located between the on-chip lenses 40 that are diagonally adjacent to each other. The second boundaries 42 are located between the on-chip lenses 40 that are adjacent to each other in the row direction or the column direction.

[0049] Fig. 4 is a cross-sectional view taken along the line A-A in Fig. 3. Fig. 5 is a cross-sectional view taken along the line B-B in Fig. 3. That is, Fig. 4 is a cross-sectional view including on-chip lenses 40 adjacent to each other in the diagonal direction, and Fig. 5 is a cross-sectional view including on-chip lenses 40 adjacent to each other in the row direction.

[0050] As shown in FIGS. 4 and 5 , the pixel array unit 10 according to the embodiment includes a semiconductor layer 20 , a plurality of color filters 30 , and a plurality of on-chip lenses 40 .

[0051] The semiconductor layer 20 is an example of a photoelectric conversion layer and includes an inorganic semiconductor material such as silicon, etc. The semiconductor layer 20 has a plurality of photodiodes PD.

[0052] In this disclosure, a photodiode PD that photoelectrically converts red light may be referred to as a "photodiode PD(R)," and a photodiode PD that photoelectrically converts green light may be referred to as a "photodiode PD(G)." In addition, in this disclosure, a photodiode PD that photoelectrically converts blue light may be referred to as a "photodiode PD(B)."

[0053] The semiconductor layer 20 has a semiconductor region 21 of a first conductivity type (for example, P type) and a semiconductor region 22 of a second conductivity type (for example, N type). Then, inside the semiconductor region 21 of the first conductivity type, the semiconductor regions 22 of the second conductivity type are formed in a matrix, thereby forming photodiodes PD by PN junctions arranged in a matrix.

[0054] Furthermore, in the semiconductor layer 20, isolation regions 23 are provided between adjacent photodiodes PD. The isolation regions 23 optically and electrically isolate the adjacent photodiodes PD. The isolation regions 23 are arranged, for example, in a grid pattern in the pixel array section 10 in plan view.

[0055] The plurality of color filters 30 are located, for example, on a first surface 20a, which is the light incident side surface of the semiconductor layer 20. In the present disclosure, the "light incident side" refers to the side on which light L from the outside is incident.

[0056] As shown in FIGS. 4 and 5, a red filter 30R is located on the light incident side of the photodiode PD(R), a green filter 30G is located on the light incident side of the photodiode PD(G), and a blue filter 30B is located on the light incident side of the photodiode PD(B).

[0057] A wiring layer (not shown) is located on the surface opposite to the first surface 20a of the semiconductor layer 20. In this wiring layer, multiple layers of wiring and multiple pixel transistors (such as the various transistors shown in FIG. 2) are provided inside an interlayer insulating film.

[0058] The multiple on-chip lenses 40 are located closer to the light incident side than the multiple color filters 30. In the embodiment, one unit pixel 11 is provided with one photodiode PD, one color filter 30, and one on-chip lens 40.

[0059] Here, in the embodiment, as shown in Figures 4 and 5, it is preferable that the first boundary 41 between the pair of on-chip lenses 40 is farther from the first surface 20a of the semiconductor layer 20 than the second boundary 42 between the pair of on-chip lenses 40.

[0060] In other words, in the embodiment, the distance L1 between the first boundary 41 and the first surface 20a of the semiconductor layer 20 is longer than the distance L2 between the second boundary 42 and the first surface 20a of the semiconductor layer 20 (i.e., L1 > L2).

[0061] This makes it possible to reduce fixed pattern noise caused by the on-chip lens 40. The reason for this will be explained below.

[0062] 6 is a cross-sectional view schematically illustrating the structure of a pixel array unit 10 according to a reference example, and corresponds to FIG. 4 of the embodiment. In the pixel array unit 10 according to the reference example, the distance L1 between the first boundary 41 and the first surface 20 a of the semiconductor layer 20 is shorter than the distance L2 between the second boundary 42 and the first surface 20 a of the semiconductor layer 20 (i.e., L1<L2). This is for the following reason.

[0063] 3 , in the multiple on-chip lenses 40 arranged in a matrix, the first boundary 41 is wider than the second boundary 42. Therefore, when the multiple on-chip lenses 40 are formed by etching, the etching progresses more at the first boundary 41, which is wider than the second boundary 42, than at the second boundary 42.

[0064] 6, the first boundary 41 is deeper than the second boundary 42, and the distance L1 is shorter than the distance L2. In the reference example, as shown in FIG. 6, the etching process progresses significantly in the portion of the on-chip lens 40 adjacent to the first boundary 41, resulting in a very steep curve.

[0065] Furthermore, it is difficult to uniformly form the steeply curved portions in all of the on-chip lenses 40. Therefore, in the reference example, the shape of the on-chip lenses 40 varies greatly. Therefore, in the reference example, it is very difficult to reduce the fixed pattern noise caused by the on-chip lenses 40.

[0066] On the other hand, in the embodiment, by forming the first boundary 41 shallower than the second boundary 42, it is possible to prevent the curve of the portion of the on-chip lens 40 adjacent to the first boundary 41 from becoming too steep, as shown in FIG.

[0067] This reduces variations in the shape of the on-chip lens 40. Therefore, according to the embodiment, fixed pattern noise caused by the on-chip lens 40 can be reduced.

[0068] 7 is a diagram showing evaluation results of fixed pattern noise in the pixel array unit 10 of the embodiment and the reference example. As shown in Fig. 7, it can be seen that the fixed pattern noise is significantly reduced in the pixel array unit 10 of the embodiment (see Fig. 4) compared to the pixel array unit 10 of the reference example (see Fig. 6).

[0069] 4 , in the embodiment, the first boundary 41 may have a structure that bridges the on-chip lenses 40 that are adjacent to each other in the diagonal direction in a cross-sectional view. This makes it possible to prevent the curve of the on-chip lens 40 at the portion adjacent to the first boundary 41 from becoming too steep.

[0070] Therefore, according to the embodiment, the shape variation of the on-chip lens 40 can be reduced, and therefore the fixed pattern noise caused by the on-chip lens 40 can be reduced.

[0071] [Manufacturing Process of On-Chip Lens] Next, an example of a manufacturing process of the on-chip lens 40 according to the embodiment will be described with reference to Fig. 8 to Fig. 15. Fig. 8 to Fig. 15 are diagrams showing an example of a manufacturing process of the on-chip lens 40 according to the embodiment of the present disclosure.

[0072] 8 to 11 show the manufacturing process of the on-chip lens 40 when viewed in cross section along the row and column directions, and Fig. 12 to 15 show the manufacturing process of the on-chip lens 40 when viewed in cross section along the diagonal direction. Also, in Fig. 8 to 15, the semiconductor layer 20 (see Fig. 4) is omitted from illustration.

[0073] In the manufacturing process of the on-chip lens 40 according to the embodiment, first, a plurality of color filters 30 are formed by a conventionally known method, as shown in Fig. 8. Then, the surfaces of the plurality of color filters 30 are coated with a base material 140 of the on-chip lens 40 (see Fig. 5) by a conventionally known method. Furthermore, a resist film 150 is coated on the surface of the base material 140 by a conventionally known method.

[0074] Next, as shown in Fig. 9, the resist film 150 is patterned into a plurality of island-shaped portions 150A by a conventionally known method. These island-shaped portions 150A are formed corresponding to the portions that will become the on-chip lenses 40 (see Fig. 11). Next, the island-shaped portions 150A are heat-treated by a conventionally known method. As a result, the cross-sectional shape of the island-shaped portions 150A changes to a semi-elliptical shape, as shown in Fig. 10.

[0075] Next, the base material 140 is etched together with the island-shaped portion 150A by a conventionally known method, whereby the shape of the island-shaped portion 150A is transferred to the base material 140, and thus an on-chip lens 40 having a semi-elliptical cross-sectional shape is formed as shown in FIG.

[0076] As shown in FIG. 11, second boundaries 42 are formed between the on-chip lenses 40 adjacent to each other in the row and column directions.

[0077] 12, a plurality of color filters 30 are also formed in the diagonal direction by a conventionally known method. Then, a base material 140 of the on-chip lens 40 (see FIG. 4) is coated on the surfaces of the plurality of color filters 30 by a conventionally known method. Furthermore, a resist film 150 is coated on the surface of the base material 140 by a conventionally known method.

[0078] 13, the resist film 150 is patterned into a plurality of island-shaped portions 150A by a conventionally known method. Further, in the diagonal direction, another portion 150B is patterned at a location corresponding to the first boundary portion 41 (see FIG. 15). The another portion 150B is formed, for example, smaller than the island-shaped portions 150A.

[0079] Next, the island-shaped portion 150A and the other portion 150B are heat-treated by a conventionally known method, which changes the cross-sectional shape of the island-shaped portion 150A and the other portion 150B into a semi-elliptical shape, as shown in FIG.

[0080] Next, the base material 140 is etched by a conventionally known method to form the island-shaped portion 150A and the other portion 150B together, thereby transferring the shape of the island-shaped portion 150A to the base material 140, and thus forming the on-chip lens 40 that is semi-elliptical in cross section as shown in FIG.

[0081] Furthermore, in the embodiment, since the separate portion 150B is provided, the progress of the etching process at the first boundary 41 is slowed. Therefore, in the embodiment, the first boundary 41 is formed to be shallower than the second boundary 42 (see FIG. 11 ). Note that the cross-sectional shape of the separate portion 150B is not limited to the examples in FIGS. 13 and 14 , and various cross-sectional shapes are applicable.

[0082] [Modification 1] Next, various modifications of the embodiment will be described with reference to Fig. 16 to Fig. 18. Fig. 16 is a plan view for explaining an example of the arrangement of the photodiodes PD, the color filters 30, and the on-chip lenses 40 of the pixel array unit 10 according to Modification 1 of the embodiment of the present disclosure.

[0083] 16 , the pixel array unit 10 according to the first modification includes a plurality of photodiodes PD and a plurality of on-chip lenses 40. In a plan view, the plurality of photodiodes PD and the plurality of on-chip lenses 40 are arranged in a matrix. In the first modification, four photodiodes PD are arranged in two rows and two columns for one on-chip lens 40.

[0084] In the first modification, one of a red filter 30R, a green filter 30G, and a blue filter 30B is provided for each on-chip lens 40. The multiple color filters 30 are arranged in a regular color array (for example, a Bayer array).

[0085] Furthermore, in Modification 1, similarly to the above-described embodiment, the multiple on-chip lenses 40 arranged in a matrix have multiple first boundaries 41 and multiple second boundaries 42. The first boundaries 41 are located between the on-chip lenses 40 that are diagonally adjacent to each other. The second boundaries 42 are located between the on-chip lenses 40 that are adjacent to each other in the row direction or the column direction.

[0086] Fig. 17 is a cross-sectional view taken along the line CC shown in Fig. 16. That is, Fig. 16 is a cross-sectional view including on-chip lenses 40 adjacent to each other in the diagonal direction.

[0087] As shown in FIG. 17, the pixel array unit 10 according to the first modification includes a semiconductor layer 20, a plurality of color filters 30, and a plurality of on-chip lenses 40.

[0088] The semiconductor layer 20 has a plurality of photodiodes PD. For example, second conductivity type semiconductor regions 22 are formed in a matrix within a first conductivity type semiconductor region 21, thereby forming PN junction photodiodes PD arranged in a matrix. In addition, in the semiconductor layer 20, an isolation region 23 is provided between adjacent photodiodes PD.

[0089] The plurality of color filters 30 are located, for example, on the first surface 20a on the light incident side of the semiconductor layer 20. As shown in Fig. 17 , a red filter 30R is located on the light incident side of the photodiode PD(R), and a blue filter 30B is located on the light incident side of the photodiode PD(B).

[0090] Although not shown, a green filter 30G (see FIG. 4) is also located on the light incident side of the photodiode PD(G) (see FIG. 4) in Modification 1. The multiple on-chip lenses 40 are located closer to the light incident side than the multiple color filters 30.

[0091] In the first modification, two rows and two columns of unit pixels 11 are provided for each on-chip lens 40. That is, one pixel group 11A is made up of two rows and two columns of unit pixels 11. One on-chip lens 40 and one of a red filter 30R, a green filter 30G, and a blue filter 30B are provided for each pixel group 11A.

[0092] In the pixel array unit 10 of the first modification described above, a phase difference can be detected by a pair of unit pixels 11 adjacent to each other in the row direction or the column direction sharing the same on-chip lens 40 and color filter 30. Therefore, according to the first modification, the solid-state imaging device 1 can be provided with an autofocus function of a phase difference detection type.

[0093] Furthermore, in the pixel array section 10 of variant example 1, the unit pixels 11 arranged in two rows and two columns share the same on-chip lens 40 and color filter 30, thereby providing the solid-state imaging element 1 with an HDR (High Dynamic Range) function and a re-mosaic function.

[0094] Here, in the first modification, similarly to the above-described embodiment, it is preferable that the first boundary 41 between the pair of on-chip lenses 40 is farther from the first surface 20 a of the semiconductor layer 20 than the second boundary 42 between the pair of on-chip lenses 40.

[0095] In other words, in variant example 1, the distance L1 between the first boundary 41 and the first surface 20a of the semiconductor layer 20 is longer than the distance L2 (see Figure 5) between the second boundary 42 and the first surface 20a of the semiconductor layer 20 (i.e., L1 > L2).

[0096] As a result, similar to the above-described embodiment, fixed pattern noise caused by the on-chip lens 40 can be reduced.

[0097] Furthermore, when a pair of unit pixels 11 share one on-chip lens 40, phase difference detection is possible by biasing the input of light L in the pair of unit pixels 11. However, for light L incident at an oblique angle, the bias in the input of this light L may appear unnatural, which may be a problem.

[0098] On the other hand, in the first modification, by forming the first boundary 41 shallower than the second boundary 42, it is possible to prevent the curve of the portion of the on-chip lens 40 adjacent to the first boundary 41 from becoming too steep, as shown in FIG. 17 .

[0099] This makes it possible to prevent unnatural bias in the input of light L even when the light L is obliquely incident on the on-chip lens 40. Therefore, according to the first modification, the accuracy of phase difference detection can be improved.

[0100] 18 is a cross-sectional view schematically illustrating a structure of a pixel array unit 10 according to Modification 2 of the embodiment of the present disclosure. The pixel array unit 10 according to Modification 2 includes a semiconductor layer 20, an organic photoelectric conversion layer 50, an organic photoelectric conversion layer 60, and a plurality of on-chip lenses 40.

[0101] In the pixel array section 10 of the second modification, a plurality of on-chip lenses 40, an organic photoelectric conversion layer 60, an organic photoelectric conversion layer 50, and a semiconductor layer 20 are stacked in this order from the light incident side.

[0102] The semiconductor layer 20 has a plurality of photodiodes PD. For example, second conductivity type semiconductor regions 22 are formed in a matrix within a first conductivity type semiconductor region 21, thereby forming PN junction photodiodes PD arranged in a matrix. In addition, in the semiconductor layer 20, an isolation region 23 is provided between adjacent photodiodes PD.

[0103] In the pixel array section 10 of the second modification, the photodiode PD provided in the semiconductor layer 20 is, for example, a photodiode PD(R) that photoelectrically converts red light.

[0104] An organic photoelectric conversion layer 50 is located on the first surface 20a of the semiconductor layer 20. The organic photoelectric conversion layer 50 has an interlayer insulating film 51 and a plurality of photoelectric conversion units 52. In the organic photoelectric conversion layer 50, the plurality of photoelectric conversion units 52 and the interlayer insulating film 51 are stacked in this order from the light incident side.

[0105] The interlayer insulating film 51 is formed of, for example, a single layer film made of one of silicon oxide, TEOS (tetra ethoxy silane), silicon nitride, silicon oxynitride, etc., or a laminated film made of two or more of these materials.

[0106] The photoelectric conversion units 52 are arranged in a matrix within the organic photoelectric conversion layer 50. The photoelectric conversion units 52 perform photoelectric conversion on, for example, blue light. The photoelectric conversion units 52 include an upper electrode 52 a, a photoelectric conversion layer 52 b, a charge storage layer 52 c, lower electrodes 52 d and 52 e, and an insulating layer 52 f.

[0107] In the photoelectric conversion section 52, an upper electrode 52a, a photoelectric conversion layer 52b, a charge storage layer 52c, an insulating layer 52f, and lower electrodes 52d and 52e are stacked in this order from the light incident side.

[0108] The upper electrode 52a, the photoelectric conversion layer 52b, the charge storage layer 52c and the insulating layer 52f are formed, for example, in common to all unit pixels 11 in the pixel array section 10, and the lower electrodes 52d and 52e are formed, for example, separately for each unit pixel 11 in the pixel array section 10.

[0109] The upper electrode 52a is electrically connected to wiring (not shown) of a wiring layer (not shown) located on the surface opposite to the first surface 20a of the semiconductor layer 20, via a wiring layer or a through electrode (neither of which are shown) in the peripheral portion of the pixel array section 10. The upper electrode 52a is made of a transparent conductive material such as indium tin oxide (ITO), for example.

[0110] The material of the upper electrode 52a and the lower electrode 52d is not limited to ITO, and various transparent conductive materials (for example, tin oxide, zinc oxide, IZO, IGO, IGZO, ATO, AZO) can be used.

[0111] The above-mentioned IZO is an oxide obtained by adding indium to zinc oxide, IGO is an oxide obtained by adding indium to gallium oxide, and IGZO is an oxide obtained by adding indium and gallium to zinc oxide. Furthermore, the above-mentioned ATO is an oxide obtained by adding antimony to tin oxide, and AZO is an oxide obtained by adding antimony to zinc oxide.

[0112] The photoelectric conversion layer 52b is made of an organic semiconductor material and performs photoelectric conversion on light in a selective wavelength range (for example, blue light) of the light L incident from the outside.

[0113] The photoelectric conversion layer 52b preferably includes one or both of a p-type organic semiconductor and an n-type organic semiconductor, and is preferably made of, for example, quinacridone, a quinacridone derivative, a subphthalocyanine, a subphthalocyanine derivative, or the like, and preferably includes at least one of these materials.

[0114] The photoelectric conversion layer 52b is not limited to such materials, and may be made of, for example, at least one of naphthalene, anthracene, phenanthrene, tetracene, pyrene, perylene, and fluoranthene (all of which include derivatives).

[0115] The photoelectric conversion layer 52b may also be made of a polymer or derivative of phenylene vinylene, fluorene, carbazole, indole, pyrene, pyrrole, picoline, thiophene, acetylene, diacetylene, or the like.

[0116] The photoelectric conversion layer 52b may contain metal complex dyes, cyanine dyes, merocyanine dyes, phenylxanthene dyes, triphenylmethane dyes, rhodacyanine dyes, xanthene dyes, or the like.

[0117] Examples of such metal complex dyes include dithiol metal complex dyes, metal phthalocyanine dyes, metal porphyrin dyes, and ruthenium complex dyes. In addition to such organic semiconductor dyes, the photoelectric conversion layer 52b may also contain, for example, fullerene (C ６０) and BCP (Bathocuproine) and other organic materials may also be included.

[0118] When blue light is photoelectrically converted in the photoelectric conversion layer 52b, for example, a rhodamine dye, a melacyanine dye, a quinacridone derivative, a subphthalocyanine dye (subphthalocyanine derivative), or the like can be used for the photoelectric conversion layer 52b.

[0119] The charge storage layer 52c is provided between the photoelectric conversion layer 52b and the insulating layer 52f and stores the charges generated in the photoelectric conversion layer 52b. The charge storage layer 52c is preferably formed using a material that has a higher charge mobility and a larger band gap than the photoelectric conversion layer 52b.

[0120] For example, the band gap of the material constituting the charge storage layer 52c is preferably 3.0 eV or more, and examples of such materials include oxide semiconductor materials such as IGZO and organic semiconductor materials.

[0121] Examples of such organic semiconductor materials include transition metal dichalcogenides, silicon carbide (SiC), diamond, graphene, carbon nanotubes, condensed polycyclic hydrocarbon compounds, and condensed heterocyclic compounds.

[0122] By providing such a charge storage layer 52c below the photoelectric conversion layer 52b, recombination of charges during charge storage can be prevented, and transfer efficiency can be improved.

[0123] The lower electrodes 52d and 52e are made of the same material as the upper electrode 52a (for example, ITO, etc.). The lower electrode 52d is electrically connected to the charge storage layer 52c and is also electrically connected to a metal wiring (not shown) that penetrates the semiconductor layer 20. This metal wiring is made of a material such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu).

[0124] The metal wiring is electrically connected to a charge accumulation portion (not shown) formed in the vicinity of the interface on the side opposite to the light incident side of the semiconductor region 21. The charge accumulation portion is formed of a semiconductor region of the second conductivity type.

[0125] The lower electrode 52e is electrically connected to the wiring of the wiring layer via a wiring film 53 formed in the interlayer insulating film 51, a through electrode (not shown), or the like.

[0126] An organic photoelectric conversion layer 60 is located on a first surface 50a, which is the light incident side surface of the organic photoelectric conversion layer 50. The organic photoelectric conversion layer 60 is an example of a photoelectric conversion layer, and includes an interlayer insulating film 61 and a plurality of photoelectric conversion units 62. In the organic photoelectric conversion layer 60, the plurality of photoelectric conversion units 62 and the interlayer insulating film 61 are stacked in this order from the light incident side.

[0127] The interlayer insulating film 61 is formed of, for example, a single layer film made of one of silicon oxide, TEOS, silicon nitride, silicon oxynitride, etc., or a laminated film made of two or more of these materials.

[0128] The photoelectric conversion units 62 are arranged in a matrix inside the organic photoelectric conversion layer 60. The photoelectric conversion units 62 perform photoelectric conversion on, for example, green light. The photoelectric conversion units 62 include an upper electrode 62 a, a photoelectric conversion layer 62 b, a charge storage layer 62 c, lower electrodes 62 d and 62 e, and an insulating layer 62 f.

[0129] In the photoelectric conversion section 62, an upper electrode 62a, a photoelectric conversion layer 62b, a charge storage layer 62c, an insulating layer 62f, and lower electrodes 62d and 62e are stacked in this order from the light incident side.

[0130] The upper electrode 62a, the photoelectric conversion layer 62b, the charge storage layer 62c and the insulating layer 62f are formed, for example, in common to all unit pixels 11 in the pixel array section 10, and the lower electrodes 62d and 62e are formed, for example, separately for each unit pixel 11 in the pixel array section 10.

[0131] The upper electrode 62a is electrically connected to wiring in a wiring layer located on the surface opposite to the first surface 20a of the semiconductor layer 20 via a wiring layer or a through electrode (neither of which is shown) in the peripheral portion of the pixel array section 10. The upper electrode 62a may be made of a material similar to that of the upper electrode 52a of the organic photoelectric conversion layer 50, for example.

[0132] The photoelectric conversion layer 62b is made of an organic semiconductor material and performs photoelectric conversion on light in a selective wavelength range (e.g., green light) of the light L incident from the outside. The material of the photoelectric conversion layer 62b can be, for example, the same material as the photoelectric conversion layer 52b of the organic photoelectric conversion layer 50.

[0133] When green light is photoelectrically converted in the photoelectric conversion layer 62b, for example, a rhodamine-based dye, a melacyanine-based dye, a quinacridone derivative, a subphthalocyanine-based dye (subphthalocyanine derivative), or the like can be used for the photoelectric conversion layer 62b.

[0134] The charge storage layer 62c is provided between the photoelectric conversion layer 62b and the insulating layer 62f, and stores the charges generated in the photoelectric conversion layer 62b. The charge storage layer 62c may be made of a material similar to that of the charge storage layer 52c of the organic photoelectric conversion layer 50, for example.

[0135] The lower electrodes 62d and 62e are made of the same material as the upper electrode 62a (for example, ITO, etc.). The lower electrode 62d is electrically connected to the charge storage layer 62c and to a metal wiring (not shown) that penetrates the semiconductor layer 20.

[0136] This metal wiring is electrically connected to a charge accumulation portion (not shown) formed in the vicinity of the interface on the side opposite to the light incident side of the semiconductor region 21. This charge accumulation portion is formed of a semiconductor region of the second conductivity type.

[0137] The lower electrode 62e is electrically connected to the wiring of the wiring layer via a wiring film 63 formed in the interlayer insulating film 61 or a through electrode (not shown).

[0138] The charges generated by photoelectric conversion in the photoelectric conversion unit 52 (or photoelectric conversion unit 62) are transferred to the charge accumulation unit via metal wiring. The charge accumulation unit temporarily accumulates the charges photoelectrically converted in the photoelectric conversion unit 52 (or photoelectric conversion unit 62) until they are read out by the corresponding pixel transistor.

[0139] For example, in the photoelectric conversion unit 52, a predetermined voltage is applied to the lower electrodes 52d and 52e and the upper electrode 52a from a drive circuit (not shown) during the charge accumulation period. For example, during the charge accumulation period, a positive voltage is applied to the lower electrodes 52d and 52e, and a negative voltage is applied to the upper electrode 52a. Furthermore, during the charge accumulation period, a larger positive voltage is applied to the lower electrode 52e than to the lower electrode 52d.

[0140] As a result, during the charge accumulation period, electrons contained in charges generated by photoelectric conversion in the photoelectric conversion layer 52b are attracted by the large positive voltage of the lower electrode 52e and accumulated in the charge accumulation layer 52c.

[0141] Furthermore, in the photoelectric conversion unit 52, a reset operation is performed by operating a reset transistor (not shown) in the latter half of the charge accumulation period, thereby resetting the potential of the charge accumulation unit and setting the potential of the charge accumulation unit to the power supply voltage.

[0142] After the reset operation is completed, a charge transfer operation is performed in the photoelectric conversion unit 52. In this charge transfer operation, a positive voltage higher than that of the lower electrode 52e is applied to the lower electrode 52d from the drive circuit. As a result, the electrons stored in the charge storage layer 52c are transferred to the charge storage unit via the lower electrode 52d and the metal wiring.

[0143] The above operations complete a series of operations, such as a charge accumulation operation, a reset operation, and a charge transfer operation, in the photoelectric conversion unit 52. Note that the series of operations, such as a charge accumulation operation, a reset operation, and a charge transfer operation, in the photoelectric conversion unit 62 are the same as those in the photoelectric conversion unit 52, and therefore a description thereof will be omitted.

[0144] The multiple on-chip lenses 40 are located on a first surface 60a on the light incident side of the organic photoelectric conversion layer 60. In the second modification, one unit pixel 11 is provided with one photodiode PD, one photoelectric conversion unit 52, one photoelectric conversion unit 62, and one on-chip lens 40.

[0145] Here, in the second modification, similarly to the above-described embodiment, the first boundary 41 between the pair of on-chip lenses 40 may be farther from the first surface 60a of the organic photoelectric conversion layer 60 than the second boundary 42 (see FIG. 5) between the pair of on-chip lenses 40.

[0146] In other words, in variant example 2, the distance L1 between the first boundary 41 and the first surface 60a of the organic photoelectric conversion layer 60 is longer than the distance L2 (see Figure 5) between the second boundary 42 and the first surface 60a of the organic photoelectric conversion layer 60 (i.e., L1 > L2).

[0147] As a result, similar to the above-described embodiment, fixed pattern noise caused by the on-chip lens 40 can be reduced.

[0148] In addition, in the second modification, light of three colors can be photoelectrically converted respectively in one unit pixel 11. Furthermore, in the second modification, light of three colors can be photoelectrically converted respectively without the color filter 30 (see FIG. 4), and therefore the utilization efficiency of light L can be improved.

[0149] Therefore, according to the second modification, the image quality of the solid-state imaging device 1 can be improved.

[0150] 18 shows an example in which the organic photoelectric conversion layer 60, the organic photoelectric conversion layer 50, and the semiconductor layer 20 are stacked in three layers in this order from the light incident side, but the present disclosure is not limited to such an example. For example, an organic photoelectric conversion layer made of an organic material may be positioned as the third layer instead of the semiconductor layer 20 made of an inorganic material, and a semiconductor layer made of an inorganic material may be positioned as the second layer instead of the organic photoelectric conversion layer 50 made of an organic material.

[0151] Furthermore, although the example of Figure 18 shows an example in which three photoelectric conversion layers are stacked, the present disclosure is not limited to such an example, and two or four or more photoelectric conversion layers may be stacked.

[0152] [Effects] The solid-state imaging element 1 according to the embodiment includes a photoelectric conversion layer (semiconductor layer 20, organic photoelectric conversion layer 60) and a plurality of on-chip lenses 40. The photoelectric conversion layer (semiconductor layer 20, organic photoelectric conversion layer 60) has a plurality of photoelectric conversion units (photodiodes PD, photoelectric conversion units 62). The plurality of on-chip lenses 40 are arranged in a matrix on the light incident side of the photoelectric conversion layer (semiconductor layer 20, organic photoelectric conversion layer 60). A first boundary 41 located between diagonally adjacent on-chip lenses 40 is farther from the first surface 20 a (60 a) located on the light incident side of the photoelectric conversion layer than a second boundary 42 located between diagonally adjacent on-chip lenses 40 in the row direction or column direction.

[0153] This makes it possible to reduce fixed pattern noise caused by the on-chip lens 40 .

[0154] In the solid-state imaging device 1 according to the embodiment, the first boundary portion 41 has a structure that bridges the gap between the on-chip lenses 40 that are adjacent to each other in the diagonal direction in a cross-sectional view.

[0155] This makes it possible to reduce fixed pattern noise caused by the on-chip lens 40 .

[0156] In the solid-state imaging device 1 according to the embodiment, one photoelectric conversion unit (photodiode PD) is located for one on-chip lens 40 .

[0157] This makes it possible to reduce fixed pattern noise caused by the on-chip lens 40 .

[0158] Furthermore, in the solid-state imaging device 1 according to the embodiment, four photoelectric conversion units (photodiodes PD) are located for one on-chip lens 40 .

[0159] This makes it possible to reduce fixed pattern noise caused by the on-chip lens 40 and improve the accuracy of phase difference detection.

[0160] Furthermore, in the solid-state imaging device 1 according to the embodiment, a plurality of photoelectric conversion units (photodiodes PD, photoelectric conversion units 62 ) stacked in the light incident direction are positioned relative to one on-chip lens 40 .

[0161] This makes it possible to reduce fixed pattern noise caused by the on-chip lens 40 and improve the image quality of the solid-state imaging device 1 .

[0162] [Electronic Device] The present disclosure is not limited to application to solid-state imaging elements, and can be applied to all electronic devices that have solid-state imaging elements, such as camera modules, imaging devices, mobile terminal devices with imaging functions, and copiers that use solid-state imaging elements in their image reading units.

[0163] Examples of such imaging devices include digital still cameras and video cameras, while examples of mobile terminal devices with imaging capabilities include smartphones and tablet terminals.

[0164] Fig. 19 is a block diagram showing an example configuration of an imaging device serving as electronic device 100 to which the technology according to the present disclosure is applied. Electronic device 100 in Fig. 19 is, for example, an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal.

[0165] In FIG. 19, electronic device 100 comprises a lens group 101, a solid-state image sensor 102, a DSP circuit 103, a frame memory 104, a display unit 105, a recording unit 106, an operation unit 107, and a power supply unit 108.

[0166] In the electronic device 100 , the DSP circuit 103 , the frame memory 104 , the display unit 105 , the recording unit 106 , the operation unit 107 , and the power supply unit 108 are interconnected via a bus line 109 .

[0167] The lens group 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging element 102. The solid-state imaging element 102 corresponds to the solid-state imaging element 1 according to the above-described embodiment, and converts the amount of incident light formed on the imaging surface by the lens group 101 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0168] The DSP circuit 103 is a camera signal processing circuit that processes signals supplied from the solid-state image sensor 102. The frame memory 104 temporarily stores image data processed by the DSP circuit 103 on a frame-by-frame basis.

[0169] The display unit 105 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or still images captured by the solid-state imaging element 102. The recording unit 106 records image data of the moving images or still images captured by the solid-state imaging element 102 on a recording medium such as a semiconductor memory or a hard disk.

[0170] In response to user operations, the operation unit 107 issues operation commands for various functions of the electronic device 100. The power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources.

[0171] In the electronic device 100 configured in this manner, by applying the solid-state imaging element 1 of each of the above-described embodiments as the solid-state imaging element 102, fixed pattern noise caused by the on-chip lens 40 can be reduced.

[0172] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0173] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0174] The present technology may also have the following configurations. (1) A solid-state imaging device including: a photoelectric conversion layer having a plurality of photoelectric conversion units; and a plurality of on-chip lenses arranged in a matrix on a light incident side of the photoelectric conversion layer, wherein a first boundary portion located between the on-chip lenses adjacent to each other in a diagonal direction is farther from a first surface located on the light incident side of the photoelectric conversion layer than a second boundary portion located between the on-chip lenses adjacent to each other in a row direction or a column direction. (2) The solid-state imaging device according to (1), wherein the first boundary portion has a structure that bridges between the on-chip lenses adjacent to each other in a diagonal direction in a cross-sectional view. (3) The solid-state imaging device according to (1) or (2), wherein one photoelectric conversion unit is located for one on-chip lens. (4) The solid-state imaging device according to (1) or (2), wherein four photoelectric conversion units are located for one on-chip lens. (5) The solid-state imaging element according to (1) or (2), wherein a plurality of the photoelectric conversion units stacked in the light incident direction are located relative to one on-chip lens. (6) An electronic device comprising: a solid-state imaging element; an optical system that takes in incident light from a subject and forms an image on an imaging surface of the solid-state imaging element; and a signal processing circuit that processes an output signal from the solid-state imaging element, wherein the solid-state imaging element has: a photoelectric conversion layer having a plurality of photoelectric conversion units; and a plurality of on-chip lenses arranged in a matrix on the light incident side of the photoelectric conversion layer, wherein a first boundary portion located between the on-chip lenses adjacent to each other in the diagonal direction is farther from the first surface located on the light incident side of the photoelectric conversion layer than a second boundary portion located between the on-chip lenses adjacent to each other in the row direction or the column direction. (7) The electronic device according to (6), wherein the first boundary portion has a structure that bridges the on-chip lenses adjacent to each other in the diagonal direction in a cross-sectional view. (8) The electronic device according to (6) or (7), wherein one photoelectric conversion unit is located for one on-chip lens. (9) The electronic device according to (6) or (7), wherein four photoelectric conversion units are located for one on-chip lens.(10) The electronic device according to (6) or (7), wherein a plurality of the photoelectric conversion units stacked in a light incident direction are positioned relative to one of the on-chip lenses.

[0175] REFERENCE SIGNS LIST 1 solid-state imaging element 10 pixel array section 20 semiconductor layer (an example of a photoelectric conversion layer) 20a first surface 40 on-chip lens 41 first boundary section 42 second boundary section 60 organic photoelectric conversion layer (an example of a photoelectric conversion layer) 60a first surface 62 photoelectric conversion section 100 electronic device L1, L2 distance PD photodiode (an example of a photoelectric conversion section)

Claims

1. A solid-state imaging device comprising: a photoelectric conversion layer having a plurality of photoelectric conversion units; and a plurality of on-chip lenses arranged in a matrix on the light incident side of the photoelectric conversion layer; wherein a first boundary portion located between diagonally adjacent on-chip lenses is farther from a first surface located on the light incident side of the photoelectric conversion layer than a second boundary portion located between diagonally adjacent on-chip lenses in the row direction or the column direction.

2. The solid-state imaging device according to claim 1, wherein the first boundary portion has a structure that bridges the gap between the on-chip lenses that are adjacent to each other in the diagonal direction in a cross-sectional view.

3. The solid-state imaging device according to claim 1, wherein one photoelectric conversion unit is located for one on-chip lens.

4. The solid-state imaging device according to claim 1, wherein four of the photoelectric conversion units are located for one of the on-chip lenses.

5. The solid-state imaging device according to claim 1, wherein a plurality of the photoelectric conversion units stacked in the light incident direction are positioned relative to one of the on-chip lenses.

6. An electronic device comprising: a solid-state imaging element; an optical system that takes in incident light from a subject and forms an image on the imaging surface of the solid-state imaging element; and a signal processing circuit that processes an output signal from the solid-state imaging element, wherein the solid-state imaging element has: a photoelectric conversion layer having a plurality of photoelectric conversion units; and a plurality of on-chip lenses arranged in a matrix on the light incident side of the photoelectric conversion layer, wherein a first boundary portion located between the on-chip lenses adjacent to each other in the diagonal direction is farther from the first surface located on the light incident side of the photoelectric conversion layer than a second boundary portion located between the on-chip lenses adjacent to each other in the row direction or the column direction.

Images