N-type ohmic electrode, method for manufacturing n-type ohmic electrode, group iii nitride semiconductor light-emitting element, and method for manufacturing group iii nitride semiconductor light-emitting element

Abstract

An n-type ohmic electrode 30 is provided on an n-type group III nitride semiconductor layer 10. The n-type ohmic electrode 30 has an Al layer 33 and a second direction-side Al-Ti region 34 located, relative to the Al layer 33, in a second direction opposite to a first direction which is toward the n-type group III nitride semiconductor layer 10. The second direction-side Al-Ti region 34 contains 50 at% or more of Al, 5-30 at% of Ti, and 10 at% or less of O.

Description

N-type ohmic electrode, method for manufacturing n-type ohmic electrode, group III nitride semiconductor light emitting device, and method for manufacturing group III nitride semiconductor light emitting device

[0001] The present invention relates to an n-type ohmic electrode, a method for manufacturing an n-type ohmic electrode, a Group III nitride semiconductor light-emitting device, and a method for manufacturing a Group III nitride semiconductor light-emitting device.

[0002] Conventionally, a method of depositing metal layers including a Ti layer and an Al layer and then performing a heat treatment is known as a method of forming a good n-type ohmic electrode on an n-type Group III nitride semiconductor layer.

[0003] For example, Patent Document 1 describes that an n-type ohmic electrode is formed by forming a Ti film with a thickness of 200 Å, an Al film with a thickness of 600 nm, and a Ti film with a thickness of 5 nm from the n-type Group III nitride semiconductor layer side, and finally performing contact annealing (RTA) at 550° C.

[0004] Japanese Patent Application Laid-Open No. 2022-67526

[0005] However, when the present inventors fabricated an n-type ohmic electrode having a stacked structure as disclosed in Patent Document 1, there were problems in that the forward voltage was large and also varied greatly within the wafer surface.

[0006] Therefore, an object of the present invention is to provide an n-type ohmic electrode having a good forward voltage and a forward voltage with small variation within the wafer surface, a method for manufacturing the same, and a Group III nitride semiconductor light-emitting device including the n-type ohmic electrode and a method for manufacturing the same.

[0007] The present inventors have conducted extensive research into ways to solve the above-mentioned problems. As a result, the present inventors have experimentally demonstrated that the above-mentioned problems can be solved by stacking a first Ti layer, an Al layer, and a second Ti layer in this order from the n-type Group III nitride semiconductor layer side and optimizing the thickness of the second Ti layer. Furthermore, the present inventors have experimentally confirmed that after the metal stack thus formed is heat-treated for contact annealing, a region where Al and Ti are thought to be alloyed (hereinafter referred to as an Al-Ti region) is formed on the side opposite the n-type Group III nitride semiconductor layer. The present inventors have also found that the above-mentioned problems can be solved when such an alloyed region is formed, and have thus completed the present invention. That is, the gist of the present invention is as follows.

[0008] (1) An n-type ohmic electrode provided on an n-type Group III nitride semiconductor layer, the n-type ohmic electrode having: an Al layer; and a second-direction-side Al-Ti region located in a second direction of the Al layer opposite to a first direction, which is a side of the Al layer facing the n-type Group III nitride semiconductor layer; the second-direction-side Al-Ti region containing 50 at % or more Al, 5 at % or more and 30 at % or less Ti, and 10 at % or less O.

[0009] (2) The n-type ohmic electrode according to (1), wherein the Al layer is present at least in the center in the thickness direction.

[0010] (3) The n-type ohmic electrode according to (1) or (2), further comprising a second-direction-side oxygen-containing region located in the second direction of the second-direction-side Al—Ti region in the thickness direction, wherein the second-direction-side oxygen-containing region contains 10 at % or more of O.

[0011] (4) The n-type ohmic electrode according to any one of (1) to (3), wherein at a point where oxygen in the second direction side oxygen-containing region is at its maximum in the thickness direction, the ratio of oxygen atoms at % to the total at % of Al atoms and Ti atoms is 1.0 or less.

[0012] (5) The n-type ohmic electrode according to any one of (1) to (4), further comprising a first direction side Al-Ti region located in the first direction of the Al layer in the thickness direction, the first direction side Al-Ti region containing 50 at % or more of Al, 5 at % or more and 30 at % or less of Ti, and 10 at % or less of O.

[0013] (6) A Group III nitride semiconductor light-emitting device comprising: an n-type Group III nitride semiconductor layer; and the n-type ohmic electrode according to any one of (1) to (5) above, provided on a surface of the n-type Group III nitride semiconductor layer.

[0014] (7) A method for manufacturing an n-type ohmic electrode, comprising: a first step of forming an n-side metal stack by sequentially forming a first Ti layer, an Al layer, and a second Ti layer on a surface of an n-type Group III nitride semiconductor layer; and a second step of performing heat treatment on the n-side metal stack, wherein the thickness of the second Ti layer formed in the first step is 15 nm or more.

[0015] (8) The method for manufacturing an n-type ohmic electrode according to (7) above, wherein in the second step, the heat treatment is performed with the second Ti layer as the outermost surface.

[0016] (9) The method for manufacturing an n-type ohmic electrode according to (7) or (8) above, wherein in the second step, the heat treatment is performed in a mixed gas atmosphere containing 1% to 60% oxygen.

[0017] (10) The method for manufacturing an n-type ohmic electrode according to any one of (7) to (9) above, wherein the second Ti layer formed in the first step has a thickness of 100 nm or less.

[0018] (11) A method for manufacturing a Group III nitride semiconductor light-emitting device, comprising: forming an n-type Group III nitride semiconductor layer; and forming the n-type ohmic electrode on the n-type Group III nitride semiconductor layer by using the method for manufacturing an n-type ohmic electrode according to any one of (7) to (10) above.

[0019] (12) The method for manufacturing a Group III nitride semiconductor light-emitting device according to (11) above, further comprising the steps of: forming a light-emitting layer on the n-type Group III nitride semiconductor layer; forming a p-type Group III nitride semiconductor layer on the light-emitting layer; and forming a p-side metal stack on the p-type Group III nitride semiconductor layer, wherein in the second step, the heat treatment is performed together with the p-side metal stack.

[0020] According to the present invention, it is possible to provide an n-type ohmic electrode having a good forward voltage and a forward voltage with small variation within the wafer surface, a method for manufacturing the same, and a Group III nitride semiconductor light-emitting device including the n-type ohmic electrode and a method for manufacturing the same.

[0021] 4 is a schematic cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention.

[0023] FIG. 4 is a schematic cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention.

[0024] FIG. 4 is a schematic cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention.

[0025] FIG. 4 is a cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention.

[0026] FIG. 4 is a cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention.

[0027] FIG. 4 is a cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention.

[0028] FIG. 4 is a cross-sectional view illustrating an n-side metal stack formed in a method for manufacturing an n-type ohmic electrode according to an embodiment of the present invention. [0029 ... 1 is a graph showing the atomic fraction of Ti atoms in the thickness direction of n-type ohmic electrodes according to Example 1, Comparative Example 1, and Comparative Example 2. FIG.

[0022] An n-type ohmic electrode according to an embodiment of the present invention is provided on an n-type Group III nitride semiconductor layer. For convenience of explanation, the thickness direction of this n-type ohmic electrode toward the n-type Group III nitride semiconductor layer will be referred to as a first direction, and the opposite side to the first direction will be referred to as a second direction. Examples of the n-type Group III nitride semiconductor layer include an n-type AlGaN layer, an n-type GaN layer, an n-type AlN layer, and an n-type AlInGaN layer. Among these, an n-type AlGaN layer is preferred. Accordingly, the following points will be explained in advance before a detailed description of an embodiment of the present invention.

[0023] First, in this specification, when the Al composition ratio is not specified and the term "AlGaN" is used, it means that the composition ratio of group III elements (the sum of Al (aluminum) and Ga (gallium)) to N (nitrogen) is 1:1, and the ratio of group III elements Al to Ga is indefinite. When simply written as "AlN (aluminum nitride)" or "GaN (gallium nitride)", it means that Ga and Al are not contained, respectively. The value of the Al composition ratio x or the In composition ratio y can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like.

[0024] In this specification, a layer that functions electrically as p-type is referred to as a p-type semiconductor layer, and a layer that functions electrically as n-type is referred to as an n-type semiconductor layer (sometimes abbreviated as an "n-type layer"). On the other hand, when specific impurities such as Si, Mg, Zn, and S are not intentionally added, the layer is called "undoped." This III-V compound semiconductor layer may contain unavoidable impurities during the manufacturing process. Specifically, in this specification, a layer is considered to be "undoped" when the dopant concentrations of both p-type and n-type impurities are low and the dopant concentrations of these impurities are close to the lower limit of detection by SIMS. In the case of Si concentration, the lower limit of detection by SIMS analysis, which will be described later, is 2×10 １４ / cm ３ Therefore, the average Si concentration in the layer is 2.5 × 10 １４ / cm ３ If it is less than 1, it is considered to be "undoped."

[0025] In this embodiment, the atomic percentage (at%) of elements in the cross section of the n-type ohmic electrode is a measured value obtained by forming a cross section of the n-type ohmic electrode using a focused ion beam (FIB) or the like and measuring nitrogen (N), oxygen (O), aluminum (Al), silicon (Si), titanium (Ti), nickel (Ni), gallium (Ga), rhodium (Rh), platinum (Pt), and gold (Au) using energy dispersive X-ray spectroscopy (EDS), where the total atomic percentage of each measured element is taken as 100%. As shown by the dashed lines in the schematic cross-sectional view of FIG. 2A and the cross-sectional TEM image of FIG. 2B, the TEM-EDS profile is a measurement of the atomic percentage of each element along an arbitrary line in the thickness direction of the cross section of the n-type ohmic electrode (a line crossing from the outermost surface of the n-type ohmic electrode to the interface with the n-type semiconductor layer) confirmed in the cross-sectional TEM (transmission electron microscope) image. The EDS analysis was performed using a TEM Talos F200E manufactured by FEI and an EDS detector Super X at an acceleration voltage of 200 kV. Furthermore, cross-sectional TEM (transmission electron microscope) images were obtained for the cross-sections formed, thereby observing the cross-sections of the fabricated n-type ohmic electrodes. The cross-sectional TEM images were obtained using the above-mentioned FEI Talos F200E at an acceleration voltage of 200 kV.

[0026] After the semiconductor layers and n-type ohmic electrodes of this embodiment are formed and subjected to heat treatment (e.g., in the state of a light-emitting device), the thickness of each semiconductor layer and the shape of the granular portions formed in the n-type ohmic electrode are confirmed using cross-sectional TEM images. The thickness of each semiconductor layer is defined as the average value within the field of view. Note that the thickness of each metal layer of each metal laminate, such as the n-type ohmic electrode, formed during the manufacturing process before heat treatment can be calculated from cross-sectional TEM images acquired immediately after film formation, as with the case after heat treatment, but it may also be a precisely controlled set value based on preliminary testing using a vacuum deposition machine or sputtering device.

[0027] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. In each drawing, the aspect ratio of the substrate and each layer is exaggerated from the actual ratio for the sake of convenience of explanation.

[0028] (Method for Manufacturing an n-Type Ohmic Electrode) A method for manufacturing an n-type ohmic electrode according to this embodiment will be described with reference to Fig. 1. The method for manufacturing an n-type ohmic electrode 30 according to the present invention includes at least a first step of forming an n-side metal stack 20 by sequentially forming a first Ti layer 21, an Al layer 22, and a second Ti layer 23 on the surface of an n-type Group III nitride semiconductor layer 10 (hereinafter sometimes abbreviated as "n-type semiconductor layer 10"), and a second step of performing a heat treatment on the n-side metal stack 20. The thickness of the second Ti layer 23 formed in the first step is set to be 15 nm or more.

[0029] <First Step> As described above, the first step is a step of forming the n-side metal stack 20 by sequentially forming the first Ti layer 21, the Al layer 22, and the second Ti layer 23 on the surface of the n-type semiconductor layer 10 ( FIG. 1 ). It is preferable that the Al layer 22 and the second Ti layer 23 are directly stacked without providing another metal layer between them. On the other hand, in this embodiment, another metal layer may be provided between the n-type semiconductor layer 10 and the first Ti layer 21, and between the first Ti layer 21 and the Al layer 22. Examples of the n-type semiconductor layer 10 include an n-type AlGaN layer, an n-type AlInGaN layer, an n-type GaN layer, or an n-type AlN layer. The n-type semiconductor layer 10 is preferably an n-type AlGaN layer. The thickness of the first Ti layer 21 is preferably 1 nm or more and 30 nm or less, more preferably 5 nm or more and 27 nm or less, and even more preferably 10 nm or more and 25 nm or less. The thickness of the Al layer 22 is preferably 300 nm or more and 1000 nm or less, more preferably 400 nm or more and 900 nm or less, and even more preferably 500 nm or more and 800 nm or less. The thickness of the second Ti layer 23 is 15 nm or more, more preferably 18 nm or more and even more preferably 20 nm or more. The thickness of the second Ti layer 23 is preferably 100 nm or less, more preferably 80 nm or less and even more preferably 60 nm or less. The total thickness of the n-side metal stack 20 is preferably 316 nm or more and 1130 nm or less, and more preferably 423 nm or more and 1007 nm or less. Each of these metal layers can be formed by a common method such as vapor deposition.

[0030] <Second Step> As described above, the second step is a step of performing heat treatment on the n-side metal stack 20, with the purpose of contact annealing. The heat treatment in the second step is preferably performed with the second Ti layer 23 as the outermost surface. Furthermore, when the heat treatment in the second step is performed in an oxygen-containing mixed gas atmosphere, the oxygen content of the mixed gas is preferably 1% to 60%, more preferably 10% to 50%, and even more preferably 20% to 40%. The mixed gas used may contain an inert gas such as nitrogen or argon. The temperature during the heat treatment is preferably 450°C to 700°C, more preferably 500°C to 600°C, and even more preferably 520°C to 580°C. Furthermore, after the start of the heat treatment, it is more preferable to heat the chamber in the treatment chamber in an inert gas atmosphere without using oxygen in the mixed gas until the chamber reaches a specified temperature, and then start flowing oxygen after the chamber reaches the specified temperature. If the temperature is raised while oxygen is present, oxidation of the surface will progress even before the second Al-Ti region 34 is formed, which may reduce the effect of the second Al-Ti region 34 in reducing resistance and suppressing the uptake or movement of oxygen.

[0031] The n-type ohmic electrode 30 obtained through the first and second steps has a good forward voltage and a forward voltage with small variations within the wafer surface.

[0032] (n-Type Ohmic Electrode) The n-type ohmic electrode 30 obtained by the above-described method for manufacturing the n-type ohmic electrode 30 will now be described. FIG. 2A shows an example of a schematic cross-sectional TEM image of the n-type ohmic electrode 30 according to this embodiment. The n-type ohmic electrode 30 is provided on the n-type semiconductor layer 10. The n-type ohmic electrode 30 has at least an Al layer 33 and a "second granular portion 34" located in a second direction of the Al layer 33 opposite to a first direction on the n-type semiconductor layer 10 side. In this specification, the granular portion refers to a granular region observed as a difference in contrast in a TEM image such as that shown in FIG. 2B. Then, the presence of a granular portion in the second direction in the cross-sectional TEM image is found, and a TEM-EDS profile is taken across the granular portion in the thickness direction to confirm the composition at the position corresponding to the granular portion. If the composition is the "second-direction-side Al-Ti region 34 (hereinafter, also referred to as the second Al-Ti region 34)" described below, the granular portion is deemed to be the "second granular portion 34." This TEM-EDS profile then confirms that the n-type ohmic electrode 30 has an Al layer 33 and a "second Al-Ti region 34" located in the second direction opposite to the first direction, which is the n-type semiconductor layer 10 side of the Al layer 33. As illustrated in FIG. 2B , there may be cases where the second-direction-side Al-Ti region 34 is not present in the second direction of the Al layer 33. When a cross-sectional TEM image with a width of 10 μm is taken, it is sufficient that the granular portions are observed at least in the second direction and the TEM-EDS profile of the granular portions confirms the presence of the "second Al-Ti region 34." In this embodiment, the "central portion in the thickness direction" refers to a region that includes the center of the n-type ohmic electrode 30 in the thickness direction, is located between the second Al-Ti region 34 and the n-type semiconductor layer 10, and has a thickness of 20% or more of the n-type ohmic electrode 30.

[0033] The Al layer 33 is preferably located at least in the center in the thickness direction of the n-type ohmic electrode 30. In the TEM-EDS profile, the composition of the region corresponding to the Al layer 33 preferably consists of 80 at % or more Al, less than 5 at % Ti, and 10 at % or less O. The thickness of the Al layer 33 is preferably 100 nm or more and 900 nm or less, more preferably 300 nm or more and 800 nm or less, and even more preferably 400 nm or more and 700 nm or less. The Al layer 33 may contain impurities such as O atoms or N atoms.

[0034] In the TEM-EDS profile, the second Al-Ti region 34 located in the second direction of the Al layer 33 contains 50 at% or more of Al, 5 at% to 30 at% of Ti, and 10 at% or less of O. As described above with reference to FIG. 2B , it is sufficient that the second Al-Ti region satisfying the above atomic ratios exists in at least a portion of the in-plane direction of the Al layer 33 in the second direction. The second Al-Ti region 34 is an intermetallic compound TiAl ３ Since the second Al-Ti region 34 is expected to have a predominant composition of Al, it contains 50 at% or more of Al, preferably 55 at% or more, and more preferably 57 at% or more. Additionally, the second Al-Ti region 34 contains 5 at% to 30 at% of Ti, preferably 7 at% to 28 at% of Ti, and more preferably 8 at% to 25 at% of Ti. As described above, the second Al-Ti region 34 contains 10 at% or less of O. The O content is not particularly limited as long as this condition is satisfied, but in principle, the O content is 0 at% or more. In the second Al-Ti region 34, the Ti content is preferably greater than the O content.

[0035] The n-type ohmic electrode 30 may have a second-direction oxygen-containing region 35 (hereinafter, sometimes abbreviated as the "second oxygen region 35") located in the second direction of the second Al-Ti region 34 (second granular portion 34) in the thickness direction. The second oxygen region 35 refers to a region containing 10 at% or more of O. The second oxygen region 35 may contain Al or Ti. When a metal layer such as a Pt-containing layer is formed on the n-type ohmic electrode, the second oxygen region 35 may appear near the interface with the metal layer on the n-type ohmic electrode. The second oxygen region 35 has a point where oxygen (O) is maximized in the thickness direction, and the atomic fraction of oxygen atoms at the maximum point is preferably 47 at% or less, more preferably 45 at% or less. The ratio of oxygen atoms at % to the total at % of Al atoms and Ti atoms at the maximum point is preferably 1.00 or less (100% or less), more preferably 0.95 or less, and even more preferably 0.85 or less. The lower limit is, for example, 0.10. The second oxygen region 35 is made of Al, which is an oxide of Al or Ti. ２ O ３ or TiO ２ It is believed that the presence of the second Al-Ti region 34 (second granular portion 34) and the proportion of oxygen atoms in the second oxygen region 35 being equal to or less than the above value improves the effect of reducing the resistance in the second direction side.

[0036] The n-type ohmic electrode 30 may have a "first granular portion 31" in the first direction of the Al layer 33 in the thickness direction. The presence of a granular portion in the first direction of a cross-sectional TEM image is found, and a TEM-EDS profile is taken across the granular portion in the thickness direction to confirm the composition at the position corresponding to the granular portion. If the composition is a "first direction side Al-Ti region 32 (hereinafter, also referred to as the first Al-Ti region 32)" described below, the granular portion is considered to be a "first granular portion 32." This TEM-EDS profile can then be used to confirm whether the n-type ohmic electrode 30 has a "first direction side Al-Ti region 32" located in the first direction, which is the n-type semiconductor layer 10 side of the Al layer 33.

[0037] In the TEM-EDS profile, the first Al-Ti region 32 located in the first direction of the Al layer 33 preferably contains 50 at% or more of Al, 5 at% to 30 at% of Ti, and 10 at% or less of O. The first direction of the Al layer 33 may have the first Al-Ti region 32 satisfying the above atomic ratio in at least a part of its in-plane direction. The first Al-Ti region 32 is an intermetallic compound TiAl ３ Since the first Al-Ti region 34 is expected to have a main composition of Al, it contains 50 at% or more of Al, preferably 55 at% or more, and more preferably 57 at% or more. In addition, the first Al-Ti region 32 contains 5 at% or more and 30 at% or less of Ti, preferably 7 at% or more and 28 at% or less, and more preferably 8 at% or more and 25 at% or less. As described above, the first Al-Ti region 32 contains 10 at% or less of O. The O content is not particularly limited as long as this condition is satisfied, but in principle the O content is 0 at% or more. In the first Al-Ti region 34, the Ti content is preferably greater than the O content.

[0038] The n-type ohmic electrode 30 may have a first direction side oxygen-containing region 31 (hereinafter, sometimes abbreviated as "first oxygen region 31") on the first direction side of the first Al-Ti region 32 in the thickness direction. The first oxygen region 31 is a region that contains more oxygen than the Al layer 33 or the first Al-Ti region 32, and has a point where the oxygen concentration is maximum in the thickness direction. The oxygen at this position may be less than in the second direction. The first oxygen region 31 has a point where the oxygen (O) concentration is maximum in the thickness direction, and the atomic fraction of oxygen atoms at this maximum point is preferably 40 at% or less, more preferably 20 at% or less, and even more preferably 16 at% or less. The first oxygen region 31 is an oxide of Al or Ti, and has a first direction side oxygen-containing region 31 (hereinafter, sometimes abbreviated as "first oxygen region 31"). ２ O ３ or TiO ２ may include:

[0039] The "second granular portion 34" and the "first granular portion 32" will be described below. For example, in a cross-sectional TEM image of a 10 μm-wide n-type ohmic electrode 30, which is created by successively photographing cross-sectional TEM images as shown in FIG. 2B while moving horizontally in the in-plane direction and stitching together multiple cross-sectional TEM images, the above-described granular portion may be present in at least a part or all of the cross section. The thickness of the "second granular portion 34" and the "first granular portion 32" in the depth direction is preferably, for example, a maximum thickness in the cross section of 30 nm or more and 400 nm or less. In the cross-sectional TEM image, there may be a range in the in-plane direction where the second granular portion 34 is partially absent. Preferably, there is at least one second granular portion 34 within a 10 μm-wide TEM image range, more preferably two or more, and even more preferably three or more. The first granular portion 32 may also have a partially absent range in the in-plane direction, and it is preferable that there is at least one first granular portion 32 within a 10 μm-wide TEM image range, more preferably two or more, and even more preferably three or more. For example, when a cross-sectional TEM image of a 10 μm-wide area is acquired, the maximum width of the granular portions is preferably 1 μm or more in total, and more preferably 5 μm or more.

[0040] In the present invention, when the thickness of the second Ti layer 23 is equal to or greater than a certain value (i.e., 15 nm or greater), heat treatment for contact annealing is performed on the n-side metal stack 20, whereby Al atoms in the Al layer 22 and Ti atoms in the second Ti layer 23 diffuse. As a result, TiAl, an intermetallic compound, is formed on the upper side of the Al layer 33. ３ It is believed that an Al-Ti alloy, which is believed to be the second granular portion 34, is generated and observed as the second granular portion 34. The melting temperature of Al is 660°C, but the formation of such an intermetallic compound can occur at temperatures between 450°C and 700°C. Therefore, in the n-type ohmic electrode 30, a second Al-Ti region 34 corresponding to the second granular portion 34 exists above the Al layer 33 (in the second direction). Furthermore, in the n-type ohmic electrode 30, an Al ２ O ３ or TiO ２On the other hand, if the thickness of the second Ti layer 23 is less than 15 nm, the second granular portion 34 is unlikely to be generated, and the second oxygen region 35 is likely to be formed on the upper side of the Al layer 33, and the Al layer 33 may have a high percentage of oxygen atoms. ２ O ３ or TiO ２ The reason why an n-type ohmic electrode 30 having a good forward voltage and a small variation in the forward voltage within the wafer surface can be obtained when the conditions of the present invention are satisfied is that TiAl ３ If the second Al-Ti region 34 satisfying the above atomic content is formed, TiAl ３ The present inventors believe that the effects of the present invention are achieved by forming an Al—Ti alloy that is thought to be the Al—Ti alloy. Based on the above, the n-type ohmic electrode 30 according to this embodiment can be obtained by depositing the second Ti layer 23 of an appropriate thickness and performing a heat treatment.

[0041] The Al atoms of the Al layer 22 and the first Ti layer 21 diffuse, and an intermetallic compound, TiAl ３ An Al-Ti alloy that is thought to be the first granular portion 32 (first Al-Ti region 32) is generated and may be observed as the first granular portion 32. The relationship between the thickness of the second Ti layer 23 and the first Al-Ti region 32 and the first direction side oxygen-containing region 31 is not clear, but according to examples described later, when the second Al-Ti region 34 is formed, the maximum oxygen value in the first direction side oxygen-containing region 31 tends to be smaller.

[0042] In the n-type ohmic electrode 30, the thickness of the entire ohmic electrode is preferably 316 nm or more and 1130 nm or less, more preferably 423 nm or more and 1007 nm or less, and even more preferably 530 nm or more and 885 nm or less.

[0043] (Method for Manufacturing Group III Nitride Semiconductor Light-Emitting Device) A method for manufacturing a Group III nitride semiconductor light-emitting device 100 (hereinafter sometimes abbreviated as "light-emitting device 100") according to this embodiment will be described with reference to FIG. 3 . The light-emitting device 100 comprises at least the steps of forming an n-type semiconductor layer 10 and forming the above-described n-type ohmic electrode 30 on the n-type semiconductor layer 10. The light-emitting device 100 may further comprise the steps of forming a light-emitting layer 11 on the n-type semiconductor layer 10, forming a p-type Group III nitride semiconductor layer 12 (hereinafter sometimes abbreviated as "p-type semiconductor layer 12") on the light-emitting layer 11, and forming a first p-side metal stack on the p-type semiconductor layer 12. Here, in the heat treatment in the second step of the method for manufacturing the n-type ohmic electrode 30, it is preferable to perform the heat treatment together with the first p-side metal stack. Simultaneously heat-treating the n-side metal stack 20 and the first p-side metal stack can simplify the manufacturing process and also reduce manufacturing costs. By heat treating the n-side metal stack 20 and the first p-side metal stack, the n-type ohmic electrode 30 and the first p-type ohmic electrode 41 are formed, respectively.

[0044] When the p-side metal stack is heat-treated in an oxygen-containing mixed gas atmosphere, it may become a low-resistance first p-type ohmic electrode 41 or second p-type ohmic electrode 42. In such a case, if the n-side metal stack 20 can be heat-treated even in an oxygen-containing atmosphere, the process can be simplified by performing the heat treatment together with the p-side metal stack. However, because the n-side metal stack 20 contains a large amount of Al, it has been thought difficult to form an n-type ohmic electrode 30 that can achieve low resistance even when heated in an oxygen-containing atmosphere. In the manufacturing method of the n-type ohmic electrode 30 of the present invention, in which the second Ti layer 23 has a thickness of 15 nm or more, the second step can be performed together with the p-side metal stack, even if the heat treatment in the second step is performed in an oxygen-containing mixed gas atmosphere. Although the reason for this is unclear, the TiAl generated in the second Al-Ti region 34 during heat treatment may be ３Such an intermetallic compound is expected to have the effect of reducing the resistance of the n-type ohmic electrode 30, as well as the effect of suppressing oxygen uptake on the second direction side due to natural oxidation or heat treatment in an oxygen-containing mixed gas atmosphere, or the effect of suppressing oxygen migration to the first direction side in the n-type ohmic electrode 30. Details of each component and each process will be described below, including specific examples.

[0045] First, an n-type semiconductor layer 10 may be formed on a substrate 1 made of sapphire, AlN single crystal, or the like. Examples of the n-type semiconductor layer 10 include an n-type AlGaN layer, an n-type AlInGaN layer, an n-type GaN layer, and an n-type AlN layer. The n-type semiconductor layer 10 is preferably an n-type AlGaN layer. Examples of dopants for the n-type semiconductor layer 10 include Si and S. The thickness of the n-type semiconductor 10 is preferably 500 nm or more and 5 μm or less, more preferably 1 μm or more and 4 μm or less, and even more preferably 1.5 μm or more and 3 μm or less. An undoped layer may be formed between the substrate 1 and the n-type semiconductor layer 10.

[0046] Next, a light-emitting layer 11 containing a Group III nitride semiconductor may be formed on the n-type semiconductor layer 10. The light-emitting layer 11 may have a single-layer structure or a quantum well structure having a barrier layer and a well layer. The light-emitting layer 11 may be undoped, or may be n- or p-doped. The thickness of the light-emitting layer 11 is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 60 nm or less, and even more preferably 20 nm or more and 40 nm or less. An n-type guide layer may be formed between the n-type semiconductor layer 10 and the light-emitting layer 11. The Group III nitride semiconductor light-emitting element 100 can be a light-emitting element having various peak wavelengths ranging from blue to ultraviolet, depending on the composition of the light-emitting layer 11. Among these, a light-emitting element emitting ultraviolet light with a peak wavelength of 340 nm or less is preferred.

[0047] The p-type semiconductor layer 12 may be formed on the light-emitting layer 11. Examples of dopants for the p-type semiconductor layer 12 include Mg and Be. The thickness of the p-type semiconductor layer 12 is preferably 40 nm or more and 1000 nm or less, more preferably 70 nm or more and 180 nm or less, and even more preferably 80 nm or more and 105 nm or less. A guide layer may be provided between the light-emitting layer 11 and the p-type semiconductor layer 12, or the p-type semiconductor layer 12 may be obtained by forming a p-type electron blocking layer, a p-type cladding layer, and a p-type contact layer in this order from the light-emitting layer 11 side.

[0048] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source and trimethylaluminum (TMAl) as an Al source are used in a predetermined mixture ratio, and these source gases are vapor-phase grown using a carrier gas, thereby forming a layer with a desired thickness depending on the growth time. When each layer is doped to p-type or n-type, a desired dopant source gas may be further used.

[0049] Thereafter, a mask is formed on the p-type semiconductor 12, and mesa etching is performed by dry etching to expose a portion of the n-type semiconductor layer 10. Next, a first p-side metal laminate is formed on the p-type semiconductor layer 12. As illustrated in FIG. 4, five first p-side metal laminates may be formed in a rectangular shape. The first p-side laminate may be, for example, Ni / Rh / Au.

[0050] On the n-type semiconductor layer 10 exposed by mesa etching, an n-side metal stack 20 is formed by sequentially stacking a first Ti layer 21, an Al layer 22, and a second Ti layer 23 using the above-described method for manufacturing the n-type ohmic electrode 30. As illustrated in FIG. 4 , the n-side metal stack 20 may be formed in a comb shape with comb teeth between the strips. In this case, an n-type protective film formation region 10a may be formed between the strips and the comb teeth (and on the periphery of the light-emitting element 100) where the n-type semiconductor layer 10 is exposed and no electrode is formed. Next, heat treatment is performed in an oxygen-containing mixed gas atmosphere. The oxygen content of the mixed gas is preferably 1% to 60%, more preferably 10% to 50%, and even more preferably 20% to 40%. The mixed gas used may also contain an inert gas such as nitrogen or argon. The temperature during the heat treatment is preferably 450°C or higher and 700°C or lower, more preferably 500°C or higher and 600°C or lower, and even more preferably 520°C or higher and 580°C or lower. After the heat treatment is started, it is preferable not to use oxygen in the mixed gas until the chamber in which the treatment is being performed reaches a specified temperature, and to flow oxygen after the chamber reaches the specified temperature. By performing this heat treatment, the first p-side metal stack becomes the first p-type ohmic electrode 41, and the n-side metal stack 20 becomes the n-type ohmic electrode 30.

[0051] Next, a second p-side metal stack may be formed on the first p-type ohmic electrode 41. The second p-side metal stack may be, for example, Pt / Au / Ti from the first p-type ohmic electrode 41 side. A heat treatment is performed to form the second p-type ohmic electrode 42. This heat treatment is the same as the heat treatment method described above, except that the temperature is increased while oxygen is flowing. The first p-type ohmic electrode 41 and the second p-type ohmic electrode 42 are combined to form the p-type ohmic electrode 40.

[0052] Next, an n-side Pt-containing layer 50 and a p-side Pt-containing layer 60 containing Pt may be formed on the n-type ohmic electrode 30 and the p-type ohmic electrode 40, respectively. The n-side Pt-containing layer 50 and the p-side Pt-containing layer 60 may be, for example, Ti / Pt / Au / Ti from the ohmic electrode side.

[0053] Next, a protective film 70 made of a dielectric may be formed on the entire surface of the light emitting element 100. The dielectric may be, for example, SiO ２ or Si ３ N ４ Examples include the above. A portion of the protective film 70 on the upper surfaces of the n-side Pt-containing layer 50 and the p-side Pt-containing layer 60 may be exposed using buffered hydrofluoric acid (BHF). The exposed area is preferably smaller than the n-side Pt-containing layer 50 and the p-side Pt-containing layer 60. A p-side buried metal layer 65, for example, a Ti layer and an Au layer stacked in this order, may be formed on the exposed p-side Pt-containing layer 60. When the top surface is solder, a Ti layer, a Pt layer, and an AuSn layer may be stacked in this order to form a p-side pad electrode 81. In this case, as shown in FIG. 5 , a p-side pad electrode 81 may also be formed on a portion of the protective film 70 so as to connect the p-side buried metal layer 65 of each strip across the n-type ohmic electrode 30 between each strip and the n-type layer protective film formation region 10a on the protective film 70. The p-side buried metal layer 65 may be, for example, Ti / Au / Ti / Pt / AuSn from the p-side Pt-containing layer 60 side.

[0054] Similar to the case of forming the p-side buried metal layer 65 and the p-side pad electrode 81, the n-side buried metal layer 55 and the n-side pad electrode 82 can also be formed on the n-side Pt-containing layer 50 through an exposed region (a portion where the n-side buried metal layer 55 is to be formed) obtained by removing the protective film 70 (see FIG. 3 ) with BHF. The n-side buried metal layer 55 can be, for example, Ti / Au from the n-side Pt-containing layer 50 side. The n-side pad electrode 82 can be, for example, Ti / Pt / AuSn from the n-side Pt-containing layer 50 side.

[0055] Finally, the wafer can be separated into individual chip-like light-emitting devices 100 using a laser dicing device, a breaking device, or the like. In this way, the group III nitride semiconductor light-emitting device 100 having the above-described n-type ohmic electrode 30 can be manufactured. This group III nitride semiconductor light-emitting device 100 has a good forward voltage and a forward voltage with small variation within the wafer surface.

[0056] An example of the n-type ohmic electrode 30 according to this embodiment will be described.

[0057] Example 1 As a light-emitting element according to Example 1, a light-emitting element 100 was produced having a basic shape similar to that of the light-emitting element 100 of the above embodiment shown in Fig. 3. Fig. 4 is a top view of the light-emitting element 100 of Example 1, showing an example of the arrangement of the n-type layer protective film formation region 10a, the n-type ohmic electrode 30, the p-type ohmic electrode 40, the n-side buried metal layer 55, the p-side buried metal layer 65, the protective film 70, the p-side pad electrode 81, and the n-side pad electrode 82.

[0058] 5 shows a cross section of the light-emitting element 100 shown in FIG. 4 taken along the line I-I. As shown in FIG. 4, the light-emitting element 100 according to Example 1 has five rectangular p-type ohmic electrodes 40 formed on almost the entire surface of the p-type semiconductor layer 12, with a comb-shaped n-type ohmic electrode 30 inserted between them. Between the p-type ohmic electrode 40 and the n-type ohmic electrode 30, an n-type layer protective film formation region 10a is formed in which no electrode is formed and the n-type semiconductor layer 10 is exposed. The rectangular shape of the p-type ohmic electrode 40, the shape of the comb-shaped portion of the n-type ohmic electrode 30, and the p-side buried metal layer 65 and n-side buried metal layer 55 described later of the light-emitting element 100 in this example are similar to those of the semiconductor light-emitting element disclosed in the specification and drawings (FIGS. 1 to 7) of JP 2019-106406 A, and were fabricated in the same manner except for the size or structure (the configuration of each ohmic electrode, barrier layer, Pt-containing layer, pad, etc.). The conditions for producing each layer are described in detail below.

[0059] A sapphire substrate (diameter 2 inches, film thickness: 430 μm, plane orientation: (0001), m-axis off-angle θ: 0.11 degrees) was prepared as the substrate 1. Next, an AlN layer with a central film thickness of 0.50 μm (average film thickness 0.51 μm) was grown on the sapphire substrate by MOCVD to prepare an AlN template substrate. At this time, the growth temperature of the AlN layer was 1330° C., the growth pressure in the chamber was 10 Torr, and the growth gas flow rates of ammonia gas and TMA gas were set so that the group V / group III ratio was 206. Group V element gas (NH ３The flow rate of the group III element gas (TMA) was 250 sccm, and the flow rate of the group III element gas (TMA) was 53 sccm. The thickness of the AlN layer was measured at a total of 25 equally spaced locations on the wafer surface (AlN template substrate), including the center, using an optical interference film thickness measurement device (Nanospec M6100a; manufactured by Nanometrics).

[0060] Next, the AlN template substrate was introduced into a heat treatment furnace, and after reducing the pressure to 10 Pa, the nitrogen gas was purged to atmospheric pressure to create a nitrogen gas atmosphere inside the furnace. The temperature inside the furnace was then raised to perform a heat treatment on the AlN template substrate. At this time, the heating temperature was 1650° C. and the heating time was 4 hours.

[0061] An undoped AlGaN layer (undoped layer) having a thickness of 30 nm and an average Al composition ratio of 0.4 was formed by MOCVD. ０．２５ Ga ０．７５ The n-type semiconductor layer 10 was made of N and doped with Si to a thickness of 2 μm. As a result of SIMS analysis, the Si concentration in the n-type semiconductor layer 10 was found to be 5.0×10 １８ atoms / cm ３ It was.

[0062] The light emitting layer 11 is formed by depositing Al ０．２５ Ga ０．７５ An n-type guide layer made of N and doped with Si was formed to a thickness of 30 nm, and a 14 nm Al barrier layer was further formed. ０．２５ Ga ０．７５ N was formed. Then, Al ０．１０ Ga ０．９０ A well layer of 2 nm thick made of N and a well layer of 14 nm thick made of Al ０．２５ Ga ０．７５ Two barrier layers made of N are formed alternately, and then Al ０．１０ Ga ０．９０ A 2-nm-thick well layer made of N was formed. That is, the number of well layers and the number of barrier layers were both 3, the Al composition ratio of the barrier layers was 0.25, and the Al composition ratio of the well layers was 0.10. The barrier layers were doped with Si. The emission center wavelength of the light-emitting layer 11 was 340 nm.

[0063] Then, on the third well layer, nitrogen gas was used as a carrier gas to deposit Al ０．２５ Ga ０．７５ An undoped AlGaN guide layer made of N was formed. The thickness of the AlGaN guide layer was set to 2 nm. Next, while stopping the supply of TMA gas, the nitrogen carrier gas was stopped and hydrogen was supplied while continuing to supply ammonia gas. After changing the carrier gas to hydrogen, TMA gas and TMG gas, which are source gases of Group III elements, were supplied again to form AlGaN guide layer. ０．４５ Ga ０．５５ A p-type electron blocking layer of 55 nm thick was formed, which was made of N and doped with Mg. After the p-type electron blocking layer was grown to a predetermined thickness, the flow rate ratio of TMAl gas and TMGa gas was changed to increase the Al ０．２０ Ga ０．８０ An Mg-doped AlGaN cladding layer (p-type cladding layer) made of N was formed to a thickness of 30 nm.

[0064] Next, the growth of the AlGaN cladding layer was stopped, the carrier gas was switched to nitrogen gas, and the gas flow rate was changed to the set conditions for the p-type GaN contact layer. After that, the carrier gas was switched to hydrogen, and a Mg-doped p-type GaN contact layer (p-type contact layer) with a thickness of 5 nm was formed as the p-type semiconductor layer 12.

[0065] A mask was formed on the p-type semiconductor layer 12, and mesa etching was performed by dry etching to expose a part of the n-type semiconductor layer 10. A first p-side metal laminate made of Ni / Rh / Au was then formed by sputtering so that five strips were arranged on the p-type semiconductor layer 12. The Ni film thickness of the first p-side metal laminate was 7 nm, the Rh film thickness was 50 nm, and the Au film thickness was 20 nm.

[0066] On the n-type semiconductor layer 10 exposed by mesa etching, an n-side metal stack 20 consisting of metal layers stacked in this order, a first Ti layer 21, an Al layer 22, and a second Ti layer 23, was formed by sputtering into a comb shape with comb teeth between the strips. At this time, an n-type semiconductor layer protective film formation region 10a was provided between the strips and the comb teeth (and on the chip periphery) where the n-type semiconductor layer 10 was exposed and no electrode was formed. In the n-side metal stack 20, the first Ti layer 21 had a thickness of 20 nm, the Al layer 22 had a thickness of 600 nm, and the second Ti layer had a thickness of 20 nm.

[0067] Next, the temperature was raised to 550°C while flowing nitrogen gas at 1000 sccm. After 5 minutes at 550°C, contact annealing (RTA: Rapid Thermal Anneal) was performed for another 10 minutes at 550°C while flowing oxygen gas at an additional 500 sccm. As a result, the n-type ohmic electrode 30 and the first p-type ohmic electrode 41 were simultaneously heat-treated, and ohmic contact was formed between the n-type semiconductor layer 10 and the p-type semiconductor layer 12. The proportion of oxygen contained in the mixed gas atmosphere when oxygen gas was flowing was 33%.

[0068] A second p-side metal stack was formed by stacking Pt / Au / Ti in this order on the first p-type ohmic electrode 41. Here, the Pt layer had a thickness of 50 nm, the Au layer had a thickness of 100 nm, and the Ti layer had a thickness of 5 nm. The temperature was raised to 550°C while flowing nitrogen gas at 1000 sccm and oxygen gas at 500 sccm, and annealed for 15 minutes after reaching 550°C. This formed a second p-type ohmic electrode 42. The first p-type ohmic electrode 41 and the second p-type ohmic electrode 42 together constituted the p-type ohmic electrode 40. The n-type ohmic electrode 30 and the p-type ohmic electrode 40 were simultaneously heat-treated.

[0069] An n-side Pt-containing layer 50 was formed by stacking Ti / Pt / Au / Ti layers in this order on the n-type ohmic electrode 30. The thicknesses of the layers, from the substrate 1 side, were a 50 nm Ti layer, a 50 nm Pt layer, a 500 nm Au layer, and a 10 nm Ti layer. The first 50 nm Ti layer of the n-side Pt-containing layer 50 is referred to as a third Ti layer 51.

[0070] Similarly, a p-side Pt-containing layer 60 was formed on the p-type ohmic electrode 40. The p-side Pt-containing layer 60 was the same as the n-side Pt-containing layer 50 and was formed at the same time. The size of the p-side Pt-containing layer 60 was a rectangle with long sides of 734 μm and short sides of 86 μm when viewed from above.

[0071] Next, SiO ２ The protective film 70 made of was formed, and the protective film 70 on the upper surface of the p-side Pt-containing layer 60 was removed using BHF to expose it. The exposed region (the portion where the p-side buried metal layer 65 is to be formed) was formed to be smaller than the p-side Pt-containing layer 60. The size of the exposed region was a rectangular shape with long sides of 329 μm and short sides of 72 μm.

[0072] Then, as shown in FIG. 4 , a p-side buried metal layer 65 was formed by stacking a Ti layer and an Au layer in this order on the exposed region of the p-side Pt-containing layer 60. When the outermost surface was to be soldered, a p-side pad electrode 81 was formed by stacking a Ti layer, a Pt layer, and an AuSn layer on top of the Ti layer. As shown in FIG. 5 , the p-side pad electrode 81 was also formed on a portion of the protective film 70 so as to connect the p-side buried metal layer 65 of each strip across the n-type ohmic electrodes 30 between each strip and the n-type layer protective film formation region 10 a. The p-side buried metal layer 65 had a Ti thickness of 10 nm and an Au thickness of 1000 nm. The p-side pad electrode 81 had a Ti thickness of 50 nm, a Pt thickness of 200 nm, and an AuSn thickness of 3000 nm.

[0073] Similar to the formation of the p-side buried metal layer 65 and the p-side pad electrode 81, the protective film 70 (see FIG. 3 ) was removed with BHF to expose the n-side Pt-containing layer 50, and an n-side buried metal layer 55 having a Ti layer and an Au layer laminated in this order was formed on the exposed region (the portion where the n-side buried metal layer 55 was to be formed). Further, an n-side pad electrode 82 having a Ti layer, a Pt layer, and an AuSn layer laminated in this order was formed. At this time, similar to the p-side pad electrode 81, the n-side pad electrode 82 was also formed on a portion of the protective film 70.

[0074] Finally, a laser dicing device and a breaking device were used to separate the light emitting elements 100 on individual chips. The chip size was a rectangle of 1000 μm×1000 μm.

[0075] Comparative Example 1 The same procedure as in Example 1 was carried out except that the film thickness of the second Ti layer 23 was set to 5 nm.

[0076] Comparative Example 2 The same procedure as in Example 1 was carried out except that the thickness of the second Ti layer 23 was set to 10 nm.

[0077] Example 2 The well layer of the light emitting layer 11 was made of Al so that the central emission wavelength was 340 nm to 310 nm. ０．３０ Ga ０．７０ Except for changing the Al composition ratio of the undoped layer to N and increasing the Al composition ratio of each semiconductor layer accordingly, the experiment was carried out in the same manner as in Example 1. The Al composition ratio of the undoped layer was 0.55, the Al composition ratio of the n-type semiconductor layer 10 was 0.45, the Al composition ratio of the n-type guide layer and barrier layer was 0.55, and the Al composition ratio of the p-type electron blocking layer was 0.58.

[0078] Comparative Example 3 The same procedure as in Example 2 was carried out except that the thickness of the second Ti layer 23 was set to 5 nm.

[0079] Comparative Example 4 The same procedure as in Example 2 was carried out except that the film thickness of the second Ti layer 23 was set to 10 nm.

[0080] Example 3 The same procedure as in Example 2 was carried out except that the film thickness of the second Ti layer 23 was set to 30 nm.

[0081] Example 4 The same procedure as in Example 2 was carried out except that the film thickness of the second Ti layer 23 was set to 100 nm.

[0082] Cross-sectional TEM images were observed for Example 1, Comparative Example 1, Comparative Example 2, and Example 2, Example 4, Comparative Example 3, and Comparative Example 4. First granular portions were observed in all cross-sectional TEM images. Second granular portions were observed in Examples 1, 2, and 4, but not in Comparative Examples 1 to 4. A cross-sectional TEM image for Example 1 is shown in FIG. 2B. Next, as shown in FIGS. 6 to 12, TEM-EDS profiles in the thickness direction of the n-type ohmic electrode 30 were measured. Nitrogen (N), oxygen (O), aluminum (Al), silicon (Si), titanium (Ti), nickel (Ni), gallium (Ga), rhodium (Rh), platinum (Pt), and gold (Au) were measured in the measurements, and all profiles were present. However, for convenience of illustration, only the profiles for oxygen (O), aluminum (Al), titanium (Ti), and gallium (Ga) are excerpted and shown. The figure also shows a profile from the third Ti layer 51, which is the first layer of the Pt-containing layer formed after heat treatment, to partway through the n-type semiconductor layer 10. Examples 1, 2, and 4 are TEM-EDS profiles at positions where the second granular portions were observed in the cross-sectional TEM images. Note that the Pt-containing layer suppresses the diffusion of metal elements formed above the Pt layer, and the elemental percentages of nickel (Ni), rhodium (Rh), platinum (Pt), and gold (Au) contained in the n-type ohmic electrode 30 are trace amounts of 0.5 at% or less.

[0083] In the TEM-EDS profiles in FIGS. 6 to 12 , the portion representing the first Al—Ti region 32 or the second Al—Ti region 34 is designated "A." Furthermore, in each profile, a region (second oxygen region 35) with 10 at % or more of oxygen is present near the interface between the n-side Pt-containing layer 50 on the second direction side of the Al layer 22 and the third Ti layer 51. It can be seen that the second oxygen region 35 is located above the second Al—Ti region 34 in Examples 1, 2, and 4, which correspond to FIGS. 6 , 9 , and 10 , respectively. In the profiles in FIGS. 6 , 9 , and 10 , the portion showing the maximum oxygen atomic percentage is designated "B." Furthermore, in Comparative Examples 2 and 4 (see FIGS. 8 and 12 ), in which the second Ti layer 23 has a thickness of 10 nm, two maximum oxygen points are observed in the second oxygen region 35, and the one inside the Al layer is designated "C." In Comparative Example 1 in which the thickness of the second Ti layer 23 is 5 nm, two oxygen maximum points are observed in the first oxygen region 31, and the one on the inner side of the Al layer is designated as "C".

[0084] 13 shows the at% ratio of oxygen atoms to the total at% of Al atoms and Ti atoms in the thickness direction of the n-type ohmic electrode 30 of Example 1, Comparative Example 1, and Comparative Example 2, starting from the interface between the Pt layer and the third Ti layer 51 in the n-side Pt-containing layer 50. It can be seen from Fig. 13 that the at% ratio of oxygen atoms to the total at% of Al atoms and Ti atoms in the second oxygen region 35 of Example 1 is in the range of 0.85 or less, which is smaller than that of Comparative Example 1 and Comparative Example 2.

[0085] 14 shows the atomic fraction of Ti atoms in the thickness direction of the n-type ohmic electrode 30 in Example 1, Comparative Example 1, and Comparative Example 2, starting from the interface between the Pt layer and the third Ti layer 51 in the n-side Pt-containing layer 50. The graph shows that in Comparative Example 1 and Comparative Example 2, the atomic fraction of Ti becomes almost 0 when the electrode depth direction exceeds approximately 90 nm, whereas in Example 1, approximately 20 at % Ti is present.

[0086] In each example and comparative example, after the elements were separated, the forward voltage Vf was measured using a sorting machine. The forward voltage (Vf) was measured by passing a forward current of 350 mA. The number of light-emitting elements 100 measured was approximately 1,000 for each example and comparative example.

[0087] Table 1 shows the film thickness of the second Ti layer 23 of the light-emitting element 100 of Example 1, Comparative Example 1, and Comparative Example 2, the presence or absence of the first Al-Ti region 32 (first granular portion), the presence or absence of the second Al-Ti region 34 (second granular portion), the maximum oxygen value of the first oxygen region, the maximum oxygen value of the second oxygen region, O [at %] / (Al+Ti) [at %] at the maximum oxygen point of the second oxygen region, and the average value [standard deviation] of the forward voltage Vf at a forward current of 350 mA.

[0088]

[0089] Table 2 shows the film thickness of the second Ti layer 23 of the light-emitting element 100 of Example 2, Example 3, Example 4, Comparative Example 3, and Comparative Example 4, the presence or absence of the first Al-Ti region 32 (first granular portion), the presence or absence of the second Al-Ti region 34 (second granular portion), the maximum oxygen value of the first oxygen region, the maximum oxygen value of the second oxygen region, O [at %] / (Al+Ti) [at %] at the maximum oxygen point of the second oxygen region, and the average value [standard deviation] of the forward voltage Vf at a forward current of 350 mA.

[0090]

[0091] From Tables 1 and 2, it can be seen that the Vf values ​​in Examples 1, 2, 3, and 4, in which the thickness of the second Ti layer 23 is 20 nm or more, are lower than those in Comparative Examples 1, 2, 3, and 4, and the variations are smaller. It can also be seen that the average value and standard deviation of Vf become smaller as the thickness of the second Ti layer 23 increases to 5 nm, 10 nm, and 20 nm. First, it is believed that the fact that Vf is smallest in Examples 1 and 2 is due to the second granular portions 34 of the second Al-Ti region 34. ３ ) reduced the resistance of the n-type ohmic electrode 30, and a good Vf was obtained. The reason why the results of Comparative Examples 2 and 4 are better than those of Comparative Examples 1 and 3 is that when the thickness of the second Ti layer 23 was 5 nm, oxygen was taken in in a layered manner uniformly within the surface, but when the thickness of the second Ti layer 23 was 10 nm, oxygen was dispersed to different depths in the thickness direction, causing a portion like "C" in the figure, and the oxygen distribution within the surface was non-uniform.

[0092] Furthermore, when the thickness of the second Ti layer 23 exceeds 20 nm and increases to 100 nm as in Example 4, the average value of Vf increases because the volume fraction of Ti, which has a higher resistance than Al, increases. However, oxygen migration is more likely to be hindered, and the amount of localized oxygen (maximum value) decreases, so the standard deviation of Vf (variation depending on location) decreases.

[0093] 10, similarly to the TEM-EDS profile (FIG. 9) of Example 2, the first Al-Ti region 32 (first granular portion) and the second Al-Ti region 34 (second granular portion) are observed, and it is found that the second oxygen region 35 is located above the second Al-Ti region 34. It is also found that the size of the second Al-Ti region 34 (second granular portion) is relatively large because the second Ti layer 23 is thick.

[0094] REFERENCE SIGNS LIST 100 Group III nitride semiconductor light emitting element 1 Substrate 10 n-type semiconductor layer 11 Light emitting layer 12 p-type semiconductor layer 20 n-side metal stack 21 First Ti layer 22 Al layer 23 Second Ti layer 30 n-type ohmic electrode 31 First oxygen region 32 First Al-Ti region (first granular portion) 33 Al layer 34 Second Al-Ti region (second granular portion) 35 Second oxygen region 40 p-type ohmic electrode 41 First p-type ohmic electrode 42 Second p-type ohmic electrode 50 n-side Pt-containing layer 51 Third Ti layer 55 n-side buried metal layer 60 p-side Pt-containing layer 65 p-side buried metal layer 70 Protective film 81 p-side pad electrode 82 n-side pad electrode

Claims

1. An n-type ohmic electrode provided on an n-type Group III nitride semiconductor layer, the n-type ohmic electrode having: an Al layer; and a second-direction-side Al-Ti region located in a second direction of the Al layer opposite to a first direction, which is the n-type Group III nitride semiconductor layer side; the second-direction-side Al-Ti region containing 50 at % or more Al, 5 at % or more and 30 at % or less Ti, and 10 at % or less O.

2. The n-type ohmic electrode according to claim 1, wherein the Al layer is present at least in the center in the thickness direction.

3. The n-type ohmic electrode according to claim 1, further comprising a second direction side oxygen-containing region located in the second direction of the second direction side Al-Ti region in the thickness direction, wherein the second direction side oxygen-containing region contains 10 at % or more of O.

4. The n-type ohmic electrode according to claim 3, wherein at the point where oxygen in the second direction side oxygen-containing region is at its maximum in the thickness direction, the ratio of oxygen atoms at % to the total at % of Al atoms and Ti atoms is 1.0 or less.

5. The n-type ohmic electrode according to claim 1, further comprising a first direction side Al-Ti region located in the first direction of the Al layer in the thickness direction, the first direction side Al-Ti region containing 50 at % or more Al, 5 at % or more and 30 at % or less Ti, and 10 at % or less O.

6. A Group III nitride semiconductor light-emitting device comprising: an n-type Group III nitride semiconductor layer; and the n-type ohmic electrode according to any one of claims 1 to 5 provided on a surface of the n-type Group III nitride semiconductor layer.

7. A method for manufacturing an n-type ohmic electrode, comprising: a first step of forming an n-side metal laminate by sequentially forming a first Ti layer, an Al layer, and a second Ti layer on the surface of an n-type Group III nitride semiconductor layer; and a second step of performing heat treatment on the n-side metal laminate, wherein the thickness of the second Ti layer formed in the first step is 15 nm or more.

8. The method for manufacturing an n-type ohmic electrode according to claim 7, wherein in the second step, the heat treatment is performed with the second Ti layer as the outermost surface.

9. The method for manufacturing an n-type ohmic electrode according to claim 7, wherein in the second step, the heat treatment is performed in a mixed gas atmosphere containing 1% to 60% oxygen.

10. The method for manufacturing an n-type ohmic electrode according to claim 7, wherein the second Ti layer formed in the first step has a thickness of 100 nm or less.

11. A method for manufacturing a Group III nitride semiconductor light-emitting device, comprising: forming an n-type Group III nitride semiconductor layer; and forming the n-type ohmic electrode on the n-type Group III nitride semiconductor layer by using the method for manufacturing an n-type ohmic electrode according to any one of claims 7 to 10.

12. The method for manufacturing a Group III nitride semiconductor light-emitting device according to claim 11, further comprising the steps of: forming a light-emitting layer on said n-type Group III nitride semiconductor layer; forming a p-type Group III nitride semiconductor layer on said light-emitting layer; and forming a p-side metal laminate on said p-type Group III nitride semiconductor layer, wherein in said second step, said heat treatment is performed together with said p-side metal laminate.

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