Semiconductor device

Abstract

This semiconductor device comprises a substrate, a plurality of semiconductor elements, and a clip (50) (plate member). The plurality of semiconductor elements include at least three semiconductor elements disposed side by side in a predetermined direction (X direction). The clip (50) has a first bonding part (50B1), a second bonding part (50B2), a third bonding part (50B3), and a wiring bonding part (50B4). The position of the wiring bonding part (50B4) in the predetermined direction (X direction) is between the first bonding part and the second bonding part. In the outer edge of the clip (50), a portion that forms a current path from the first bonding part (50B1) to the wiring bonding part (50B4) is defined as a first outer edge (50A1), and a portion that forms a current path from the second bonding part (50B2) to the wiring bonding part (50B4) is defined as a second outer edge (50A2). The first outer edge (50A1) and the second outer edge (50A2) are inclined in different directions with respect to a reference direction (Y direction).

Description

Semiconductor Devices CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Patent Application No. 2024-087270 filed in Japan on May 29, 2024, and the contents of the original application are incorporated by reference in their entirety.

[0002] TECHNICAL FIELD The disclosure herein relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification.

[0004] Japanese Patent Application Laid-Open No. 2002-153079

[0005] In Patent Document 1, multiple IGBTs (semiconductor elements) connected in parallel to one another are mounted on a substrate. Collector electrodes (first main electrodes) of the multiple semiconductor elements are bonded to a first wiring pattern on the substrate. Emitter electrodes (second main electrodes) are connected to a second wiring pattern on the substrate by bonding wires (conductors). Multiple bonding wires are connected to one emitter electrode.

[0006] Here, if a structure using a metal plate member instead of bonding wires is adopted, the number of conductor connection points to the second main electrode can be reduced. Moreover, since one plate member can be used for multiple semiconductor elements, the number of conductor parts can be reduced.

[0007] However, when multiple semiconductor elements are connected using a single plate member, the length of the electrical path from each semiconductor element to the second wiring pattern differs for each semiconductor element. For example, the length of the electrical path from the portion of the plate member to which each semiconductor element is connected to the portion of the plate member connected to the second wiring pattern differs for each semiconductor element. As a result, the impedance in the electrical path differs for each semiconductor element. This causes a current imbalance between the multiple semiconductor elements connected in parallel. This current imbalance becomes particularly noticeable when the semiconductor elements are turned on due to the variation in impedance.

[0008] One disclosed object is to provide a semiconductor device that includes a plurality of semiconductor elements connected in parallel and that suppresses current imbalance.

[0009] One aspect of the disclosure is a semiconductor device comprising: a substrate having first wiring and second wiring; a plurality of semiconductor elements each having a first main electrode and a second main electrode provided on a surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member that shorts the second main electrodes of the plurality of semiconductor elements to each other and is bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction, wherein of the three semiconductor elements, the semiconductor elements located at both ends are referred to as a first semiconductor element and a second semiconductor element, and the semiconductor element located between the first semiconductor element and the second semiconductor element is referred to as a third semiconductor element, and the plate member has a first bonding portion that is a bonding portion with the first semiconductor element, a second bonding portion that is a bonding portion with the second semiconductor element, a third bonding portion that is a bonding portion with the third semiconductor element, and a wiring bonding portion bonded to the second wiring, and the position of the wiring bonding portion in the predetermined direction is between the first bonding portion and the second bonding portion, Of the outer edges of the plate member, the outer edge of a portion that forms a current path from the first joint to the wiring joint is defined as the first outer edge, and the outer edge of a portion that forms a current path from the second joint to the wiring joint is defined as the second outer edge; a direction perpendicular to the plate surface of the plate member and a direction perpendicular to the specified direction are defined as reference directions; and the first outer edge and the second outer edge are shaped to be inclined in different directions relative to the reference direction so as to suppress variations in the first impedance due to the current path from the first joint to the wiring joint, the second impedance due to the current path from the second joint to the wiring joint, and the third impedance due to the current path from the third joint to the wiring joint.

[0010] In other words, in the semiconductor device, the outer edge of the plate member is inclined so as to suppress variations in the first, second, and third impedances. In the following description, the current path from the first joint to the wiring joint is referred to as the first current path, the current path from the second joint to the wiring joint is referred to as the second current path, and the current path from the third joint to the wiring joint is referred to as the third current path.

[0011] In the semiconductor device described above, because the wiring junction is located between the first junction and the second junction in the predetermined direction, the length of the third current path is likely to be shorter than the first current path and the second current path. In other words, the third impedance is likely to be smaller than the first impedance and the second impedance. In consideration of this, the outer edge of the plate member in the semiconductor device is inclined, so the first current path and the second current path are shorter than when the outer edge is not inclined. Therefore, the variation in each impedance is suppressed, and imbalances in the magnitude of the currents flowing through the at least three semiconductor elements are suppressed.

[0012] Another aspect of the disclosure is a semiconductor device comprising: a substrate having first wiring and second wiring; a plurality of semiconductor elements each having a first main electrode and a second main electrode provided on a surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member which shorts the second main electrodes of the plurality of semiconductor elements to each other and is bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction, wherein of the three semiconductor elements, the semiconductor elements located at both ends are referred to as a first semiconductor element and a second semiconductor element, and the semiconductor element located between the first semiconductor element and the second semiconductor element is referred to as a third semiconductor element, and the plate member has a first bonding portion which is a bonding portion with the first semiconductor element, a second bonding portion which is a bonding portion with the second semiconductor element, a third bonding portion which is a bonding portion with the third semiconductor element, and a wiring bonding portion which is bonded to the second wiring, and the position of the wiring bonding portion in the predetermined direction is between the first bonding portion and the second bonding portion, A through hole is formed in a portion of the plate member that forms the current path from the third junction to the wiring junction so as to suppress variations among the first impedance due to the current path from the first junction to the wiring junction, the second impedance due to the current path from the second junction to the wiring junction, and the third impedance due to the current path from the third junction to the wiring junction.

[0013] In other words, in the semiconductor device, the plate member has a through hole formed therein to suppress variations in the first, second, and third impedances. Here, in the semiconductor device, the wiring junction in the predetermined direction is located between the first junction and the second junction. Therefore, the length of the third current path tends to be shorter than the first and second current paths, and the third impedance tends to be smaller than the first and second impedances.

[0014] In consideration of this, the semiconductor device has a through hole formed in the plate member, and the through hole is located on the current path from the third joint to the wiring joint. Therefore, the cross-sectional area of ​​the plate member forming the third current path is smaller than when no through hole is formed. In other words, the third impedance is increased. Therefore, the variation in each impedance is suppressed, and imbalances in the magnitude of the current flowing through each element are suppressed for at least three semiconductor elements.

[0015] Another aspect of the disclosure is a semiconductor device comprising: a substrate having first wiring and second wiring; a plurality of semiconductor elements each having a first main electrode and a second main electrode provided on a surface opposite to the first main electrode, the first main electrode being joined to the first wiring; and a metal plate member that shorts the second main electrodes of the plurality of semiconductor elements to each other and is joined to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction, and of the three semiconductor elements, the semiconductor elements located at both ends are referred to as a first semiconductor element and a second semiconductor element, and the semiconductor element located between the first semiconductor element and the second semiconductor element is referred to as a third semiconductor element, and the plate member has a first joint that is a joint with the first semiconductor element, a second joint that is a joint with the second semiconductor element, a third joint that is a joint with the third semiconductor element, and a wiring joint that is joined to the second wiring, Furthermore, the plate member has a first extension portion that forms a current path from the first joint to the wiring joint, a second extension portion that forms a current path from the second joint to the wiring joint, and a third extension portion that forms a current path from the third joint to the wiring joint, and the position of the wiring joint in the specified direction is between the first joint and the second joint, and the extension plate width of the third extension portion is set smaller than both the extension plate width of the first extension portion and the extension plate width of the second extension portion so as to suppress variations among the first impedance due to the current path from the first joint to the wiring joint, the second impedance due to the current path from the second junction to the wiring joint, and the third impedance due to the current path from the third junction to the wiring joint.

[0016] In other words, in the semiconductor device, the extension plate width of the third extension portion is set small so as to suppress variations in the first, second, and third impedances. Here, in the semiconductor device, the position of the wiring junction in the predetermined direction is between the first junction and the second junction. Therefore, the length of the third current path tends to be shorter than the first current path and the second current path, and the third impedance tends to be smaller than the first impedance and the second impedance.

[0017] In consideration of this point, in the semiconductor device, the extension plate width of the third extension portion is set to be small. Therefore, the cross-sectional area of ​​the third extension portion is smaller than when the three extension portions are formed with the same extension plate width. In other words, the third impedance is increased. Therefore, the variation in each impedance is suppressed, and imbalance in the magnitude of the current flowing through each element is suppressed for at least three semiconductor elements.

[0018] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings.

[0019] 1 is a diagram illustrating a circuit configuration of a power conversion device to which the semiconductor device according to the first embodiment is applied; FIG. 2 is a diagram illustrating an equivalent circuit diagram of upper and lower arm circuits provided by the semiconductor device; FIG. 3 is a plan view of the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view illustrating a connection structure of a clip, a semiconductor element, and a substrate in the semiconductor device according to the first embodiment; FIG. 5 is a plan view illustrating the shape of the clip according to the first embodiment; FIG. 6 is a plan view illustrating the function of each part of the clip according to the first embodiment; FIG. 7 is a diagram for illustrating oscillation in a parallel circuit; FIG. 8 is a graph illustrating test results of a semiconductor device as a comparative example; FIG. 9 is a cross-sectional view illustrating the shape of a clip in a semiconductor device according to a modification of the first embodiment; FIG. 10 is a plan view illustrating an example of a connection structure between a clip and a semiconductor element in a semiconductor device according to a modification of the second embodiment; FIG. 11 is a plan view of a semiconductor device according to a third embodiment; FIG. 12 is a plan view of a semiconductor device according to a fourth embodiment; FIG. 13 is a plan view of a semiconductor device according to a fifth embodiment; and FIG. 14 is a plan view of a semiconductor device according to a sixth embodiment.

[0020] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment described previously can be applied to the remaining portions of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can also be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination. Note that the term "A and / or B" means at least one of A and B. In other words, it may include only A, only B, or both A and B.

[0021] The semiconductor device and the semiconductor module including the semiconductor device according to the present embodiment are applied to, for example, a power conversion device for a mobile body using a rotating electric machine as a drive source. The mobile body may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, construction machinery, or agricultural machinery. An example of application to a vehicle will be described below.

[0022] First Embodiment First, a schematic configuration of a vehicle drive system will be described with reference to FIG.

[0023] <Vehicle Drive System> As shown in FIG. 1 , a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

[0024] The DC power supply 2 is a DC voltage source formed by a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0025] <Power Conversion Device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6, which is a power conversion circuit.

[0026] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0027] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts DC voltage into three-phase AC voltage under switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage under switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

[0028] The inverter 6 is configured to include upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side.

[0029] The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. Of the upper and lower arm circuits 9, the U-phase upper and lower arm circuit 9U is connected to the U-phase winding 3a via a corresponding output line 10. The V-phase upper and lower arm circuit 9V is connected to the V-phase winding 3a via a corresponding output line 10. The W-phase upper and lower arm circuit 9W is connected to the W-phase winding 3a via a corresponding output line 10. At least a portion of each of the P line 7, the N line 8, and the output lines 10 is formed of a conductive member such as a bus bar.

[0030] The inverter 6 has six arms. Each arm is configured with a switching element. The number of switching elements constituting each arm is not particularly limited. It may be one or more. In the case of more than one, the multiple switching elements connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage). In the example shown in FIGS. 2 and 3, one arm is configured with three switching elements connected in parallel.

[0031] In this embodiment, an n-channel MOSFET 11 is used as the switching element constituting each arm. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0032] A freewheeling diode 12 is connected in antiparallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0033] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0034] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage, for example, into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

[0035] The power conversion device 4 may include a drive circuit for the switching elements that constitute the inverter 6 and the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0036] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a host ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0037] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0038] <Semiconductor Module> The semiconductor device 21 shown in Fig. 3 is incorporated into a semiconductor module. The semiconductor module may include the semiconductor device 21, a housing 22 and a cooler 23 as shown in Fig. 9. The semiconductor module, together with a capacitor device that provides the smoothing capacitor 5, an input terminal block, an output terminal block, and the like, constitutes the power conversion device 4. The semiconductor module may be housed in a case of the power conversion device 4 together with other elements such as the capacitor device.

[0039] In the following, the thickness direction of the substrate is referred to as the Z direction, and one direction perpendicular to the Z direction is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction may be simply referred to as the planar view.

[0040] The semiconductor device 21 is arranged on one surface of the cooler 23 in the Z direction. The semiconductor device 21 provides at least one arm of the inverter 6, which is a power conversion circuit. Each of the semiconductor devices 21 illustrated in FIG. 3 provides the upper and lower arm circuits 9 for one phase. The semiconductor module includes three semiconductor devices 21 to provide the inverter 6. The three semiconductor devices 21 are arranged on the same surface of the cooler 23 and are lined up in the X direction. Each of the semiconductor devices 21 is fixed to the cooler 23.

[0041] One of the semiconductor devices 21, a semiconductor device 21U, provides the U-phase upper and lower arm circuit 9U. Another of the semiconductor devices 21, a semiconductor device 21V, provides the V-phase upper and lower arm circuit 9V. Another of the semiconductor devices 21, a semiconductor device 21W, provides the W-phase upper and lower arm circuit 9W.

[0042] The housing 22 is formed using an electrically insulating material such as resin. The housing 22 may be, for example, a resin molded body. The housing 22 may hold some of the components of the semiconductor device 21. Some of the components of the semiconductor device 21 may be integrally molded with the housing 22 as an insert part. The housing 22 may be fixed to the cooler 23. The housing 22 may be fixed to the case of the power conversion device 4 together with the cooler 23. The housing 22 may be arranged on one side of the cooler 23 to provide a storage space for the semiconductor device 21 together with the cooler 23. A sealant 90 (see FIG. 9 ) that seals the semiconductor element 30 and the like may be arranged in the storage space formed by the housing 22 and the cooler 23. The sealant 90 is, for example, a gel or a potting resin.

[0043] The semiconductor module may include a circuit board (not shown). The drive circuit described above is formed on the circuit board. The circuit board is arranged above the semiconductor device 21 in the Z direction. The semiconductor module may also include a cover that provides a housing together with the housing 22 and the cooler 23. The cover is arranged on the opposite side of the semiconductor device 21 from the cooler 23. The cover may be arranged to cover the three semiconductor devices 21 as a whole.

[0044] <Semiconductor Device> As described above, the semiconductor device 21 may provide one phase of the upper and lower arm circuits 9. As illustrated in FIG. 3 , the semiconductor device 21 may include a semiconductor element 30, a substrate 40, a clip 50, and an external connection terminal 60.

[0045] The semiconductor element 30 is a vertical element formed on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor having a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ ), diamond. The semiconductor element 30 may be called a power element, a semiconductor chip, or the like.

[0046] The vertical element is configured to pass a main current in the thickness direction of the semiconductor element 30 (semiconductor substrate). The semiconductor element 30 is disposed so that its thickness direction is substantially parallel to the Z direction. The semiconductor element 30 has main electrodes on both sides in the thickness direction. The semiconductor element 30 of this embodiment is formed by forming an n-channel MOSFET 11 as a vertical element on a semiconductor substrate made of SiC. As shown in FIG. 4 , the semiconductor element 30 has, as main electrodes, a drain electrode 31 on its lower surface facing the substrate 40 and a source electrode 32 on its upper surface opposite the lower surface. The drain electrode 31 corresponds to a first main electrode, and the source electrode 32 corresponds to a second main electrode.

[0047] When the MOSFET 11 is turned on, a current (main current) flows between the main electrodes, that is, between the drain electrode 31 and the source electrode 32. If the diode 12 is a parasitic diode, the source electrode 32 also serves as the anode electrode, and the drain electrode 31 also serves as the cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 31 is the main electrode on the high potential side, and the source electrode 32 is the main electrode on the low potential side. The drain electrode 31 is formed over almost the entire bottom surface. The source electrode 32 is formed on a portion of the top surface.

[0048] The semiconductor element 30 has a generally rectangular shape in plan view. The semiconductor element 30 has, on its upper surface, pads 33 that are electrodes for signals. The pads 33 are formed at positions on the upper surface that are different from the source electrodes 32. The pads 33 include at least a gate pad.

[0049] The plurality of semiconductor elements 30 include a semiconductor element 30H constituting the upper arm 9H and a semiconductor element 30L constituting the lower arm 9L. The semiconductor element 30H is sometimes referred to as an upper arm element. The semiconductor element 30L is sometimes referred to as a lower arm element. For example, the semiconductor elements 30H and 30L may have a common configuration. In this embodiment, the semiconductor element 30H corresponds to the semiconductor element group A, and the semiconductor element 30L corresponds to the semiconductor element group B. Of the plurality of semiconductor elements 30, the semiconductor elements belonging to the semiconductor element group A include a first semiconductor element 30A1, a second semiconductor element 30A2, and a third semiconductor element 30A3. Of the plurality of semiconductor elements 30, the semiconductor elements belonging to the semiconductor element group B include a first semiconductor element 30B1, a second semiconductor element 30B2, and a third semiconductor element 30B3.

[0050] The pad 33 of the semiconductor element 30H is provided near the end on the P terminal 611 and N terminal 612 side in the Y direction. The pad 33 of the semiconductor element 30L is provided near the end on the O terminal 613 side in the Y direction. The semiconductor elements 30H and 30L are arranged at approximately the same position as each other in the Z direction. The semiconductor elements 30H and 30L are arranged in the same orientation so that the drain electrodes 31 face the substrate 40 side.

[0051] The number of each of the semiconductor elements 30H, 30L is not particularly limited. There may be one of each, or multiple of each. In the example shown in FIGS. 2 and 3 , the semiconductor element 30 includes three each of the semiconductor elements 30H, 30L. The three semiconductor elements 30H are connected in parallel to provide the MOSFET 11 of the upper arm 9H of one phase. The three semiconductor elements 30L are connected in parallel to provide the MOSFET 11 of the lower arm 9L of one phase. The three semiconductor elements 30H are arranged in a row in the X direction. The three semiconductor elements 30L are arranged in a row in the X direction.

[0052] The substrate 40 contains all of the semiconductor elements 30 (30H, 30L) in a plan view. The substrate 40 is disposed on the drain electrode 31 side of the semiconductor elements 30. The substrate 40 is electrically connected to the drain electrode 31 and provides a wiring function. The substrate 40 may also be referred to as a wiring board, a printed circuit board, or the like.

[0053] The substrate 40 has an insulating base material and conductors disposed on the insulating base material. The insulating base material is formed using an electrically insulating material such as ceramic or resin. The conductors are formed using a metal with good electrical and thermal conductivity, such as Cu or Al. The patterned conductors provide wiring, i.e., circuits. The conductors include P wiring 421, N wiring 422, O wiring 423, and signal wiring 425 and 426. Each wiring is electrically separated by a predetermined interval (gap).

[0054] The P wiring 421 is connected to the drain electrode 31 of the semiconductor element 30H. The P wiring 421 is connected to the P terminal 611. The P wiring 421 electrically connects the drain electrode 31 of the semiconductor element 30H to the P terminal 611. The P wiring 421 corresponds to the first wiring, and may be referred to as a positive wiring, a high-potential power supply wiring, or the like.

[0055] The N wiring 422 is connected to the N terminal 612. The source electrode 32 of the semiconductor element 30L is electrically connected to the N wiring 422 via the clip 50L. The N wiring 422 electrically connects the source electrode 32 of the semiconductor element 30L and the N terminal 612. The N wiring 422 may be referred to as a negative wiring, a low-potential power supply wiring, or the like.

[0056] The O wiring 423 is connected to the drain electrode 31 of the semiconductor element 30L. The O wiring 423 is connected to the O terminal 613. The source electrode 32 of the semiconductor element 30H is electrically connected to the O wiring 423 via the clip 50H. The O wiring 423 electrically connects the source electrode 32 of the semiconductor element 30H, the drain electrode 31 of the semiconductor element 30L, and the O terminal 613. The O wiring 423 corresponds to the second wiring, and may be referred to as an output wiring, etc.

[0057] The signal wiring 425 electrically connects the pad 33 of the semiconductor element 30H to the corresponding signal terminal 62 (see FIG. 9 ). The signal wiring 425 is connected to the pad 33 and the signal terminal 62 via a bonding wire 80. The signal wiring 426 electrically connects the pad 33 of the semiconductor element 30L to the corresponding signal terminal (not shown). The signal wiring 426 is connected to the pad 33 and the signal terminal via a bonding wire 80.

[0058] The clip 50 may also be referred to as a bridging member, relay member, metal bridge, etc. The clip 50 is formed from a plate material whose base material is a metal with good conductivity, such as Cu or a Cu alloy, and corresponds to a plate member. The clip 50 may be formed by punching and pressing a metal plate of a predetermined thickness. The clip 50 may also be formed using a profile material with partially different thicknesses. The clip 50 may also be formed by joining multiple members.

[0059] The clip 50 may have a film applied to the surface of a base material by surface treatment. The clip 50 may have a plated film of Ni, Au, or the like on its surface. The clip 50 may have a Ni plated film containing P formed on the base material. The NiP film is formed by electroless plating. Ag, Au, Al, Mg, or the like may be used as the base material instead of Cu. Sn, Ag, or the like may be used as the film applied to the base material instead of Ni or Au.

[0060] The clips 50 include a clip 50H connected to the semiconductor element 30H and a clip 50L connected to the semiconductor element 30L. The clip 50H electrically connects the source electrode 32 of the semiconductor element 30H to the O wiring 423. The clip 50H also electrically connects the source electrodes 32 of the multiple semiconductor elements 30H to each other. The clip 50L electrically connects the source electrode 32 of the semiconductor element 30L to the N wiring 422. The clip 50L also electrically connects the source electrodes 32 of the multiple semiconductor elements 30L to each other. The semiconductor device 21 includes one clip 50H and one clip 50L.

[0061] The external connection terminals 60 are terminals for electrically connecting the semiconductor device 21 to external devices. The external connection terminals 60 are formed using a metal material with good conductivity, such as copper. The external connection terminals 60 are, for example, plate material. The external connection terminals 60 include a main terminal 61 and a signal terminal 62 (see FIG. 9 ). The main terminal 61 is a terminal electrically connected to a main electrode of the semiconductor element 30. The signal terminal 62 is a terminal electrically connected to a pad 33 of the semiconductor element 30. The main terminals 61 include a P terminal 611 and an N terminal 612, which are power supply terminals, and an O terminal 613.

[0062] The P terminal 611 is an external connection terminal 60 electrically connected to the P line 7 described above. The P terminal 611 is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 611 may be referred to as a positive terminal, a high-potential power supply terminal, or the like. The P terminal 611 is connected to the P wiring 421. The P terminal 611 is electrically connected to the drain electrode 31 of the semiconductor element 30H constituting the upper arm 9H via the P wiring 421. The smoothing capacitor 5 is connected to the P terminal 611, for example, via a bus bar or the like.

[0063] The N terminal 612 is an external connection terminal 60 electrically connected to the above-described N line 8. The N terminal 612 is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 612 may also be referred to as a negative terminal, a low-potential power supply terminal, or the like. The N terminal 612 is connected to the N wiring 422. The N terminal 612 is electrically connected to the source electrode 32 of the semiconductor element 30L constituting the lower arm 9L via the N wiring 422 and a clip 50L. The smoothing capacitor 5 is connected to the N terminal 612, for example, via a bus bar or the like.

[0064] The O terminal 613 is an external connection terminal 60 electrically connected to the output line 10. The O terminal 613 is electrically connected to the winding 3a of the opposing phase of the motor generator 3. The O terminal 613 may also be referred to as an output terminal, an AC terminal, etc. The semiconductor module includes, as the O terminals 613, a U-phase O terminal, a V-phase O terminal, and a W-phase O terminal.

[0065] The O terminal 613 is connected to the O wiring 423. The O terminal 613 is electrically connected to the drain electrode 31 of the semiconductor element 30L constituting the lower arm 9L via the O wiring 423. The O terminal 613 is electrically connected to the source electrode 32 of the semiconductor element 30H constituting the upper arm 9H via the O wiring 423 and a clip 50H. The O terminal 613 is connected to the motor generator 3 via, for example, a bus bar.

[0066] The signal terminal 62 electrically connects the semiconductor element 30 to a circuit board (not shown). The signal terminal 62 is electrically connected to the pad 33 of the semiconductor element 30 via a connecting member such as a bonding wire 80. The signal terminal 62 may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 30. The signal terminal 62 may include a terminal for detecting the source potential of the semiconductor element 30. The signal terminal 62 may include a terminal for detecting the drain potential of the semiconductor element 30. The signal terminal 62 may include a terminal for detecting the temperature of the semiconductor element 30.

[0067] <Clip> The shape and function of the clip 50 will be described in detail below. As shown in Fig. 4, the clip 50 has a plate portion 50C and a joint portion 50B. The plate portion 50C and the joint portion 50B are separate metal members that are joined together. The plate portion 50C and the joint portion 50B are joined by solder, for example. The plate portion 50C and the joint portion 50B may be made of the same material or different materials.

[0068] The bonding portion 50B includes a first bonding portion 50B1, a second bonding portion 50B2, a third bonding portion 50B3, and a wiring bonding portion 50B4, which will be described below. The first bonding portion 50B1 is bonded to the source electrode 32 of the first semiconductor element 30A1. The second bonding portion 50B2 is bonded to the source electrode 32 of the second semiconductor element 30A2. The third bonding portion 50B3 is bonded to the source electrode 32 of the third semiconductor element 30A3. The wiring bonding portion 50B4 is bonded to the O wiring 423. The semiconductor element 30 and the O wiring 423 are bonded to the bonding portion 50B by, for example, solder.

[0069] The joint portion 50B functions to space the plate portion 50C and the substrate 40 in the Z direction, and functions as a spacer that forms a space of a predetermined size between the plate portion 50C and the substrate 40. The dimension of the joint portion 50B in the Z direction is larger than the thickness dimension of the plate portion 50C.

[0070] As shown in FIG. 5 , the plate portion 50C has a short-circuit portion 50Ca and a connecting portion 50Cb. The short-circuit portion 50Ca is connected to the first bonding portion 50B1, the second bonding portion 50B2, and the third bonding portion 50B3, connecting these three bonding portions together. This electrically shorts the source electrodes 32 of the first semiconductor element 30A1, the second semiconductor element 30A2, and the third semiconductor element 30A3. The short-circuit portion 50Ca connects the three bonding portions together over the shortest distance. The short-circuit portion 50Ca has a shape that extends linearly in a predetermined direction (X direction) in which the three bonding portions are arranged. For example, the short-circuit portion 50Ca has a rectangular shape in a plan view. The short-circuit portion 50Ca is a rectangle whose longitudinal direction is the direction in which the three bonding portions are arranged (X direction). The short-circuit portion 50Ca corresponds to the dotted area in FIG. 6 .

[0071] The connecting portion 50Cb is the entire portion of the plate portion 50C other than the short-circuit portion 50Ca. The connecting portion 50Cb is a trapezoid extending from the short-circuit portion 50Ca toward the wiring joint portion 50B4. The base of this trapezoid is a pair of opposite sides extending in the X direction. Here, the direction in which the first semiconductor element 30A1, the second semiconductor element 30A2, and the third semiconductor element 30A3 are aligned in a row is the X direction (predetermined direction). The direction perpendicular to the plate surface of the plate portion 50C is the Z direction. The direction perpendicular to these X and Z directions corresponds to the reference direction (Y direction). The legs of the trapezoid are inclined with respect to the Y direction. The inclination angle θ of the legs with respect to the Y direction is greater than 0 degrees and less than 90 degrees. The legs of the trapezoid correspond to the first outer edge 50A1 and the second outer edge 50A2, which will be described later.

[0072] As shown in Fig. 6, the portion of the coupling portion 50Cb that forms the current path I1 from the first joint 50B1 to the wiring joint 50B4 corresponds to the first coupling portion 50C1. The portion of the coupling portion 50Cb that forms the current path I2 from the second joint 50B2 to the wiring joint 50B4 corresponds to the second coupling portion 50C2. The portion of the coupling portion 50Cb that forms the current path I3 from the third joint 50B3 to the wiring joint 50B4 is the shaded portion in Fig. 6 and corresponds to the third coupling portion 50C3.

[0073] Among the outer edges of the plate portion 50C, the outer edge of the first connecting portion 50C1 is a leg of the trapezoid described above and corresponds to the first outer edge 50A1. Among the outer edges of the plate portion 50C, the outer edge of the second connecting portion 50C2 is a leg of the trapezoid described above and corresponds to the second outer edge 50A2. The first outer edge 50A1 and the second outer edge 50A2 are inclined at a predetermined inclination angle θ with respect to the reference direction (Y direction). The inclination angle θ of the first outer edge 50A1 and the inclination angle θ of the second outer edge 50A2 are the same magnitude. However, the inclination directions are different from each other. In other words, the connecting portion 50Cb has a shape that is line-symmetrical with respect to the reference direction as the central axis. Furthermore, the plate portion 50C has a shape that is line-symmetrical with respect to the center line extending in the reference direction.

[0074] The impedance due to current path I1 is referred to as the first impedance. The impedance due to current path I2 is referred to as the second impedance. The impedance due to current path I3 is referred to as the third impedance. The length of current path I3 is longer than both current path I1 and current path I2. The lengths of current path I1 and current path I2 are the same.

[0075] <Oscillation in Parallel Connection> Figure 7 is an equivalent circuit diagram showing an example of the upper arm 9H. In Figure 7, two MOSFETs 11 are connected in parallel to form the upper arm 9H. The MOSFETs 11 have parasitic capacitances between the gate and source, between the gate and drain, and between the drain and source. The gate electrodes of the two MOSFETs 11 are connected to each other. A gate drive signal is input to each gate electrode from a common gate driver 14. The gate wiring connecting the gate driver 14 to each gate electrode has resistance Rg and parasitic inductance Lg. The source electrodes of the two MOSFETs 11 are connected to each other. The wiring connecting the source electrodes has parasitic inductance Ls.

[0076] In a parallel circuit of multiple MOSFETs 11, an oscillation circuit is formed by the parasitic capacitance of the MOSFETs 11, the parasitic inductance of the wiring, etc. Oscillation occurs when the input signal input from the gate driver 14 to the gate electrode and the feedback signal on the path via the parasitic capacitance, parasitic inductance, etc. are in phase and the gain is 0 dB or more, that is, when the feedback signal is amplified. Oscillation occurs when the resonance condition is met.

[0077] The parasitic inductance Ls between the source electrodes is large, while the parasitic inductance Lg of the gate wiring is small. To suppress oscillation, it is effective to reduce the parasitic inductance Ls between the source electrodes and / or increase the gate impedance. Therefore, in this embodiment, the clip 50 is used to reduce the parasitic inductance Ls between the source electrodes.

[0078] 2, the source electrodes 32 of the upper arm 9H are short-circuited by the clip 50H, thereby shortening the current path between the source electrodes. This reduces the parasitic inductance Ls between the source electrodes of the upper arm 9H. Similarly, the source electrodes 32 of the lower arm 9L are short-circuited by the clip 50L, thereby reducing the parasitic inductance Ls between the source electrodes of the lower arm 9L.

[0079] In particular, in the clip 50H of the upper arm 9H, the first joint portion 50B1, the second joint portion 50B2, and the third joint portion 50B3 are connected by the short-circuit portion 50Ca at the shortest distance, which further shortens the current path between the source electrodes in the upper arm 9H and promotes a reduction in the parasitic inductance Ls between the source electrodes.

[0080] For example, if the shape of the clip 50H were to be such that the short-circuiting portion 50Ca was eliminated, contrary to the present embodiment, the current path LS1x between the source electrodes of the first semiconductor element 30A1 and the second semiconductor element 30A2 would be the path shown by the dashed line in FIG. 6 . That is, this current path LS1x would pass through the first connecting portion 50C1 and the second connecting portion 50C2. In contrast, in this embodiment, since the short-circuiting portion 50Ca is provided, the current path LS1 between the source electrodes of the first semiconductor element 30A1 and the second semiconductor element 30A2 would be the path shown by the solid line in FIG. 6 . Therefore, the current path LS1 can be made shorter than the current path LS1x, which facilitates a reduction in the parasitic inductance Ls between the source electrodes.

[0081] <Current Imbalance> Even if the clip 50H has a shape that eliminates the first connecting portion 50C1 and the second connecting portion 50C2, contrary to the present embodiment, the above-described current path LS1 can be maintained and the parasitic inductance Ls can be reduced. That is, even if the clip 50H has a T-shape consisting of the short-circuiting portion 50Ca and the third connecting portion 50C3, the parasitic inductance Ls can be reduced. However, with such a T-shape, the aforementioned current paths I1 and I2 shown by the solid lines in FIG. 6 become longer, as shown by the current paths I1x and I2x shown by the dashed-dotted lines in FIG. 6 . As a result, the first impedance and the second impedance increase, and the difference between the first impedance and the third impedance and the difference between the second impedance and the third impedance also increase. In other words, an imbalance occurs in the magnitude of the currents flowing through the three semiconductor elements 30A1, 30A2, and 30A3.

[0082] FIG. 8 is a graph showing test results for a comparative semiconductor device using the T-shaped clip described above. In this test, a gate drive signal was input from a common gate driver 14 to each gate electrode of three semiconductor elements 30A1, 30A2, and 30A3 to turn them on. The vertical axis of FIG. 8 represents the magnitude of the drain-source current. The horizontal axis of FIG. 8 represents elapsed time. When the semiconductor elements 30A1, 30A2, and 30A3 are turned on at time Ton, the currents of the semiconductor elements 30A1, 30A2, and 30A3 increase. After that, as shown by the dashed-dotted line T2, if sufficient time has passed, the three current values ​​converge to the same value. However, as shown by the dashed-dotted line T1, if the time elapses too quickly, variations occur among the three current values. This variation is the current imbalance described above. This current imbalance immediately after turn-on is caused by variations in the first impedance, second impedance, and third impedance.

[0083] To address this issue of current imbalance, the semiconductor device 21 according to this embodiment employs the following structure. Specifically, the first outer edge 50A1 and the second outer edge 50A2 are shaped to incline in different directions relative to the reference direction (Y direction) so as to suppress variations in the first impedance, the second impedance, and the third impedance. Therefore, compared to the T-shape described above, variations in the impedances are suppressed, and current imbalance is suppressed.

[0084] Furthermore, in this embodiment, the clip 50H includes a short-circuiting portion 50Ca that shorts the source electrodes 32 (second main electrodes) of the semiconductor elements 30A1, 30A2, and 30A3 to each other. The short-circuiting portion 50Ca extends linearly in the predetermined direction (X direction) in which the semiconductor elements 30A1, 30A2, and 30A3 are arranged. This further shortens the current path between the source electrodes 32, thereby promoting a reduction in the parasitic inductance Ls between the source electrodes 32. As a result, the aforementioned oscillation caused by connecting the semiconductor elements 30A1, 30A2, and 30A3 in parallel can be suppressed.

[0085] (Modification) This modification is a modification based on the first embodiment, and the description of the first embodiment can be used.

[0086] In the first embodiment, the plate portion 50C and the joint portion 50B of the clip 50H are separate members that are joined together to form the clip 50H. However, as shown in Fig. 9, the plate portion 50C and the joint portion 50B may be integrally formed by bending a single member.

[0087] The clip 50H has an inclined portion 50F in addition to the plate portion 50C and the joint portion 50B. The inclined portion 50F rises obliquely upward from the joint portion 50B. The inclined portion 50F has an inclination such that the further away from the joint portion 50B in the Y direction the more it is separated from the joint portion 50B (semiconductor element 30) in the Z direction.

[0088] Second Embodiment In this embodiment, the shape of the clip 50H according to the first embodiment is changed. That is, the shape of the clip 50H shown in Fig. 5 is changed to the shape shown in Fig. 10. The shape of the clip 50H according to this embodiment will be described below with reference to Fig. 10. Note that other structures of the clip shape are the same in this embodiment as in the first embodiment.

[0089] The clip 50H has a first extending portion 50E1, a second extending portion 50E2, a third extending portion 50E3, a gathering portion 50E4, and a short-circuiting portion 50E5. The clip 50H further has a joint portion 50B similar to that shown in FIG.

[0090] The short-circuit portion 50E5 has the same shape and function as the short-circuit portion 50Ca shown in FIG. 5 . The short-circuit portion 50E5 is joined to the first joint portion 50B1, the second joint portion 50B2, and the third joint portion 50B3, connecting these three joint portions together. The short-circuit portion 50E5 has a shape that extends linearly in the X direction so as to connect the three joint portions over the shortest distance. The short-circuit portion 50E5 has a rectangular shape in plan view, with its longitudinal direction being the direction in which the three joint portions are lined up (the X direction).

[0091] The assembly portion 50E4 is connected to the ends of the first extending portion 50E1, the second extending portion 50E2, and the third extending portion 50E3. The assembly portion 50E4 is joined to the wiring joint portion 50B4. The assembly portion 50E4 electrically connects the first extending portion 50E1, the second extending portion 50E2, and the third extending portion 50E3 to the wiring joint portion 50B4.

[0092] The first extending portion 50E1 extends from a portion of the short-circuit portion 50E5 joined to the first joint portion 50B1 toward the assembly portion 50E4. The second extending portion 50E2 extends from a portion of the short-circuit portion 50E5 joined to the second joint portion 50B2 toward the assembly portion 50E4. The third extending portion 50E3 extends from a portion of the short-circuit portion 50E5 joined to the third joint portion 50B3 toward the assembly portion 50E4.

[0093] The first extending portion 50E1 forms a first current path that is a current path from the first joint portion 50B1 to the wiring joint portion 50B4. The second extending portion 50E2 forms a second current path that is a current path from the second joint portion 50B2 to the wiring joint portion 50B4. The third extending portion 50E3 forms a third current path that is a current path from the third joint portion 50B3 to the wiring joint portion 50B4. The impedance related to the first current path corresponds to the first impedance. The impedance related to the second current path corresponds to the second impedance. The impedance related to the third current path corresponds to the third impedance.

[0094] These extensions extend linearly with a constant extension width. The extension width refers to the length of the extensions in the direction perpendicular to the direction of extension and the plate thickness. The clip 50 shown in FIG. 10 has two through holes 50D1 and 50D2. The through hole 50D1 is a triangular hole surrounded by the short-circuit portion 50E5, the third extension portion 50E3, and the first extension portion 50E1. The through hole 50D2 is a triangular hole surrounded by the short-circuit portion 50E5, the third extension portion 50E3, and the second extension portion 50E2.

[0095] Of the outer edges of the first extending portion 50E1, the edge located opposite the third extending portion 50E3 corresponds to the first outer edge 50A1. Of the outer edges of the second extending portion 50E2, the edge located opposite the third extending portion 50E3 corresponds to the second outer edge 50A2. The first outer edge 50A1 and the second outer edge 50A2 are shaped to incline in different directions relative to the reference direction (Y direction) so as to suppress variations in the first impedance, second impedance, and third impedance. Therefore, similar to the first embodiment, variations in the impedances are suppressed, and current imbalance is suppressed.

[0096] Furthermore, in this embodiment, the clip 50H includes a short-circuiting portion 50E5 that short-circuits the source electrodes 32 (second main electrodes) of the semiconductor elements 30A1, 30A2, and 30A3. The short-circuiting portion 50E5 extends linearly in the predetermined direction (X direction) in which the semiconductor elements 30A1, 30A2, and 30A3 are arranged. Therefore, similar to the first embodiment, the current path between the source electrodes 32 is further shortened, promoting a reduction in the parasitic inductance Ls between the source electrodes 32. As a result, oscillation caused by connecting the semiconductor elements 30A1, 30A2, and 30A3 in parallel can be suppressed.

[0097] (Modification) As a modification of the clip 50H according to the second embodiment, as shown in FIG. 11 , the short-circuiting portion 50E5 may be eliminated. The clip 50H shown in FIG. 11 includes a first extending portion 50E1, a second extending portion 50E2, a third extending portion 50E3, a collection portion 50E4, and a joint portion 50B. The first outer edge 50A1 of the first extending portion 50E1 and the second outer edge 50A2 of the second extending portion 50E2 are shaped to slope in different directions relative to the reference direction (Y direction). Therefore, this modification also reduces variations in the impedances and current imbalances, similar to the second embodiment.

[0098] Third Embodiment In this embodiment, the shape of the clip 50L associated with the lower arm is changed as shown in Fig. 12 compared to the first embodiment shown in Fig. 3. The shape of the clip 50H associated with the upper arm is the same as that of the first embodiment. The clip 50H corresponds to the first plate member, and the clip 50L corresponds to the second plate member.

[0099] 12, the clip 50L has a plate portion 500C and a plurality of joint portions 500B. The plate portion 500C and the joint portions 500B are separate metal members that are joined together, similar to the first embodiment.

[0100] Three of the bonding portions 500B are bonded to the source electrode 32 of the semiconductor element. One of the bonding portions 500B is bonded to the N wiring 422 (third wiring). The semiconductor element 30 and the N wiring 422 are bonded to the bonding portions 500B by, for example, soldering. The bonding portions 500B function to space the plate portion 500C and the substrate 40 apart in the Z direction, and function as spacers that form a space of a predetermined size between the plate portion 500C and the substrate 40.

[0101] The plate portion 500C has a short-circuit portion 500Ca and a connecting portion 500Cb. The source electrodes of the first semiconductor element 30B1, the second semiconductor element 30B2, and the third conductor element 30B3, which belong to semiconductor element group B, are short-circuited to each other by the short-circuit portion 500Ca. The short-circuit portion 50Ca connects the three semiconductor elements belonging to semiconductor element group B over the shortest distance. The short-circuit portion 500Ca has a shape that extends linearly in a predetermined direction (X direction) in which the three semiconductor elements are arranged. For example, the short-circuit portion 500Ca has a rectangular shape in a plan view. The short-circuit portion 500Ca is a rectangle whose longitudinal direction is the direction in which the three semiconductor elements are arranged (X direction).

[0102] The connecting portion 500Cb is the entire portion of the plate portion 500C other than the short-circuit portion 500Ca. The connecting portion 500Cb is formed in the shape of two trapezoids extending from the short-circuit portion 500Ca toward the N wiring 422. The bases of these trapezoids are a pair of opposite sides extending in the X direction. Here, the direction in which the first semiconductor element 30B1, the second semiconductor element 30B2, and the third semiconductor element 30B3 are aligned in a row is the X direction (predetermined direction). The direction perpendicular to the plate surface of the plate portion 500C is the Z direction. The direction perpendicular to these X and Z directions corresponds to the reference direction (Y direction).

[0103] One trapezoid includes a leg that faces the first outer edge 50A1 of the clip 50H. This leg corresponds to the first opposing outer edge 500A1. The first opposing outer edge 500A1 is inclined with respect to the Y direction. The other leg included in this trapezoid extends along the Y direction. One trapezoid includes a leg that faces the second outer edge 50A2 of the clip 50H. This leg corresponds to the second opposing outer edge 500A2. The second opposing outer edge 500A2 is inclined with respect to the Y direction. The other leg included in each of these trapezoids extends along the Y direction.

[0104] The inclination angle θ1 of the first opposing outer edge 500A1 and the second opposing outer edge 500A2 is greater than 0 degrees and less than 90 degrees. The inclination angle θ1 of the first opposing outer edge 500A1 and the inclination angle θ2 of the second opposing outer edge 500A2 are the same. Of the legs included in the trapezoid, the legs facing the first opposing outer edge 500A1 and the second opposing outer edge 500A2 extend in the Y direction. However, the inclination directions are different from each other. In other words, the connecting portion 500Cb has a shape that is line-symmetrical with the reference direction as the central axis. Furthermore, the plate portion 500C has a shape that is line-symmetrical with respect to the center line extending in the reference direction.

[0105] In this embodiment, the clip 50L, which is the second plate member, shorts the source electrodes of the semiconductor elements B and is joined to the N wiring 422, which is the third wiring. The clip 50L also has a shape having a first opposing outer edge 500A1 and a second opposing outer edge 500A2. The first opposing outer edge 500A1 faces the first outer edge 50A1 of the clip 50H and is inclined in the same direction as the first outer edge 50A1. The second opposing outer edge 500A2 faces the second outer edge 50A2 of the clip 50H and is inclined in the same direction as the second outer edge 50A2.

[0106] The direction of the current flowing through the first opposing outer edge 500A1 is opposite to the direction of the current flowing through the first outer edge 50A1. The direction of the current flowing through the second opposing outer edge 500A2 is opposite to the direction of the current flowing through the second outer edge 50A2.

[0107] As described above, according to this embodiment, the magnetic field generated by the current flowing through clip 50H along first opposing outer edge 500A1 and the magnetic field generated by the current flowing through clip 50L along first opposing outer edge 500A1 act to cancel each other out. Similarly, the magnetic field generated by the current flowing through clip 50H along second opposing outer edge 500A2 and the magnetic field generated by the current flowing through clip 50L along second opposing outer edge 500A2 act to cancel each other out. Therefore, the impedance of clip 50H and the impedance of clip 50L can be reduced.

[0108] Fourth Embodiment In this embodiment, the shape of the clip 50H associated with the upper arm is changed as shown in Fig. 13 compared to the first embodiment shown in Fig. 3. Other structures of the semiconductor device 21 in this embodiment are similar to those in the first embodiment.

[0109] As shown in Figure 13, the clip 50H has a plate portion 50C and multiple joint portions 50B. Similar to the first embodiment, the plate portion 50C and the joint portions 50B are separate metal members that are joined together. Three joint portions 50B1, 50B2, and 50B3 are joined to the source electrode 32 of the semiconductor element. One joint portion 50B4 is joined to the O wiring 423. The structure of these joint portions is similar to that of the first embodiment.

[0110] The connecting portion 50Cb includes a first connecting portion 50C1, a second connecting portion 50C2, and a third connecting portion 50C3. The first connecting portion 50C1 forms a first current path I1 from the first joint portion 50B1 to the wiring joint portion 50B4. The second connecting portion 50C2 forms a second current path I2 from the second joint portion 50B2 to the wiring joint portion 50B4. In this embodiment, the first outer edge 50A1 and the second outer edge 50A2 extend along the Y direction. In other words, the clip 50H according to this embodiment does not include a structure that tilts the first outer edge 50A1 and the second outer edge 50A2.

[0111] The third connecting portion 50C3 forms a third current path I3 from the third joint portion 50B3 to the wiring joint portion 50B4. A through hole 50D0 is formed in the third connecting portion 50C3. The through hole 50D0 has a rectangular shape in a plan view. The width of the through hole 50D0 in the X direction may be larger or smaller than that of the third joint portion 50B3. In addition, the width of the through hole 50D0 in the X direction is set smaller than the width dimension of the third semiconductor element 30A3.

[0112] Due to the presence of the through hole 50D0, the current path I3 in the third coupling portion 50C3 is bifurcated as shown by the arrows in Fig. 13. The through hole 50D0 is located in a straight line region connecting the third joint portion 50B3 and the wiring joint portion 50B4.

[0113] In the semiconductor device according to this embodiment, a through hole 50D0 is formed in the clip 50H to suppress variations in the first, second, and third impedances. The wiring joint 50B4 is located between the first joint 50B1 and the second joint 50B2 in the predetermined direction (X direction). Therefore, the length of the third current path I3 tends to be shorter than the first current path I1 and the second current path I2, and the third impedance tends to be smaller than the first impedance and the second impedance.

[0114] In consideration of this point, in this embodiment, a through hole 50D0 is formed in the clip 50H, and the position of the through hole 50D0 is on the third current path I3. Therefore, compared to when the through hole 50D0 is not formed, the cross-sectional area of ​​the third coupling portion 50C3 is smaller and the third impedance is larger. Therefore, the variation in each impedance is suppressed, and imbalance in the magnitude of the current flowing through each of the at least three semiconductor elements 30A1, 30A2, and 30A3 is suppressed.

[0115] Fifth Embodiment In this embodiment, the shape of the clip 50H associated with the upper arm is changed as shown in Fig. 14 compared to the second embodiment shown in Fig. 10. Other structures of the semiconductor device 21 in this embodiment are similar to those in the second embodiment.

[0116] 14, the clip 50H has a first extending portion 50E1, a second extending portion 50E2, a third extending portion 50E3, a gathering portion 50E4, a short-circuiting portion 50E5, and a joint portion 50B. The structures of the short-circuiting portion 50E5 and the joint portion are similar to those of the second embodiment.

[0117] The assembly portion 50E4 is connected to the ends of the first extending portion 50E1, the second extending portion 50E2, and the third extending portion 50E3, and is joined to the wiring joint portion 50B4. The assembly portion 50E4 electrically connects the first extending portion 50E1, the second extending portion 50E2, and the third extending portion 50E3 to the wiring joint portion 50B4. The assembly portion 50E4 has a rectangular shape in a plan view, with its longitudinal direction aligned in the X direction.

[0118] The first extending portion 50E1 extends in the Y direction from the portion of the short-circuit portion 50E5 joined to the first joint portion 50B1 to the assembly portion 50E4. The second extending portion 50E2 extends in the Y direction from the portion of the short-circuit portion 50E5 joined to the second joint portion 50B2 to the assembly portion 50E4. The third extending portion 50E3 extends in the Y direction from the portion of the short-circuit portion 50E5 joined to the third joint portion 50B3 to the assembly portion 50E4.

[0119] The first extending portion 50E1 forms a first current path I1 extending from the first joint 50B1 to the wiring joint 50B4. The second extending portion 50E2 forms a second current path I2 extending from the second joint 50B2 to the wiring joint 50B4. The third extending portion 50E3 forms a third current path I3 extending from the third joint 50B3 to the wiring joint 50B4. The impedance associated with the first current path I1 corresponds to the first impedance. The impedance associated with the second current path I2 corresponds to the second impedance. The impedance associated with the third current path I3 corresponds to the third impedance.

[0120] These extension portions have a shape that extends linearly with a constant extension plate width. The extension plate width refers to the length in the direction in which the extension portion extends and in the direction perpendicular to the plate thickness direction. The extension plate width A3 of the third extension portion 50E3 is set smaller than the extension plate width A1 of the first extension portion 50E1. The extension plate width A3 of the third extension portion 50E3 is set smaller than the extension plate width A2 of the second extension portion 50E2. The extension plate width A1 and the extension plate width A2 are set to be the same size.

[0121] 14 has two through holes 50D1 and 50D2. The through hole 50D1 is a rectangular hole surrounded by the collection portion 50E4, the short-circuit portion 50E5, the third extending portion 50E3, and the first extending portion 50E1. The through hole 50D2 is a rectangular hole surrounded by the collection portion 50E4, the short-circuit portion 50E5, the third extending portion 50E3, and the second extending portion 50E2.

[0122] In this embodiment, the first outer edge 50A1 and the second outer edge 50A2 have a shape that extends along the Y direction. In other words, the clip 50H according to this embodiment does not have a structure that inclines the first outer edge 50A1 and the second outer edge 50A2.

[0123] In the semiconductor device according to this embodiment, the extension width A3 of the third extension portion 50E3 is set smaller than the extension widths A1 and A2 of the other extension portions 50E3 so as to suppress variations in the first, second, and third impedances. In the semiconductor device according to this embodiment, the wiring joint 50B4 is located between the first joint 50B1 and the second joint 50B2 in the predetermined direction (X direction). Therefore, the length of the third current path I3 tends to be shorter than the first current path I1 and the second current path I2, and the third impedance tends to be smaller than the first impedance and the second impedance.

[0124] In consideration of this point, in the semiconductor device according to this embodiment, the extension width A3 of the third extension portion 50E3 is set small. Therefore, compared to when the three extension portions 50E1, 50E2, and 50E3 are formed with the same extension width, the cross-sectional area of ​​the third extension portion 50E3 is smaller and the third impedance is larger. Therefore, the variation in each impedance is suppressed, and imbalance in the magnitude of the current flowing through each of the at least three semiconductor elements 30A1, 30A2, and 30A3 is suppressed.

[0125] Sixth Embodiment As shown in Fig. 15, a clip 50H according to this embodiment has a shape that combines the shape of the clip 50H shown in Fig. 5 and the shape of the clip 50H shown in Fig. 13. Other structures of the semiconductor device 21 in this embodiment are similar to those in the first embodiment.

[0126] As shown in Figure 15, a clip 50H according to this embodiment has a plate portion 50C and a joint portion 50B. The structure of the joint portion 50B is the same as that of the first embodiment. The plate portion 50C has a short-circuit portion 50Ca and a connecting portion 50Cb. The structure of the short-circuit portion 50Ca is the same as that of the first embodiment.

[0127] The connecting portion 50Cb is the entire portion of the plate portion 50C except for the short-circuit portion 50Ca. The connecting portion 50Cb according to this embodiment has a shape similar to that of the connecting portion 50Cb shown in FIG. 5 but with a through-hole 50D0 shown in FIG. 13. That is, the connecting portion 50Cb has a first connecting portion 50C1, a second connecting portion 50C2, and a third connecting portion 50C3. The through-hole 50D0 is formed in the third connecting portion 50C3.

[0128] In the clip 50H according to this embodiment, similarly to the first embodiment, the first outer edge 50A1 and the second outer edge 50A2 are shaped to be inclined in different directions relative to the Y direction so as to suppress variations in impedance. Therefore, this embodiment also suppresses variations in impedance and suppresses current imbalance.

[0129] Furthermore, in this embodiment, as in the fourth embodiment, a through hole 50D0 is formed in the clip 50H, and the through hole 50D0 is located on the third current path I3. This reduces the cross-sectional area of ​​the third coupling portion 50C3, and increases the third impedance. This reduces the variation in the impedances, and prevents imbalances in the magnitude of the currents flowing through at least three semiconductor elements 30A1, 30A2, and 30A3.

[0130] Furthermore, in this embodiment, similarly to the first embodiment, clip 50H includes short-circuiting portion 50Ca that short-circuits source electrodes 32 of multiple semiconductor elements 30A1, 30A2, and 30A3 together, thereby further shortening the current path between source electrodes 32 and promoting reduction in parasitic inductance Ls between source electrodes 32, thereby promoting the suppression of oscillation described above.

[0131] (Other Embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0132] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0133] The vehicle drive system 1 is not limited to the above-described configuration. For example, although an example has been shown in which one motor generator 3 is provided, this is not limiting. Multiple motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, this is not limiting. For example, a configuration may be provided with multiple inverters. A configuration may be provided with at least one inverter and a converter. Or only a converter may be provided.

[0134] In the above embodiments, each of the upper arm and the lower arm includes three semiconductor elements arranged in a row in a predetermined direction (X direction). Alternatively, in addition to the semiconductor elements in the first row, a second row of multiple semiconductor elements may be included.

[0135] In each of the above embodiments, the Y-direction positions of the multiple semiconductor elements lined up in the X direction are the same. Alternatively, the Y-direction positions of the multiple semiconductor elements lined up in the X direction may be shifted. However, it is desirable that the Y-direction positions of at least a portion of the semiconductor elements overlap among the multiple semiconductor elements. In other words, it is desirable that the projection ranges of the multiple semiconductor elements in the X direction overlap with each other. Furthermore, when shifting the Y-direction positions as described above, the Y-direction positions of the multiple semiconductor elements may be shifted alternately and arranged in a staggered pattern in the X direction.

[0136] For example, when applying a staggered arrangement to the semiconductor elements shown in FIG. 3, the Y-direction positions of the first semiconductor element 30A1 and the second semiconductor element 30A2 may be shifted toward the O wiring 423 relative to the Y-direction position of the third semiconductor element 30A3. This can promote reductions in the first impedance and the second impedance and can promote suppression of variations in the first to third impedances. Furthermore, the hottest part of the semiconductor device 21 is the central portion (element center) of the semiconductor element. In light of this, the staggered arrangement as described above increases the separation distance between the element centers of adjacent semiconductor elements, which is also advantageous for reducing temperature.

[0137] The structure of the clip 50H relating to the upper arm described in each of the above embodiments may be applied to the structure of the clip 50L relating to the lower arm. The short-circuiting portions 50Ca, 500Ca, and 50E5 described in each of the above embodiments may be metal plates or bonding wires.

[0138] In the sixth embodiment, the shape of the clip 50H shown in Fig. 5 is a combination of the shape of the clip 50H shown in Fig. 13. Alternatively, the shape of the clip 50H shown in Fig. 5 may be a combination of the shape of the clip 50H shown in Fig. 14. Furthermore, the shapes of the clips according to the above-described embodiments may be appropriately combined.

[0139] (Disclosure of Technical Ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be described in a multiple dependent form, with the subsequent clause alternatively referring to the preceding clause. Furthermore, some clauses may be described in a multiple dependent form, with the subsequent clause referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0140] (Technical Idea 1) A substrate (40) having first wiring (421) and second wiring (423); a plurality of semiconductor elements (30) each having a first main electrode (31) and a second main electrode (32) provided on the surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member (50) short-circuiting the second main electrodes of the plurality of semiconductor elements and bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction (X), and of the three semiconductor elements, the semiconductor elements located at both ends are designated as a first semiconductor element (30A1) and a second semiconductor element (30A2), and the semiconductor element located between the first semiconductor element and the second semiconductor element is designated as a third semiconductor element (30A3), the plate member has a first bonding portion (50B1) which is a bonding portion with the first semiconductor element, a second bonding portion (50B2) which is a bonding portion with the second semiconductor element, a third bonding portion (50B3) which is a bonding portion with the third semiconductor element, and a wiring bonding portion (50B4) which is bonded to the second wiring, the position of the wiring bonding portion in the predetermined direction is between the first bonding portion and the second bonding portion, the outer edge of the plate member at a portion which forms a current path from the first bonding portion to the wiring bonding portion is defined as a first outer edge (50A1), and the outer edge of a portion which forms a current path from the second bonding portion to the wiring bonding portion is defined as a second outer edge (50A2), the direction perpendicular to the plate surface of the plate member and the predetermined direction is defined as a reference direction (Y), A semiconductor device, wherein the first outer edge and the second outer edge are shaped to be inclined in different directions relative to the reference direction so as to suppress variations in a first impedance due to a current path from the first junction to the wiring junction, a second impedance due to a current path from the second junction to the wiring junction, and a third impedance due to a current path from the third junction to the wiring junction.

[0141] (Technical Idea 2) A semiconductor device described in Technical Idea 1, in which a through hole (50D0) is formed in a portion of the plate member that forms a current path from the third junction to the wiring junction so as to suppress variations among a first impedance due to the current path from the first junction to the wiring junction, a second impedance due to the current path from the second junction to the wiring junction, and a third impedance due to the current path from the third junction to the wiring junction.

[0142] (Technical Idea 3) The plate member further has a first extension portion (50E1) that forms a current path from the first joint portion to the wiring joint portion, a second extension portion (50E2) that forms a current path from the second joint portion to the wiring joint portion, and a third extension portion (50E3) that forms a current path from the third joint portion to the wiring joint portion, and the extension plate width (A3) of the third extension portion is set smaller than both the extension plate width (A1) of the first extension portion and the extension plate width (A2) of the second extension portion so as to suppress variations in a first impedance due to the current path from the first joint portion to the wiring joint portion, a second impedance due to the current path from the second joint portion to the wiring joint portion, and a third impedance due to the current path from the third junction to the wiring joint portion. This is a semiconductor device described in Technical Idea 1 or 2.

[0143] (Technical Idea 4) A semiconductor device according to any one of Technical Ideas 1 to 3, comprising: a second plate member (50L) made of metal, separate from the first plate member (50H) which is the plate member; and a semiconductor element B group (30B1, 30B2, 30B3), separate from the three semiconductor elements, semiconductor element A group (30A1, 30A2, 30A3), including a plurality of semiconductor elements each having one electrode bonded to the second wiring; the substrate has third wiring (422); the second plate member short-circuits the other electrodes of the semiconductor element B group and is bonded to the third wiring; and the second plate member has a shape having a first opposing outer edge (500A1) which faces the first outer edge and is inclined in the same direction as the first outer edge, and a second opposing outer edge (500A2) which faces the second outer edge and is inclined in the same direction as the second outer edge.

[0144] (Technical Idea 5) A semiconductor device comprising: a substrate (40) having first wiring (421) and second wiring (423); a plurality of semiconductor elements (30) each having a first main electrode (31) and a second main electrode (32) provided on the surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member (50) short-circuiting the second main electrodes of the plurality of semiconductor elements and bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction (X), and of the three semiconductor elements, the semiconductor elements located at both ends are designated as a first semiconductor element (30A1) and a second semiconductor element (30A2), and the semiconductor element located between the first semiconductor element and the second semiconductor element is designated as a third semiconductor element (30A3), a second junction (50B2) that is a junction with the second semiconductor element; a third junction (50B3) that is a junction with the third semiconductor element; and a wiring junction (50B4) that is joined to the second wiring; the position of the wiring junction in the predetermined direction is between the first junction and the second junction; and a through hole (50D0) is formed in a portion of the plate member that forms a current path from the third junction to the wiring junction so as to suppress variations in a first impedance due to a current path from the first junction to the wiring junction, a second impedance due to a current path from the second junction to the wiring junction, and a third impedance due to a current path from the third junction to the wiring junction.

[0145] (Technical Idea 6) The plate member further has a first extension portion (50E1) that forms a current path from the first joint portion to the wiring joint portion, a second extension portion (50E2) that forms a current path from the second joint portion to the wiring joint portion, and a third extension portion (50E3) that forms a current path from the third joint portion to the wiring joint portion, and the extension plate width (A3) of the third extension portion is set smaller than both the extension plate width (A1) of the first extension portion and the extension plate width (A2) of the second extension portion so as to suppress variations in a first impedance due to the current path from the first joint portion to the wiring joint portion, a second impedance due to the current path from the second joint portion to the wiring joint portion, and a third impedance due to the current path from the third junction to the wiring joint portion. This is a semiconductor device described in Technical Idea 5.

[0146] (Technical Idea 7) A semiconductor device comprising: a substrate (40) having first wiring (421) and second wiring (423); a plurality of semiconductor elements (30) each having a first main electrode (31) and a second main electrode (32) provided on the surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member (50) short-circuiting the second main electrodes of the plurality of semiconductor elements and bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction (X), and of the three semiconductor elements, the semiconductor elements located at both ends are designated as a first semiconductor element (30A1) and a second semiconductor element (30A2), and the semiconductor element located between the first semiconductor element and the second semiconductor element is designated as a third semiconductor element (30A3), the plate member has a first bonding portion (50B1) which is a bonding portion with the first semiconductor element, a second bonding portion (50B2) which is a bonding portion with the second semiconductor element, a third bonding portion (50B3) which is a bonding portion with the third semiconductor element, and a wiring bonding portion (50B4) which is bonded to the second wiring, the plate member further has a first extension portion (50E1) which forms a current path from the first bonding portion to the wiring bonding portion, a second extension portion (50E2) which forms a current path from the second bonding portion to the wiring bonding portion, and a third extension portion (50E3) which forms a current path from the third bonding portion to the wiring bonding portion, the position of the wiring bonding portion in the predetermined direction is between the first bonding portion and the second bonding portion, A semiconductor device in which the extension plate width (A3) of the third extension portion is set smaller than both the extension plate width (A1) of the first extension portion and the extension plate width (A2) of the second extension portion so as to suppress variations among a first impedance due to the current path from the first joint to the wiring joint, a second impedance due to the current path from the second joint to the wiring joint, and a third impedance due to the current path from the third joint to the wiring joint.

[0147] (Technical Idea 8) A semiconductor device according to any one of Technical Ideas 1 to 7, wherein a short-circuit portion (50Ca, 50E5) of the plate member, which is a portion that short-circuits the second main electrodes of the plurality of semiconductor elements, has a shape that extends linearly in the predetermined direction.

[0148] (Technical Idea 9) A semiconductor device according to any one of Technical Ideas 1 to 8, comprising an external connection terminal (611) for electrically connecting to an external device and connected to the first wiring, wherein the pattern shape of the first wiring is set so that, among the current paths included in the first wiring, the impedance of the current path from the external connection terminal to the third semiconductor element is greater than both the impedance of the current path from the external connection terminal to the first semiconductor element and the impedance of the current path from the external connection terminal to the second semiconductor element.

Claims

1. A substrate (40) having first wiring (421) and second wiring (423); a plurality of semiconductor elements (30) each having a first main electrode (31) and a second main electrode (32) provided on the surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member (50) short-circuiting the second main electrodes of the plurality of semiconductor elements and bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction (X), and of the three semiconductor elements, the semiconductor elements located at both ends are referred to as a first semiconductor element (30A1) and a second semiconductor element (30A2), and the semiconductor element located between the first semiconductor element and the second semiconductor element is referred to as a third semiconductor element (30A3), the plate member has a first bonding portion (50B1) which is a bonding portion with the first semiconductor element, a second bonding portion (50B2) which is a bonding portion with the second semiconductor element, a third bonding portion (50B3) which is a bonding portion with the third semiconductor element, and a wiring bonding portion (50B4) which is bonded to the second wiring, the position of the wiring bonding portion in the predetermined direction is between the first bonding portion and the second bonding portion, the outer edge of the plate member at a portion which forms a current path from the first bonding portion to the wiring bonding portion is defined as a first outer edge (50A1), and the outer edge of a portion which forms a current path from the second bonding portion to the wiring bonding portion is defined as a second outer edge (50A2), the direction perpendicular to the plate surface of the plate member and the predetermined direction is defined as a reference direction (Y), A semiconductor device, wherein the first outer edge and the second outer edge are shaped to be inclined in different directions relative to the reference direction so as to suppress variations in a first impedance due to a current path from the first junction to the wiring junction, a second impedance due to a current path from the second junction to the wiring junction, and a third impedance due to a current path from the third junction to the wiring junction.

2. The semiconductor device described in claim 1, wherein a through hole (50D0) is formed in a portion of the plate member that forms a current path from the third junction to the wiring junction, so as to suppress variations among a first impedance due to a current path from the first junction to the wiring junction, a second impedance due to a current path from the second junction to the wiring junction, and a third impedance due to a current path from the third junction to the wiring junction.

3. The semiconductor device according to claim 1 or 2, wherein the plate member further has a first extension (50E1) forming a current path from the first joint to the wiring joint, a second extension (50E2) forming a current path from the second joint to the wiring joint, and a third extension (50E3) forming a current path from the third joint to the wiring joint, and wherein an extension width (A3) of the third extension is set smaller than both the extension width (A1) of the first extension and the extension width (A2) of the second extension so as to suppress variations in a first impedance due to the current path from the first joint to the wiring joint, a second impedance due to the current path from the second joint to the wiring joint, and a third impedance due to the current path from the third junction to the wiring junction.

4. The semiconductor device according to claim 1 or 2, further comprising: a second plate member (50L) made of metal separate from the first plate member (50H) that is the plate member; and a group of semiconductor elements B (30B1, 30B2, 30B3) including a plurality of semiconductor elements having one electrode bonded to the second wiring separate from the group of semiconductor elements A (30A1, 30A2, 30A3) that are the three semiconductor elements; the substrate has third wiring (422); the second plate member short-circuits the other electrodes of the group of semiconductor elements B and is bonded to the third wiring; and the second plate member has a shape having a first opposing outer edge (500A1) that faces the first outer edge and is inclined in the same direction as the first outer edge, and a second opposing outer edge (500A2) that faces the second outer edge and is inclined in the same direction as the second outer edge.

5. A semiconductor device comprising: a substrate (40) having first wiring (421) and second wiring (423); a plurality of semiconductor elements (30) each having a first main electrode (31) and a second main electrode (32) provided on the surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member (50) short-circuiting the second main electrodes of the plurality of semiconductor elements and bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction (X), and of the three semiconductor elements, the semiconductor elements located at both ends are referred to as a first semiconductor element (30A1) and a second semiconductor element (30A2), and the semiconductor element located between the first semiconductor element and the second semiconductor element is referred to as a third semiconductor element (30A3), a second junction (50B2) that is a junction with the second semiconductor element; a third junction (50B3) that is a junction with the third semiconductor element; and a wiring junction (50B4) that is joined to the second wiring; the position of the wiring junction in the predetermined direction is between the first junction and the second junction; and a through hole (50D0) is formed in a portion of the plate member that forms a current path from the third junction to the wiring junction so as to suppress variations in a first impedance due to a current path from the first junction to the wiring junction, a second impedance due to a current path from the second junction to the wiring junction, and a third impedance due to a current path from the third junction to the wiring junction.

6. The semiconductor device according to claim 5, wherein the plate member further has a first extension (50E1) forming a current path from the first joint to the wiring joint, a second extension (50E2) forming a current path from the second joint to the wiring joint, and a third extension (50E3) forming a current path from the third joint to the wiring joint, and wherein an extension width (A3) of the third extension is set smaller than both the extension width (A1) of the first extension and the extension width (A2) of the second extension so as to suppress variations in a first impedance due to the current path from the first joint to the wiring joint, a second impedance due to the current path from the second joint to the wiring joint, and a third impedance due to the current path from the third joint to the wiring joint.

7. A semiconductor device comprising: a substrate (40) having first wiring (421) and second wiring (423); a plurality of semiconductor elements (30) each having a first main electrode (31) and a second main electrode (32) provided on the surface opposite to the first main electrode, the first main electrode being bonded to the first wiring; and a metal plate member (50) short-circuiting the second main electrodes of the plurality of semiconductor elements and bonded to the second wiring, wherein the plurality of semiconductor elements include at least three semiconductor elements arranged side by side in a predetermined direction (X), and of the three semiconductor elements, the semiconductor elements located at both ends are referred to as a first semiconductor element (30A1) and a second semiconductor element (30A2), and the semiconductor element located between the first semiconductor element and the second semiconductor element is referred to as a third semiconductor element (30A3), the plate member has a first bonding portion (50B1) which is a bonding portion with the first semiconductor element, a second bonding portion (50B2) which is a bonding portion with the second semiconductor element, a third bonding portion (50B3) which is a bonding portion with the third semiconductor element, and a wiring bonding portion (50B4) which is bonded to the second wiring, the plate member further has a first extension portion (50E1) which forms a current path from the first bonding portion to the wiring bonding portion, a second extension portion (50E2) which forms a current path from the second bonding portion to the wiring bonding portion, and a third extension portion (50E3) which forms a current path from the third bonding portion to the wiring bonding portion, the position of the wiring bonding portion in the predetermined direction is between the first bonding portion and the second bonding portion, A semiconductor device in which the extension plate width (A3) of the third extension portion is set smaller than both the extension plate width (A1) of the first extension portion and the extension plate width (A2) of the second extension portion so as to suppress variations among a first impedance due to the current path from the first joint to the wiring joint, a second impedance due to the current path from the second joint to the wiring joint, and a third impedance due to the current path from the third joint to the wiring joint.

8. A semiconductor device as described in any one of claims 1, 2, 5, 6 and 7, wherein the short-circuiting portion (50Ca, 50E5) of the plate member, which is a portion that short-circuits the second main electrodes of the plurality of semiconductor elements, has a shape that extends linearly in the specified direction.

9. A semiconductor device as described in any one of claims 1, 2, 5, 6 and 7, comprising an external connection terminal (611) for electrically connecting to an external device and connected to the first wiring, wherein the pattern shape of the first wiring is set so that, among the current paths included in the first wiring, the impedance of the current path from the external connection terminal to the third semiconductor element is greater than both the impedance of the current path from the external connection terminal to the first semiconductor element and the impedance of the current path from the external connection terminal to the second semiconductor element.

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