High electron mobility transister, and method for producing same

Abstract

A high electron mobility transistor according to the present invention may comprise: a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a first protective layer formed on the barrier layer to reduce interface traps, surface traps, and deep level traps of the channel layer and the barrier layer; and a second protective layer formed on the first protective layer to reduce leakage current generation in a gate electrode.

Description

High electron mobility transistor and its manufacturing method

[0001] The present invention relates to a high electron mobility transistor and a method for manufacturing the same, and more particularly, to a high electron mobility transistor and a method for manufacturing the same, which can improve traps and minimize current collapse phenomena by forming a multilayer structure of SiNx with different deposition conditions.

[0002] Advances in ultra-high frequency wireless communication technology have led to an increase in the use of high-voltage transistors capable of operating in high-speed switching or high-voltage environments. Recently introduced III-V compound semiconductor transistors not only enable faster switching compared to conventional silicon-based transistors, making them suitable for ultra-high frequency wireless communications, but also offer the advantage of being usable in high-voltage environments due to the inherent high-voltage characteristics of the material, attracting industry attention.

[0003] In particular, in the case of a high electron mobility transistor (HEMT) using a group III-V compound semiconductor, the mobility of electrons can be increased by utilizing a two-dimensional electron gas (2DEG) generated at the interface between different materials, which makes it suitable for wireless communication in the ultra-high frequency band.

[0004] Among the materials used in high-electron-mobility transistors utilizing Group III-V compound semiconductors, gallium nitride (GaN) is utilized as a high-power, high-frequency communications semiconductor due to its excellent material properties. However, despite its superior material properties, it faces various reliability and performance issues. Surface traps, a key issue arising from the technical limitations of epitaxial growth, are identified as a critical technical challenge that must be addressed for the commercialization of GaN transistors.

[0005] Methods for improving surface traps include wet surface treatment using various solutions and dry surface treatment using various gas and plasma conditions. Conventional methods for improving surface traps generally involve etching the oxide film formed by natural oxidation. However, these methods have limitations in improving surface quality due to issues such as surface instability after etching and the tendency for re-oxidation to occur easily.

[0006] [Prior Art Literature]

[0007] (Patent Document 0001) U.S. Patent Publication No. 2010-0171150 (Published on July 8, 2010)

[0008] The present invention was developed to solve such conventional problems, and its purpose is to improve traps and minimize current collapse by forming a multilayer structure of SiNx with different deposition conditions, such as deposition materials and thicknesses.

[0009] In order to achieve the above object, the high electron mobility transistor of the present invention may include a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a first protective layer formed on the barrier layer to reduce at least one of an interface trap, a surface trap, and a deep level trap of the channel layer and the barrier layer, and a second protective layer formed on the first protective layer to reduce leakage current generation at a gate electrode.

[0010] In an embodiment, the first protective layer is characterized in that it is formed within 10 nm to 30 nm using Si-rich SiNx.

[0011] In an embodiment, the second protective layer is characterized in that it is formed within 50 nm to 100 nm using Si-poor SiNx.

[0012] In an embodiment, the second protective layer is formed using Si-poor SiNx to a thickness of 10 nm to 90 nm, and a third protective layer for moisture protection is further formed on the first protective layer.

[0013] In an embodiment, the third protective layer is characterized in that it is formed using SiO2 to a thickness of 10 nm to 40 nm.

[0014] A method for manufacturing a high electron mobility transistor according to an embodiment of the present invention may be performed by preparing a substrate, forming a channel layer on the substrate, forming a barrier layer on the channel layer, forming a first protective layer on the barrier layer to reduce at least one of an interface trap, a surface trap, and a deep level trap of the channel layer and the barrier layer, and then forming a second protective layer on the first protective layer to reduce leakage current generation at the gate electrode.

[0015] In an embodiment, the first protective layer may be formed using Si-rich SiNx to a thickness of 10 nm to 30 nm.

[0016] In an embodiment, the second protective layer may be formed to a thickness of 10 nm to 90 nm using Si-poor SiNx, and a third protective layer for moisture protection may be further formed on the first protective layer.

[0017] In an embodiment, the third protective layer can be formed using SiO2 to a thickness of 10 nm to 40 nm.

[0018] In an embodiment, after forming the second protective layer, multiple heat treatments may be performed to remove N-vacancy (Nitrogen-vacancy) of the barrier layer and the channel layer exposed on the surface of the second protective layer.

[0019] According to the present invention configured as described above, by forming a multilayer structure of SiNx with different deposition conditions, traps can be reduced and gate leakage current can be maintained low.

[0020] Specifically, by forming the first protective layer using Si-rich SiNx, which is deposited in the first step, a Si doping effect can occur on the surface of the AlGaN / GaN HEMT, which allows nitrogen in the channel layer to combine with the N-vacancy. This allows deep-level traps and surface traps to be minimized.

[0021] In addition, according to the present invention, the second protective layer deposited secondarily uses Si-poor SiNx, and the second protective layer has a higher resistance than the first protective layer, thereby preventing current leakage from the gate and minimizing the current collapse phenomenon.

[0022] Moreover, there is an advantage in that the moisture penetration rate of the transistor can be minimized by forming a protective layer with a multilayer structure of SiO2 and SiNx.

[0023] FIG. 1 is a drawing showing a state in which a channel layer, a barrier layer, and a first protective layer are formed on a substrate according to an embodiment of the present invention.

[0024] FIG. 2 is a drawing showing a state in which a second protective layer is formed on a channel layer, a barrier layer, and a first protective layer on a substrate according to an embodiment of the present invention.

[0025] FIG. 3 is a drawing showing a state in which a third protective layer is formed on a channel layer, a barrier layer, and a first protective layer on a substrate according to an embodiment of the present invention.

[0026] Figure 4 is a drawing showing a state in which a third protective layer is formed on a channel layer, a barrier layer, and a first protective layer, and a second protective layer is formed on the third protective layer.

[0027] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing reference numerals, identical or similar components will be assigned the same reference numerals, and redundant descriptions thereof will be omitted. Furthermore, when describing embodiments disclosed in this specification, if a detailed description of a related known technology is judged to obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted.

[0028] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0029] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0030] In this application, each step described may be performed regardless of the listed order, except in cases where a special causal relationship requires that the steps be performed in the listed order.

[0031] In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0032] Hereinafter, a high electron mobility transistor and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0033] Before explaining the drawings, the high electron mobility transistor (HEMT), which is the subject of the present invention, is known as a heterojunction FET (HFET) or a modulation-doped FET (MODFET), and is a type of field effect transistor (FET) in which a heterojunction is formed between a channel layer composed of a group III-V compound semiconductor element and a barrier layer having an electron affinity lower than that of the channel layer. The high electron mobility transistor can operate at a higher frequency than a general transistor, up to millimeter frequencies, and is applicable to high-frequency and high-power products such as power amplifiers between mobile phone base stations and phased array lasers in military applications, making it one of the semiconductor devices that has been most actively researched and developed recently.

[0034] FIG. 1 is a drawing showing a state in which a channel layer, a barrier layer, and a first protective layer are formed on a substrate according to an embodiment of the present invention, and FIG. 2 is a drawing showing a state in which a second protective layer is formed on the channel layer, the barrier layer, and the first protective layer on a substrate according to an embodiment of the present invention.

[0035] Compound semiconductor devices, including high electron mobility transistors, can be basically formed by sequentially stacking a buffer layer (20), a channel layer (30), and a barrier layer (40) on a substrate (10). The stacking process of each layer can be performed by one or a combination of various epitaxial growth processes such as LPE, VPE, MOVPE, MOCVD, and MBE, and some layers may be omitted depending on the epitaxial process.

[0036] The high electron mobility transistor has the characteristic that a two-dimensional electron gas (2DEG: 2-Dimensional Electron Gas) is formed at the interface between heterogeneous materials between the channel layer (30) and the barrier layer (40), and this can be used to increase the mobility of electrons.

[0037] However, since the buffer layer (20), channel layer (30), and barrier layer (40) are formed according to various epitaxial processes, they are formed very smoothly on the layer surfaces. For example, the surface of the barrier layer (40) that is epitaxially grown at the very end can also be smooth with almost no damage. Due to this characteristic, as the gap between the interface of the channel layer (30) and the barrier layer (40) and the gate electrode (not shown) increases, the control performance for electron movement may decrease. For this, since a higher voltage must be applied to the gate electrode, a leakage current (current collapse phenomenon) occurs, resulting in a decrease in performance, and this can be mainly caused by traps in the transistor.

[0038] In the case of traps, there are surface traps, deep level traps, interface traps, and buffer traps, and in the case of double interface traps and buffer traps, they can be improved during transistor manufacturing, but in the case of surface traps and deep level traps, it is difficult to improve during the transistor manufacturing process, so a process of depositing a protective layer on the substrate surface to minimize traps is essential. In other words, surface traps are defects that are formed on the surface during the epi growth process. If the epi growth technology is developed, it can be improved like deep level traps, but it is a problem that continuously occurs even if we try to improve it during the current epi growth process. Accordingly, it may be more efficient to improve surface traps and deep level traps through the formation of a protective layer rather than through epi growth.

[0039] Typically, SiNx, SiO2, Al2O3, SiON, HfO2, etc. are used as the protective layer, and in the case of a transistor manufactured using an AlGaN / GaN HEMT device as in the embodiment of the present invention, SiNx and SiO2 are generally used.

[0040] However, in the case of SiO2, there is a limitation that oxygen impurities can easily diffuse into the GaN crystal, forming oxides at wafer surface traps and generating additional current collapse. In addition, when using a single SiO2 protective layer, an interface trap charge density three times higher than that of SiNx is generated, and there is a limitation that a higher current collapse phenomenon occurs compared to SiNx during pulsed measurements due to the high interface trap charge density.

[0041] To this end, a protective layer of SiNx having different deposition conditions such as deposition materials and thicknesses is deposited in a multilayer structure to improve traps in the transistor and minimize the current collapse phenomenon. Specifically, referring to FIG. 1, the transistor may form a substrate (10), a buffer layer (20) on the substrate (10), a channel layer (30) on the buffer layer, a barrier layer (40) on the channel layer (30), and a first protective layer (100) on the barrier layer (40) to reduce at least one of interface traps, surface traps, and deep level traps.

[0042] First, the substrate (10) may be an insulating substrate such as glass, sapphire, or quartz, or a semiconductor material substrate such as silicon, silicon carbide, indium-phosphorus, silicon-germanium, gallium-arsenide, or gallium-nitrogen, or a diamond substrate with excellent heat dissipation properties. In addition, various materials suitable for stacking semiconductor materials may be used.

[0043] The buffer layer (20) above can reduce lattice mismatch between the substrate (10) and the channel layer (30), which is a semiconductor element formed on the substrate (10), and can suppress the diffusion of defects by being formed of a material that traps defects (e.g., dislocations). The buffer layer (20) can be composed of a compound of two materials including In, Ga, Al, etc. and N.

[0044] The above channel layer (30) may be a semiconductor element having a uniform composition and not doped with impurities, formed using an epitaxial growth technique. The channel layer (30) may include a two-dimensional electron gas (2DEG) region, which is a region where charge (electrons) movement occurs in a high electron mobility transistor element, between the channel layer (30) and the barrier layer (40).

[0045] In one embodiment, the channel layer (30) may be formed by combining group III-V compound semiconductor elements, and the number and form thereof may vary. For example, representative binary compounds may include gallium-nitrogen (GaN), gallium-arsenide (GaAs), indium-phosphorus (InP), aluminum-arsenide (AlAs), indium-arsenide (InAs), and indium-tin (In-Sb), and representative ternary compounds may include aluminum-gallium-nitrogen (AlGaN), indium-gallium-nitrogen (InGaN), aluminum-gallium-arsenide (AlGaAs), indium-gallium-arsenide (InGaAs), indium-gallium-phosphorus (InGaP), indium-aluminum-phosphorus (InAlP), indium-gallium-phosphorus (InGaP), and indium-aluminum-arsenide (InAlAs).

[0046] The channel layer (30) of the present invention may be made of GaN.

[0047] The above barrier layer (40) has a larger band gap energy than the channel layer (30), and acts as a barrier to charge flow, thereby allowing a two-dimensional electron gas (2DEG) region in which charges (electrons) move between the channel layer (30) and the barrier layer (40) to be formed. In addition, the barrier layer (40) can form a Schottky junction (a junction between a semiconductor channel layer and a metal connected to the semiconductor channel layer) necessary for forming a transistor requiring a high operating speed between the gate electrode and the channel layer (30).

[0048] In addition, the barrier layer (40) can be composed of AlGaN among group III-V compounds, and when a surface treatment process such as oxygen plasma treatment or oxygen heat treatment is performed, a fine oxide film layer made of Ga2O3, Al2O3, etc. is formed through the combination of the cationic components among the constituent elements of AlGaN with oxygen. These fine oxide film layers are denser and have superior surface quality than the naturally occurring oxide film, GaOX, and thus can improve surface bonding with the gate electrode.

[0049] The first protective layer (100) may be formed to a thickness of 10 nm to less than 30 nm using Si-rich SiNx. The Si-rich SiNx may have a ratio of Si to N of, for example, about 59:41, and may be formed such that the silicon content ratio of the first protective layer (100) is relatively higher compared to the second protective layer (200) described later. The formed first protective layer (100) may cause a Si doping effect on the surface (AlGaN / GaN HEMT surface) of the channel layer (30) and the barrier layer (40), and the Si doping effect allows nitrogen in the barrier layer (40) to combine with N-vacancy, which is an empty site, to reduce deep-level traps and surface traps. In addition, the nitrogen vacancy (N-Vacancy) existing between the surface of the channel layer (30) and the barrier layer (40) (AlGaN / GaN HEMT surface) and the first protective layer (100) can be raised to the surface, thereby reducing the density of interface traps and deep level traps between the barrier layer (40) and the first protective layer (100).

[0050] Additionally, the first protective layer (100) can be performed by either an LPCVD or a PECVD process.

[0051] The LPCVD process refers to the low-pressure CVD process among deposition CVD processes, and is characterized by performing deposition at subatmospheric pressure. For example, the reaction chamber can be operated under low pressure and utilize high-temperature thermal energy (0.1–1000 Torr, 600°C or higher).

[0052] In addition, the PECVD process is a Plasma CVD process, and unlike the existing high-pressure CVD (APCVD) process and LPCVD, which use high-temperature heat energy to deposit using heat, it induces a reaction of gases within a plasma state, which is characterized by the fact that a relatively low-temperature process is possible. However, the chamber is in a vacuum state and can be maintained at low pressure. In particular, the area where the PECVD method is widely used is mainly used in processes that require deposition related to metals. This is because metals frequently used in areas such as metal wiring processes, such as Al, generally melt at low temperatures, with a melting point below 600℃. Therefore, the previous LPCVD process has the characteristic that it cannot use metals with low melting points when the process is performed in a high-temperature condition over 600℃. To improve this, a method of depositing an insulating film before the metal process is also used.

[0053] In this embodiment, the first protective layer (100) is described as being performed by one of the LPCVD or PECVD processes, but it is to be understood that the deposition of the first protective layer (100) may be performed by one or a combination of various deposition processes, such as PVD (Physical Vapor Deposition) such as sputtering, electron beam, thermal evaporation, etc., and CVD (Chemical Vapor Deposition) such as LPCVD, MOCVD, PECVD, ALCVD, etc.

[0054] Referring to FIG. 2, a second protective layer (200) can be laminated and formed on the first protective layer (100) to minimize leakage current generated at the gate electrode of the barrier layer (40).

[0055] The second protective layer (200) can be deposited within 50 nm to 100 nm using Si-poor SiNx. The ratio of Si and N in the formed second protective layer (200) is, for example, about 50:50, and can be formed with a relatively low silicon content ratio compared to the first protective layer (100), and is characterized by having high resistance. By forming the second protective layer (200), the overall resistance can be increased and current leakage to the gate electrode can be prevented, thereby minimizing the occurrence of the current collapse phenomenon.

[0056] When the second protective layer (200) is formed directly on the first protective layer (100), the thickness of the second protective layer (200) can be thicker than the thickness of the first protective layer (100), and by forming protective layers with different conditions in this way, the trap of the transistor can be improved while the current collapse phenomenon can be minimized.

[0057] In an embodiment, the second protective layer (200) can be formed with a thickness of 50 nm to 100 nm, but in an embodiment of the present invention, the thickness of the second protective layer (200) can be changed depending on conditions.

[0058] In contrast, a third protective layer (300) may be formed on the first protective layer (100). The third protective layer (300) is intended to address the problem that the first protective layer (100) formed using Si-rich SiNx is limited in moisture protection. The third protective layer (300) formed on the first protective layer (100) will be described with reference to FIG. 3, which will be described later.

[0059] After the third protective layer (300) is formed, a second protective layer (200) can be formed on the third protective layer (300). At this time, the second protective layer (200) can be formed in a range of 10 nm to 90 nm using Si-poor SiNx. The second protective layer (200) can prevent current from leaking to the gate electrode, thereby minimizing the occurrence of the current collapse phenomenon. The second protective layer (200) can be performed through a PECVD process. The PECVD process is a process that uses plasma as an energy source to activate a reaction source. It is a process that can induce a reaction (deposition) on the wafer surface at a low temperature by using high energy in the plasma to activate the reaction source at a lower temperature than the existing CVD process.

[0060] The second protective layer (200) is described as an example performed by a PECVD process, but it is obvious that it can be performed by one or a combination of various deposition processes, such as PVD (Physical Vapor Deposition) such as sputtering, electron beam, thermal evaporation, etc., and CVD (Chemical Vapor Deposition) such as LPCVD, MOCVD, PECVD, ALCVD, etc., as in the case of the first protective layer (100).

[0061] After the second protective layer (200) is deposited, a heat treatment process of the transistor can be performed. The heat treatment process can be performed for approximately 10 to 40 minutes using nitrogen gas at a temperature of 300 to 700°C, and can remove nitrogen vacancies_N-vacancy (Nitrogen-vacancy center) existing between the surface of the barrier layer (40) and the channel layer (30) and the protective layer by pulling them up to the surface of the second protective layer (200).

[0062] The heat treatment can be performed at least once, and preferably twice to remove nitrogen vacancies.

[0063] In this way, during the transistor manufacturing process, a protective layer having a different structure is deposited on the barrier layer (40) to reduce traps and maintain low gate leakage current. Specifically, by depositing the first protective layer formed first using Si-rich SiNx, a Si doping effect can occur on the surface of the AlGaN / GaN HEMT, which can bind to the N-vacancy (Nitrogen-vacancy) of the channel layer. This allows deep-level traps and surface traps to be minimized.

[0064] In addition, the second protective layer formed secondarily uses Si-poor SiNx, and the second protective layer has a higher resistance than the first protective layer, so that current leakage from the gate can be prevented, thereby minimizing the current collapse phenomenon.

[0065] FIG. 3 is a drawing showing a state in which a third protective layer is deposited on a channel layer, a barrier layer, and a first protective layer on a substrate according to an embodiment of the present invention, and FIG. 4 is a drawing showing a state in which a third protective layer is deposited on a channel layer, a barrier layer, and a first protective layer, and a second protective layer is deposited on the third protective layer.

[0066] Referring to the drawing, a substrate (10), a buffer layer (20) on the substrate (10), a channel layer (30) on the buffer layer (20), and a barrier layer (40) on the channel layer (30) can be laminated and formed.

[0067] Thereafter, a first protective layer (100) can be formed on the barrier layer (40), and the first protective layer (100) can be deposited to a thickness of 10 nm to less than 30 nm using Si-rich SiNx. The Si-rich SiNx to be deposited has a ratio of Si and N of, for example, about 59:41, and can be formed to have a relatively higher silicon content ratio compared to the second protective layer (200). By generating a Si doping effect on the surfaces of the channel layer (30) and the barrier layer (40), deep level traps and interface traps can be reduced by combining with N vacancy (Nitrogen-vacancy).

[0068] As described, the first protective layer (100) deposited using Si-rich SiNx has a problem in that it is limited in moisture protection, and to compensate for this, a third protective layer (300) can be formed on the first protective layer (100).

[0069] The third protective layer (300) can be formed using SiO2 with a PECVD process within 10 nm to 40 nm. After the third protective layer (300) is formed, a second protective layer (200) can be formed on the third protective layer (300). At this time, the second protective layer (200) can be formed using Si-poor SiNx with a thickness within a range of 10 nm to 90 nm. The second protective layer (200) formed on the third protective layer (300) can prevent current from leaking to the gate electrode, thereby minimizing the occurrence of a current collapse phenomenon.

[0070] After forming a third protective layer (300) by laminating it between the first protective layer (100) and the second protective layer (200), heat treatment can be performed. The heat treatment can be performed at least twice for 10 to 40 minutes in a nitrogen atmosphere at a temperature between 300 and 700°C. Through this heat treatment, the N-vacancy (Nitrogen-vacancy center) between the channel layer (30) and the barrier layer (40) can be raised to the surface of the second protective layer (200) and removed.

[0071] By forming a multilayer structure protective layer on the transistor according to the embodiment, it is possible to minimize the occurrence of leakage current and increase in trap density at the gate electrode, which are disadvantages of a single protective layer protecting the channel layer (30) and the barrier layer (40).

[0072] The technical features disclosed in each embodiment of the present invention are not limited to that embodiment, and, unless they are mutually incompatible, the technical features disclosed in each embodiment may be combined and applied to different embodiments.

[0073] Therefore, although each embodiment focuses on its own technical features, each technical feature can be applied in combination with each other as long as they are not mutually incompatible.

[0074] The present invention is not limited to the above-described embodiments and the attached drawings, and various modifications and variations are possible within the scope of those skilled in the art. Therefore, the scope of the present invention should be defined not only by the claims of this specification but also by equivalents thereof.

[0075] [Explanation of symbols]

[0076] 10: Substrate

[0077] 20: Buffer layer

[0078] 30: Channel layer

[0079] 40: Barrier layer

[0080] 100: First protective layer

[0081] 200: Second protective layer

[0082] 300: Third protective layer

[0083] [National Research and Development Project Supporting This Invention]

[0084] [Project ID] 9991008828

[0085] [Assignment Number] 22-CM-TN-15

[0086] Ministry of Trade, Industry and Energy, Defense Acquisition Program Administration

[0087] [Name of Project Management (Specialist) Agency] Civil-Military Cooperation Promotion Agency

[0088] [Research Project Name] Civilian-Military Dual-Use Technology Development Project

[0089] [Research Project Name] Development of a 150nm gallium nitride (GaN)-based process technology and application system (3.5km-class drone detection radar)

[0090] [Name of the project performing organization] RFHIC Co., Ltd.

[0091] Research Period: January 1, 2025 - December 31, 2025

Claims

1. Substrate, A channel layer formed on the above substrate, A barrier layer formed on the above channel layer, A first protective layer formed on the barrier layer to reduce at least one of an interface trap, a surface trap, and a deep level trap of the channel layer and the barrier layer, and A high electron mobility transistor comprising a second protective layer formed on the first protective layer to reduce leakage current generation at the gate electrode.

2. In claim 1, A high electron mobility transistor characterized in that the first protective layer is formed within 10 nm to 30 nm using Si-rich SiNx.

3. In claim 1, A high electron mobility transistor characterized in that the second protective layer is formed within 50 nm to 100 nm using Si-poor SiNx.

4. In claim 1, The second protective layer is formed using Si-poor SiNx to a thickness of 10 nm to 90 nm, A high electron mobility transistor characterized in that a third protective layer for moisture protection is further formed on the first protective layer.

5. In claim 4, A high electron mobility transistor characterized in that the third protective layer is formed using SiO2 to a thickness of 10 nm to 40 nm.

6. Step for preparing the substrate; A step of forming a channel layer on the substrate; A step of forming a barrier layer on the above channel layer; A step of forming a first protective layer on the barrier layer to reduce at least one of interface traps, surface traps, and deep level traps of the channel layer and the barrier layer; and A method for manufacturing a high electron mobility transistor, comprising the step of forming a second protective layer on the first protective layer to reduce leakage current generation at the gate electrode.

7. In claim 6, The step of forming the first protective layer is: A method for manufacturing a high electron mobility transistor, characterized by including a step of forming a Si-rich SiNx within 10 nm to 30 nm.

8. In claim 6, The step of forming the second protective layer is: A method for manufacturing a high electron mobility transistor, characterized by including a step of forming a Si-poor SiNx within 50 nm to 100 nm.

9. In claim 6, The step of forming the second protective layer is: A step of forming within 10 nm to 90 nm using Si-poor SiNx; and A method for manufacturing a high electron mobility transistor, characterized in that it includes a step of further forming a third protective layer for moisture protection on the first protective layer.

10. In claim 9, The step of forming the third protective layer is: A method for manufacturing a high electron mobility transistor, characterized by including a step of forming a layer of SiO2 to a size of 10 nm to 40 nm.

11. In claim 6, After the step of forming the second protective layer, A method for manufacturing a high electron mobility transistor, characterized in that it further comprises a plurality of heat treatment steps for removing nitrogen vacancy (Nvacancy) of the barrier layer and the channel layer exposed on the surface of the second protective layer.

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