Thin film transistor structures

Abstract

Embodiments disclosed herein generally relate to thin-film transistor (TFT) structures. The structures include forming one or more layers by atomic layer deposition (ALD). The layer formed by ALD may be implemented in a first gate insulating (Gl) layer, a second Gl layer, and / or an interlayer dielectric (ILD) layer. Implementing an ALD formed layer results in various functional improvements of the TFTs.

Description

THIN FILM TRANSISTOR STRUCTURESBACKGROUNDField

[0001] Embodiments of the present disclosure generally relate to semiconductor device structures for display devices. More specifically, embodiments described herein relate to thin-film transistor (TFT) structures with a layer formed by atomic layer deposition (ALD).Description of the Related Art

[0002] Thin-film transistors (TFTs) are metal oxide layered semiconductor devices used in integrated circuits and in displays to control pixel operation. TFTs have gained significant interest in display applications due to their high resolution, low power consumption, and high speed operation for liquid crystal display (LCD) and organic light-emitting diode (OLED) displays. Current materials used in the layers making up TFTs often have limited electron mobility due to the methods of depositing the layers relative to one another and relative to a metal oxide layer of the TFT.

[0003] Accordingly, what is needed in the art are improved TFTs and methods of fabricating TFTs. In particular, there is a need for improved methods of forming layers for TFTs having better short channel performance, thermal stability, and interface.SUMMARY

[0004] Embodiments disclosed herein generally relate to thin-film transistor (TFT) structures. The TFT structures include layers with a layer formed by atomic layer deposition (ALD).

[0005] One exemplary thin-film transistor structure includes a first gate electrode, a first gate insulating (Gl) layer disposed on the first gate electrode, a channel region formed between source and drain regions disposed on the first Gl layer, a second Gl layer disposed on the channel region, the second Gl layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD), a second gate electrode disposed on the second Gl layer, an interlayer dielectric (ILD) layer disposed on the second gate electrode, and an interlayer formed by ALD, the interlayer in contact with the second Gl layer.

[0006] Another exemplary thin-film transistor structure includes a first gate electrode, a first Gl layer disposed on the first gate electrode, the first Gl layer formed by PECVD or CVD, a channel region formed between source and drain regions disposed on the first Gl layer, a second Gl layer disposed on the channel region, a second gate electrode disposed on the second Gl layer, an ILD layer disposed on the second gate electrode, and an interlayer formed by ALD, the interlayer in contact with the first Gl layer.

[0007] Yet another exemplary thin-film transistor structure includes a first gate electrode, a first Gl layer disposed on the first gate electrode, a channel region formed between source and drain regions disposed on the first Gl layer, a second Gl layer disposed on the channel region, a second gate electrode disposed on the second Gl layer, an ILD layer disposed on the second gate electrode, the ILD layer formed by PECVD or CVD, and an interlayer formed by ALD, the interlayer in contact with the ILD layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of scope, as the disclosure may admit to other equally effective embodiments.

[0009] FIG. 1 illustrates a schematic cross-sectional view of a thin-film transistor (TFT), according to embodiments.

[0010] FIG. 2 is a flow diagram of a method of forming a TFT, according to embodiments.

[0011] FIGs. 3A-3G are schematic cross-sectional views of a TFT at various stages of fabrication, according to embodiments.

[0012] FIGs. 4A-4I are schematic cross-sectional views of TFTs with a layer formed by atomic layer deposition (ALD), according to embodiments.

[0013] FIG. 5 is a flow diagram of another method of forming a TFT, according to embodiments.

[0014] FIGs. 6A-6D are schematic cross-sectional views of exemplary TFTs with at least two layers formed by ALD, according to embodiments.

[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0016] Embodiments disclosed herein generally relate to semiconductor device structures, such as thin-film transistor (TFT) structures, which include one or more layers formed by atomic layer deposition (ALD). In certain examples, the layer(s) formed by ALD may be included in, or formed adjacent to, a first gate insulating (Gl) layer, a second Gl layer, and / or an interlayer dielectric (ILD) layer. TFT structures including a layer formed by ALD exhibit various improvements in performance over conventional TFTs without such layers.

[0017] Note that although the following embodiments are described with reference to TFT structures, other semiconductor devices and structures can also benefit from the techniques and arrangements described herein.

[0018] FIG. 1 illustrates a schematic cross-sectional view of an example TFT 100, according to one embodiment. The TFT 100 is formed on a substrate 102, such as a silicon wafer. A first gate electrode 104 is formed on the substrate 102. A first Gl layer 106 is formed over the first gate electrode 104 and portions of the substrate 102. The first Gl layer 106 includes a single layer formed by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Alternatively, the first Gl layer 106 includes a plurality of sublayers formed by CVD or PECVD, including a first Gl sublayer 106a and a second Gl sublayer 106b. The first Gl sublayer 106a and / or the second Gl sublayer 106b may be collectively referred to herein as the layer 106.

[0019] The first Gl layer 106, or sublayers thereof, is formed of one or more insulating materials such as silicon (Si), silicon oxide (SiOx), silicon nitride (SiNx),other insulating materials, combinations thereof, and the like. Where the first Gl layer 106 includes the first Gl sublayer 106a and the second Gl sublayer 106b, the first Gl sublayer 106a and the second Gl sublayer 106b are formed of different materials. For example, the first Gl sublayer 106a may include SiNx and the second Gl sublayer 106b may include SiOx. Generally, the first Gl layer 106 is formed by PECVD.

[0020] A metal oxide layer 108 is formed over the first Gl layer 106, and includes a source region 109a and a drain region 109b. A second Gl layer 110 is formed over the metal oxide layer 108, and is formed using similar techniques and materials as used to form the first Gl layer 106. A second gate electrode 112 is formed over the second Gl layer 110, and is similar to the first gate electrode 104.

[0021] An ILD layer 114 is formed over the second gate electrode 112 and the first Gl layer 106, and over portions of the second Gl layer 110. The ILD layer 114 includes a single layer formed by CVD or PECVD. Alternatively, the ILD layer 114 includes a plurality of sublayers formed by CVD or PECVD, including a first ILD sublayer 114a and a second ILD sublayer 114b. The first ILD sublayer 114a and / or the second ILD sublayer 114b may be collectively referred to herein as the layer 114.

[0022] The ILD layer 114, or sublayers thereof, may be formed of one or more insulating materials such as single SiOx, SiNx, multi-layer silicon nitride / silicon oxide (SiNx / SiOx), silicon oxynitride (SiON), other insulating materials, combinations thereof, and the like. Where the ILD layer 114 includes the first ILD sublayer 114a and the second ILD sublayer 114b, the first ILD sublayer 114a and the second ILD sublayer 114b are formed of different materials. For example, the first ILD sublayer 114a may include SiOx and the second ILD sublayer 114b may include SiNx. Generally, the ILD layer 114 is formed by PECVD. A source electrode 116 and a drain electrode 118 are formed over and / or through the ILD layer 114. The source electrode 116 is in contact with the source region 109a, and the drain electrode 118 is in contact with the drain region 109b.

[0023] The TFT 100 in FIG. 1 may be limited by the techniques used to form the first Gl layer 106, the second Gl layer 110, and the ILD layer 114. For example, the first Gl layer 106, the second Gl layer 110, and the ILD layer 114 are formed using PECVD or CVD, which can result in a reduced thermal budget and limited performanceof such layers. Reduced thermal budget and limited performance may be caused by unwanted hydrogen that is contained by layers formed using PECVD or CVD (e.g., the first Gl layer 106, the second Gl layer 110, and / or the ILD layer 114) because plasma may not be able to fully dissociate reactant gases such as, for example, silane (SiH4) or ammonia (NH3). Thus, the short channel performance and thermal stability of the TFT 100 may be hindered by the layers formed using PECVD or CVD. However, as described elsewhere herein, TFT structures incorporating a layer or interlayer formed by ALD may exhibit improved performance as compared to TFT structures formed by PECVD or CVD alone.

[0024] The inclusion of one or more interlayer(s) formed by ALD (sometimes referred to herein as “ALD formed interlayer(s)” or “ALD interlayer(s)”) can enhance short channel performance, improve thermal stability, and / or better interface between layers of semiconductor devices, such as TFTs for displays. For example, ALD formed interlayer(s), as described herein, can improve the ability of a channel (e.g., a metal oxide layer) to maintain desirable electrical characteristics when channel length (e.g., distance between source and drain electrodes) is reduced. ALD formed interlayer(s) can also facilitate better bonding and / or compatibility with other layers or interlayers in contact therewith, which creates a more uniform interface (e.g., with less air gaps or pockets formed therein), and improves a device’s ability to maintain its electrical properties over a range of different temperatures or under varying thermal conditions. As such, positive bias temperature stress (PBTS) of the devices is improved via a higher thermal budget and better interface. Generally, such benefits are realized by the improved uniformity, density, and over film quality of layers deposited by ALD.

[0025] The ALD formed interlayer(s) described herein can also reduce the occurrence of hysteresis, which allows for quicker, more predictable changes to input. Hysteresis depends on interface quality due to the difference of charge trapping and de-trapping speed, and as such, the large excess oxygen and bi-stability of the ALD formed interlayer(s) demonstrates smaller hysteresis than Gl layers formed by CVD. The better interface with the ALD formed interlayer(s) is due to the low-power plasma damage.

[0026] Other benefits provided by the utilization of ALD formed interlayer(s) include low hydrogen content, low temperature deposition, and low radio-frequency ofdevices. As an example, utilization of the ALD formed interlayer(s) in TFTs may lower hydrogen levels by 25% to 35% in comparison to TFTs without ALD formed interlayer(s). The reduction of hydrogen content may be particularly useful in display devices as high-mobility oxide materials are more sensitive to hydrogen diffusion due to their higher carrier concentration. Further, the deposition rate of an ALD formed interlayer may be, for example, between 5 to 300 A per minute (A / min) (e.g., between 25 to 280 A / min, 45 to 260 A / min, 65 to 240 A / min, or 85 to 220 A / min), whereas the deposition rate of a layer or interlayer formed by PECVD may be between 700 and 2000 A / min.

[0027] Even further, fabricating TFTs with the ALD formed interlayer(s) described herein enables wider process windows and better base to source (BTS) in high temperature processes. That is, the fabrication process can operate with a wider range of process parameters while still producing desired characteristics for the device. The ALD formed interlayer(s) also enable improved flow of charger carriers between source and drain electrodes of TFTs as a result of the better BTS.

[0028] Techniques for fabricating a TFT structure with ALD formed interlayer(s) are described with reference to FIGs. 2 and 3A-3G. FIG. 2 is a flow diagram of a method 200 of forming a TFT structure 300, according to embodiments. FIGs. 3A-3G illustrate schematic cross-sectional views illustrating various stages of the method 200, according to embodiments.

[0029] As shown, the TFT structure 300 is formed over a substrate 302 (FIG. 3A). As an example, the substrate 302 includes a glass substrate or an indium tin oxide (ITO) glass substrate that includes a TFT backplane.

[0030] The method 200 begins at operation 202, where a first gate electrode 304 is formed over the substrate 302, as shown in FIG. 3A. The first gate electrode 304 is formed of a material that includes at least one of molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), an alloy metal such as MoW, a combination of conductive materials such as MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, an electrically conductive material such as a conductive metal oxide like indium tin oxide (InSnO) (ITO) or indium zinc oxide (InZnO) (IZO), combinations thereof, or the like.

[0031] The first gate electrode 304 is deposited in a single operation, but multiple deposition operations are also contemplated. For example, material of the first gate electrode 304 may be deposited in a first suboperation to form a metal layer, and one or more residual portions of the metal layer may be thereafter etched in a second suboperation to make the first gate electrode 304. The first gate electrode 304 is configured to be connected to a gate line signal as a power source (not shown) to provide a voltage across layers of the TFT structure 300.

[0032] At operation 204, a first Gl layer 306 is formed over at least a portion of the first gate electrode 304 and the substrate 302, as shown in FIG. 3B. The first Gl layer 306 includes a single layer, which can be deposited by CVD or PECVD. Alternatively, the first Gl layer 306 may include a plurality of sublayers, including at least a first Gl sublayer 306a and a second Gl sublayer 306b. The first Gl sublayer 306a and the second Gl sublayer 306b can each be deposited by CVD or PECVD, and may be collectively referred to herein as the first Gl layer 306. Note that it is contemplated that the first Gl layer 306 can include more than two sublayers.

[0033] The first Gl layer 306, or sublayers thereof, is generally formed of one or more insulating materials such as silicon, SiOx, SiNx, other insulating materials, combinations thereof, and the like. Where the first Gl layer 306 includes the first Gl sublayer 306a and the second Gl sublayer 306b, the first Gl sublayer 306a and the second Gl sublayer 306b are formed of different materials. For example, the first Gl sublayer 306a may include SiNx and the second Gl sublayer 306b may include SiOx. It is also contemplated that the first Gl sublayer 306a and the second Gl sublayer 306b are formed of the same materials.

[0034] The first Gl layer 306 can have an overall thickness from about 200 angstroms (A) to about 8000 A, such as for example, an overall thickness from about 500 A to about 7500 A, an overall thickness from about 1000 A to about 7000 A, an overall thickness from about 1500 A to about 6500 A, an overall thickness from about 2000 A to about 6000 A, an overall thickness from about 3000 A to about 5000 A, an overall thickness of about 3500 A to about 5500 A, or the like.

[0035] As seen in FIG. 2, operation 204 may also optionally include depositing an interlayer formed by ALD, wherein the ALD interlayer is in contact with the first Gl layer306. Depending on a composition of the first Gl layer 306, e.g., whether the first Gl layer 306 includes a single layer or multiple sublayers, one or more ALD interlayers may be formed between, below, and / or over layers of the first Gl layer 306.

[0036] It is contemplated that an ALD interlayer can be formed over the first Gl layer 306, as indicated by the arrow 320 in FIG. 3B. That is, the ALD interlayer is formed on the first Gl layer 306, and in embodiments, on the second Gl sublayer 306b. Examples of TFTs with an ALD interlayer formed at the position indicated by arrow 320 are described with further reference to FIGs. 4B-4C.

[0037] It is also contemplated that an ALD interlayer can be formed between sublayers of the first Gl layer 306. For example, where the first Gl layer 306 includes at least the first Gl sublayer 306a and the second Gl sublayer 306b, the ALD interlayer can be formed between the Gl sublayers 306a, 306b as indicated by the arrow 322 in FIG. 3B. An example of a TFT with the ALD interlayer formed at the position indicated by arrow 322 is described with further reference to FIG. 4D.

[0038] It is also contemplated that a first ALD interlayer can be formed between sublayers of the first Gl layer 306, and a second ALD interlayer formed over the first Gl layer 306. For example, where the first Gl layer 306 includes at least the first Gl sublayer 306a and the second Gl sublayer 306b, a first ALD interlayer can be formed between the Gl sublayers 306a and 306b, and a second ALD interlayer can be formed over the second Gl sublayer 306b. In embodiments with more than two Gl sublayers, ALD interlayers can be formed between / above any one or more of the Gl sublayers.

[0039] An ALD interlayer formed at operation 204 can have a thickness between about 30 A and 300 A (e.g., between 50 A and 280 A, 70 A and 260 A, 90 A and 240 A, or 110 A and 220 A).

[0040] At operation 206, a metal oxide layer 308 is formed over the first Gl layer 306, as shown in FIG. 3C. The metal oxide layer 308 may also be referred to herein as a “channel region.” The metal oxide layer 308 can be formed by physical vapor deposition (PVD), PECVD, CVD, or ALD. In particular, the metal oxide layer 308 is deposited by a high density plasma chemical vapor deposition (HDPCVD) process.Further, if the metal oxide layer 308 is deposited using selective deposition to create the metal oxide layer 308 with a desired shape, operation 208 may be optional.

[0041] It is contemplated that the metal oxide layer 308 is formed of a material that includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf). It is also contemplated that the metal oxide layer 308 is formed of a material that includes amorphous silicon (Si) or a low temperature polycrystalline silicon (LTPS). Examples of materials for the metal oxide layer 308 include, but are not limited to, In-Ga-Zn-O, In-Zn-O, In-Ga-Sn-O, In-Zn-Sn- O In-Ga-Zn-Sn-O, In-Sn-O, Hf-ln-Zn-O, Ga-Zn-O, In-O, Al-Sn-Zn-O, Zn-O, Zn-Sn-O, Al-Zn-O, Al-Zn-Sn-O, Hf-Zn-O, Sn-O, and Al-Sn-Zn-ln-O. Further, the material of the metal oxide layer 308 can include an indium oxide (InxOy) contained semiconductor layer. Operation 206 may also include doping the metal oxide layer 308 with n-type or p-type dopants, such as boron (B) or nitrogen (N), or high oxygen affinity metal such as W, Ta, Ti, iron (Fe), nickel (Ni), cobalt (Co), or neodymium (Nd). Operation 206 may also include doping the metal oxide layer 308 with Lanthanides (Ln) such as lanthanum (La), cerium (Ce), or Promethium (Pm).

[0042] The metal oxide layer 308 can have an overall thickness of about 10 nanometers (nm) to about 100 nm, such as a thickness of about 30 nm, about 50 nm, about 70 nm, or the like.

[0043] At operation 208, the metal oxide layer 308 is patterned using any suitable methods of patterning, such as by a wet etch process. For example, the patterning may include forming either a photolithographic mask or a hard mask (not shown) over the metal oxide layer 308 and exposing the metal oxide layer 308 to an etchant which is referred to herein as “etching.” Depending on the material used in the metal oxide layer 308, the metal oxide layer 308 can be patterned by exposing portions thereof not covered by a mask to a wet etchant, or by exposing portions of the metal oxide layer 308 not covered by the mask to an etching plasma. Further, the metal oxide layer 308 can be patterned by etching portions of the metal oxide layer 308 not covered by the mask to an etching plasma, which plasma includes sulfur hexafluoride gas, oxygen gas, chlorine gas, or combination(s) thereof. The etching plasma and the etching process described can be used in any of the patterning and etching of any layer described herein.

[0044] At operation 210, the metal oxide layer 308 (and thus, TFT structure 300) undergoes annealing. As an example, annealing is performed for about 5 to about 15 seconds maintaining a temperature of about 70 °C to about 250 °C.

[0045] At operation 212, a second Gl layer 310 is formed over at least a portion of the metal oxide layer 308, as shown in FIG. 3D. The second Gl layer 310 is formed in direct contact with the metal oxide layer 308. The second Gl layer 310 includes a single layer, which can be formed by CVD or PECVD. Alternatively, the second Gl layer 310 includes a plurality of sublayers, wherein one of more of the sublayers are deposited by CVD or PECVD.

[0046] The second Gl layer 310 is generally formed of one or more insulating materials such as silicon, SiOx, SiNx, other insulating materials, combinations thereof, and the like. Where the second Gl layer 310 includes a plurality of sublayers, at least two of the sublayers may be formed of different materials.

[0047] The second Gl layer 310 can have an overall thickness from about 200 A to about 8000 A, such as for example, an overall thickness from about 500 A to about 7500 A, an overall thickness from about 1000 A to about 7000 A, an overall thickness from about 1500 A to about 6500 A, an overall thickness from about 2000 A to about 6000 A, an overall thickness from about 3000 A to about 5000 A, an overall thickness from about 3500 A to about 5500 A, or the like.

[0048] As seen in FIG. 2, operation 212 may also optionally include depositing an interlayer formed by ALD, wherein the ALD interlayer is in contact with the second Gl layer 310. Depending on a composition of the second Gl layer 310, i.e., whether the second Gl layer 310 includes a single layer or multiple sublayers, one or more ALD interlayers may be formed between, below, and / or over layers of the second Gl layer 310.

[0049] An ALD interlayer is formed below the second Gl layer 310 and over the metal oxide layer 308, as indicated by the arrow 324 in FIG. 3D. An example of a TFT with the ALD interlayer formed at the position indicated by arrow 322 is described with further reference to FIG. 4D. It is also contemplated that an ALD interlayer can be formed over the second Gl layer 310 and / or between sublayers of the second Gl layer310, which can be in addition or alternative to the ALD interlayer formed at the position indicated by arrow 322. The one or more ALD interlayer(s) formed at operation 212 can be formed in addition or alternative to any ALD interlayers formed at operation 204.

[0050] An ALD interlayer formed at operation 212 can have a thickness between about 30 A and 300 A (e.g., between 50 A and 280 A, 70 A and 260 A, 90 A and 240 A, or 110 A and 220 A).

[0051] At operation 213, the second Gl layer 310 (and thus, TFT structure 300) undergoes annealing. As an example, annealing is performed for no more than 2 hours at a temperature of no more than 400 °C.

[0052] At operation 214, a second gate electrode 312 is formed, as shown in Fig. 3E. The second gate electrode 312 is formed over the second Gl layer 310. The second gate electrode 312 may be formed of a material that includes at least one of Mo, Or, Cu, Ti, Ta, W, an alloy metal such as MoW, a combination of conductive materials such as MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, any electrically conductive material such as a conductive metal oxide like ITO and IZO, any combinations thereof, or the like.

[0053] The second gate electrode 312 is deposited in a single operation. Alternatively, material of the second gate electrode 312 is deposited in a first suboperation to form a metal layer, and one or more residual portions of the metal layer are thereafter etched in a second suboperation to make the second gate electrode 312. The second gate electrode 312 is configured to be connected to a gate line signal as a power source (not shown) to provide a voltage across layers of the TFT structure 300.

[0054] At operation 216, the second Gl layer 310 and / or the second gate electrode 312 are etched / patterned, as shown in FIG. 3E. The second gate electrode 312 can act as a mask to etch the second Gl layer 310 to a desired size and shape. Operation 216 may also include a wet etch process, where the wet etch rate (WER) of the second Gl layer 310 and / or the second gate electrode 312 is from about 200 A / min to about 7000 A / min. Operation 216 may also include a dry etch process. After etching, asource region 309a and a drain region 309b are formed in the metal oxide layer 308 by an ion doping process using, for example, helium (He) plasma.

[0055] At operation 218, an ILD layer 314 is formed over the second gate electrode 312 and the first Gl layer 306, and over portions of the metal oxide layer 308 and the second Gl layer 310, as shown in FIG. 3F. The ILD layer 314 includes a single layer, which can be formed by CVD or PECVD. Alternatively, the ILD layer 314 includes a plurality of sublayers, including at least a first ILD sublayer 314a and a second ILD sublayer 314b. The first ILD sublayer 314a and / or the second ILD sublayer 314b can be deposited by CVD or PECVD, and may be collectively referred to herein as the ILD layer 314.

[0056] The ILD layer 314, or sublayers thereof, is generally formed of one or more insulating materials such as single SiOx, SiNx, multi-layer SiOx / SiNx, SiON, other insulating materials, combinations thereof, and the like. Where the ILD layer 314 includes the first ILD sublayer 314a and the second ILD sublayer 314b, the first ILD sublayer 314a and the second ILD sublayer 314b are formed of different materials. For example, the first ILD sublayer 314a may include SiOx and the second ILD sublayer 314b may include SiNx. Alternatively, the first ILD sublayer 314a and the second ILD sublayer 314b are formed of the same materials. It is contemplated that the ILD layer 314 is further planarized at operation 218, such as by chemical mechanical polishing (CMP).

[0057] The ILD layer 314 can have an overall thickness from about 200 angstroms (A) to about 8000 A, such as for example, an overall thickness from about 500 A to about 7500 A, an overall thickness from about 1000 A to about 7000 A, an overall thickness from about 1500 A to about 6500 A, an overall thickness from about 2000 A to about 6000 A, an overall thickness from about 3000 A to about 5000 A, an overall thickness from about 3500 A to about 5500 A, or the like.

[0058] As seen in FIG. 2, operation 218 may also optionally include depositing an interlayer formed by ALD, wherein the ALD interlayer is in contact with the ILD layer 314. Depending on a composition of the ILD layer 314, i.e., whether the ILD layer 314 includes a single layer or multiple sublayers, one or more ALD interlayers may be formed between, below, and / or over layers of the ILD layer 314.

[0059] It is contemplated that an ALD interlayer can be formed below the ILD layer 314, and over the second gate electrode 312 and the first Gl layer 306, and over portions of the metal oxide layer 308 and the second Gl layer 310, as indicated by the arrow 326 in FIG. 3F. The first ILD sublayer 314a may be comprised of SiOx and the second ILD sublayer 314b may be comprised of SiNx. Examples of TFTs with the ALD interlayer formed at the position indicated by the arrow 326 are described with further reference to FIGs. 4E-4F.

[0060] It is also contemplated that an ALD interlayer can be formed between sublayers of the ILD layer 314. For example, where the ILD layer 314 includes the first ILD sublayer 314a and the second ILD sublayer 314b, the ALD interlayer can be formed between the ILD sublayers 314a, 314b as indicated by the arrow 328 in FIG. 3F. An example of a TFT with the ALD interlayer formed at the position indicated by arrow 328 is described with further reference to FIG. 4G.

[0061] It is also contemplated that an ALD interlayer can be formed over the ILD layer 314. A first ALD interlayer is formed between sublayers of the ILD layer 314 and a second ALD interlayer is formed below and / or above the ILD layer 314. Where there are more than two ILD sublayers, ALD interlayers can be formed between / above any one or more of the ILD sublayers. The one or more ALD interlayer(s) formed at operation 218 can be formed in addition or alternative to any ALD interlayers formed at operation 204 and / or 212.

[0062] An ALD interlayer formed at operation 218 can have a thickness between about 30 A and 300 (e.g., between 50 A and 280 A, 70 A and 260 A, 90 A and 240 A, or 110 A and 220 A). At operation 220, the ILD layer 314 undergoes a via carbon nanotube (CNT) etch process. For example, the ILD layer 314 is etched to form bores in the TFT structure 300 for subsequent source and drain electrode metallization. The etch process at operation 220 may be a dry etch process or a plasma-based etch process. At operation 222, the first gate electrode 304 undergoes via CNT dry etching.

[0063] At operation 224, a source electrode 316 and a drain electrode 318 are formed in the TFT structure 300, as shown in FIG. 3G. Portions of the ILD layer 314 that expose the source region 309a and the drain region 309b of the metal oxide layer 308 are filled with a conducting material to form the source electrode 316 and the drainelectrode 318. The conducting material may include at least one of Mo, Cr, Cu, Ti, Ta, W, an alloy metal such as MoW, a combination of conductive materials such as MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, and MoWCuMoW, a metal oxide such as ITO or IZO, any combinations thereof, or the like.

[0064] At operation 226, a final annealing process is performed on the TFT structure 300. Operation 226 may help to eliminate any defects in the formation of any layers of the TFT structure 300, or at the interface between any of the layers of the TFT structure 300. At operation 226, thermal energy may be directed to the substrate through any known annealing process, including laser annealing, both continuous wave and pulsed, spike annealing, rapid thermal annealing, flash annealing, and the like. The final annealing process may include a melt process or a submelt process.

[0065] As described above with reference to operations 204, 212, and / or 218, ALD interlayer(s) may be deposited at a deposition rate between 5 to 300 A / min (e.g., between 25 to 280 A / min, 45 to 260 A / min, 65 to 240 A / min, or 85 to 220 A / min). The ALD interlayer(s) may be formed of one or more suitable insulating materials, including SiNx, SiOx, silicon oxynitride (SiON), aluminum oxide (AIOx), zirconium oxide (ZrOx), titanium oxide (TiOx), hafnium oxide (HfOx), or the like.

[0066] FIGs. 4A-4I are schematic cross-sectional views of exemplary TFT structures with at least one ALD layer formed by the method 200, according to embodiments. The TFT structures shown in FIGs. 4A-4I can be representative of the TFT structure 300 described with reference to FIGs. 2 and 3A-3G.

[0067] In FIG. 4A, a TFT structure 400a is shown. As shown, the TFT structure 400a includes an ALD interlayer 402 that is formed below the second Gl layer 310, which includes a single layer. However, the ALD interlayer 402 may also be formed above the second Gl layer 310. To form this structure, the ALD interlayer 402 is deposited at operation 212.

[0068] Turning to FIG. 4B, a TFT structure 400b is shown. As shown, the TFT structure 400b includes an ALD interlayer 404 formed above the first Gl layer 306,which includes a single layer. To form this structure, the ALD interlayer 404 is deposited at operation 204.

[0069] Turning to FIG. 40, a TFT structure 400c is shown. As shown, the first Gl layer 306 of the TFT structure 400c includes the first Gl sublayer 306a and the second Gl sublayer 306b. In this example, an ALD interlayer 406 is formed above the second Gl sublayer 306b and the first Gl sublayer 306a. To form this structure, the ALD interlayer 406 is deposited at operation 204.

[0070] Turning to FIG. 4D, a TFT structure 400d is shown. Similar to the TFT structure in FIG. 4C, the first Gl layer 306 of the TFT structure 400d includes the first Gl sublayer 306a and the second Gl sublayer 306b. In this example, an ALD interlayer 408 is formed between the first Gl sublayer 306a and the second Gl sublayer 306b. To form this structure, the ALD interlayer 408 is deposited at operation 204.

[0071] Turning to FIG. 4E, a TFT structure 400e is shown. As shown, the TFT structure 400e includes an ALD interlayer 410 that is formed below the ILD layer 314. To form this structure, the ALD interlayer 410 is deposited at operation 218.

[0072] Turning to FIG. 4F, a TFT structure 400f is shown. In this example, the ILD layer 314 of the TFT structure 400f includes the first ILD sublayer 314a and the second ILD sublayer 314b. An ALD interlayer 412 is formed below both of the first ILD sublayer 314a and the second ILD sublayer 314b. To form this structure, the ALD interlayer 412 is deposited at operation 218.

[0073] Turning to FIG. 4G, a TFT structure 400g is shown. In this example, an ALD interlayer 414 is formed between the first ILD sublayer 314a and the second ILD sublayer 314b of the ILD layer 314 of the TFT structure 400g. To form this structure, the ALD interlayer 414 is deposited at operation 218.

[0074] While 4A-4G each show a single ALD interlayer, multiple ALD interlayers can be formed in a single device. For example, ALD interlayers may be formed at two or more of the positions shown in FIG. 4A-4G in a single device. When multiple ALD interlayers are formed, each of the two or more ALD interlayers may have a thickness which is less than the thickness of the ALD interlayer when only one ALD interlayer is formed. By reducing the thickness of the ALD interlayers, the fabrication time neededto form the ALD interlayers is reduced, which further improves overall fabrication efficiency and productivity. In other words, including two or more thinner ALD interlayers in a TFT structure may reduce fabrication time while still providing similar or better benefits relative to when one thicker ALD interlayer is included in the TFT structure. Multiple ALD interlayers formed in a single device are shown in FIGs. 4H and 4I.

[0075] Turning to FIG. 4H, a TFT structure 400h is shown. In this example, the TFT structure 400h includes the ALD interlayers 402, 412. The ALD interlayer 402 is formed below the second Gl layer 310, which includes a single layer, and the ALD interlayer 412 is formed below the ILD layer 314. To form this structure, the ALD interlayer 402 is deposited at operation 212, and the ALD interlayer 412 is deposited at operation 218.

[0076] Turning to FIG. 4I, a TFT structure 400i is shown. In this example, the TFT structure 400i includes the ALD interlayers 402, 406, 412. The ALD interlayer 406 is formed above the first Gl layer 306, the ALD interlayer 402 is formed below the second Gl layer 310, and the ALD interlayer 412 is formed below the ILD layer 314. To form this structure, the ALD interlayer 406 is deposited at operation 204, the ALD interlayer 402 is deposited at operation 212, and the ALD interlayer 412 is deposited at operation 218.

[0077] By including multiple ALD interlayers, for example, as shown in FIGs. 4H and 4I, the ALD interlayer 402 covers edges of the metal oxide layer 308, which helps prevent hydrogen content from entering the metal oxide layer 308, and the ALD interlayer 412 helps prevent hydrogen content from entering the second Gl layer 310. As such, the TFT structure 400h enables better fabrication productivity and short channel performance by reducing the number of hydrogen diffusion paths.

[0078] FIG. 5 is a flow diagram of another method 500 of forming a TFT structure, according to embodiments. The method 500 shown in FIG. 5 is substantially similar to the method 200 shown and described with reference to FIG. 2. Accordingly, in FIG. 5, similar operations are labeled with similar reference numerals.

[0079] In addition to the operations 202-226 shown and described with reference to method 200 of FIG. 2, the method 500 includes operations 510, 515, 520, and 525.

[0080] At operation 510, the second gate electrode is etched / patterned. Operation 510 may also include a wet etch process, where the WER of the second gate electrode is from about 200 A / min to about 7000 A / min. Operation 510 may also include a dry etch process.

[0081] At operation 515, an ion implantation process is performed, for example, on the second Gl layer and / or the second gate electrode. Ion implantation is a surface modification technique capable of modifying the optical properties of a portion of a surface layer of the TFT structure. Ion implantation allows accurate control of both dopant composition and penetration depth through the choice of the species and the energy of the doping ions. In the ion implantation process, doping ions are accelerated and implanted within the TFT structure through openings in a patterned layer. The doping ions may include at least one of Al, P, F, Cl, P, or gases N, Ar or Kr. As described herein, the doping ions provided in the ion implantation process are generated from a plasma formed by applying a high voltage RF to a processing region of a plasma processing chamber. The plasma dissociated ions are then biased toward the surface of the TFT structure and implanted at a certain desired depth. By implanting ions in the TFT structure, the second Gl layer may have lower hydrogen content than the ILD layer, which improves short channel performance.

[0082] When performing the ion implantation process at operation 515, the TFT structure is placed on a substrate supporting pedestal of a plasma processing chamber, a gas is flowed into the interior of the plasma processing chamber and ignited to generate a plasma. A bias is then applied to the TFT structure to accelerate the doping ions generated in the plasma towards a surface of the TFT structure. As a result of the plasma and the biasing, the doping ions generated in the plasma are implanted into the TFT structure to form a portion thereof. One example of the ion implantation apparatus is the Varian VIISTA® Trident, available from Applied Materials, Inc., Santa Clara, Calif.

[0083] At operation 520, second Gl layer is etched. Operation 510 may also include a wet etch process, where the WER of the second Gl layer is from about 200 A / min to about 7000 A / min. Operation 510 may also include a dry etch process.

[0084] At operation 525, the ILD layer and the second Gl layer undergo a via CNT etch process. For example, the ILD layer and the second Gl layer are etched to form bores in the TFT structure for subsequent source and drain electrode metallization. The etch process at operation 525 may be a dry etch process or a plasma-based etch process.

[0085] FIGs. 6A-6D are schematic cross-sectional views of exemplary TFT structures with at least two ALD layers formed by the method 500, according to embodiments.

[0086] In FIG. 6A, a TFT structure 600a is shown. In this example, the TFT structure 600a includes two ALD interlayers 602 and 604. The ALD interlayer 602 is formed below a second Gl layer 610, which is formed over the metal oxide layer 308, the source region 309a, the drain region 309b, and portions of the first Gl layer 306. The ALD interlayer 604 is formed below the ILD layer 314. To form this structure, the ALD interlayer 602 is deposited at operation 212, and the ALD interlayer 604 is deposited at operation 218. The ALD interlayer 602 helps prevent hydrogen content from entering the metal oxide layer 308, and the ALD interlayer 604 helps prevent hydrogen content from entering the second Gl layer 610. The ALD interlayers 602 and 604 also help improve short channel performance.

[0087] Turning to FIG. 6B, a TFT structure 600b is shown. In this example, the TFT structure 600b includes two ALD interlayers 602 and 606. The ALD interlayer 602 is formed below a second Gl layer 610, which is formed over the metal oxide layer 308, the source region 309a, the drain region 309b, and portions of the ALD interlayer 606. The ALD interlayer 606 is formed over the first Gl layer 306. To form this structure, the ALD interlayer 602 is deposited at operation 212, and the ALD interlayer 606 is deposited at operation 204. The ALD interlayers 602 and 606 help prevent hydrogen content from entering the metal oxide layer 308 and improve short channel performance.

[0088] Turning to FIG. 60, a TFT structure 600c is shown. In this example, the TFT structure 600c includes two ALD interlayers 604 and 606. The ALD interlayer 604 is formed below the ILD layer 314 and the ALD interlayer 606 is formed over the first Gl layer 306. To form this structure, the ALD interlayer 604 is deposited at operation 218, and the ALD interlayer 606 is deposited at operation 204. The ALD interlayers 604 and 606 help prevent hydrogen content from entering the metal oxide layer 308 and improve short channel performance.

[0089] Turning to FIG. 6D, a TFT structure 600d is shown. In this example, the TFT structure 600d includes three ALD interlayers 602, 604, and 606. The ALD interlayer 602 is formed below a second Gl layer 610, which is formed over the metal oxide layer 308, the source region 309a, the drain region 309b, and portions of the ALD interlayer 606. The ALD interlayer 604 is formed below the ILD layer 314 and the ALD interlayer 606 is formed over the first Gl layer 306. To form this structure, the ALD interlayer 602 is deposited at operation 212, the ALD interlayer 604 is deposited at operation 218, and the ALD interlayer 606 is deposited at operation 204. The ALD interlayers 602, 604, and 606 help prevent hydrogen content from entering the metal oxide layer 308 and improve short channel performance.

[0090] In various embodiments of the present disclosure, layers or other materials are referred to as being etched. It is understood that the etching of these materials can be performed using any conventional methods used in semiconductor manufacturing, such as, but not limited to, reactive ion etching (RIE), dry etching, wet etching, plasma etching, microloading, the selective etching of any of the above, combinations of the above, and any other suitable method. It is to be understood that when a method operation is described herein as etching two or more types of materials, or two or more portions of the same material, the etching can occur simultaneously with the same etching process, or the etching can be performed in separate suboperations using different etching processes. For example, an operation describing etching a metal and a dielectric includes a first etching suboperation using a first etching process that etches the metal, and the operation further includes a second etching suboperation using a second etching process that etches the dielectric.

[0091] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”

[0092] While various examples of the invention have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. Likewise, the various diagrams may depict an example architectural or other configuration for the disclosure, which is done to aid in understanding the features and functionality that can be included in the disclosure. The disclosure is not restricted to the illustrated example architectures or configurations, but can be implemented using a variety of alternative architectures and configurations. Additionally, although the disclosure is described above in terms of various example examples and aspects, it should be understood that the various features and functionality described in one or more of the individual examples are not limited in their applicability to the particular example with which they are described. They instead can be applied, alone or in some combination, to one or more of the other examples of the disclosure, whether or not such examples are described, and whether or not such features are presented as being a part of a described example. Thus the breadth and scope of the present disclosure should not be limited by any of the above-described example examples.

[0093] All references cited herein are incorporated herein by reference in their entirety. To the extent publications and patents or patent applications incorporated by reference contradict the disclosure contained in the specification, the specification is intended to supersede and / or take precedence over any such contradictory material.

[0094] Unless otherwise defined, all terms (including technical and scientific terms) are to be given their ordinary and customary meaning to a person of ordinary skill in the art, and are not to be limited to a special or customized meaning unless expressly so defined herein.

[0095] Terms and phrases used in this application, and variations thereof, especially in the appended claims, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing, the term ‘including’ should be read to mean ‘including, without limitation,’ ‘including but not limited to,’ or the like; the term ‘including’ as used herein is synonymous with ‘including,’ ‘containing,’ or ‘characterized by,’ and is inclusive or open-ended and does not exclude additional, unrecited elements or method steps; the term ‘having’ should be interpreted as ‘having at least;’ the term ‘includes’ should be interpreted as ‘includes but is not limited to;’ the term ‘example’ is used to provide example instances of the item in discussion, not an exhaustive or limiting list thereof; adjectives such as ‘known’, ‘normal’, ‘standard’, and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass known, normal, or standard technologies that may be available or known now or at any time in the future; and use of terms like ‘preferably,’ ‘preferred,’ ‘desired,’ or ‘desirable,’ and words of similar meaning should not be understood as implying that certain features are critical, essential, or even important to the structure or function of the invention, but instead as merely intended to highlight alternative or additional features that may or may not be utilized in a particular example of the invention. Likewise, a group of items linked with the conjunction ‘and’ should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as ‘and / or’ unless expressly stated otherwise. Similarly, a group of items linked with the conjunction ‘or’ should not be read as requiring mutual exclusivity among that group, but rather should be read as ‘and / or’ unless expressly stated otherwise.

[0096] The term “including as used herein is synonymous with “including,” “containing,” or “characterized by” and is inclusive or open-ended and does not exclude additional, unrecited elements or method steps.

[0097] All numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification are to be understood as being modified in all instances by the term ‘about.’ Accordingly, unless indicated to the contrary, the numerical parameters set forth herein are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of any claims in any application claiming priority to the present application, each numerical parameter should be construed in light of the number of significant digits and ordinary rounding approaches.

[0098] Furthermore, although the foregoing has been described in some detail by way of illustrations and examples for purposes of clarity and understanding, it is apparent to those skilled in the art that certain changes and modifications may be practiced. Therefore, the description and examples should not be construed as limiting the scope of the invention to the specific examples and examples described herein, but rather to also cover all modification and alternatives coming with the true scope and spirit of the invention.Example Embodiments

[0099] Embodiment 1 : A thin-film transistor structure, comprising: a first gate electrode; a first gate insulating (Gl) layer disposed on the first gate electrode; a channel region formed between source and drain regions disposed on the first Gl layer; a second Gl layer disposed on the channel region, the second Gl layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD); a second gate electrode disposed on the second Gl layer; an interlayer dielectric (ILD) layer disposed on the second gate electrode; and an interlayer formed by atomic layer deposition (ALD), the interlayer in contact with the second Gl layer.

[0100] Embodiment 2: The thin-film transistor structure of Embodiment 1 , wherein the channel region is comprised of a metal oxide, amorphous silicon (Si), or a low temperature polycrystalline silicon (LTPS).

[0101] Embodiment 3: The thin-film transistor structure of Embodiment 1 , wherein the channel region is formed of a material that includes oxygen (0) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (0), tin (Sn), aluminum (Al), and hafnium (Hf).

[0102] Embodiment 4: The thin-film transistor structure of Embodiment 3, wherein the material is doped with boron (B) or nitrogen (N).

[0103] Embodiment 5: The thin-film transistor structure of Embodiment 3, wherein the material is doped with a high oxygen affinity metal.

[0104] Embodiment 6: The thin-film transistor structure of Embodiment 5, wherein the high oxygen affinity metal is at least one of tungsten (W), tantalum (Ta), titanium (Ti), iron (Fe), nickel (Ni), cobalt (Co), Lanthanides (Ln), or neodymium (Nd).

[0105] Embodiment 7: thin-film transistor structure, comprising: a first gate electrode; a first gate insulating (Gl) layer disposed on the first gate electrode, the first Gl layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD); a channel region formed between source and drain regions disposed on the first Gl layer; a second Gl layer disposed on the channel region; a second gate electrode disposed on the second Gl layer; an interlayer dielectric (ILD) layer disposed on the second gate electrode; and an interlayer formed by atomic layer deposition (ALD), the interlayer in contact with the first Gl layer.

[0106] Embodiment 8: The thin-film transistor structure of Embodiment 7, wherein the channel region is comprised of a metal oxide, amorphous silicon (Si), or a low temperature polycrystalline silicon (LTPS).

[0107] Embodiment 9: The thin-film transistor structure of Embodiment 7, wherein the channel region is formed of a material that includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf).

[0108] Embodiment 10: The thin-film transistor structure of Embodiment 9, wherein the material is doped with boron (B) or nitrogen (N).

[0109] Embodiment 11 : The thin-film transistor structure of Embodiment 9, wherein the material is doped with a high oxygen affinity metal.

[0110] Embodiment 12: The thin-film transistor structure of Embodiment 11 , wherein the high oxygen affinity metal is at least one of tungsten (W), tantalum (Ta), titanium (Ti), iron (Fe), nickel (Ni), cobalt (Co), Lanthanides (Ln), or neodymium (Nd).

[0111] Embodiment 13: A thin-film transistor structure, comprising: a first gate electrode; a first gate insulating (Gl) layer disposed on the first gate electrode; a channel region formed between source and drain regions disposed on the first Gl layer; a second Gl layer disposed on the channel region; a second gate electrode disposed on the second Gl layer; an interlayer dielectric (ILD) layer disposed on the second gate electrode, the ILD layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD); and an interlayer formed by atomic layer deposition (ALD), the interlayer in contact with the ILD layer.

[0112] Embodiment 14: The thin-film transistor structure of Embodiment 13, wherein the channel region is comprised of a metal oxide, amorphous silicon (Si), or a low temperature polycrystalline silicon (LTPS).

[0113] Embodiment 15: The thin-film transistor structure of Embodiment 13, wherein the channel region is formed of a material that includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf).

[0114] Embodiment 16: The thin-film transistor structure of Embodiment 15, wherein the material is doped with boron (B) or nitrogen (N).

[0115] Embodiment 17: The thin-film transistor structure of Embodiment 15, wherein the material is doped with a high oxygen affinity metal.

[0116] Embodiment 18: The thin-film transistor structure of Embodiment 17, wherein the high oxygen affinity metal is at least one of tungsten (W), tantalum (Ta), titanium (Ti), iron (Fe), nickel (Ni), cobalt (Co), Lanthanides (Ln), or neodymium (Nd).

Claims

What is claimed is:1 . A thin-fi Im transistor structure, comprising: a first gate electrode; a first gate insulating (Gl) layer disposed on the first gate electrode; a channel region formed between source and drain regions disposed on the first Gl layer; a second Gl layer disposed on the channel region, the second Gl layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD); a second gate electrode disposed on the second Gl layer; an interlayer dielectric (ILD) layer disposed on the second gate electrode; and an interlayer formed by atomic layer deposition (ALD), the interlayer in contact with the second Gl layer.

2. The thin-film transistor structure of claim 1 , wherein the interlayer formed by ALD has a deposition rate between 5 and 300 angstroms per minute (A / min).

3. The thin-film transistor structure of claim 1 , wherein the interlayer formed by ALD has a thickness between 30 angstroms (A) and 300 A.

4. The thin-film transistor structure of claim 1 , wherein the interlayer formed by ALD is comprised of one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (AIOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or hafnium oxide (HfOx).

5. The thin-film transistor structure of claim 1 , wherein the channel region is comprised of a metal oxide, amorphous silicon (Si), or a low temperature polycrystalline silicon (LTPS).

6. The thin-film transistor structure of claim 1 , wherein the first Gl layer comprises: a first layer formed by PECVD; and a second layer formed by ALD.

7. The thin-film transistor structure of claim 1 , wherein the ILD layer comprises: a first layer formed by ALD; and a second layer formed by PECVD.

8. A thin-film transistor structure, comprising: a first gate electrode; a first gate insulating (Gl) layer disposed on the first gate electrode, the first Gl layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD); a channel region formed between source and drain regions disposed on the first Gl layer; a second Gl layer disposed on the channel region; a second gate electrode disposed on the second Gl layer; an interlayer dielectric (ILD) layer disposed on the second gate electrode; and an interlayer formed by atomic layer deposition (ALD), the interlayer in contact with the first Gl layer.

9. The thin-film transistor structure of claim 8, wherein: the first Gl layer comprises a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer, and the interlayer formed by ALD is disposed between the SiNx layer and the SiOx layer.

10. The thin-film transistor structure of claim 8, wherein: the first Gl layer comprises a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer disposed on the SiNx layer, and the interlayer formed by ALD is disposed on the SiOx layer.

11. The thin-film transistor structure of claim 8, wherein the interlayer formed by ALD has a deposition rate between 5 and 300 angstroms per minute (A / min).

12. The thin-film transistor structure of claim 8, wherein the interlayer formed by ALD has a thickness between 30 angstroms (A) and 300 A.

13. The thin-film transistor structure of claim 8, wherein the interlayer formed by ALD is comprised of one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (AIOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or hafnium oxide (HfOx).

14. A thin-film transistor structure, comprising: a first gate electrode; a first gate insulating (Gl) layer disposed on the first gate electrode; a channel region formed between source and drain regions disposed on the first Gl layer; a second Gl layer disposed on the channel region; a second gate electrode disposed on the second Gl layer; an interlayer dielectric (ILD) layer disposed on the second gate electrode, the ILD layer formed by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD); and an interlayer formed by atomic layer deposition (ALD), the interlayer in contact with the ILD layer.

15. The thin-film transistor structure of claim 14, wherein: the interlayer formed by ALD is disposed on the second gate electrode, the source and drain regions, and the first Gl layer, and the ILD layer is disposed on the interlayer, the ILD layer comprising a silicon oxide (SiOx) layer.

16. The thin-film transistor structure of claim 14, wherein: the interlayer formed by ALD is disposed on the second gate electrode, the source and drain regions, and the first Gl layer, and the ILD layer is disposed on the interlayer, the ILD layer comprising a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer.

17. The thin-film transistor structure of claim 14, wherein:the ILD layer comprises a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer, and the interlayer formed by ALD is disposed between the SiOx layer and the SiNx layer.

18. The thin-film transistor structure of claim 14, wherein the interlayer formed by ALD has a deposition rate between 5 and 300 angstroms per minute (A / min).

19. The thin-film transistor structure of claim 14, wherein the interlayer formed by ALD has a thickness between 30 angstroms (A) and 300 A.

20. The thin-film transistor structure of claim 14, wherein the interlayer formed by ALD is comprised of one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (AIOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or hafnium oxide (HfOx).

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