Pulsed DC systems and methods for controlling ETCH rate using an LC circuit

Abstract

A system includes a pulsed direct current (DC) source. The pulsed DC source generates a DC voltage signal. The system includes an inductor-capacitor (LC) circuit coupled to the pulsed DC source to receive the DC voltage signal to output a square waveform voltage. The system further includes a high frequency (HF) radio frequency (RF) generator that generates an RF waveform. The system includes an impedance matching circuit coupled to the HF RF generator to receive the RF waveform to output a modified RF waveform. The LC circuit is coupled to the impedance matching circuit at a point to combine the modified RF waveform with the square waveform voltage. The modified RF waveform is combined with the square waveform voltage to output a modified square waveform voltage. The system includes a plasma chamber coupled to the point to receive the modified square waveform voltage.

Description

PULSED DC SYSTEMS AND METHODS FOR CONTROLLING ETCH RATE USING AN LC CIRCUITFIELD

[0001] The embodiments described in the present disclosure relate to pulsed direct current (DC) systems and methods for controlling an etch rate using an inductor-capacitor (LC) circuit.BACKGROUND

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] A plasma tool is used to fabricate semiconductor wafers. The plasma tool has a radio frequency (RF) generator, an impedance matching network, and a plasma chamber. The RF generator is coupled to the plasma chamber via impedance matching network. The RF generator generates an RF signal, and power of the RF signal is transferred via the impedance matching network to the plasma chamber for processing the semiconductor wafer. However, the semiconductor wafer is not processed efficiently.

[0004] It is in this context that embodiments described in the present disclosure arise.SUMMARY

[0005] Embodiments of the disclosure provide pulsed direct current (DC) systems and methods for controlling an etch rate using an inductor-capacitor (LC) circuit. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0006] In one embodiment, a system includes a pulsed DC source. The pulsed DC source generates a DC voltage signal. The system includes an LC circuit coupled to the pulsed DC source to receive the DC voltage signal to output a square waveform voltage. The system further includes a high frequency (HF) radio frequency (RF) generator that generates an RF waveform. The system includes an impedance matching circuit coupled to the HF RF generator to receive the RF waveform to output a modified RF waveform. The LC circuit is coupled to the impedance matching circuit at a point to combine the modified RF waveform with the square waveform voltage. The modified RF waveform is combined with the square waveform voltageto output a modified square waveform voltage. The system includes a plasma chamber coupled to the point to receive the modified square waveform voltage.

[0007] In an embodiment, a system is described. The system includes an LC circuit coupled to a pulsed DC source to receive a DC voltage signal from the pulsed DC source to output a square waveform voltage. The system includes a controller coupled to the LC circuit to modify an amplitude of a plurality of oscillations of the square waveform voltage.

[0008] In one embodiment, a controller is described. The controller includes a memory device and a processor coupled to the memory device. The processor is coupled to an LC circuit that is coupled to a pulsed DC source. The LC circuit is coupled to the pulsed DC source to receive a DC voltage signal from the pulsed DC source to output a square waveform voltage. The processor modifies an amplitude of a plurality of oscillations of the square waveform voltage.

[0009] In an embodiment, the LC circuit to control voltage oscillations of a square waveform voltage generated from a DC signal is provided. Amplitudes of the voltage oscillations define a width of a high energy peak of an ion energy distribution function. When more ions are generated at the high energy peak, process results, such as a high etch rate or a small critical dimension (CD) or both, are achieved. For example, the process results are achieved when a narrow ion energy distribution is achieved.

[0010] Some advantages of the herein described systems and methods include achieving the process results by controlling a capacitance of a shunt capacitor that is coupled to a pulsed DC source. For example, when the capacitance is increased to achieve a predetermined capacitance, there is a decrease in an amplitude of oscillations of the oscillations of the square waveform voltage that is output to a plasma chamber. With the decrease in the amplitude, a narrow ion energy distribution is achieved. When the narrow ion energy distribution is achieved, an etch rate of etching a substrate increases. Also, a critical dimension of features of the substrate decreases.

[0011] As an additional advantage, the etch rate is controlled by controlling the capacitance of the shunt capacitor. For example, when the capacitance is decreased to achieve the predetermined capacitance, there is an increase in an amplitude of oscillations of the square waveform voltage output to the plasma chamber. With the increase in the amplitude, a wide ion energy distribution is achieved. When the wide ion energy distribution is achieved, an etch rate of etching the substrate decreases.

[0012] Some other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0014] Figure 1 is a diagram of an embodiment of a system to illustrate use of an inductor-capacitor (LC) circuit.

[0015] Figure 2 is a diagram of an embodiment of a system to illustrate details of the LC circuit of Figure 1.

[0016] Figure 3A is an embodiment of a graph to illustrate a high amplitude of oscillations of a square waveform voltage.

[0017] Figure 3B is an embodiment of a graph to illustrate an intermediate amplitude oscillations of a square waveform voltage.

[0018] Figure 3C is an embodiment of a graph to illustrate a low amplitude of oscillations of a square waveform voltage.

[0019] Figure 4 is an embodiment of a graph to illustrate that with an increase in a predetermined capacitance, an amplitude of oscillations of a square waveform voltage decreases.

[0020] Figure 5A is an embodiment of a graph of wide ion energy distribution.

[0021] Figure 5B is an embodiment of a graph having a square waveform voltage to illustrate that with an increase in an amplitude of oscillations of the square waveform voltage, the wide ion energy distribution is achieved.

[0022] Figure 5C is an embodiment of a graph of narrow ion energy distribution.

[0023] Figure 5D is an embodiment of a graph having a square waveform voltage to illustrate that with a decrease in an amplitude of oscillations of the square waveform voltage, the narrow ion energy distribution is achieved.

[0024] Figure 6A is a cross-sectional side view of an embodiment of a substrate in which features are formed at a low etch rate.

[0025] Figure 6B is a cross-sectional side view of an embodiment of a substrate in which features are formed at an intermediate etch rate.

[0026] Figure 6C is a cross-sectional side view of an embodiment of a substrate in which features are formed at a high etch rate.

[0027] Figure 7A is an embodiment of a graph to illustrate that with an increase in the predetermined capacitance, there is an increase in an etch rate of etching a substrate.

[0028] Figure 7B is an embodiment of a graph to illustrate that with a change in the predetermined capacitance, a critical dimension (CD) of a bow of a feature of a substrate S is controlled.

[0029] Figure 8 is a diagram of an embodiment of a system to illustrate details of a pulsed DC source.DETAILED DESCRIPTION

[0030] The following embodiments describe pulsed direct current (DC) systems and methods for controlling an etch rate using an inductor-capacitor (LC) circuit. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0031] Figure 1 is a diagram of an embodiment of a system 100 to illustrate use of an LC circuit 102. The system 100 includes the LC circuit 102, a pulsed DC source 104, a high frequency (HF) RF generator (RFG), an impedance matching circuit (IMC) 108, and a plasma chamber 110. The system 100 further includes a host computer 112, which includes a processor 114 and a memory device 116. The plasma chamber 110 includes a substrate support 118 and an upper electrode 120. The system 100 further includes a driver and motor system 122.

[0032] An example of the pulsed DC source 104 is a nanopulser that generates a DC voltage signal 124. To illustrate, the pulsed DC source 104 does not generate a sinusoidal signal. As another illustration, the DC voltage signal 124 is a pulsed DC signal that repeats at a low frequency. To further illustrate, the DC voltage signal 124 transitions from a first voltage to a second voltage periodically at the low frequency and transitions from the second voltage to the first voltage at the low frequency. An illustration of the first voltage is zero and an illustration of the second voltage is a high voltage greater than zero.

[0033] When the DC voltage signal 124 passes through the LC filter 102, the LC filter 102 outputs a square waveform voltage 101. As an example, the square waveform voltage 101 has the low frequency, such as one ranging from and including 100 kilohertz (kHz) to 1000 kHz. To illustrate, during a cycle of a clock signal, a square waveform voltage has a positive slope during a charging phase to achieve a maximum amplitude. The maximum amplitude is followed by a negative slope during a discharging phase, and the negative slope is followed by multiple oscillations. The positive slope, the negative slope, and the oscillations form a square pulse of the square waveform voltage. In this manner, the positive slope, the negative slope, and the oscillations repeat during each cycle of the clock signal to generate multiple square pulses of the square waveform voltage. A square pulse of the square waveform voltage is formed during a respective cycle of the clock signal to form the multiple square pulses of the square waveform voltage. As an example, the clock signal is generated by the processor 114 to synchronizeoperation of the pulsed DC source 104 with the clock signal to control output of the square waveform voltage 101.

[0034] An example of the HF RFG 106 includes a radiofrequency generator that operates at a high frequency from and including 1 megahertz (MHz) to 60 MHz. To illustrate, the HF RFG generates an RF waveform 126 having the high frequency, and the RF waveform 126 is a sinusoidal waveform or a sinusoidal signal.

[0035] As an example, the LC circuit 102 includes an HF filter that filters out high frequencies from an RF waveform reflected from the plasma chamber 110. Also, the HF filter filters out high frequencies from voltage of a modified RF waveform 156 output from the IMC 108.

[0036] Examples of the host computer 112 include a controller, a desktop computer, a laptop computer, a smart phone, and a tablet. Examples of the processor 114 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 116 include a read-only memory or a random access memory or a combination thereof.

[0037] As an example, the IMC 108 includes a network of capacitors and inductors or a network of capacitors, resistors and inductors. To illustrate, the IMC 108 includes one or more series capacitors, or one or more shunt capacitors, or one or more inductors, or a combination thereof.

[0038] An example of the driver and motor system 112 includes a combination of a motor and a driver. To illustrate, the driver includes one or more transistors and the motor is an electric motor that converts electrical energy into mechanical energy.

[0039] An example of the substrate support 118 includes an electrostatic chuck (ESC). As an example, the ESC includes a lower electrode and is located at a level below the upper electrode 120 to form a gap 128 from the upper electrode 120. A substrate S, such as a semiconductor wafer, is placed on a top surface of the substrate support 118 for being processed.

[0040] The processor 114 is coupled to the memory device 116, the pulsed DC source 104, the HF RFG 106, and the driver and motor system 122. For example, the processor 114 is coupled to the pulsed DC source 104 via a transfer cable 128 and is coupled to the HF RFG 106 via a transfer cable 130. As an example, a transfer cable is a cable that enables the serial transfer of data or parallel transfer of data or a transfer of data via a universal serial bus (USB) protocol.

[0041] Also, the pulsed DC source 104 is coupled to the LC circuit 102 via an RF connection 132. For example, an output 134 of the pulsed DC source 104 is connected to an input 136 of the LC circuit 102 via an RF strap. An example of an RF connection includes an RF cable or one or more RF straps. To illustrate, the RF straps of the RF connection are coupled toeach other in series. The RF connection is capable of transferring a high voltage signal, such as the DC voltage signal 124. To illustrate, an RF strap is a rectangular-shaped strap, such as an elongated sheet, made from a conductive material, such as copper or an alloy of copper, and has as an inductance.

[0042] An output 138 of the LC circuit 102 is coupled via an RF strap 140 to an RF output 142, which is a point on an RF transmission line 144. For example, the RF strap 140 is connected to the RF transmission line 144 via a conductive connector, such as a metal connector. As another example, the RF strap 140 is soldered to the RF rod of the RF transmission line 144. As an example, an RF transmission line includes an RF rod and an RF sheath that surrounds the RF rod.

[0043] The HF RFG 106 is coupled to an input 146 of the IMC 108 via an RF cable 148. An output 150 of the IMC 108 is coupled via the RF transmission line 144 to the lower electrode. The upper electrode 120 is coupled to a reference potential, such as a ground potential or a ground connection.

[0044] The processor 114 generates and sends a control set point signal 152 via the transfer cable 128 to the pulsed DC source 104. As an example, the control set point signal 152 includes the low frequency with which the square pulses of the square waveform voltage 101 are to repeat periodically and the maximum amplitude of each square pulse of the square waveform voltage 101. Also, the processor 114 generates and sends the clock signal via the transfer cable 128 to the pulsed DC source 104. Moreover, the processor 114 generates and sends a trigger signal via the transfer cable 128 to the pulsed DC source 104.

[0045] Similarly, the processor 114 generates and sends a control set point signal 154 via the transfer cable 130 to the HF RFG 104. As an example, the control set point signal 154 includes the high frequency with which each sinusoidal wave of the RF waveform 126 is to repeat periodically and a peak-to-peak voltage of each sinusoidal wave. Also, the processor 114 generates and sends the clock signal via the transfer cable 130 to the HF RFG 154. The processor 114 generates and sends the trigger signal via the transfer cable 130 to HF RFG 106.

[0046] In response to receiving the trigger signal, the pulsed DC source 104 generates the DC signal 124 and sends the DC signal 124 via the RF connection 132 to the input 136 of the LC circuit 102. Upon receiving the DC signal 124, the LC circuit 102 converts the DC signal 124 into the square waveform voltage 101, and provides the square waveform voltage 101 at the output 138. The square waveform voltage 101 has the low frequency and each square pulse of the square waveform voltage 101 has the maximum amplitude indicated in the control set point signal 152. For example, a frequency of repetition of two consecutive square pulses of the squarewaveform voltage 101 is the low frequency. The square waveform voltage 101 is provided from the output 138 via the RF strap 140 to the RF output 142.

[0047] Also, in response to receiving the trigger signal, the HF RFG 106 generates the RF waveform 126 and sends the RF waveform 126 via the RF cable 148 to the input 146 of the IMC 108. Upon receiving the RF waveform 126, the IMC 108 matches an impedance of a load coupled to the output 150 with an impedance of a source coupled to the input 146 to provide the modified RF waveform 156 at the output 150. An example of the load includes the RF transmission line 144 and the plasma chamber 110, and an example of the source includes the RF cable 148 and the HF RFG 106. For example, an impedance of the modified RF waveform 156 is different from an impedance of the RF waveform 126. The modified RF waveform 156 is sent from the output 150 via the RF transmission line 144 to the RF output 142.

[0048] At the RF output 142, the square waveform voltage 101 is combined with the modified RF waveform 156 to output a modified square waveform voltage 158. For example, a voltage of each square pulse of the square waveform voltage 101 is added to a voltage at the high frequency of the RF waveform 156 to output the modified square waveform voltage 158. The modified square waveform voltage 158 is transferred from the RF output 142 via the RF transmission line 144 to the lower electrode.

[0049] When one or more process gases, such as an oxygen containing gas, or a fluorine containing gas, or a combination thereof, are supplied to the gap 128 in addition to the modified square waveform voltage 158, plasma is stricken or maintained within the gap 128 to process the substrate S. An example of processing the substrate S includes etching features within the substrate S, or depositing layers on the substrate S, or cleaning the substrate S, or a combination thereof.

[0050] It should be noted that power, at the high frequency, is reflected from the plasma chamber 110 via the RF transmission line 144, the RF output 142, the RF strap 140, the LC circuit 102, and the RF connection 132 towards the pulsed DC source 104. Also, some power, at the high frequency, of the modified RF signal 156 is transferred via the RF connection 142, the RF strap 140, the LC circuit 102, and the RF connection 132 towards the pulsed DC source 104. The LC circuit 102 includes an HF filter, such as an inductor 208 (Figure 2), further described below, to filter out, such as reduce or remove, the power, at the high frequency, reflected from the plasma chamber 110, and the power, at the high frequency, of the modified RF signal 156.

[0051] The system 100 further includes a voltage (V) sensor 160 that is coupled to the RF transmission line 144. For example, the voltage sensor 160 is coupled to the RF output 142 or to a point, on the RF transmission line 144, between the RF output 142 and the lower electrode. The voltage sensor 160 measures a voltage of the modified square waveform voltage158 supplied via the RF transmission line 144 to the lower electrode. The voltage sensor 160 is used to generate multiple graphs, described below, with reference to Figures 3 A through 3C.

[0052] In one embodiment, the output 138 is coupled to the RF output 142 via multiple RF straps that are coupled to each other in series.

[0053] In an embodiment, the terms pulsed DC source and DC source are used herein interchangeably.

[0054] Figure 2 is a diagram of an embodiment of a system 200 to illustrate details of the LC circuit 102 (Figure 1). The system 200 includes an LC circuit 202, which is an example of the LC circuit 102. The system 200 further includes the processor 114 and the motor and driver system 122. The motor and driver system 122 includes a driver 204 and a motor 206. The LC circuit 202 includes the inductor 208 and a capacitor 210, which is a shunt capacitor and a variable capacitor. As an example, a capacitance of the variable capacitor ranges from and including 5 picoFarads (pF) to 200 pF. As an example, the inductor 208 has a fixed inductance that has a value ranging from and including 2.2 microHenry (pH) to 2.5 pH. To illustrate, the inductor 208 has a fixed inductance of 2.2 pH or 2.3 pH or 2.5 pH.

[0055] An end 212 of the capacitor 210 is coupled to the reference potential and an opposite end 214 of the capacitor 210 is coupled to the input 136, which is coupled to the RF connection 132. An example of the input 136 is a connector that connects the end 214 to the RF connection 132. The inductor 208 has an end 216 that is coupled to the end 214. Also, the inductor 208 has an opposite end 218 that is coupled to the output 138. An example of the output 138 is a connector that connects the end 218 to the RF strap 140.

[0056] During a time period in which the DC voltage signal 124 is received from the pulsed DC source 104 at the input 136, the processor 114 controls the capacitor 210 via the driver 204 and the motor 206 to modify, such as increase or decrease, a capacitance of the capacitor 210. For example, the processor 114 accesses a predetermined etch rate from the memory device 116. Also, in the example, the processor 114 determines that the predetermined etch rate corresponds to, such as one-to-one relationship or a unique relation with, a predetermined capacitance of the capacitor 210. As an illustration, the predetermined capacitance is a capacitance that is greater than an initial capacitance of the capacitor 210 before the predetermined capacitance is applied to the capacitor 210. As another illustration, the predetermined capacitance is a capacitance that is less than the initial capacitance of the capacitor 210. Further in the example, the predetermined capacitance is stored within the memory device 116. The processor 114 generates and sends a capacitor control signal to the driver 204 to modify the initial capacitance to the predetermined capacitance. The capacitor control signal is generated based on the predetermined capacitance to be achieved.

[0057] In the example, upon receiving the capacitor control signal, the driver 204 generates a current signal according to the predetermined capacitance to be achieved and sends the current signal to the motor 206. To illustrate, the driver 204 generates a first current signal according to the predetermined capacitance to be achieved and sends the first current signal to the motor 206 to rotate the motor 206 in a first direction. The first current signal is generated when the predetermined capacitance is greater than the initial capacitance. As another illustration, the driver 204 generates a second current signal according to the predetermined capacitance to be achieved and sends the second current signal to the motor 206 to rotate the motor 206 in a second direction. The second current signal is generated when the predetermined capacitance is less than the initial capacitance.

[0058] Continuing with the example, upon receiving the current signal, the motor 206 operates, such as rotates, to move a first plate of the capacitor 210 with respect to a second plate of the capacitor 210. To illustrate, upon receiving the first current signal, a rotor of the motor 206 rotates in the first direction with respect to a stator of the motor 206. When the rotor rotates in the first direction, the first plate linearly moves closer to the second plate or the first plate rotates with respect to the second plate to increase an amount of overlap between the first and second plates to increase the initial capacitance to the predetermined capacitance. When the first plate linearly moves closer to the second plate, a distance between the first and second plates decreases. As another illustration, in response to receiving the second current signal, the rotor of the motor 206 rotates in the second direction with respect to the stator of the motor 206. When the rotor rotates in the second direction, the first plate linearly moves away from the second plate or the first plate rotates with respect to the second plate to decrease an amount of overlap between the first and second plates to decrease the initial capacitance to the predetermined capacitance. When the first plate linearly moves away from the second plate, a distance between the first and second plates increases. In the example, an illustration of the motion of the first plate is movement in a linear direction to modify a distance between the first and second plates or rotational movement to modify an amount of overlap between the first and second plates.

[0059] When the capacitance of the capacitor 210 is changed to achieve the predetermined capacitance, an impedance of a pulsed DC transmission line, such as the RF connection 132, is changed, and therefore a shape of the DC voltage signal 124 is modified. When the shape of the DC voltage signal 124 is modified, a modified DC voltage signal 220 is output at the end 214. The modified DC voltage signal 220 is sent from the end 214 via the end 216 to the inductor 208. The inductor 208 converts a shape of the modified DC voltage signal 220 into a predetermined waveform shape of the square waveform voltage 101 that is providedat the end 218. The square waveform voltage 101 is sent from the end 218 via the output 138 and the RF strap 140 to the RF output 142.

[0060] Figure 3A is an embodiment of a graph 300 to illustrate a high amplitude of oscillations of a square waveform voltage 302, which is an example of the square waveform voltage 101 (Figure 1). The graph 300 plots an amplitude of the square waveform voltage 302 on a y-axis and time t on an x-axis. The time t includes a time tl, a time t2, a time t3, a time t4, and a time t5. The times tl through t5 progressively increase. For example, the time t2 occurs after the time tl and so on until the time t5 occurs after the time t4.

[0061] Square pulses of the square waveform voltage 302 repeat during the cycles of the clock signal. For example, during a cycle n of the clock signal, an nthsquare pulse of the square waveform voltage 302 occurs and during a cycle (n+1) of the clock signal, an (n+l)thsquare pulse of the square waveform voltage 302 occurs, where n is an integer. The cycle n extends from the time tl to the time t3 and the cycle (n+1) extends from the time t3 to the time t5.

[0062] Each cycle of the clock signal has the same time interval. For example, a time interval from the time tl to the time t3 is equal to a time interval from the time t3 to the time t5.

[0063] Each square pulse of the square waveform voltage 302 has a positive slope during the charging phase, a negative slope during the discharging phase, and multiple oscillations. For example, the nthsquare pulse includes a positive slope 304 that starts occurring at the time tl . The positive slope 304 extends from an end of multiple oscillations occurring during an (n-l)thcycle of the clock signal until a maximum amplitude 306 of the nthsquare pulse is reached. Also, after an occurrence of the maximum amplitude 306, the nthsquare pulse has a negative slope 308. The negative slope 308 extends from the maximum amplitude 306 and occurs until the time t2 at which multiple oscillations 310 occur.

[0064] The oscillations 310 of the square waveform voltage 302 have an amplitude 312. For example, a maximum amplitude from among multiple maximum amplitudes of the oscillations 310 is the amplitude 312. As another example, a maximum peak-to-peak amplitude from among multiple peak-to-peak amplitudes of the oscillations 310 is the amplitude 312. As still another example, a statistical amplitude, such as an average amplitude or a median amplitude, of multiple maximum amplitudes of the oscillations 310 is the amplitude 312. As another example, a statistical peak-to-peak amplitude, such as an average peak-to-peak amplitude or a median peak-to-peak amplitude, of multiple peak-to-peak amplitudes of oscillations 310 is the amplitude 312. The oscillations 310 occurs from the time t2 until the time t3 at which a positive slope of the (n+l)thsquare pulse starts to occur.

[0065] It should be noted that the oscillations 310 are generated when a capacitance of capacitor 210 (Figure 2) is not implemented within the LC circuit 202. For example, the amplitude 312 of the oscillations 310 is generated when the predetermined capacitance of the LC circuit 202 (Figure 2) is controlled by the processor 114 (Figure 2) to be zero. As another example, the amplitude 312 of the oscillations 310 is generated when the LC circuit 202 excludes the capacitor 210.

[0066] Figure 3B is an embodiment of a graph 320 to illustrate an intermediate amplitude of oscillations of a square waveform voltage 322, which is an example of the square waveform voltage 101 (Figure 1). The graph 320 plots an amplitude of the square waveform voltage 322 on a y-axis and the time t on an x-axis.

[0067] Square pulses of the square waveform voltage 322 repeat during the cycles of the clock signal. For example, during the cycle n of the clock signal, an nthsquare pulse of the square waveform voltage 322 occurs and during the cycle (n+1) of the clock signal, an (n+l)thsquare pulse of the square waveform voltage 322 occurs.

[0068] Square pulses of the square waveform voltage 322 repeat during the cycles of the clock signal in the same manner in which square pulses of the square waveform voltage 302 (Figure 3A) repeat periodically. Each square pulse of the square waveform voltage 322 has a positive slope during the charging phase, a negative slope during the discharging phase, and multiple oscillations. For example, the nthsquare pulse includes a positive slope 324 and that occurs at the time tl. The positive slope 324 extends from an end of oscillations occurring during the (n-l)thcycle of the clock signal until a maximum amplitude 326 of the nthsquare pulse is reached. Also, after an occurrence of the maximum amplitude 326, the nthsquare pulse has a negative slope 328. The negative slope 328 starts from the maximum amplitude 326 until the time t2 at which the oscillations 330 occur.

[0069] The oscillations 330 of the square waveform voltage 322 have an amplitude 332. For example, a maximum amplitude from among multiple maximum amplitudes of the oscillations 330 is the amplitude 332. As another example, a maximum peak-to-peak amplitude from among multiple peak-to-peak amplitudes of the oscillations 330 is the amplitude 332. As still another example, a statistical amplitude, such as an average amplitude or a median amplitude, of multiple maximum amplitudes of the oscillations 330 is the amplitude 332. As another example, a statistical peak-to-peak amplitude, such as an average peak-to-peak amplitude or a median peak-to-peak amplitude, of multiple peak-to-peak amplitudes of the oscillations 330 is the amplitude 332.

[0070] It should be noted that the oscillations 330 are generated when the processor 114 (Figure 2) controls the predetermined capacitance of the capacitor 210 (Figure 2) to be greaterthan the capacitance of zero. For example, the amplitude 332 of the oscillations 330 is generated when the predetermined capacitance of the capacitor 210 is 5 pF.

[0071] In an embodiment, the capacitance of zero is an example of the initial capacitance and the capacitance of 5 pF is an example of the predetermined capacitance.

[0072] In an embodiment, the capacitance of 5 pF is an example of the initial capacitance and the capacitance of zero is an example of the predetermined capacitance.

[0073] Figure 3C is an embodiment of a graph 340 to illustrate a low amplitude oscillations of a square waveform voltage 342, which is an example of the square waveform voltage 101 (Figure 1) . The graph 340 plots an amplitude of the square waveform voltage 342 on a y-axis and the time t on an x-axis.

[0074] Square pulses of the square waveform voltage 342 repeat during the cycles of the clock signal. For example, during the cycle n of the clock signal, an nthsquare pulse of the square waveform voltage 342 occurs and during the cycle (n+1) of the clock signal, an (n+l)thsquare pulse of the square waveform voltage 342 occurs.

[0075] Square pulses of the square waveform voltage 342 repeat during the cycles of the clock signal in the same manner in which square pulses of the square waveform voltage 302 (Figure 3A) repeat periodically. Each square pulse of the square waveform voltage 342 has a positive slope during the charging phase, a negative slope during the discharging phase, and multiple oscillations. For example, the nthsquare pulse includes a positive slope 344 and that occurs at the time tl. The positive slope 344 extends from an end of oscillations occurring during the (n-l)thcycle of the clock signal until a maximum amplitude 346 of the nthsquare pulse is reached. Also, after an occurrence of the maximum amplitude 346, the nthsquare pulse has a negative slope 348. The negative slope 348 starts from the maximum amplitude 346 until the time t2 at which the oscillations 350 occur.

[0076] The oscillations 350 of the square waveform voltage 342 have an amplitude 352. For example, a maximum amplitude from among multiple maximum amplitudes of the oscillations 350 is the amplitude 352. As another example, a maximum peak-to-peak amplitude from among multiple peak-to-peak amplitudes of the oscillations 350 is the amplitude 352. As still another example, a statistical amplitude, such as an average amplitude or a median amplitude, of multiple maximum amplitudes of the oscillations 350 is the amplitude 352. As another example, a statistical peak-to-peak amplitude, such as an average peak-to-peak amplitude or a median peak-to-peak amplitude, of multiple peak-to-peak amplitudes of the oscillations 350 is the amplitude 352.

[0077] It should be noted that the oscillations 350 are generated when the processor 114 (Figure 2) controls the predetermined capacitance of the capacitor 210 (Figure 2) to be greaterthan the capacitance used to generate the oscillations of the square waveform voltage 322 of Figure 3B. For example, the amplitude 352 of the oscillations 350 is generated when the predetermined capacitance of the capacitor 210 is 130 pF.

[0078] It should be noted that with an increase in the predetermined capacitance of the capacitor 210, an amplitude of oscillations of a square waveform voltage decreases. For example, the amplitude 332 of the graph 320 of Figure 3B is less than the amplitude 312 of the graph 300 of Figure 3 A, and the amplitude 352 of the graph 340 is less than the amplitude 332. On the other hand, with a decrease in the predetermined capacitance of the capacitor 210, an amplitude of oscillations of a square waveform voltage increases.

[0079] In one embodiment, the capacitance of 5 pF is an example of the initial capacitance and the capacitance of 130 pF is an example of the predetermined capacitance.

[0080] In an embodiment, the capacitance of 130 pF is an example of the initial capacitance and the capacitance of 5 pF is an example of the predetermined capacitance

[0081] Figure 4 is an embodiment of a graph 400 to illustrate that with an increase in the predetermined capacitance, an amplitude of oscillations of a square waveform voltage decreases. The graph 400 plots an amplitude of voltage of oscillations of the square waveform voltage 101 (Figure 1) on a y-axis and an amount of the predetermined capacitance on an x-axis. The graph 400 includes a plot 402, which has a negative slope. As illustrated by the negative slope of the plot 402, with an increase in the predetermined capacitance, an amplitude of oscillations of the square waveform voltage 101 decreases. On the other hand, as illustrated by the negative slope of the plot 402, with a decrease in the predetermined capacitance, an amplitude of oscillations of the square waveform voltage 101 increases.

[0082] Figure 5A is an embodiment of a graph 500 and Figure 5B is an embodiment of the graph 320 to illustrate that with an increase in an amplitude of oscillations of the square waveform voltage 101 (Figure 1), wide ion energy distribution is achieved. The graph 500 plots ion energy, measured in electron volts (eV), on a y-axis and an ion count on an x-axis. The graph 500 includes a plot 502 of wide ion energy distribution.

[0083] Figure 5C is an embodiment of a graph 550 and Figure 5D is an embodiment of the graph 340 to illustrate that with a decrease in an amplitude of oscillations of the square waveform voltage 101 (Figure 1), narrow ion energy distribution is achieved. The graph 550 plots ion energy on a y-axis and an ion count on an x-axis. The graph 550 includes a plot 552 of narrow ion energy distribution.

[0084] As illustrated from the graphs 5A through 5D, when the amplitude 332 decreases to the amplitude 352, the wide ion energy distribution of the plot 502 is modified to achieve the narrow ion energy distribution of the plot 552. For example, a first range of ion energies of thewide ion energy distribution that is achieved during a time period of application of the amplitude 332 of the oscillations 330 to the lower electrode is greater than a second range of ion energies. The second range of ion energies of the narrow ion energy distribution is achieved during a time period of application of the amplitude 352 of the oscillations 350 to the lower electrode. It should be noted that the second range of ion energy is less than the first range of ion energy. Also, as illustrated from the graphs 5 A through 5D, when the amplitude 352 increases to the amplitude 332, the narrow ion energy distribution is modified to achieve the wide ion energy distribution.

[0085] When the narrow ion energy distribution is achieved, a first etch rate at which features of the substrate S are etched increases. The etch rate increases compared to a second etch rate achieved using the wide ion energy distribution. The second etch rate is to etch features of the substrate S.

[0086] Figure 6A is a cross-sectional side view of an embodiment of a substrate 600 in which features 602 and 604, such as channels, are formed. The substrate 600 is an example of the substrate S (Figure 1). It should be noted that the features 602 and 604 are formed when a capacitance of the capacitor 210 (Figure 2) is not implemented within the LC circuit 202. For example, the predetermined capacitance of the capacitor 210 is zero. As another example, the LC circuit 202 excludes the capacitor 210.

[0087] Figure 6B is a cross-sectional side view of an embodiment of a substrate 610 in which features 612 and 614, such as channels, are formed. The substrate 610 is an example of the substrate S (Figure 1). It should be noted that the features 612 and 614 are formed when the capacitor 210 (Figure 2) is controlled by the processor 114 (Figure 1) to have the predetermined capacitance of 30 pF. It should be noted that with an increase in the predetermined capacitance from 0 pF to 30 pF, there is an increase etch depths of the features 612 and 614 compared to etch depths of the features 602 and 604 of Figure 6A.

[0088] The increase in the etch depths is a result of an increase in an etch rate. For example, with an increase in the predetermined capacitance from 0 pF to 30 pF, an etch rate with which the features 612 and 614 are etched is greater than an etch rate with which the features 602 and 604 are etched.

[0089] Figure 6C is a cross-sectional side view of an embodiment of a substrate 620 in which features 622 and 624, such as channels, are formed. The substrate 620 is an example of the substrate S (Figure 1). It should be noted that the features 622 and 624 are formed when the capacitor 210 (Figure 2) is controlled by the processor 114 (Figure 1) to have the predetermined capacitance of 120 pF. It should be noted that with an increase in the predetermined capacitancefrom 30 pF to 120 pF, there is an increase in etch depths of the features 622 and 624 compared to etch depths of the features 612 and 614 of Figure 6B.

[0090] The increase in the etch depths is a result of an increase in an etch rate. For example, with an increase in the predetermined capacitance from 30 pF to 120 pF, an etch rate with which the features 622 and 624 are etched is greater than an etch rate with which the features 612 and 614 are etched.

[0091] Each feature of the substrate S is defined by an opening, a left vertical wall, a right vertical wall, a bottom side, and a space between the left and right vertical walls. For example, the feature 622 is formed by an opening 630 at a top of the feature 622, a left vertical wall 626, a right vertical wall 628, and a bottom side 632.

[0092] Figure 7A is an embodiment of the graph 700 to illustrate that with an increase in the predetermined capacitance of the capacitor 210 (Figure 2), there is an increase in an etch rate of etching the substrate S (Figure 1). The graph 700 plots an etch rate, in nanometers (nm) per minute (min) on a y-axis and the predetermined capacitance on an x-axis. The predetermined capacitance is illustrated in arbitrary units (a.u.) in the graph 700. As illustrated from a plot 702 of the graph 700, when the capacitor 210 is controlled by the processor 114 to increase the predetermined capacitance of the capacitor 210, there is an increase in the etch rate with which the substrate S is etched. On the other hand, when the capacitor 210 is controlled by the processor 114 to decrease the predetermined capacitance of the capacitor 210, there is a decrease in the etch rate with which the substrate S is etched.

[0093] Figure 7B is an embodiment of a graph 710 to illustrate that with a change in the predetermined capacitance of the capacitor 210 (Figure 2), a critical dimension (CD ) of a bow of a feature of the substrate S is controlled. For example, when the processor 114 (Figure 1) controls the capacitor 210 to increase the predetermined capacitance of the capacitor 210 to a capacitance Ca, the CD decreases. Also, when the processor 114 controls the capacitor 210 to further increase the predetermined capacitance of the capacitor 210 from the capacitance Ca, the CD increases. As such, an optimal CD, such as a value CDa of the CD corresponding to the capacitance Ca, is achieved by controlling the capacitor 210 to achieve the capacitance Ca. As another example, when the processor 114 controls the capacitor 210 to decrease the predetermined capacitance of the capacitor 210 to the capacitance Ca, the CD decreases. Also, when the processor 114 controls the capacitor 210 to further decrease the predetermined capacitance of the capacitor 210 from the capacitance Ca, the CD increases. Again, the optimal CD is achieved by controlling the capacitor 210 to achieve the capacitance Ca. As shown, the graph 710 plots the CD on a y-axis and the predetermined capacitance on an x-axis. The predetermined capacitance is illustrated in arbitrary units in the graph 710.

[0094] It should be noted that an example of the CD of a feature of the substrate S is a horizontal distance between two oppositely-located vertical walls of the feature. For example, with reference to Figure 6C, an example of the CD of the feature 622 is a distance between the left vertical wall 626 (Figure 6C) and the right vertical wall 628 of the feature 622.

[0095] Figure 8 is a diagram of an embodiment of a system 800 to illustrate details of a pulsed DC source 802. The system 800 includes the pulsed DC source 802, the LC circuit 202, and the plasma chamber 110. The pulsed DC source 802 is an example of the pulsed DC source 104 (Figure 1).

[0096] The pulsed DC source 802 includes a DC voltage source 804, a resistor 806, a resistor 808, and a switch SW1. An example of a switch includes a transistor. The DC voltage source 804 is coupled to an end 810 of the resistor 806. An opposite end 812 of the resistor 806 is coupled to an end 814 of the resistor 808. An opposite end 816 of the resistor 808 is coupled to a terminal 818 of the switch SW1. An opposite terminal 820 of the switch SW1 is coupled to a ground potential. The resistor 808 and the switch SW1 are coupled to each other in series to form a series circuit. The end 814 is coupled to the output 134 of the pulsed DC source 802. The DC voltage source 804 is coupled via the transfer cable 152 to the processor 114. The processor 114 is also coupled to the switch SW1 via a connection 801 to control the switch SW1.

[0097] During the charging phase occurring within a time period of the cycle n, the processor 114 sends an off control signal to the switch SW1 via the connection 801 to open the switch SW1. When the switch SW1 is open, the terminal 816 is disconnected from the terminal 820. The DC voltage source 804 receives the control set point signal 152 from the processor 114 via the transfer cable 152. After receiving the control set point signal 152 indicating the maximum amplitude and the low frequency of the square waveform voltage 101, the DC voltage source 804 generates a DC voltage signal 822 having the maximum amplitude and the low frequency and provides the DC voltage signal 822 to the resistor 806. The DC voltage signal 822 is generated during the charging base.

[0098] The resistor 806 receives the DC voltage signal 822 and modifies an impedance of the DC voltage signal 822 to output the DC voltage signal 124. The DC voltage signal 124 has the maximum amplitude of the square waveform voltage 101 and pulses at the low frequency, and is transferred from the end 812 via the end 814, the output 134, the RF connection. 132, the input 136, and the opposite end 214 of the capacitor 210 to the inductor 208.

[0099] The inductor 208 converts the DC voltage signal 822 into the square waveform voltage 101. For example, during the charging phase, a positive slope of a square pulse of the square waveform voltage 101 is output from the inductor 208 to charge the plasma chamber 110with RF energy to process the substrate S. To illustrate, during the charging phase, the DC voltage signal 822 charges the inductor 208. When the inductor 208 is charged, the positive slope of a square pulse of the square waveform voltage 101 is output from the inductor 208. The positive slope extends to the maximum amplitude indicated within the control set point signal 152.

[0100] After the charging phase, the discharging phase occurs within the time period of the cycle n. During the discharging phase, the processor 114 sends an on control signal to the switch SW1 to close the switch SW1. Upon receiving the on control signal, the terminal 818 of the switch SW 1 connects to the terminal 820 of the switch SW 1 to close the switch SW 1. When the switch SW 1 is closed during the discharging phase, RF energy from the plasma chamber 110 is discharged via the RF transmission line 144, the inductor 208, the RF connection. 132, the end 814, the resistor 808, and the switch SW1 to the ground potential. When the RF energy is discharged, a negative slope of the square waveform voltage 101 is output from the inductor 208 towards the plasma chamber 110 and the negative slope extends from the maximum amplitude to oscillations of the square waveform voltage 101. Also, after the discharging phase, the oscillations of the square waveform voltage 101 are formed within the time period of the cycle n. For example, the inductor 208 outputs the oscillations of the square waveform voltage 101 after the discharging phase. In this manner, the charging phase, the discharging phase, and the oscillations repeat to form a square pulse of the square waveform voltage 101 during the cycle (n+1) of the clock signal.

[0101] In an embodiment, the terms square waveform voltage and square voltage waveform are used herein interchangeably. In one embodiment, the terms modified square waveform voltage and modified square voltage waveform are used herein interchangeably.

[0102] Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessorbased or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0103] In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the“controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and / or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with the system.

[0104] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0105] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0106] In some embodiments, a remote computer (e.g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that arenetworked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

[0107] Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and / or manufacturing of semiconductor wafers.

[0108] It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a capacitively-coupled plasma (CCP) chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, a pulsed DC source is coupled to an RF coil within the ICP plasma chamber.

[0109] As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0110] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are those that manipulate physical quantities.

[0111] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0112] In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in a computer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0113] One or more embodiments, described herein, can also be fabricated as computer- readable code on a non-transitory computer-readable medium. The non-transitory computer- readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non- transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[0114] Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[0115] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[0116] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

CLAIMS1. A system comprising: a pulsed direct current (DC) source configured to generate a DC voltage signal; an inductor-capacitor (LC) circuit coupled to the pulsed DC source to receive the DC voltage signal to output a square waveform voltage; a high frequency (HF) radio frequency (RF) generator configured to generate an RF waveform; an impedance matching circuit coupled to the HF RF generator to receive the RF waveform to output a modified RF waveform, wherein the LC circuit is coupled to the impedance matching circuit at a point to combine the modified RF waveform with the square waveform voltage, wherein the modified RF waveform is combined with the square waveform voltage to output a modified square waveform voltage; and a plasma chamber coupled to the point to receive the modified square waveform voltage.

2. The system of claim 1, further comprising: a controller coupled to the LC circuit to modify an amplitude of a plurality of oscillations of the square waveform voltage.

3. The system of claim 2, wherein the inductor-capacitor circuit includes an inductor and a shunt capacitor, wherein the controller is configured to increase a capacitance of the shunt capacitor to decrease the amplitude of the plurality of oscillations to achieve a narrow ion energy distribution, wherein the narrow ion energy distribution is achieved to increase a rate of etching features within a substrate.

4. The system of claim 2, wherein the inductor-capacitor circuit includes an inductor and a shunt capacitor, wherein the controller is configured to decrease a capacitance of the shunt capacitor to increase the amplitude of plurality of oscillations to achieve a wide ion energy distribution.

5. The system of claim 1, wherein the inductor-capacitor circuit includes an inductor and a capacitor, wherein the capacitor is a shunt capacitor.

6. The system of claim 5, wherein the shunt capacitor is coupled to a ground potential at one end and to the inductor and the pulsed DC source at an opposite end.

7. The system of claim 1, wherein the LC circuit is coupled to the impedance matching circuit and the plasma chamber via one or more RF straps.

8. A system comprising: an inductor-capacitor (LC) circuit configured to be coupled to a pulsed direct current (DC) source to receive a DC voltage signal from the pulsed DC source to output a square waveform voltage; anda controller coupled to the LC circuit to modify an amplitude of a plurality of oscillations of the square waveform voltage.

9. The system of claim 8, wherein during a first cycle of a clock signal, the square waveform voltage has a positive slope during a charging phase, a negative slope during a discharging phase, and the plurality of oscillations, wherein during a second cycle of the clock signal, the square waveform voltage has a positive slope during the charging phase, a negative slope during the discharging phase, and a plurality of oscillations, wherein the plurality of oscillations during the first cycle occur between an occurrence of the negative slope during the first cycle and the positive slope during the second cycle.

10. The system of claim 8, wherein the inductor-capacitor circuit includes an inductor and a shunt capacitor, wherein the controller is configured to increase a capacitance of the shunt capacitor to decrease the amplitude of the plurality of oscillations to achieve a narrow ion energy distribution, wherein the narrow ion energy distribution is achieved to increase a rate of etching features within a substrate.

11. The system of claim 8, wherein the inductor-capacitor circuit includes an inductor and a shunt capacitor, wherein the controller is configured to decrease a capacitance of the shunt capacitor to increase the amplitude of the plurality of oscillations to achieve a wide ion energy distribution.

12. The system of claim 8, wherein the inductor-capacitor circuit includes an inductor and a capacitor, wherein the capacitor is a shunt capacitor.

13. The system of claim 12, wherein the shunt capacitor is configured to be coupled to a ground potential at one end and to the inductor and the pulsed DC source at an opposite end.

14. The system of claim 8, wherein the LC circuit is configured to be coupled to a plasma chamber and an impedance matching circuit via one or more RF straps.

15. A controller comprising: a memory device; and a processor coupled to the memory device, wherein the processor is configured to be coupled to an inductor-capacitor (LC) circuit that is coupled to a pulsed direct current (DC) source, wherein the LC circuit is coupled to the pulsed DC source to receive a DC voltage signal from the pulsed DC source to output a square waveform voltage, wherein the processor is configured to modify an amplitude of a plurality of oscillations of the square waveform voltage.

16. The controller of claim 15, wherein during a first cycle of a clock signal, the square waveform voltage has a positive slope during a charging phase, a negative slope during a discharging phase, and the plurality of oscillations, wherein during a second cycle of the clock signal, the square waveform voltage has a positive slope during the charging phase, a negative slope during the discharging phase, and a plurality of oscillations, wherein the plurality of oscillations during the first cycle occur between an occurrence of the negative slope during the first cycle and the positive slope during the second cycle.

17. The controller of claim 15, wherein the inductor-capacitor circuit includes an inductor and a shunt capacitor, wherein the processor is configured to increase a capacitance of the shunt capacitor to decrease the amplitude of the plurality of oscillations to achieve a narrow ion energy distribution, wherein the narrow ion energy distribution is achieved to increase a rate of etching features within a substrate.

18. The controller of claim 15, wherein the inductor-capacitor circuit includes an inductor and a shunt capacitor, wherein the processor is configured to decrease a capacitance of the shunt capacitor to increase the amplitude of the plurality of oscillations to achieve a wide ion energy distribution.

19. The system of claim 15, wherein the inductor-capacitor circuit includes an inductor and a capacitor, wherein the capacitor is a shunt capacitor.

20. The system of claim 19, wherein the shunt capacitor is configured to be coupled to a ground potential at one end and to the inductor and the pulsed DC source at an opposite end.

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