Semiconductor device

Abstract

A semiconductor device provided in the present application, the device comprising a semiconductor epitaxial wafer, several semiconductor unit cells and a gate bus, wherein the semiconductor epitaxial wafer comprises an active region and an edge terminal region surrounding outside the active region; the several semiconductor unit cells are arranged in the active region, and extend from the active region to the edge of the active region; and the gate bus is disposed on the edge terminal region, surrounds the active region, and is connected to an end of a gate structure in each semiconductor unit cell. Specifically, by means of arranging the gate bus on the edge terminal region and connecting same to an end of each gate structure, the area of the active region is saved, such that the semiconductor device consists essentially of the active region apart from the edge terminal region, thereby improving the current-carrying capability of the device and reducing on-resistance, without affecting the reliability of the device.

Description

Semiconductor device TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device. BACKGROUND

[0002] As the core component in power electronic system, power semiconductor device is an important electronic component indispensable to modern life, which is widely used in consumer electronics, automotive electronic system, smart grid, various industrial equipment, locomotive, aerospace and ship system. SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) device has become the mainstream device in high-voltage and high-frequency field due to its high input impedance, good temperature stability, excellent high-frequency and high-voltage performance, and large safe working area.

[0003] In order to further improve the current-carrying capacity of SiC MOSFET and reduce the on-resistance, optimization can be made from multiple aspects. Among them, increasing the active area under the same chip size is the most simple method. TECHNICAL SOLUTION

[0004] The semiconductor device provided by the present application can increase the active area, thereby improving the current-carrying capacity of the device and reducing the on-resistance.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a semiconductor device, which comprises:

[0006] A semiconductor epitaxial wafer, comprising an active area and an edge termination area surrounding the active area;

[0007] A plurality of semiconductor cells are arranged in the active area, each semiconductor cell comprising a well region, a well region contact region and a source region arranged in the semiconductor epitaxial wafer, and a gate structure arranged on the semiconductor epitaxial wafer and located between two adjacent source regions, wherein the well region, the well region contact region and the source region extend along the surface of the semiconductor epitaxial wafer in the semiconductor epitaxial wafer; the semiconductor cell extends from the active area to the edge of the active area;

[0008] A gate bus is arranged on the edge termination area, and the gate bus surrounds the active area and is connected to the end of each gate structure.

[0009] To solve the above technical problems, another technical solution adopted by the present application is to provide a semiconductor device, which comprises:

[0010] A semiconductor epitaxial wafer, comprising an active area and an edge termination area surrounding the active area;

[0011] a plurality of semiconductor cells arranged in the active region, each of the semiconductor cells extending from the active region to an edge of the active region along a first direction, the semiconductor cells being arranged in a second direction with a spacing between each of the semiconductor cells, each of the semiconductor cells comprising a well region arranged in the semiconductor epi wafer, a well contact region, a source region, and a gate structure arranged on the semiconductor epi wafer between adjacent two of the source regions, the well region, the well contact region, and the source region extending along a surface of the semiconductor epi wafer along the semiconductor epi wafer;

[0012] a gate bus arranged on the edge termination region and surrounding the active region, the gate bus being connected to the gate structure in the first direction and being arranged with a spacing from the gate structure in the second direction.

[0013] Compared with the prior art, the semiconductor device provided by the application has the advantages that the semiconductor device comprises a semiconductor epi wafer, a plurality of semiconductor cells, and a gate bus, wherein the semiconductor epi wafer comprises an active region and an edge termination region surrounding the active region; the plurality of semiconductor cells are arranged in the active region and extend from the active region to an edge of the active region; and the gate bus is arranged on the edge termination region and surrounds the active region and is connected to an end of the gate structure in each of the semiconductor cells. Specifically, the gate bus is arranged on the edge termination region and connected to the end of each of the gate structures, thereby saving the area of the active region, so that the semiconductor device is basically the active region except for the edge termination region, thereby improving the current-carrying capacity of the device, reducing the on-resistance, and not affecting the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0015] FIG. 1 is a top view of some embodiments of the semiconductor device provided by the application;

[0016] FIG. 2 is a partial structure sectional view of the semiconductor device shown in FIG. 1 along line A-A;

[0017] FIG. 3 is a partial structure sectional view of the semiconductor device shown in FIG. 1 along line B-B;

[0018] FIG. 4 is a partial structure sectional view of the semiconductor device shown in FIG. 1 along line C-C;

[0019] Fig. 5 is a partial structure top view of the semiconductor device shown in Fig. 1 ;

[0020] Fig. 6 is a flowchart of some embodiments of the semiconductor device provided by the present application;

[0021] Fig. 7 is a partial intermediate product structure schematic diagram after step S1 in Fig. 6;

[0022] Fig. 8 is a partial intermediate product structure schematic diagram after step S2 in Fig. 6;

[0023] Fig. 9 is a partial intermediate product structure schematic diagram after step S3 in Fig. 6;

[0024] Fig. 10 is a product top view shown in Fig. 9;

[0025] Fig. 11 is a partial intermediate product structure schematic diagram after step S4 in Fig. 6;

[0026] Fig. 12 is a partial intermediate product structure schematic diagram after step S5 in Fig. 6;

[0027] Fig. 13 is a product top view shown in Fig. 12;

[0028] Fig. 14 is a partial intermediate product structure schematic diagram after step S6 in Fig. 6;

[0029] Fig. 15 is a partial intermediate product structure schematic diagram after step S7 in Fig. 6;

[0030] Fig. 16 is a partial intermediate product structure schematic diagram after step S8 in Fig. 6;

[0031] Fig. 17 is a product top view shown in Fig. 16;

[0032] Fig. 18 is a partial intermediate product structure schematic diagram after step S9 in Fig. 6;

[0033] Fig. 19 is a product top view shown in Fig. 18;

[0034] Fig. 20 is a partial intermediate product structure schematic diagram after step S10 in Fig. 6;

[0035] Fig. 21 is a product top view shown in Fig. 20;

[0036] Fig. 22 is a partial product structure schematic diagram after step S11 in Fig. 6.

[0037] BRIEF DESCRIPTION OF DRAWINGS

[0038] semiconductor epitaxial wafer-10; semiconductor cell-20; well region-21; well region contact region-22; source region-23; gate structure-24; first gate oxide layer-241; first gate layer-242; gate bus-30; dielectric layer-31; second gate layer-32; termination structure-40; pad structure-50; source pad-51; first source pad-511; second source pad-512; gate pad-52; first gate pad-521; second gate pad-522; first pad part-5221; second pad part-5222; drain pad-53; first dielectric layer-60; ohmic contact metal-70; second dielectric layer-80;

[0039] active region-A1; edge termination region-A2; first opening-H1; second opening-H2; third opening-H3; fourth opening-H4; notch-H5. Embodiments of the present application

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0041] The terms “first”, “second”, “third” in the present application are only used for description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second”, “third” can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of “plurality” is at least two, for example, two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0042] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0043] The application will be described in detail below with reference to the accompanying drawings and embodiments.

[0044] Referring to FIG. 1-4, FIG. 1 is a top view of some embodiments of the semiconductor device provided by the application; FIG. 2 is a partial structural sectional view of the semiconductor device shown in FIG. 1 along line A-A; FIG. 3 is a partial structural sectional view of the semiconductor device shown in FIG. 1 along line B-B; FIG. 4 is a partial structural sectional view of the semiconductor device shown in FIG. 1 along line C-C; and FIG. 5 is a partial structural top view of the semiconductor device shown in FIG. 1.

[0045] The application provides a semiconductor device, which includes a semiconductor epitaxial wafer 10, a plurality of semiconductor cells 20, and a gate bus 30.

[0046] The semiconductor epitaxial wafer 10 includes an active region A1 and an edge termination region A2 surrounding the active region A1; the plurality of semiconductor cells 20 are arranged in the active region A1, and each semiconductor cell 20 extends from the active region A1 to the edge of the active region A1; and the edge termination region A2 is provided with a termination structure 40 for protecting the device from overvoltage or overcurrent, etc. The termination structure 40 can be a field limiting ring structure or a junction termination extension (JTE) region, and the functions and structures of the field limiting ring structure and the JTE region are known in the art and will not be described here.

[0047] Referring to FIG. 2, each semiconductor cell 20 includes a well region 21, a well region contact region 22, a source region 23, and a gate structure 24 arranged on the semiconductor epitaxial wafer 10 and located between adjacent source regions 23. The well region 21, the well region contact region 22, and the source region 23 all extend along the surface of the semiconductor epitaxial wafer 10.

[0048] The semiconductor epitaxial wafer 10 and the source region 23 have a first conductivity type, and the ion doping concentration of the source region 23 is greater than the ion doping concentration of the semiconductor epitaxial wafer 10; the well region 21 and the well region contact region 22 have a second conductivity type, and the ion doping concentration of the well region contact region 22 is greater than the ion doping concentration of the well region 21.

[0049] The first conductive type can be one of N type or P type, and the second conductive type can be the other of N type or P type. In this application, the first conductive type is taken as N type, and the second conductive type is taken as P type as an example.

[0050] In combination with FIGS. 2-5, the gate bus line 30 is arranged on the edge terminal area A2, and surrounds the active area A1 and is connected to the end of each gate structure 24.

[0051] In some embodiments, in combination with FIGS. 3 and 5, each semiconductor cell 20 extends from the active area A1 to the edge of the active area A1 in the first direction, and a plurality of semiconductor cells 20 are arranged in the second direction, and in the first direction, the gate bus line 30 is connected to each gate structure 24, specifically, the gate bus line 30 is connected to the end of each gate structure 24 in the first direction, and in the second direction, the gate bus line 30 is arranged apart from the plurality of semiconductor cells 20.

[0052] Specifically, in the embodiments of this application, the gate bus line 30 is arranged on the edge terminal area A2, compared with the prior art in which the gate bus line 30 is arranged on the active area A1, the area of the active area A1 can be saved, so that the semiconductor device is basically the active area A1 except for the edge terminal area A2, thereby the current-carrying capacity of the device can be improved, and the on-resistance can be reduced, and the gate bus line 30 is connected to the end of each gate structure 24 extending to the edge of the active area A1, the gate bus line 30 can drive the gate structure 24 in each semiconductor cell 20, thereby the reliability of the device is not affected.

[0053] In some embodiments, referring to FIG. 2, each gate structure 24 includes a first gate oxide layer 241 and a first gate layer 242, and the first gate oxide layer 241 isolates the first gate layer 242 from the semiconductor epitaxial wafer 10, the well region 21, the well region contact area 22 and / or the source region 23.

[0054] The gate bus line 30 includes a dielectric layer 31 and a second gate layer 32, the dielectric layer 31 is located on the edge terminal area A2 and arranged on the semiconductor epitaxial wafer 10, and the second gate layer 32 is arranged on the surface of the dielectric layer 31 away from the semiconductor epitaxial wafer 10, and the second gate layer 32 is connected to the end of the first gate layer 242 in each gate structure 24.

[0055] In some embodiments, the materials of the first gate oxide layer 241 and the dielectric layer 31 can be silicon oxide or silicon nitride, etc., which are not limited herein, as long as the first gate layer 242 and the second gate layer 32 can be dielectrically isolated from the semiconductor epitaxial wafer 10. The materials of the first gate layer 242 and the second gate layer 32 can be polysilicon or conductive metal, which are not limited herein, as long as they have the function of conducting electricity.

[0056] In some embodiments, the first gate oxide layer 241 has a thickness of 30-60 nm. For example, the first gate oxide layer 241 can have a thickness of 30 nm, 40 nm, 50 nm, or 60 nm, etc., without limitation.

[0057] In some embodiments, the dielectric layer 31 has a thickness greater than that of the first gate oxide layer 241.

[0058] In some embodiments, the first gate layer 242 and the second gate layer 32 have the same thickness, and the thickness is 200-1000 nm. For example, the first gate layer 242 and the second gate layer 32 can each have a thickness of 200 nm, 400 nm, 600 nm, 800 nm, or 1000 nm, etc., without limitation.

[0059] It should be noted that the specific thicknesses of the first gate oxide layer 241, the dielectric layer 31, the first gate layer 242, and the second gate layer 32 are designed according to the actual device size.

[0060] Of course, based on actual needs, in other embodiments, the thicknesses of the first gate oxide layer 241, the dielectric layer 31, the first gate layer 242, and the second gate layer 32 can be greater than or less than the above thickness range.

[0061] The thickness direction is the direction from the epitaxial wafer 10 to the first gate oxide layer 241.

[0062] Specifically, the second gate layer 32 surrounds the active region A1, and each first gate layer 242 extends to the edge of the active region A1 and is connected to the second gate layer 32.

[0063] The semiconductor device can be a planar gate semiconductor device or a trench gate semiconductor device. When the semiconductor device is a planar gate semiconductor device, referring to FIG. 2, the first gate oxide layer 241 is disposed on the surface of the semiconductor epitaxial wafer 10, the first gate layer 242 is disposed on the surface of the first gate oxide layer 241 away from the semiconductor epitaxial wafer 10, the first gate oxide layer is used to isolate the first gate layer 242 from the semiconductor epitaxial wafer 10, and when the first gate oxide layer 241 and the first gate layer 242 are also disposed on the well region 21 and at least part of the well region contact region 22, the first gate oxide layer 241 is also used to isolate the first gate layer 242 from the semiconductor epitaxial wafer 10, the well region 21, and the well region contact region 22. When the semiconductor device is a trench gate semiconductor device, not shown in the figure, the gate structure 24 extends along the surface of the semiconductor epitaxial wafer 10 into the semiconductor epitaxial wafer 10, and the first gate oxide layer 241 wraps the first gate layer 242 to isolate the first gate layer 242 from the semiconductor epitaxial wafer 10, the well region 21, the well region contact region 22, and the source region 23.

[0064] As shown in FIGS. 2-4, the present application takes the semiconductor device as an example of a planar gate semiconductor device, and the first gate layer 242 and the second gate layer 32 are arranged in the same layer. Specifically, the first gate layer 242 and the second gate layer 32 are arranged in the same layer, so that the first gate layer 242 and the second gate layer 32 can be formed in the same process step, thereby simplifying the process step and reducing the cost.

[0065] In some embodiments, referring to FIG. 2, the semiconductor device further includes a pad structure 50 for electrically connecting the device with external equipment, and the pad structure 50 includes a source pad 51, a gate pad 52, and a drain pad 53.

[0066] The material of the source pad 51, the gate pad 52, and the drain pad 53 includes but is not limited to any one or a combination of multiple of aluminum, copper, tungsten, silver, or nickel.

[0067] The source pad 51 is arranged corresponding to the active area A1, and the source pad 51 is ohmically connected with each source region 23 and is insulated from each gate structure 24; the gate pad 52 is at least partially arranged in the edge termination area A2 and is connected with the gate bus 30, and the gate pad 52 is insulated from the source pad 51; and the drain pad 53 is arranged on the side of the semiconductor epitaxial wafer 10 away from the source pad 51 and the gate pad 52.

[0068] In some embodiments, the gate pad 52 can be completely arranged in the edge termination area A2, or at least part of the gate pad 52 extends to the active area A1 and is insulated from the source pad 51, which can be designed as needed.

[0069] In some embodiments, referring to FIG. 2, the semiconductor device further includes a first dielectric layer 60 and a plurality of ohmic contact metals 70.

[0070] In some embodiments, the material of the first dielectric layer 60 can be silicon oxide or silicon nitride, and the thickness of the first dielectric layer 60 is 0.4-1.2 μm. For example, the thickness of the first dielectric layer 60 can be 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, or 1.2 μm, etc., which is not limited herein. The actual device size is designed accordingly.

[0071] In some embodiments, the material of the ohmic contact metal 70 includes but is not limited to any one or a combination of multiple of Ti, Ni, Al, Au, Ta, or W.

[0072] The first dielectric layer 60 covers each gate structure 24 to isolate the gate structures 24, and the first dielectric layer 60 has a first opening H1 corresponding to each source region 23 to expose the source region 23 through the first opening H1. An ohmic contact metal 70 is arranged in each first opening H1 to form an ohmic contact with the source region 23. The source pad 51 includes a first source pad 511 arranged on the first dielectric layer 60 and extending into the first opening H1 to connect with the ohmic contact metal 70.

[0073] Further, the first dielectric layer 60 also covers the gate bus 30 to isolate the gate bus 30, and the first dielectric layer 60 has a second opening H2 corresponding to the gate bus 30 to expose at least part of the gate bus 30 through the second opening H2. The gate pad 52 includes a first gate pad 521 arranged on the first dielectric layer 60 of the edge terminal region A2 and surrounding the active region A1, and the first gate pad 521 also extends into the second opening H2 to connect with the gate bus 30.

[0074] Specifically, the first source pad 511 and the first gate pad 521 are used for electrical connection between the device and an external device.

[0075] In some embodiments, the first source pad 511 and the first gate pad 521 have the same thickness, and the thickness is 0.4 μm-5 μm. For example, the thickness of the first source pad 511 and the first gate pad 521 is 0.4 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm, etc., which is not limited herein and is designed according to the actual device size.

[0076] In some embodiments, referring to FIG. 2, in order to improve the heat conduction efficiency and mechanical strength, the source pad 51 further includes a second source pad 512 arranged on a side of the first source pad 511 away from the semiconductor epitaxial wafer 10 and connected with the first source pad 511. The gate pad 52 further includes a second gate pad 522 arranged on a side of the first gate pad 521 away from the semiconductor epitaxial wafer 10 and connected with the first gate pad 521. The second gate pad 522 at least partially corresponds to the edge terminal region A2.

[0077] In some embodiments, the second gate pad 522 can be completely arranged in the edge terminal region A2, or referring to FIGS. 1 and 2, at least part of the second gate pad 522 also extends to the active region A1 and is insulated from the source pad 51.

[0078] Specifically, the specific structure of the second gate pad 522 is designed based on the process allowance and the packaging wire allowance. If the area of the second gate pad 522 located in the edge terminal area A2 can meet the packaging wire requirement of the device, the second gate pad 522 does not need to extend into the active area A1. In the embodiment of the present application, at least part of the second gate pad 522 extends into the active area A1, which can meet the packaging wire requirement of the small-size device and will not affect the proportion of the active area A1.

[0079] In addition, the edge terminal area A2 can be used as the connection area of the first gate pad 521 and the second gate pad 522, and can also be provided with a resistor (not shown in the figure) as the series resistor of the first gate pad 521 and the second gate pad 522, so as to adjust the Rg without considering the area limitation too much.

[0080] In some embodiments, referring to FIG. 1, the second source pad 512 has a notch H5 on the side close to the gate pad 52, the second gate pad 522 includes a first pad part 5221 and a second pad part 5222 connected with each other, the first pad part 5221 is located in the edge terminal area A2, and the second pad part 5222 is arranged in the active area A1 and extends into the notch H5.

[0081] Specifically, by arranging the second source pad 512 with the notch H5 and extending the second pad part 5222 into the notch H5, the area of the second source pad 512 and the second gate pad 522 can be ensured to meet the packaging wire requirement to a large extent.

[0082] In some embodiments, referring to FIG. 2, the semiconductor device further includes a second dielectric layer 80, the second dielectric layer 80 covers the first source pad 511 to isolate the first source pad 511, and the area of the second dielectric layer 80 corresponding to the first source pad 511 has a third opening H3 to expose part of the first source pad 511 through the third opening H3; wherein the second source pad 512 is arranged on the second dielectric layer 80 and extends into the third opening H3 and is connected with the first source pad 511.

[0083] Further, the second dielectric layer 80 also covers the first gate pad 521 to isolate the first gate pad 521, and the area of the second dielectric layer 80 corresponding to the first gate pad 521 has a fourth opening H4 to expose part of the first gate pad 521 through the fourth opening H4; wherein the second gate pad 522 is arranged on the second dielectric layer 80 and extends into the fourth opening H4 and is connected with the first gate pad 521.

[0084] In other embodiments, the first gate pad 521 and the second gate pad 522 are connected and arranged in the same layer (not shown), specifically, the first gate pad 521 and the second gate pad 522 can be arranged on the first dielectric layer 60, and the second pad structure 50 is connected with the gate bus 30 through the first pad structure 50. Specifically, the second source pad 512 and the gate pad 52 (the first gate pad 521 and the second gate pad 522) are designed in staggered layers, so that the area of the second source pad 512 can be set to be larger than the area of the gate pad 52, and the second source pad 512 and the first source pad 511 combine to form the source pad 51, so that the area of the active region A1 can be increased by increasing the area of the second source pad 512, thereby improving the current output capability of the device and reducing the on-resistance.

[0085] Specifically, the semiconductor device provided by the embodiments of the present application can save the area of the active region A1 by arranging the gate bus 30 on the edge terminal region A2, compared with arranging the gate bus 30 on the active region A1 in the prior art, so that the semiconductor device is basically composed of the active region A1 except for the edge terminal region A2, thereby improving the current output capability of the device and reducing the on-resistance, and the gate bus 30 is connected with the end of each gate structure 24 extending to the edge of the active region A1, so that the gate bus 30 can drive the gate structure 24 in each semiconductor cell 20, thereby not affecting the reliability of the device. In addition, the edge terminal region A2 can also be provided with a series resistor, so as to adjust the Rg without considering the limitation of the occupied area.

[0086] Referring to FIGS. 6-22, FIG. 6 is a flow diagram of some embodiments of the semiconductor device provided by the present application; FIG. 7 is a schematic diagram of a partial intermediate product structure after step S1 in FIG. 6; FIG. 8 is a schematic diagram of a partial intermediate product structure after step S2 in FIG. 6; FIG. 9 is a schematic diagram of a partial intermediate product structure after step S3 in FIG. 6; FIG. 10 is a top view of the product shown in FIG. 9; FIG. 11 is a schematic diagram of a partial intermediate product structure after step S4 in FIG. 6; FIG. 12 is a schematic diagram of a partial intermediate product structure after step S5 in FIG. 6; FIG. 13 is a top view of the product shown in FIG. 12; FIG. 14 is a schematic diagram of a partial intermediate product structure after step S6 in FIG. 6; FIG. 15 is a schematic diagram of a partial intermediate product structure after step S7 in FIG. 6; FIG. 16 is a schematic diagram of a partial intermediate product structure after step S8 in FIG. 6; FIG. 17 is a top view of the product shown in FIG. 16; FIG. 18 is a schematic diagram of a partial intermediate product structure after step S9 in FIG. 6; FIG. 19 is a top view of the product shown in FIG. 18; FIG. 20 is a schematic diagram of a partial intermediate product structure after step S10 in FIG. 6; FIG. 21 is a top view of the product shown in FIG. 20; and FIG. 22 is a schematic diagram of a partial product structure after step S11 in FIG. 6.

[0087] The application further provides a preparation method of a semiconductor device, comprising:

[0088] Step S1: providing a semiconductor epitaxial wafer 10, wherein the semiconductor epitaxial wafer 10 comprises an active region A1 and an edge termination region A2.

[0089] Specifically, please refer to FIG. 7. In some embodiments, the semiconductor epitaxial wafer comprises a substrate (not shown) and a semiconductor epitaxial layer (not shown) arranged in a stack.

[0090] In some embodiments, the substrate is a SiC substrate, the crystal form is 4H-SiC, and the SiC epitaxial layer is grown on the SiC substrate using a vapor deposition process.

[0091] Step S2: forming a plurality of well regions 21, a plurality of well region contact regions 22 and a plurality of source regions 23 in the active region A1.

[0092] Specifically, please refer to FIG. 8, wherein the plurality of well regions 21, the plurality of well region contact regions 22 and the plurality of source regions 23 all extend along the surface of the semiconductor epitaxial wafer 10 within the semiconductor epitaxial wafer 10; and the plurality of well regions 21, the plurality of well region contact regions 22 and the plurality of source regions 23 extend from the active region A1 to the edge of the active region A1. The plurality of well regions 21 are arranged at intervals, and each well region 21 is provided with a well region contact region 22 and a source region 23 connected thereto.

[0093] Wherein the semiconductor epitaxial wafer 10 and the source region 23 have a first conductivity type, and the ion doping concentration of the source region 23 is greater than the ion doping concentration of the semiconductor epitaxial wafer 10; the well region 21 and the well region contact region 22 have a second conductivity type, and the ion doping concentration of the well region contact region 22 is greater than the ion doping concentration of the well region 21.

[0094] Wherein the first conductivity type can be one of N-type or P-type, and the second conductivity type can be the other of N-type or P-type. In this application, the first conductivity type is taken as N-type, and the second conductivity type is taken as P-type as an example.

[0095] Please continue to refer to FIG. 8, in step S2, a termination structure 40 is also formed in the edge termination region A2 at the same time, for protecting the device from damage caused by overvoltage or overcurrent, etc.

[0096] Step S3: high-temperature activation of the semiconductor epitaxial wafer 10, and forming a dielectric layer 31 on the first surface of the semiconductor epitaxial wafer 10 in the region of the edge termination region A2.

[0097] Specifically, the dielectric material layer can be grown by a thermal oxidation growth method, and then oxidized and annealed at a temperature range of 1200°C-1450°C, for 10-30 min of oxidation time and 30-300 min of annealing time, and finally patterned to form the dielectric layer 31 located in the edge termination region A2.

[0098] Specifically, please refer to FIG. 9 and FIG. 10, wherein the dielectric layer 31 surrounds the active region A1.

[0099] Step S4: Forming a plurality of first gate oxide layers 241 at intervals in the region where the first surface of the semiconductor epitaxial wafer 10 is located in the active region A1.

[0100] Specifically, the first gate oxide layer 241 with a thickness of 30-60 nm can be formed by the same process as forming the dielectric layer 31. Specifically, in the embodiment of the present application, since the thickness of the first gate oxide layer 241 is different from that of the dielectric layer 31, specifically, the thickness of the dielectric layer 31 is greater than that of the first gate oxide layer 241, the first gate oxide layer 241 and the dielectric layer 31 are not formed in the same step.

[0101] The thickness of the first gate oxide layer 241 can be 30 nm, 40 nm, 50 nm or 60 nm, etc., which is not limited here and is designed according to the actual device size.

[0102] Of course, based on actual needs, in other embodiments, the thickness of the first gate oxide layer 241 and other film layers in the present application can be greater than or less than the thickness range of each film layer provided in the embodiment of the present application.

[0103] The thickness direction is the direction from the epitaxial wafer 10 to the first gate oxide layer 241.

[0104] Specifically, please refer to FIG. 11, wherein each of the first gate oxide layers 241 is located between two adjacent source regions 23, and the first gate oxide layer 241 also extends to the edge of the active region A1.

[0105] Step S5: Forming a first gate layer 242 on the first gate oxide layer 241, and forming a second gate layer 32 on the dielectric layer 31.

[0106] In some embodiments, the first gate layer 242 and the second gate layer 32 can be formed in the same step by magnetron sputtering or vapor deposition, and the thickness of the first gate layer 242 and the second gate layer 32 is the same and is 200-1000 nm.

[0107] The thickness of the first gate layer 242 and the second gate layer 32 can be 200 nm, 400 nm, 600 nm, 800 nm or 1000 nm, etc., which is not limited here.

[0108] Specifically, referring to FIG. 12 and FIG. 13, a gate material is formed on the semiconductor epitaxial wafer 10 with the first gate oxide layer 241 and the dielectric layer 31, where the gate material can be polysilicon or conductive metal material, and then the gate material is patterned to form a plurality of first gate layers 242 arranged on the surface of the first gate oxide layer 241 and a second gate layer 32 arranged on the surface of the dielectric layer 31.

[0109] The second gate layer 32 surrounds the active region A1, and the first gate oxide layer 241 extends to the edge of the active region A1 and is connected with the dielectric layer 31.

[0110] The first gate oxide layer 241 and the first gate layer 242 form a gate structure 24, and the gate structure 24, the well region 21, the well region contact region 22, and the source region 23 form a semiconductor cell 20. In this application, each gate structure 24 is located between adjacent source regions 23.

[0111] Step S6: forming a first dielectric layer 60 covering each gate structure 24 and the gate bus 30; where the first dielectric layer 60 has a first opening H1 corresponding to the area of each source region 23, and the first dielectric layer 60 has a second opening H2 corresponding to the area of the gate bus 30.

[0112] In some embodiments, the first dielectric layer 60 is formed by magnetron sputtering or vapor deposition, and the material of the first dielectric layer 60 can be silicon oxide or silicon nitride, etc.

[0113] The thickness of the first dielectric layer 60 is 0.4 μm-1.2 μm. For example, the thickness of the first dielectric layer 60 can be 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, or 1.2 μm, etc., which is not limited herein. The actual device size is designed accordingly.

[0114] Specifically, referring to FIG. 14, the first dielectric layer 60 is used to isolate each gate structure 24 and isolate the gate bus 30.

[0115] The first opening H1 is used to expose each source region 23, and the second opening H2 is used to expose at least part of the gate bus 30.

[0116] Step S7: forming an ohmic contact metal 70 in each first opening H1.

[0117] In some embodiments, the ohmic contact metal 70 is formed in the first opening H1 by evaporation or magnetron sputtering and patterning, and the annealing process temperature range is 800℃-1100℃, and the time range is 60s-300s; the ohmic contact metal 70 can be any one or a combination of Ti, Ni, Al, Au, Ta, or W.

[0118] Please refer to FIG. 15.

[0119] Step S8: Forming the first source pad 511 located in the active area A1 and the first gate pad 521 located at least partially in the edge termination area A2 on the first dielectric layer 60.

[0120] In some embodiments, a metal layer is formed on the first dielectric layer 60 by evaporation or magnetron sputtering, and then patterned to form the first source pad 511 located in the active area A1 and the first gate pad 521 located at least partially in the edge termination area A2.

[0121] Please refer to FIG. 16 and FIG. 17, wherein the first source pad 511 is disposed on the first dielectric layer 60 and extends into each first opening H1 and is connected with the ohmic contact metal 70 in each first opening H1, thereby being connected with each source region 23, and the first gate pad 521 is disposed on the first dielectric layer 60 and extends into the second opening H2 and is connected with the gate bus 30.

[0122] Step S9: Forming a second dielectric layer 80 covering the first source pad 511 and the first gate pad 521; wherein the second dielectric layer 80 has a third opening H3 corresponding to the region of the first source pad 511, and the second dielectric layer 80 has a fourth opening H4 corresponding to the region of the first gate pad 521.

[0123] The second dielectric layer 80 can be formed by the same process as the first dielectric layer 60, which is not described here.

[0124] Please refer to FIG. 18 and FIG. 19, specifically, the second dielectric layer 80 is used to isolate the first source pad 511, and is used to isolate the first gate pad 521.

[0125] Step S10: Forming the second source pad 512 located in the active area A1 and the second gate pad 522 located at least partially in the edge termination area A2 on the second dielectric layer 80.

[0126] The second source pad 512 and the second gate pad 522 can be formed by the same process as the first source pad 511 and the first gate pad 521, which is not described here.

[0127] Please refer to FIG. 20 and FIG. 21, wherein the second source pad 512 is disposed on the second dielectric layer 80 and extends into the third opening H3 and is connected with the first source pad 511; the second gate pad 522 is disposed on the second dielectric layer 80 and extends into the fourth opening H4 and is connected with the first gate pad 521.

[0128] And in the embodiment, the second source pad 512 has a notch H5 on the side close to the gate pad 52, the second gate pad 522 comprises a first pad part 5221 and a second pad part 5222 connected with each other, the first pad part 5221 is located in the edge terminal area A2, and the second pad part 5222 is arranged in the active area A1 and extends into the notch H5.

[0129] Specifically, by arranging the second source pad 512 with the notch H5 and the second pad part 5222 extending into the notch H5, the area of the second source pad 512 and the second gate pad 522 can be ensured to meet the packaging wire bonding requirement to a large extent.

[0130] Step S11: forming the drain pad 53 on the side of the semiconductor epitaxial wafer 10 away from the source pad 51 and the gate pad 52.

[0131] In some embodiments, an ohmic contact is first formed on the back of the semiconductor epitaxial wafer 10 (for reference, see step S7), and then a full-area metal layer is formed on the back of the semiconductor epitaxial wafer 10 as the drain pad 53 by means of evaporation or magnetron sputtering.

[0132] For details, see FIG. 22.

[0133] Specifically, the preparation method of the semiconductor device provided in the embodiment of the application can save the area of the active area A1 by arranging the gate bus 30 on the edge terminal area A2, compared with arranging the gate bus 30 on the active area A1 in the prior art, so that the semiconductor device is basically composed of the active area A1 except the edge terminal area A2, thereby improving the current output capability of the device and reducing the on-resistance, and the gate bus 30 is connected with the end of each gate structure 24 extending to the edge of the active area A1, so that the gate bus 30 can drive the gate structure 24 in each semiconductor cell 20, thereby not affecting the reliability of the device.

[0134] The above description is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. A semiconductor device, wherein, The semiconductor device comprises: a semiconductor epitaxial wafer comprising an active region and an edge termination region surrounding the active region; a plurality of semiconductor cells arranged in the active region, each of the semiconductor cells comprising a well region, a well region contact region, a source region arranged in the semiconductor epitaxial wafer, and a gate structure arranged on the semiconductor epitaxial wafer between two adjacent source regions, the well region, the well region contact region, and the source region extending along the surface of the semiconductor epitaxial wafer in the semiconductor epitaxial wafer; the semiconductor cells extending from the active region to the edge of the active region; a gate bus arranged on the edge termination region and surrounding the active region, and connected to the end of each of the gate structures.

2. The semiconductor device of claim 1, wherein, Each of the gate structures comprises a first gate oxide layer and a first gate layer, the first gate oxide layer separating the first gate layer from the semiconductor epitaxial layer, the well region, the well region contact region, and / or the source region; The gate bus comprises: a dielectric layer arranged on the semiconductor epitaxial wafer in the edge termination region; a second gate layer arranged on the surface of the dielectric layer away from the semiconductor epitaxial wafer, and connected to the end of the first gate layer in each of the gate structures.

3. The semiconductor device of claim 2, wherein, The first gate oxide layer is arranged on the surface of the semiconductor epitaxial wafer, and the first gate layer is arranged on the surface of the first gate oxide layer away from the semiconductor epitaxial wafer; the first gate layer is arranged in the same layer as the second gate layer and is spaced apart from the second gate layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein The semiconductor device further comprises: a source pad arranged corresponding to the active region, and ohmically connected to each of the source regions and insulated from each of the gate structures; a gate pad at least partially arranged in the edge termination region and connected to the gate bus, and insulated from the source pad.

5. The semiconductor device of claim 4, wherein, The semiconductor device further comprises: a first dielectric layer covering each of the gate structures and the gate bus; wherein the first dielectric layer has a first opening corresponding to the region of each of the source regions, so that each of the source regions is exposed through the first opening corresponding thereto; and the first dielectric layer has a second opening corresponding to the region of the gate bus, so that at least part of the gate bus is exposed through the second opening; a plurality of ohmic contact metals arranged in each of the first openings, respectively; The source pad comprises a first source pad arranged on the first dielectric layer and extending into each of the first openings and connected to the ohmic contact metals; The gate pad comprises a first gate pad arranged on the first dielectric layer in the edge termination region and surrounding the active region, and extending into the second opening and connected to the gate bus.

6. The semiconductor device of claim 5, wherein, The source pad further comprises a second source pad arranged on the side of the first source pad away from the semiconductor epitaxial wafer and connected to the first source pad; The gate pad further comprises a second gate pad, which is arranged on a side of the first gate pad away from the semiconductor epitaxial wafer and connected with the first gate pad; wherein the second gate pad is arranged at least partially corresponding to the edge termination region.

7. The semiconductor device of claim 6, wherein, The second gate pad further extends to the active region, and the second gate pad is arranged in insulation with the source pad.

8. The semiconductor device according to claim 6 or 7, wherein The semiconductor device further comprises: A second dielectric layer covering the first source pad and the first gate pad, wherein the second dielectric layer has a third opening corresponding to a region of the first source pad, so that part of the first source pad is exposed through the third opening; and the second dielectric layer has a fourth opening corresponding to a region of the first gate pad, so that part of the first gate pad is exposed through the fourth opening; The second source pad is arranged on the second dielectric layer and extends into the third opening and is connected with the first source pad; The second gate pad is arranged on the second dielectric layer and extends into the fourth opening and is connected with the first gate pad.

9. A semiconductor device, wherein, The semiconductor device comprises: A semiconductor epitaxial wafer, comprising an active region and an edge termination region surrounding the active region; A plurality of semiconductor cells arranged in the active region, each semiconductor cell extending from the active region to the edge of the active region in a first direction; the semiconductor cells are arranged in intervals in a second direction, and each semiconductor cell comprises: a well region arranged in the semiconductor epitaxial wafer, a well region contact region, a source region, and a gate structure arranged on the semiconductor epitaxial wafer and located between adjacent two source regions, the well region, the well region contact region and the source region all extend in the semiconductor epitaxial wafer along the surface of the semiconductor epitaxial wafer; A gate bus arranged on the edge termination region and surrounding the active region, in the first direction, the gate bus is connected with the gate structure, and in the second direction, the gate bus is arranged in intervals with the gate structure.

10. The semiconductor device of claim 9, wherein, The semiconductor device further comprises: A source pad arranged corresponding to the active region, and the source pad is ohmically connected with each source region and is arranged in insulation with each gate structure; A gate pad arranged at least partially in the edge termination region and connected with the gate bus, and the gate pad is arranged in insulation with the source pad.

11. The semiconductor device of claim 10, wherein, The semiconductor device further comprises: A first dielectric layer covering each gate structure and the gate bus; wherein the first dielectric layer has a first opening corresponding to a region of each source region, so that each source region is exposed through the first opening corresponding thereto; and the first dielectric layer has a second opening corresponding to a region of the gate bus, so that at least part of the gate bus is exposed through the second opening; A plurality of ohmic contact metals arranged in each first opening, respectively. The source pads include a first source pad disposed on the first dielectric layer and extending into each of the first openings and connected with the ohmic contact metal; The gate pads include a first gate pad disposed on the first dielectric layer of the edge termination region and surrounding the active region, and the first gate pad extends into the second openings and is connected with the gate bus.

12. The semiconductor device of claim 11, wherein, The source pads further include a second source pad disposed on a side of the first source pad away from the semiconductor epitaxial wafer and connected with the first source pad; The gate pads further include a second gate pad disposed on a side of the first gate pad away from the semiconductor epitaxial wafer and connected with the first gate pad; wherein the second gate pad is disposed at least partially corresponding to the edge termination region.

Images