Chiplet, chip module, electronic device, and manufacturing method for chiplet

Abstract

The present application provides a chiplet, a chip module, an electronic device, and a manufacturing method for a chiplet. The chiplet comprises a substrate, an active device, and a passive device. The active device is arranged on a first side of the substrate, the passive device is arranged on a second side of the substrate, and the orthographic projection of the active device on the substrate at least partially overlaps with the orthographic projection of the passive device on the substrate, thereby reducing the sum of the projection areas occupied by the two devices. The chiplet further comprises conductive holes, and the conductive holes include a first conductive hole. The active device comprises a first connecting piece, and the first connecting piece covers one end surface of the first conductive hole and is electrically connected to the first conductive hole; the passive device comprises a second connecting piece, and the second connecting piece covers the other end surface of the first conductive hole and is electrically connected to the first conductive hole. In this way, the first conductive hole is connected to the active device and the passive device. The miniaturization of the chiplet is improved, and thus, the mounting area of the chip module is reduced, the integration level of the electronic device is improved, and the reliability of the connections between the conductive holes and the devices is high.

Description

A core particle, a chip module, an electronic device and a preparation method of the core particle

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202410740873.X, filed on June 7, 2024, and entitled "A core particle, a chip module, an electronic device and a preparation method of the core particle", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of electronic devices, and in particular to a core particle, a chip module, an electronic device and a preparation method of the core particle. BACKGROUND

[0004] With the rapid development of communication technology and the popularity of smart phones, people's demand for mobile terminals is getting higher and higher. In particular, the requirement for the communication capability of mobile terminals is also getting higher and higher. At present, the communication system is becoming more and more complex, the communication frequency band is gradually increasing, and the number of front-end module elements included in the radio frequency chip module is also increasing. However, the internal space of communication terminals such as mobile phones and watches is limited, so there is an urgent need for a radio frequency chip module with a higher degree of miniaturization.

[0005] At present, the size of the radio frequency chip module is mainly reduced from the aspects of packaging method and device size, and with the increasing demand for miniaturization of the radio frequency chip module, the current radio frequency chip module still needs to be further miniaturized. SUMMARY

[0006] The present application provides a core particle, a chip module, an electronic device and a preparation method of the core particle, which improves the miniaturization degree of the core particle. In particular, the projection area of the core particle on the substrate is reduced, so that the area of the substrate of the chip module is smaller, thereby reducing the installation area of the chip module and improving the integration of the electronic device. In addition, the connection reliability between the conductive hole and the devices on both sides is high.

[0007] In a first aspect, the present application provides a chiplet, which has two devices on two sides thereof and is connected by a first conductive hole in the interior of the chiplet. Specifically, the chiplet includes a substrate, an active device, and a passive device. The substrate includes a first side and a second side facing away from each other, the active device is arranged on the first side of the substrate, and the passive device is arranged on the second side of the substrate. That is, the active device and the passive device are arranged on the two sides of the substrate facing away from each other, and the projection of the active device on the substrate and the projection of the passive device on the substrate at least partially overlap, thereby reducing the total projection area occupied by the two devices. The chiplet further includes a conductive hole, which includes the first conductive hole. The active device includes a first connecting piece covering an end surface of one end of the first conductive hole and electrically connected to the first conductive hole. The passive device includes a second connecting piece covering an end surface of the other end of the first conductive hole and electrically connected to the first conductive hole. Thus, the first conductive hole connects the active device and the passive device.

[0008] The projection of the active device on the substrate and the projection of the passive device on the substrate at least partially overlap, and the projection of the first conductive hole on the substrate is completely located within the projection of the first connecting piece on the substrate and the projection of the second connecting piece on the substrate. The preparation space of the chiplet is fully utilized, which is conducive to improving the miniaturization degree of the chiplet. In particular, the projection area of the chiplet on the substrate is reduced, the area of the substrate of the chip module is smaller, and the installation area of the chip module is reduced. In addition, the first connecting piece covers the end surface of one end of the first conductive hole, and the second connecting piece covers the end surface of the other end of the first conductive hole, which improves the connection area of the first conductive hole with the first connecting piece and the second connecting piece, and the connection reliability is higher. In addition, this connection method will not damage the first connecting piece or the second connecting piece due to the preparation of the first conductive hole, which is also conducive to improving the connection reliability.

[0009] In a further embodiment, the side of the active device facing away from the substrate is provided with a wiring layer, and the wiring layer is electrically connected to the first connecting piece, so that the wiring layer is connected to the active device through the first conductive hole and the second connecting piece, that is, the wiring layer can also be connected to the passive device. The side of the wiring layer facing away from the first connecting piece is connected to a solder column for electrical connection with the substrate to realize flip-chip of the chiplet. In the present application, any two of the projection of the active device on the substrate, the projection of the passive device on the substrate, and the projection of the solder column on the substrate at least partially overlap. Thus, the volume of the chiplet is further reduced, the integration of the chip module is improved, and the area occupied by the installation of the chip module is reduced.

[0010] The conductive hole of the chiplet can further include a second conductive hole connecting the passive device and the wiring layer. In this scheme, the passive device can be directly connected to the wiring layer without passing through the active device. For example, the second conductive hole can be used to realize grounding of the passive device.

[0011] In the implementation of the connection between the second conductive hole and the passive device and the wiring layer, the passive device can further include a second connecting piece connected with the second conductive hole, and the second connecting piece covers the end surface of the second conductive hole, so as to improve the connection reliability of the two.

[0012] Similarly, in the implementation of the connection between the second conductive hole and the wiring layer, the wiring layer can further include a third connecting piece connected with the second conductive hole, and the third connecting piece covers the end surface of the second conductive hole, so as to improve the connection reliability of the two.

[0013] In the embodiment, the conductive hole is filled with a metal column, that is, the conductive hole is a solid conductive hole. The end surface of the solid conductive hole is a flat end surface, which is conducive to the preparation and formation of the first connecting piece and / or the second connecting piece on the end surface of the conductive hole. In addition, it is conducive to improving the connection area of the first connecting piece and the conductive hole, and the connection area of the second connecting piece and the conductive hole, so as to improve the connection reliability of the conductive hole and the first connecting piece and the second connecting piece, and improve the connection reliability of the active device and the passive device.

[0014] In some embodiments, due to special process requirements and the like, the conductive hole can also be a hollow conductive hole.

[0015] The active device is arranged close to the substrate, which is conducive to heat dissipation of the active device, and is conducive to shortening the length of the circuit, reducing the loss of the transmission path, and improving the performance of the active device.

[0016] Specifically, the active device can include at least one of a power amplifier, a low-noise amplifier, and a radio frequency switch; and the passive device includes at least one of a filter, a capacitor device, an inductor device, a balun device, a matching element, or an integrated circuit of the passive device. The active device and the passive device can be designed according to the specific structure and requirements of the chip module. The core grain in the technical solution can be a core grain in a radio frequency chip module, which is used to realize the transceiving function of an antenna.

[0017] Specifically, the active device further includes an active device body, the active device body is arranged in the same layer as the first connecting piece, and the active device body is electrically connected with the first connecting piece. The passive device further includes a passive device body, the passive device body is arranged in the same layer as the second connecting piece, and the passive device body is electrically connected with the second connecting piece. The first conductive hole between the first connecting piece and the second connecting piece is used to realize the electrical connection between the active device and the passive device. In this embodiment, an additional wiring layer is not needed to connect the active device and the passive device, which is conducive to reducing the volume of the core grain, and further improving the integration of the chip module and reducing the installation area of the chip module.

[0018] The passive device can be provided with the second connection piece in various ways. For example, the passive device can include a passive device body including a metal piece that is multiplexed as the second connection piece. In this technical solution, part of the structure of the passive device body is used as the second connection piece, which is advantageous for further reducing the volume of the core particle and improving the integration of the core particle.

[0019] Alternatively, the second connection piece can be provided independently of the passive device body, but the second connection piece is directly connected to one end of the passive device body, that is, the passive device body and the second connection piece are connected without using a wire or other structure, which is also advantageous for reducing the volume of the core particle and improving the integration of the core particle.

[0020] Alternatively, the second connection piece is provided independently of the passive device body, and the second connection piece is electrically connected to the passive device body through a wire. In this solution, the position of the second connection piece is relatively flexible, and the position of the second connection piece can be selected and designed according to actual needs.

[0021] In a second aspect, the application further provides a chip module. The chip module includes a substrate and the core particle provided in the first aspect, and the core particle is fixed to the substrate and electrically connected to the circuit of the substrate. In the specific technical solution, the core particle can be packaged with the substrate. Since the core particle has high integration and occupies a small area of the substrate, the integration of the chip module can be improved, the area of the substrate of the chip module can be reduced, and the space required for installing the chip module can be reduced. In addition, a large number of core particles can be installed in the chip module to improve the function of the chip module.

[0022] The chip module can be a radio frequency chip module, which is used to be connected with an antenna to realize the receiving and transmitting function of the antenna.

[0023] In a third aspect, the application further provides an electronic device including a housing and the chip module provided in the second aspect, and the chip module is arranged in the housing. The core particle provided in the chip module has high integration, and the area required for installing the chip module in the electronic device is small, which is advantageous for improving the integration of the electronic device, and a large number of core particles can be installed in the chip module to improve the function of the chip module.

[0024] Based on the same inventive concept, the application further provides a preparation method of a core particle, which includes:

[0025] The wafer is provided, and the wafer includes a first side and a second side facing away from each other; an active device is prepared on the first side of the wafer, and the active device includes a first connecting piece; the wafer is flipped, a conductive hole is formed in the wafer, and an end surface of the conductive hole is connected with a surface of the first connecting piece, which is equivalent to that the first connecting piece covers the end surface of the conductive hole, and the first connecting piece is not damaged by the conductive hole. A passive device is prepared on the second side of the wafer, and the passive device includes a second connecting piece, the second connecting piece covers the conductive hole, and is electrically connected with the conductive hole. The wafer prepared by the method has the active device and the passive device on the two sides of the wafer respectively, and a projection of the active device on the wafer at least partially overlaps with a projection of the passive device on the wafer, and a projection of the first conductive hole on the wafer is completely located in a projection of the first connecting piece on the wafer, and a projection of the first conductive hole on the wafer is completely located in a projection of the second connecting piece on the wafer. It is beneficial to improve the miniaturization degree of the core grain. In addition, the first conductive hole is directly connected with the active device and the passive device, and the first connecting piece of the active device and the second connecting piece of the passive device both cover the first conductive hole. Therefore, the first conductive hole directly arranged between the active device and the passive device can realize the electrical connection of the active device and the passive device, which not only improves the electrical connection reliability between the active device and the passive device, but also reduces the space occupied by the first conductive hole, which is beneficial to improve the integration of the core grain and reduce the volume of the core grain. In particular, the projection area of the core grain on the substrate is reduced, so that the area of the substrate of the chip module is smaller, and the setting area of the chip module is also smaller, that is, the area occupied by the chip module in the electronic equipment is also smaller. In the case of the same area of the substrate, the above chip module can set more devices, and the function of the chip module can be improved.

[0026] The above flipping the wafer, forming the conductive hole in the wafer, and connecting the end surface of the conductive hole with the surface of the first connecting piece specifically includes:

[0027] The wafer is flipped, the second side of the wafer is thinned, and the conductive hole is formed in the wafer, and the end surface of the conductive hole is connected with the surface of the first connecting piece. That is, the substrate of the core grain is subjected to a thinning process in the technical solution of the present application, so that the substrate of the core grain is thin, which reduces the volume of the core grain on the one hand, and also shortens the signal transmission path and improves the performance of the core grain on the other hand.

[0028] In addition, the above step of preparing the passive device on the second side of the wafer, the passive device including the second connecting piece, the second connecting piece covering the conductive hole, and being electrically connected with the conductive hole; and then includes:

[0029] The wafer is flipped, a circuit layer is prepared on a first side of the wafer, the circuit layer is electrically connected with the first connecting piece, a solder column is prepared on a surface of the circuit layer, and the solder column is electrically connected with the circuit layer. The solder column is located on a side of the active device away from the passive device, and the flip-chip can be realized. Specifically, any two of a projection of the active device on the substrate, a projection of the passive device on the substrate, and a projection of the solder column on the substrate at least partially overlap. Thus, the volume of the chip grain is further reduced, and the space required for mounting the chip grain on the substrate is reduced, thereby reducing the volume of the chip module and the area occupied by the chip module.

[0030] The preparation method is specifically used for preparing a plurality of chip grains, each of which includes an active device, a passive device, and a conductive hole connecting the active device and the passive device. Thus, the preparation efficiency of the preparation method can be improved. The solder column is prepared on the surface of the circuit layer, and the solder column is electrically connected with the circuit layer, and then includes:

[0031] The wafer is singulated to form a plurality of chip grains, and the chip grains are peeled off from a carrier plate used for fixing the wafer. The carrier plate is relatively thick, the wafer is fixed on the carrier plate, the wafer and the carrier plate are fixed as an integrated structure, and the carrier plate can reduce the deformation of the wafer caused by stress. The singulation is performed in the state that the wafer is fixed on the carrier plate, thereby facilitating the release of stress of the thin wafer, and preventing problems such as deformation, fragmentation, and damage to the structure of the chip grain product of the large-area thin wafer, and improving the product yield and maintaining the advantage of thin thickness of the chip grain. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

[0033] FIG. 2 is a schematic structural diagram of a chip module according to an embodiment of the present application;

[0034] FIG. 3 is a schematic structural diagram of a chip grain according to an embodiment of the present application;

[0035] FIG. 4 is a schematic structural diagram of a chip grain according to a comparative example;

[0036] FIG. 5 is a schematic structural diagram of a chip grain according to an embodiment of the present application;

[0037] FIG. 6 is a schematic structural diagram of a chip grain according to an embodiment of the present application;

[0038] FIG. 7 is a schematic structural diagram of a chip module according to an embodiment of the present application;

[0039] FIG. 8 is a schematic structural diagram of a chip module according to a comparative example;

[0040] FIG. 9 is a schematic structural diagram of a chip grain according to an embodiment of the present application;

[0041] FIGS. 10a-10g show schematic diagrams of a preparation process of the core pellet in the embodiments of the present application.

[0042] Reference signs: 100-chip module; 200-housing; 1-substrate; 2-core pellet; 21-substrate; 22-active device; 221-first connecting sheet; 222-active device body; 23-passive device; 231-second connecting sheet; 232-passive device body; 24-conductive hole; 241-first conductive hole; 242-second conductive hole; 25-wiring layer; 26-solder column; 27-wafer; 28-first bonding glue layer; 29-first carrier plate; 210-second bonding glue layer; 211-second carrier plate. DETAILED DESCRIPTION

[0043] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings.

[0044] The terms used in the following embodiments are only for the purpose of describing the specific embodiments and are not intended to be limiting to the present application. As used in the specification and the appended claims of the present application, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] Reference to "one embodiment" or "an embodiment" or "a specific embodiment" or "certain embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" or "in a specific embodiment" or "in certain embodiments" in various places in the specification are not necessarily all referring to the same embodiment.

[0046] Hereinafter, terms that can appear in embodiments of the present application are explained.

[0047] Active device: an electronic component that requires a power supply to achieve its specific function. It mainly includes electronic tubes, transistors, integrated circuits, etc. It is generally used for signal amplification, conversion, etc. From the physical structure, circuit function and engineering parameters, active devices can be divided into discrete devices and integrated circuits.

[0048] Passive device: an electronic device that can independently achieve its specific function without relying on the presence of an external power supply. Passive devices mainly include resistors, capacitors, inductors, converters, graders, matching networks, resonators, filters and mixers, etc.

[0049] RF chip module: is a combination of all components of an antenna for receiving and transmitting RF waves. In the case of a receiving antenna, the RF chip can be considered as the antenna part from the first amplifier to the front transmitter. In a transmitting antenna, the RF chip can be considered as the part after the last power amplifier. In some cases, the RF chip can also be understood as a feed unit. The RF chip has the function of converting radio waves into electrical signals and sending them to the receiver component. Usually, it is considered as part of the antenna system for converting radio waves into electrical signals and vice versa.

[0050] In order to facilitate the understanding of the core particles, chip modules, electronic devices and preparation methods of core particles provided by the embodiments of the present application, the application scenarios thereof are introduced as follows.

[0051] The electronic device in the embodiments of the present application can be an information and communications technology (ICT) device, a communication device (such as a router), a computing device (such as a server), a network device (such as a switch) or a storage device (such as a storage array) electronic device, or it can also be a vehicle-mounted device or a terminal device electronic device, for example, it can be a mobile terminal such as a mobile phone and a watch. The present application does not limit the specific type of electronic device, as long as the electronic device includes a chip module, the technical solutions provided by the present application can be used.

[0052] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present application. In Figure 1, the electronic device is taken as an example of a mobile phone. As shown in Figure 1, in one embodiment, the electronic device can include a chip module 100 and a housing 200, and the chip module 100 is arranged in the housing 200 of the electronic device. In a specific embodiment, the chip module 100 can be accommodated in the interior of the housing 200, so that the housing 200 can protect the chip module 100.

[0053] Figure 2 is a schematic diagram of a side view of a chip module according to an embodiment of the present application. As shown in Figure 2, in one embodiment, the chip module 100 includes a substrate 1 and at least one chip 2, the chip 2 is mounted on the substrate 1 and electrically connected to the substrate 1. Specifically, the substrate 1 includes a circuit, and the chip 2 is electrically connected to the circuit of the substrate 1.

[0054] In a specific embodiment, the chip 2 can also be referred to as a die.

[0055] Specifically, the chip module 100 includes one or more chips 2, and the one or more chips 2 are arranged on the substrate 1 and electrically connected to the substrate 1. The plurality of chips 2 can be the same chip 2 or different chips 2. In addition, different chips 2 can be interconnected through the circuit of the substrate 1. In some embodiments, there can be some chips 2 that are not interconnected.

[0056] The chip 2 can be packaged on the substrate 1 by packaging. The packaging structure can protect the chip 2, and make the chip module 100 have high structural strength, and the structure has high regularity and integrity, which is convenient for transportation, storage and assembly of the chip module 100. Specifically, the chip 2 can be packaged on the substrate 1 in a flip-chip manner.

[0057] Specifically, the chip module 100 can be a radio frequency chip module 100, or the chip module 100 can be a radio frequency transceiver front-end module. The chip module 100 can be used to connect with an antenna radiator to realize transmission and reception of radio frequency signals.

[0058] Please continue to refer to FIG. 2, the core grain 2 of the chip module 100 in the embodiment of the present application includes a substrate 21, an active device 22 and a passive device 23. The active device 22 and the passive device 23 are arranged on two sides of the substrate 21 respectively, and the active device 22 and the passive device 23 are electrically connected. Specifically, the substrate 21 includes a first side and a second side facing away from each other, the active device 22 is arranged on the first side of the substrate 21, and the passive device 23 is arranged on the second side of the substrate 21. The orthographic projection of the active device 22 on the substrate 21 at least partially overlaps the orthographic projection of the passive device 23 on the substrate 21, which is conducive to reducing the space required when the core grain 2 is mounted on the substrate 1, thereby improving the integration of the chip module 100, reducing the volume of the chip module 100, and reducing the area occupied by the installation of the chip module 100.

[0059] The core grain 2 includes a conductive hole 24, and the conductive hole 24 includes a first conductive hole 241. The first conductive hole 241 connects the active device 22 and the passive device 23, so that the active device 22 and the passive device 23 can be electrically connected through the first conductive hole 241, so that the core grain 2 forms a whole structure in the circuit relationship.

[0060] FIG. 3 is a schematic view of a structure of a core grain in an embodiment of the present application. As shown in FIG. 3, in a specific implementation of the scheme of electrically connecting the active device 22 and the passive device 23, the active device 22 includes a first connecting piece 221 covering an end surface of one end of the first conductive hole 241. In this embodiment, the connection mode of the first connecting piece 221 and the first conductive hole 241 is that the first connecting piece 221 covers the end surface of the first conductive hole 241, so that the first connecting piece 221 is in contact with and electrically connected to the end surface of the first conductive hole 241. This electrical connection mode is relatively reliable. For example, FIG. 4 is a schematic view of a structure of a core grain of a comparative example. As shown in FIG. 4, if the first conductive hole 241 passes through the first connecting piece 221 to connect the first connecting piece 221, the cross section of the first connecting piece 221 in the thickness direction is connected to the first conductive hole 241, and the connection area is small. In addition, in the preparation process, the first conductive hole 241 passing through the first connecting piece 221 will also cause the first connecting piece 221 to be damaged, resulting in poor connection reliability. In the present application, the first connecting piece 221 covers the end surface of the first conductive hole 241, so that the preparation process does not damage the first connecting piece 221, and the surface of the first connecting piece 221 is connected to the end surface of the first conductive hole 241, so that the connection area is large, which is conducive to improving the connection reliability of the first connecting piece 221 and the first conductive hole 241.

[0061] Similarly, the passive device 23 includes a second connecting piece 231 covering the end face of the other end of the first conductive hole 241, and the second connecting piece 231 is electrically connected with the end face of the first conductive hole 241. The second connecting piece 231 also covers the end face of the first conductive hole 241, and the second connecting piece 231 is a complete structure, the manufacturing process will not damage the second connecting piece 231, and the surface of the second connecting piece 231 is connected with the end face of the first conductive hole 241, the connection area is large, which is conducive to improving the connection reliability of the second connecting piece 231 and the first conductive hole 241. Specifically, the first conductive hole 241 is located between the first connecting piece 221 and the second connecting piece 231, and the end faces of the two ends of the first conductive hole 241 are connected with the first connecting piece 221 and the second connecting piece 231 respectively, so that the first conductive hole 241 is connected with the active device 22 and the passive device 23 in a more reliable manner. For example, as shown in FIG. 4, if the first conductive hole 241 passes through the second connecting piece 231 to connect with the second connecting piece 231, the cross section of the second connecting piece 231 in the thickness direction is connected with the first conductive hole 241, the connection area is small, and in the manufacturing process, the first conductive hole 241 passing through the second connecting piece 231 will also cause the second connecting piece 231 to be damaged, resulting in poor connection reliability. In the present application, the second connecting piece 231 covers the end face of the first conductive hole 241, so that the manufacturing process will not damage the second connecting piece 231, and the surface of the second connecting piece 231 is connected with the end face of the first conductive hole 241, the connection area is large, which is conducive to improving the connection reliability of the second connecting piece 231 and the first conductive hole 241.

[0062] In the scheme, the substrate 21 of the core particle 2 has the active device 22 and the passive device 23 on two sides respectively, the active device 22 and the passive device 23 are arranged back-to-back, and the orthographic projection of the active device 22 on the substrate 21 at least partially overlaps the orthographic projection of the passive device 23 on the substrate 21, and the orthographic projection of the first conductive hole 241 on the substrate 21 is completely located in the orthographic projection of the first connecting piece 221 on the substrate 21, and the orthographic projection of the first conductive hole 241 on the substrate 21 is completely located in the orthographic projection of the second connecting piece 231 on the substrate 21. It can also be understood that the orthographic projection of the first conductive hole 241 on the substrate 21 is completely located in the orthographic projection of the active device 22 on the substrate 21, and the orthographic projection of the first conductive hole 241 on the substrate 21 is completely located in the orthographic projection of the passive device 23 on the substrate 21. The preparation space of the core particle 2 is fully utilized, which is conducive to improving the miniaturization degree of the core particle 2. In addition, the first conductive hole 241 is used to directly connect the active device 22 and the passive device 23, and the first connecting piece 221 of the active device 22 and the second connecting piece 231 of the passive device 23 both cover the first conductive hole 241. Therefore, the first conductive hole 241 arranged directly between the active device 22 and the passive device 23 can realize the electrical connection of the active device 22 and the passive device 23, which not only improves the electrical connection reliability between the active device 22 and the passive device 23, but also reduces the space occupied by the first conductive hole 241, which is conducive to improving the integration of the core particle 2 and reducing the volume of the core particle 2. In particular, the projection area of the core particle 2 mounted on the substrate 1 is reduced, so that the area of the substrate 1 of the chip module 100 is smaller, and the mounting area of the chip module 100 is reduced, that is, the area occupied by the chip module 100 in the electronic equipment is also smaller. The scheme is conducive to improving the miniaturization of the electronic equipment, and in the case of the same area of the substrate 1, the chip module 100 in the present application can set a larger number of devices, which can improve the function of the chip module 100.

[0063] It can be understood that the active device 22 can be considered to include the active device body 222 and the first connecting piece 221, the active device body 222 and the first connecting piece 221 are arranged in the same layer, and the active device body 222 is electrically connected with the first connecting piece 221. The passive device 23 includes the passive device body 232 and the second connecting piece 231, the passive device body 232 and the second connecting piece 231 are arranged in the same layer, and the passive device body 232 is electrically connected with the second connecting piece 231. Thus, the first conductive hole 241 located between the first connecting piece 221 and the second connecting piece 231 is used to realize the electrical connection of the active device 22 and the passive device 23. In this embodiment, there is no need to additionally prepare a wiring layer to connect the active device 22 and the passive device 23, which is conducive to reducing the volume of the core particle 2, thereby improving the integration of the chip module 100 and reducing the mounting area of the chip module 100.

[0064] Specifically, the active device body 222 is a part of the active device 22 that implements the core function, and the first connecting piece 221 can be a metal piece or a conductive element such as polysilicon; the passive device body 232 is a part of the passive device 23 that implements the core function, and the second connecting piece 231 can be a metal piece or a conductive element such as polysilicon. For example, the active device body 222 can be a body for implementing the low-noise amplification function of a low-noise amplifier; the passive device body 232 can be a capacitor and / or inductor body.

[0065] In some embodiments, part of the structure of the active device body 222 can be reused as the first connecting piece 221. Part of the structure of the passive device body 232 can be reused as the second connecting piece 231. Specifically, the passive device body 232 includes a metal piece that is reused as the second connecting piece 231, and the metal piece covers the end face of the other end of the first conductive hole 241 and is electrically connected with the first conductive hole 241. Alternatively, the second connecting piece 231 can be independent of the passive device body 232 and separately serve as a structure, but the second connecting piece is directly connected with one end of the passive device body. The above embodiments can further reduce the volume of the core grain 2, improve the integration of the chip module 100, and reduce the area occupied by the installation of the chip module 100.

[0066] Fig. 5 is a schematic view of a partial top view of a core grain in an embodiment of the present application, and Fig. 6 is a schematic view of a partial side view of a core grain in an embodiment of the present application. As shown in Figs. 5 and 6, taking the passive device 23 as a capacitor, an inductor and a resistor as an example, when the end of the passive device 23 connected with the conductive hole 24 is a capacitor, the two capacitor plates of the capacitor are the passive device body 232, and at least one of the two capacitor plates is a metal piece that can be reused as the second connecting piece 231. The capacitor plate directly covers the surface of the conductive hole 24, thereby being electrically connected with the conductive hole 24. When the end of the passive device connected with the conductive hole 24 is an inductor or a resistor, the inductor and the resistor are the passive device body 232. The inductor and the resistor are the end parts of the inductor and the resistor, and the areas of the end parts are small, which is not conducive to the connection with the conductive hole 24. Therefore, the second connecting piece 231 can be directly connected with one end of the inductor and the resistor, and then the second connecting piece 231 is connected with the conductive hole 24. In this scheme, although the second connecting piece 231 needs to be additionally prepared, the second connecting piece 231 is directly located at one end of the passive device body 232, which is also conducive to reducing the space occupied by the passive device and improving the integration of the chip.

[0067] In some embodiments, the second connecting piece 231 is independent of the passive device body 232, and the second connecting piece 231 can be electrically connected with the passive device body 232 through a wire, thereby flexibly arranging the position of the second connecting piece 231 according to actual needs.

[0068] Figure 7 is a schematic diagram of a top view of a chip module according to an embodiment of the present application, and Figure 8 is a schematic diagram of a top view of a chip module according to a comparative example. The chip module 100 in Figures 7 and 8 includes the same devices. For example, the chip module 100 is a radio frequency chip module, and the chip module 100 includes two power amplifiers (PA), one low noise amplifier (LNA), one power switch (PSW), one controller (CTRL), four filters, two Balun devices, and one antenna switch module (ASM). As shown in Figure 8, each device is a die 2 in the comparative example, and multiple devices are tiled on the surface of the substrate 1. As shown in Figure 7, in the embodiment of the present application, the same number of devices are stacked on both sides of the die 2, so that the number of the die 2 is halved. Moreover, the two devices are connected by the first conductive hole 241, and no additional interconnection space is occupied, so that the die 2 occupies a smaller area on the substrate 1, and thus the substrate 1 of the chip module 100 in the present application is smaller. It can be seen that, compared with the comparative example, the substrate 1 of the chip module 100 in the technical solution of the present application is greatly reduced in size, and the space required for installation of the chip module 100 is greatly reduced, and the integration of the electronic device is improved.

[0069] Please continue to refer to Figure 3. In the embodiment of the present application, the die 2 is provided with a wiring layer 25 on the side of the active device 22 away from the substrate 21. One side of the wiring layer 25 is electrically connected to the first connecting piece 221 connected to the active device 22. The side of the wiring layer 25 away from the first connecting piece 221 is connected to a solder column 26, and the solder column 26 is used to electrically connect to the substrate 1. In a specific embodiment, the solder column 26 is located on the side of the active device 22 away from the passive device 23, so that the die 2 can be flip-chip mounted. Specifically, in the embodiment of the present application, any two of the orthographic projection of the active device 22 on the substrate 1, the orthographic projection of the passive device 23 on the substrate 1, and the orthographic projection of the solder column 26 on the substrate 1 at least partially overlap. Thus, the volume of the die 2 is further reduced, and the space required for mounting the die 2 on the substrate 1 is reduced, so that the integration of the chip module 100 is further improved, and the volume of the chip module 100 and the area occupied by the chip module 100 are reduced.

[0070] Fig. 9 is a schematic view of a structure of a core in an embodiment of the present application. As shown in Fig. 9, in some embodiments, the soldering column 26 needs to be electrically connected with the passive device 23 in addition to being electrically connected with the active device 22, or in some embodiments, the passive device 23 can not be directly connected with the soldering column 26 through the active device 22. In this case, the conductive hole 24 can further include a second conductive hole 242 connecting the passive device 23 and the wiring layer 25, so that the passive device 23 can be directly connected with the soldering column 26. For example, this embodiment can realize the grounding of the passive device 23.

[0071] In the implementation of this embodiment, the passive device 23 is connected with the second conductive hole 242 in the same way as the passive device 23 is connected with the first conductive hole 241. That is, the passive device 23 further includes a second connecting piece 231 electrically connected with the second conductive hole 242, and the second connecting piece 231 covers the end surface of the second conductive hole 242. This can increase the connection area between the second connecting piece 231 and the second conductive hole 242, and improve the connection reliability between the second connecting piece 231 and the second conductive hole 242.

[0072] Similarly, in the implementation of the connection between the second conductive hole and the wiring layer, the wiring layer 25 can further include a third connecting piece connected with the second conductive hole 242, and the third connecting piece covers the end surface of the second conductive hole 242, so as to improve the connection reliability between the wiring layer and the second conductive hole 242.

[0073] In specific embodiments, the conductive hole 24 provided by the present application can be a hollow conductive hole, and the inner wall of the hollow conductive hole is a metal layer to realize electrical connection.

[0074] In another specific embodiment, the conductive hole 24 provided by the present application can also be a solid conductive hole, and the conductive hole 24 is filled with a metal column. The conductive hole can be prepared and formed by electroplating and other processes. In this embodiment, the end surface of the conductive hole 24 is a flat end surface, which is conducive to the preparation and formation of the first connecting piece 221 and / or the second connecting piece 231 on the end surface of the conductive hole 24. In addition, it is conducive to increasing the connection area between the first connecting piece 221 and the conductive hole 24, and the connection area between the second connecting piece 231 and the conductive hole 24, so as to improve the connection reliability between the conductive hole 24 and the first connecting piece 221 and the second connecting piece 231, and improve the connection reliability between the active device 22 and the passive device 23.

[0075] In the embodiment of the present application, the soldering post 26 is located on the side where the active device 22 is located, and the active device 22 is arranged adjacent to the substrate 1 when mounted to the substrate 1, which is beneficial to improve the heat dissipation capacity of the active device 22. The active device 22 has strong heat dissipation requirements, and therefore the present application can improve the heat dissipation effect of the active device 22. In addition, the path length of the ground and the path length of the signal transmission also have a strong influence on the performance of the active device, and in the embodiment of the present application, the active device 22 is arranged adjacent to the soldering post 26, which is beneficial to shorten the path length of the ground and the length of the signal transmission path, thereby improving the performance of the active device 22.

[0076] The core particle 2 in the embodiment of the present application can be the core particle 2 in the radio frequency chip module 100, and the active device 22 includes at least one of a power amplifier, a low-noise amplifier and a radio frequency switch. The radio frequency switch can further include a power switch, which is usually used to control a larger power signal, and the specific structure and type of the active device 22 can be selected and designed according to actual needs.

[0077] The passive device 23 includes at least one of a filter, a capacitor device, an inductor device, a balun device, a matching element or an integrated passive device (IPD). The specific type of the filter also has multiple choices, for example, the filter can be a surface acoustic wave filter (SAW), a bulk acoustic wave filter (BAW) or a film bulk acoustic resonator (FBAR). The specific structure and type of the passive device 23 can be selected and designed according to actual needs. In addition, the matching element can be a combination of a capacitor device and an inductor device, which is used to realize the matching function of the antenna; and the integrated passive device can also be a combination of a capacitor device and an inductor device, which is used to realize a specific function.

[0078] The combination of the active device 22 and the passive device 23 on the two sides of the core particle 2 can be selected and designed according to requirements. For example, the active device 22 in one core particle 2 can be a power amplifier, and the passive device 23 can be a filter; the active device 22 in one core particle 2 can be a low-noise amplifier, and the passive device 23 can be a filter; the active device 22 in one core particle 2 can be a radio frequency switch, and the passive device 23 can be a filter; the active device 22 in one core particle 2 can be a power amplifier, and the passive device 23 can be an integrated circuit of passive devices; the active device 22 in one core particle 2 can be a low-noise amplifier, and the passive device 23 can be an integrated circuit of passive devices; the active device 22 in one core particle 2 can be a radio frequency switch, and the passive device 23 can be an integrated circuit of passive devices; or in some embodiments, the active device 22 in one core particle 2 can be a low-noise amplifier, and the passive device 23 can be a matching element; the active device 22 in one core particle 2 can be a radio frequency switch, and the passive device 23 can be a capacitor, and the like. Here, all the above combinations are not listed one by one.

[0079] Based on the same inventive concept, the application further provides a preparation method of the core particle 2. The core particle 2 in any of the above embodiments can be prepared by using the preparation method. FIGS. 10a-10g show schematic diagrams of the preparation process of the core particle in the embodiments of the application. As shown in FIGS. 10a-10g, the preparation method of the core particle 2 provided by the application comprises the following steps:

[0080] In step S101, a wafer 27 is provided, the wafer 27 comprising a first side and a second side facing away from each other.

[0081] The left diagram in FIG. 10a schematically shows a cross-sectional structure of the wafer 27 in the preparation process of the core particle 2, and the right diagram schematically shows a top view of the wafer 27. As shown in FIG. 8, the wafer 27 can be a silicon-based wafer 27, for example, a silicon-on-insulator (SOI) wafer 27 obtained by using a smart cut process, which comprises a silicon dioxide layer and a high-resistance silicon layer, and the like. In other embodiments, it can also be a gallium nitride (GaN) wafer 27 or a gallium arsenide (GaAs) wafer 27, and the like. The application does not make any limitation in this regard.

[0082] In step S102, an active device 22 is prepared on the first side of the wafer 27, the active device 22 comprising a first connecting piece 221.

[0083] The left drawing in FIG. 10b schematically shows a cross-sectional structure of a core particle 2 in a preparation process, and the right drawing schematically shows a cross-sectional structure of the wafer 27. As shown in FIG. 10b, in a specific embodiment, the active device 22 can include an active device 22 body 222 and a first connecting piece 221. The active device 22 body 222 and the first connecting piece 221 are located in the same layer, i.e., the active device 22 body 222 and the first connecting piece 221 are arranged in the same layer, and the active device 22 body 222 and the first connecting piece 221 are electrically connected. By being electrically connected with the first connecting piece 221, the active device 22 body 222 can be electrically connected with the active device 22.

[0084] As shown in FIG. 10b, in order to perform step S103, a first bonding glue layer 28 can also be formed on the surface of the active device 22. The first bonding glue layer 28 can be a polybenzoxazole (PBO) layer or a polyimide (PI) layer, which is not limited in the present application.

[0085] Step S103: flip the wafer 27, and form a conductive hole 24 in the wafer 27, an end surface of the conductive hole 24 being connected with the surface of the first connecting piece 221;

[0086] The left drawing in FIG. 10c schematically shows a cross-sectional structure of a core particle 2 in a preparation process, and the right drawing schematically shows a cross-sectional structure of the wafer 27. As shown in FIG. 10c, in this embodiment, the wafer 27 can be temporarily bonded to a first carrier 29 through the first bonding glue layer 28 after being flipped, so as to facilitate subsequent processes. The specific process of forming the conductive hole 24 has multiple choices. For example, a chemical etching or ion bombardment process can be used to form a hole extending to the surface of the first connecting piece 221, i.e., the surface of the first connecting piece 221 is the bottom wall of the hole. Then, a deposition or electroplating process is used to prepare a metal structure in the hole to form the conductive hole 24, so that the conductive hole 24 has a conductive function, and one end of the conductive hole 24 is connected with the surface of the first connecting piece 221.

[0087] In the embodiment, the first connecting piece 221 serves as the bottom wall of the conductive hole 24, and the first connecting piece 221 covers the end surface of the conductive hole 24. The first connecting piece 221 is in contact with and electrically connected to the end surface of the conductive hole 24, and the connection area is large, and the electrical connection is reliable. In addition, the connection mode does not need to damage the structure of the first connecting piece 221, and is also beneficial to improve the connection reliability of the first connecting piece 221 and the conductive hole 24. For example, if the conductive hole 24 passes through the first connecting piece 221 and is connected to the first connecting piece 221, the cross section of the first connecting piece 221 in the thickness direction is connected to the first conductive hole 241, the connection area is small, and in the preparation process, the first conductive hole 241 passing through the first connecting piece 221 will also cause the first connecting piece 221 to be damaged, and the connection reliability is poor. Therefore, the embodiment of the present application is beneficial to improve the connection reliability of the first connecting piece 221 and the first conductive hole 241. The first connecting piece 221 is electrically connected to the end surface of the conductive hole 24, and the first connecting piece 221 and the conductive hole 24

[0088] In step S104, the passive device 23 and the second connecting piece 231 are prepared on the second side of the wafer 27, the passive device 23 and the second connecting piece 231 are connected, the second connecting piece 231 covers the conductive hole 24, and the second connecting piece 231 is electrically connected to the conductive hole 24.

[0089] The left side of FIG. 10d schematically shows a cross-sectional structure diagram of a preparation process of a core particle 2, and the right side of FIG. 10d schematically shows a cross-sectional structure diagram of a wafer 27. As shown in FIG. 10d, the preparation sequence of the second connecting piece 231 and the conductive hole 24 belongs to the hole first and then the surface, and similarly, the second connecting piece 231 covers the end surface of the conductive hole 24, and the second connecting piece 231 is electrically connected to the end surface of the conductive hole 24. The second connecting piece 231 also covers the end surface of the conductive hole 24, and the preparation process does not damage the second connecting piece 231, the second connecting piece 231 is a complete structure, and the surface of the second connecting piece 231 is connected to the end surface of the conductive hole 24, the connection area is large, and is beneficial to improve the connection reliability of the second connecting piece 231 and the conductive hole 24. Specifically, the conductive hole 24 is located between the first connecting piece 221 and the second connecting piece 231, and the end surfaces at both ends of the conductive hole 24 are connected to the first connecting piece 221 and the second connecting piece 231 respectively, so that the conductive hole 24 is connected to the active device 22 and the passive device 23 in a more reliable manner.

[0090] In addition, the wafer 27 of the core particle 2 prepared by the method has the active device 22 and the passive device 23 on two sides of the wafer 27, the active device 22 and the passive device 23 are arranged back to back, the front projection of the active device 22 on the wafer 27 at least partially overlaps the front projection of the passive device 23 on the wafer 27, and the front projection of the first conductive hole 241 on the wafer 27 is completely located in the front projection of the first connecting piece 221 on the wafer 27, and the front projection of the first conductive hole 241 on the wafer 27 is completely located in the front projection of the second connecting piece 231 on the wafer 27. It can also be understood that the front projection of the first conductive hole 241 on the wafer 27 is completely located in the front projection of the active device 22 on the wafer 27, and the front projection of the first conductive hole 241 on the wafer 27 is completely located in the front projection of the passive device 23 on the wafer 27. The preparation space of the core particle 2 is fully utilized, which is conducive to improving the miniaturization degree of the core particle 2. In addition, the first conductive hole 241 is directly connected to the active device 22 and the passive device 23, and the first connecting piece 221 of the active device 22 and the second connecting piece 231 of the passive device 23 both cover the first conductive hole 241. Therefore, the first conductive hole 241 can be directly arranged between the active device 22 and the passive device 23 to realize the electrical connection of the active device 22 and the passive device 23. In addition to improving the electrical connection reliability between the active device 22 and the passive device 23, it also reduces the space occupied by the first conductive hole 241, which is conducive to improving the integration of the core particle 2 and reducing the volume of the core particle 2. In particular, the projection area of the core particle 2 mounted on the substrate 1 is reduced, so that the area of the substrate 1 of the chip module 100 is smaller, and the setting area of the chip module 100 is also smaller, that is, the area occupied by the chip module 100 in the electronic equipment is also smaller. This scheme is conducive to improving the miniaturization of the electronic equipment, and in the case of the same area of the substrate 1, the chip module 100 in the present application can set a larger number of devices, which can improve the function of the chip module 100.

[0091] Further, please refer to FIG. 10b and FIG. 10c, the step S103 specifically includes:

[0092] Step S1031, flipping the wafer 27;

[0093] Step S1032, thinning the second side of the wafer 27;

[0094] Step S1033, forming the conductive hole 24 in the wafer 27, the end surface of the conductive hole 24 is connected with the surface of the first connecting piece 221.

[0095] In this embodiment, the wafer 27 can be thinned by a grinding process. The thickness of the whole die 2 is thin, which is beneficial to reduce the volume of the die 2, improve the integration of the chip module 100, and reduce the area occupied by the installation of the chip module 100. In addition, the length of the conductive hole 24 is also shortened, which can reduce the loss of signal in the transmission path and improve the performance of the die 2.

[0096] After step S104, the following steps are further included:

[0097] In step S105, the wafer 27 is flipped, and a circuit layer is prepared on the first side of the wafer 27, and the circuit layer is electrically connected with the first connecting piece 221.

[0098] The left side of FIG. 10e schematically shows a cross-sectional structure diagram of a die 2 preparation process, and the right side of FIG. 10e schematically shows a cross-sectional structure diagram of a wafer 27. As shown in FIG. 10e, in this embodiment, a first protective layer can be formed on the surface of the passive device 23 in step S104, and a second bonding glue layer 210 is formed on the surface of the first protective layer. After the wafer 27 is flipped, the wafer 27 is temporarily bonded to the second carrier 211 through the second bonding glue layer 210, so as to facilitate subsequent processes. The first protective layer can be a passivation layer, for example, a silicon nitride layer. In addition, before the wafer 27 is flipped, the first bonding glue layer 28 and the first carrier 29 are peeled off, and the first bonding glue layer 28 is removed according to the needs, and the first protective layer is reserved. The first protective layer protects the active device 22 on the surface of the active device 22.

[0099] In step S106, a solder column 26 is prepared on the surface of the circuit layer, and the solder column 26 is electrically connected with the circuit layer.

[0100] The left side of FIG. 10f schematically shows a cross-sectional structure diagram of a die 2 preparation process, and the right side of FIG. 10f schematically shows a cross-sectional structure diagram of a wafer 27. As shown in FIG. 10f, in this embodiment, the solder column 26 is connected with the first connecting piece 221 through the circuit layer, and the solder column 26 is used for electrical connection with the substrate 1. In a specific embodiment, the solder column 26 is located on the side of the active device 22 away from the passive device 23, which can realize flip of the die 2. Specifically, any two of the orthographic projection of the active device 22 on the substrate 1, the orthographic projection of the passive device 23 on the substrate 1, and the orthographic projection of the solder column 26 on the substrate 1 at least partially overlap. Thus, the volume of the die 2 is further reduced, and the space required for installing the die 2 on the substrate 1 is also reduced, thereby further improving the integration of the chip module 100, reducing the volume of the chip module 100, and reducing the area occupied by the installation of the chip module 100.

[0101] In order to improve the preparation efficiency, in the embodiment of the present application, a plurality of core particles 2 can be prepared in one process, each of the core particles 2 comprising an active device 22, a passive device 23, and a conductive hole 24 connecting the active device 22 and the passive device 23, and the core particle 2 is specifically the core particle 2 provided in the above-mentioned embodiment of the present application. It can be understood that the wafer 27 is a wafer 27 with a larger area, and the process of preparing the active device 22 prepares a plurality of active devices 22, and the process of preparing the passive device 23 prepares a plurality of passive devices 23.

[0102] The left side of FIG. 10g schematically shows a cross-sectional structure diagram of a core particle 2 preparation process, and the right side of FIG. 10g schematically shows a top view structure diagram of the wafer 27. As shown in FIG. 10g, after step S104, the process further comprises:

[0103] Step S107, dicing the wafer 27 to form a plurality of core particles 2;

[0104] Specifically, laser dicing or soft knife dicing process can be used to dice the wafer 27, specifically between adjacent core particles 2, to separate different core particles 2.

[0105] Step S108, peeling the core particle 2 from the carrier plate for fixing the wafer 27.

[0106] Specifically, the laser peeling method can be used to peel the core particle 2 from the carrier plate to form a complete core particle 2. The above-mentioned carrier plate can be specifically the second carrier plate 211, and then a mechanical arm or the like can be used for subsequent processes such as material taking.

[0107] In the embodiment of the present application, the above-mentioned carrier plate is relatively thick, and the wafer 27 is fixed in the state of the carrier plate, and the wafer 27 and the carrier plate are fixed as an integrated structure, and the carrier plate can reduce the deformation of the wafer 27 caused by stress. Dicing and dicing are performed in the state that the wafer 27 is fixed to the carrier plate, thereby facilitating the release of stress of the thin wafer 27, and preventing problems such as deformation, fragmentation and damage of the core particle 2 product structure of the large-area thin wafer 27, and facilitating the improvement of product yield and the maintenance of the advantage of thin thickness of the core particle 2.

[0108] In the optional embodiment, the above-mentioned step S107 and step S108 can also be performed after step S106.

[0109] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A core particle, characterized in that, The chip includes a substrate, an active device and a passive device, wherein: the substrate includes a first side and a second side facing away from each other, the active device is arranged on the first side of the substrate, and the passive device is arranged on the second side of the substrate; a projection of the active device on the substrate at least partially overlaps a projection of the passive device on the substrate; the core particle further includes a conductive hole, the conductive hole includes a first conductive hole; the active device includes a first connecting piece, the first connecting piece covers an end surface of one end of the first conductive hole and is electrically connected with the first conductive hole; the passive device includes a second connecting piece, the second connecting piece covers an end surface of the other end of the first conductive hole and is electrically connected with the first conductive hole.

2. The core particle of claim 1, wherein The side of the active device facing away from the substrate is provided with a wiring layer, the wiring layer is electrically connected with the first connecting piece, and the side of the wiring layer facing away from the first connecting piece is connected with a solder column, the solder column is used for electrically connecting with a substrate.

3. The core particle of claim 2, wherein The conductive hole further includes a second conductive hole, the second conductive hole connects the passive device and the wiring layer.

4. The core particle according to any one of claims 1 to 3, wherein The conductive hole is filled with metal.

5. The core particle according to any one of claims 1 to 4, wherein The passive device includes a passive device body, the passive device body includes a metal sheet, and the metal sheet is multiplexed as the second connecting piece. Or the second connecting piece is directly connected with one end of the passive device body.

6. The core particle according to any one of claims 1 to 4, wherein The passive device includes a passive device body, and the passive device body is electrically connected with the second connecting piece through a wire.

7. The core particle according to any one of claims 1 to 6, wherein The active device includes at least one of a power amplifier, a low-noise amplifier and a radio frequency switch.

8. A chip module, characterized by The chip includes a substrate and the core particle as claimed in any one of claims 1-7, the core particle is fixed to the substrate and is electrically connected with a circuit of the substrate.

9. The chip module according to Claim 8, wherein The chip module is a radio frequency chip module.

10. An electronic device, comprising: The chip module as claimed in claim 8 or 9 is arranged in the shell.

11. A method of producing a core particle, characterized by, Providing a wafer, the wafer includes a first side and a second side facing away from each other; An active device is prepared on the first side of the wafer, the active device includes the first connecting piece; The wafer is flipped, and a conductive hole is formed in the wafer, an end surface of the conductive hole is connected with a surface of the first connecting piece; A passive device is prepared on the second side of the wafer, the passive device includes a second connecting piece, the second connecting piece covers the conductive hole and is electrically connected with the conductive hole. The flipping of the wafer and the forming of the conductive hole in the wafer, the end surface of the conductive hole is connected with the surface of the first connecting piece, specifically includes:

12. The production method according to claim 11, wherein The wafer is flipped; The second side of the wafer is thinned; The conductive hole is formed in the wafer, the end surface of the conductive hole is connected with the surface of the first connecting piece. The passive device is prepared on the second side of the wafer, the passive device includes a second connecting piece, the second connecting piece covers the conductive hole and is electrically connected with the conductive hole; and then includes:

13. The production method according to claim 11 or 12, characterized by, The wafer is flipped, and a circuit layer is prepared on the first side of the wafer, the circuit layer is electrically connected with the first connecting piece; A solder column is prepared on a surface of the circuit layer, the solder column is electrically connected with the circuit layer. ​ 14. The production method according to any one of claims 11 to 13, characterized by, The preparation method is used for preparing a plurality of core particles, each of which comprises the active device, the passive device and the conductive hole connecting the active device and the passive device; The surface of the circuit layer is prepared with a solder column which is electrically connected with the circuit layer, and then includes: The wafer is scribed to form a plurality of core particles; The core particles are peeled off from the carrier plate used for fixing the wafer.

Images