Instruction processing method and apparatus, electronic device and computer program product

Abstract

Disclosed in the present application are an instruction processing method and apparatus, an electronic device, and a computer program product. The method comprises: receiving a target data write instruction, the target data write instruction carrying a target memory address where target data to be written into a physical register is located; in response to the target data write instruction, on the basis of a corresponding relationship between physical registers and memory addresses, searching for whether there is a target physical register corresponding to the target memory address; and when a search result indicates that there is the target physical register corresponding to the target memory address, returning a data write result that the target data has been written into the target physical register. The present application solves the technical problems of high power consumption and long time consumption of multiple data write actions during multiple executions of the data write instruction by a processor.

Description

Instruction processing method and device, electronic device and computer program product TECHNICAL FIELD

[0001] The present application relates to the field of processors, in particular to an instruction processing method, device, electronic device and computer program product. BACKGROUND

[0002] When a processor performs data operations, data write instructions are usually used to load data from memory into the registers of the processor for subsequent processing and calculation. Registers are high-speed storage units inside the processor, and their access speed is much faster than that of memory. When the processor needs to perform data operations, it can use data write instructions to load data from memory into registers. Once the data is loaded into the registers, the processor can quickly process and calculate it without waiting for memory access.

[0003] In actual processing, the processor writes corresponding data into the registers every time a data write instruction is executed, and the power consumption of multiple data write actions is large and the time consumption is long.

[0004] To solve the above problems, no effective solution has been proposed so far. SUMMARY

[0005] Embodiments of the present application provide an instruction processing method, device, electronic device and computer program product to at least solve the technical problem of large power consumption and long time consumption of multiple data write actions in the process of multiple execution of data write instructions by the processor.

[0006] According to an aspect of an embodiment of the present application, an instruction processing method is provided, comprising: receiving a target data write instruction, wherein the target data write instruction carries a target memory address of target data to be written into a physical register; in response to the target data write instruction, based on the correspondence between the physical register and the memory address, checking whether there is a target physical register corresponding to the target memory address; in the case where the checking result is that there is a target physical register corresponding to the target memory address, returning a data write result that the target data has been written into the target physical register.

[0007] According to a further aspect of the embodiments of the present application, an instruction processing apparatus is also provided, comprising: a receiving module configured to receive a target data write instruction, wherein the target data write instruction carries a target memory address of target data to be written into a physical register; a responding module configured to, in response to the target data write instruction, find whether there is a target physical register corresponding to the target memory address based on a correspondence between the physical register and the memory address; and a returning module configured to return a data write result that the target data has been written into the target physical register when the finding result is that there is the target physical register corresponding to the target memory address.

[0008] According to a further aspect of the embodiments of the present application, an electronic device is also provided, comprising: a memory storing an executable program; and a processor configured to run the program, wherein the program performs the instruction processing method in the embodiments of the present application when running.

[0009] According to a further aspect of the embodiments of the present application, a computer readable storage medium is also provided, comprising a stored executable program, wherein the executable program controls a device where the storage medium is located to perform the instruction processing method in the embodiments of the present application when running.

[0010] According to a further aspect of the embodiments of the present application, a computer program product is also provided, comprising a computer program, which, when executed by a processor, implements the instruction processing method in the embodiments of the present application.

[0011] In the embodiments of the present application, the correspondence between the physical register and the memory address is established, the target data write instruction is received, wherein the target data write instruction carries the target memory address of the target data to be written into the physical register; in response to the target data write instruction, whether there is the target physical register corresponding to the target memory address is found based on the correspondence between the physical register and the memory address; and when the finding result is that there is the target physical register corresponding to the target memory address, the data write result that the target data has been written into the target physical register is returned, so that when the target physical register storing the data of the target memory address is found, the target physical register is directly used for subsequent processing, and the data of the target memory address does not need to be written into the physical register again, thereby achieving the technical effect of reducing the power consumption and time of the processor executing the data write instruction, and further solving the technical problem of large power consumption and long time consumption of multiple data write actions in the process of the processor executing the data write instruction multiple times.

[0012] It is easily noticed that the general description and the following detailed description are merely examples and illustrations of the present application, and do not constitute limitations of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0014] Fig. 1 shows a hardware structure block diagram of a RISC-V system for implementing an instruction processing method;

[0015] Fig. 2 shows a schematic diagram of a System On Chip (SOC) using the RISC-V architecture shown in Fig. 1;

[0016] Fig. 3 is a flow chart of an instruction processing method according to Embodiment 1 of the present application;

[0017] Fig. 4 is a schematic diagram of processing a matrix instruction according to an optional embodiment of the present application;

[0018] Fig. 5 is a schematic diagram of a physical matrix register stack according to an optional embodiment of the present application;

[0019] Fig. 6 is a schematic diagram of a physical matrix register state table according to an optional embodiment of the present application;

[0020] Fig. 7 is a schematic diagram of an instruction processing method according to an optional embodiment of the present application;

[0021] Fig. 8 is a structure block diagram of an instruction processing device according to Embodiment 2 of the present application;

[0022] Fig. 9 is a structure block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0025] First, some of the nouns or terms that appear in the description of the embodiments of the present application are applicable to the following explanations:

[0026] Access: read or write.

[0027] Register: a structure for storing data that can be directly accessed by CPU instructions.

[0028] Architectural Register: a software concept of a register state. Architectural register is a concept in computer architecture. Computer architecture is the interface between computer hardware and software, which defines how a computer executes instructions, stores data, and handles input and output. In computer architecture, registers are high-speed storage units used to store instructions, data, and control information. Architectural registers refer to registers that are specifically defined in computer architecture, which have specific functions and operating rules in different instruction set architectures (ISA). The main functions of architectural registers include: (1) storing instruction addresses: the program counter (PC) is a common architectural register that stores the address of the instruction currently being executed. (2) data transfer: general purpose registers (GPR) are used to store temporary data such as operation results, variables, etc. (3) state control: status registers (SR) or flag registers are used to store processor state information such as interrupt flags, condition codes, etc. (4) control registers: control registers are used to control specific functions of the processor, such as exception handling, interrupt masking, etc. Architectural registers are usually defined in the instruction set architecture (ISA), and programmers need to follow these rules to access and operate these registers when writing programs. Different computer architectures may have different architectural registers, but their basic functions and roles are similar.

[0029] Physical register: A register entity implemented on hardware, which can be seen by software as a mapping of an architectural register.

[0030] Register file: A collection of multiple registers.

[0031] Cache: A memory used to temporarily store data at a portion of memory space.

[0032] Memory access: Reading or writing data from or to memory or cache.

[0033] Load instruction: An instruction used to move data at a specified address in memory to a register.

[0034] Store instruction: An instruction used to write data in a register to a specified address in memory.

[0035] Stride: The difference between the memory addresses corresponding to two adjacent rows of a register in a matrix load or store instruction.

[0036] Base address: The starting address of memory accessed by a matrix load or store instruction.

[0037] Cacheline: The smallest granularity of data managed by a cache, typically 64 bytes in size.

[0038] Cache hit: The memory data required by a load instruction is already completely present in the cache.

[0039] Register renaming: Hardware mapping of an architectural register to a certain physical register, after which access to the physical register represents access to the corresponding architectural register.

[0040] A matrix coprocessor is a hardware device or software component designed for matrix operations. In the field of computer science and engineering, matrix operations are a class of very important computational tasks, such as linear algebra, image processing, signal processing, and machine learning, etc. The matrix coprocessor can significantly improve the overall computing efficiency by optimizing the performance of these matrix operations. The main features and functions of the matrix coprocessor include: (1) dedicated hardware: the matrix coprocessor may be a separate hardware device, or a specific hardware module integrated in the CPU or other processors. These hardware are specially designed for efficient processing of matrix operations. (2) optimized algorithms: compared with CPU, the matrix coprocessor usually uses optimized algorithms and data structures to process matrix operations, which helps to reduce the calculation time and resource consumption. (3) parallel processing: the matrix coprocessor usually supports parallel processing, which can process multiple matrix elements simultaneously, thereby improving the calculation speed. (4) floating-point operation capability: since matrix operations usually involve a large number of floating-point operations, the matrix coprocessor usually has a powerful floating-point operation unit. (5) memory management: the matrix coprocessor may optimize memory access patterns to reduce the impact of memory latency and bandwidth limitations on performance. (6) software support: the matrix coprocessor usually has corresponding software libraries or APIs, which make it easy for programmers to call the functions of these hardware in the program. (7) specific application optimization: some matrix coprocessors may be optimized for specific types of matrix operations or applications, such as graphics processing, machine learning algorithms, etc. Using the matrix coprocessor can greatly improve the performance of specific types of computing tasks, especially in application scenarios that require a large number of matrix operations. However, they are usually not suitable for general computing tasks, because their design focuses on specific computing patterns.

[0041] Embodiment 1

[0042] According to an embodiment of the present application, a method for processing instructions is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] The method provided in the embodiment one of the application can be executed in a RISC-V system, a RISC-V chip or similar devices. FIG. 1 shows a hardware structure block diagram of a RISC-V system for implementing an instruction processing method. As shown in FIG. 1, the RISC-V system 100 can be divided into a reduced instruction set architecture 101 (containing a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, peripheral hardware circuits 102-2 and the like), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, …, 104-n, such as Linux, FreeSBD, RT-Tread and the like), a middleware and library layer 105 (containing system libraries 105-1, APIs 105-2 and middleware services 105-3) and an application program layer 106 (including multiple user programs and services 106-1, 106-2, …, 106-n) from bottom to top. The RISC-V system 100 further contains a tool chain 107 between the bottom hardware and the application program layer, which can include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7 and a version control system 107-8 and the like.

[0044] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set, wherein the basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operation, compression instruction and the like.

[0045] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction and the like. This layer is the process of mapping abstract instructions to physical hardware.

[0046] The operating system layer 104 is located above the hardware, providing a hardware abstraction layer and management mechanism, so that the application program can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling and the like.

[0047] The middleware and library layer 105 provides a set of rich services and interfaces to help the application program run more efficiently. For example, the standard library provides file operations, mathematical calculations and the like, and the middleware can provide network communication, graphical user interface and the like complex services.

[0048] The application program layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic, and these application programs can be command line tools, graphical interface applications, server side services and the like.

[0049] The tool chain 107 is a key component that connects the underlying hardware to the upper software. Various tools in the tool chain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0050] It should be noted that the hierarchical design of the RISC-V architecture allows decoupling between different levels, so that each level can be developed and optimized independently.

[0051] In an optional embodiment, FIG. 2 shows a schematic diagram of a System On Chip (SOC) using the RISC-V architecture shown in FIG. 1 described above. As shown in FIG. 2, the SOC internally includes at least one RISC-V core 202 (only one is shown in the figure), which is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0052] In the related art, when a processor performs data operations, data write instructions are usually used to load the data to be processed from the memory into the registers of the processor for subsequent processing and calculation. The register is a high-speed storage unit inside the processor, and its access speed is much faster than that of the memory. When the processor needs to perform data operations, it can quickly process and calculate the data written in the register without waiting for memory access.

[0053] However, in actual processing, when the amount of data to be processed is large or the data structure is complex, the processor needs to execute a large number of data write instructions. In this case, frequent data writing will cause high power consumption and long time consumption. More seriously, if there is a large amount of repeated data in the data written multiple times, this process will cause a waste of resources.

[0054] Taking matrix operation as an example, if there is a large amount of repeated matrix in the matrix data written multiple times, the same matrix data will be written into the register multiple times when executing the data write instruction. This not only causes a waste of resources, but also reduces the efficiency of the operation.

[0055] To solve this problem, in the above operating environment, the application provides an instruction processing method as shown in FIG. 3. FIG. 3 is a flowchart of the instruction processing method according to Embodiment 1 of the application.

[0056] In step S301, a target data write instruction is received, wherein the target data write instruction carries a target memory address of target data to be written into a physical register.

[0057] In this step, the execution subject can be a processor, and the target data write instruction is an instruction for writing target data into a physical register, which includes a target memory address of the target data in the memory. The processor can find the target data in the memory according to the target memory address, and copy and write the target data into the physical register, so that the processor can quickly read and process data from the physical register when processing the target data.

[0058] It should be noted that the instruction processing method provided by the application can be applied in the operation process of matrix data, at this time, the execution subject can be a matrix coprocessor, and the target data can be matrix data. Correspondingly, the target data write instruction can be a target matrix load instruction. In this case, a plurality of physical registers need to be set to store matrix data, and each physical register can be a two-dimensional structure, containing multiple rows, and each row can store data.

[0059] In FIG. 4, the matrix coprocessor is used to process the matrix instruction. The extended matrix register, the newly added matrix instruction execution unit, the matrix memory access subsystem, the matrix data cache and other hardware structures can be implemented inside the matrix coprocessor outside the CPU core, and are decoupled from the CPU core. The matrix coprocessor and the CPU core are connected through a bus and can communicate with each other. A certain level of cache is shared between the matrix coprocessor and the CPU core.

[0060] The working mode of the matrix coprocessor is as follows: the CPU fetches the instruction stream of a program from an instruction memory and decodes. If the CPU judges that a certain instruction is a matrix instruction, the instruction is sent to the matrix coprocessor outside the core through the bus, and the matrix coprocessor is responsible for the specific execution process of the matrix instruction, including accessing the matrix register stack, completing the matrix operation, accessing the internal matrix data cache, and initiating the access request of the shared cache.

[0061] In step S302, in response to the target data write instruction, whether there is a target physical register corresponding to the target memory address is found based on the correspondence between the physical register and the memory address.

[0062] In this step, after receiving the target data write instruction, the processor can search based on the previously established correspondence between the physical register and the memory address, and determine whether there is a target physical register that has stored the target data at the target memory address, that is, in the correspondence between the physical register and the memory address, it is determined that the memory address corresponding to the target physical register is the same as the target memory address.

[0063] Because when data processing is performed, it is likely to involve calculation of a large amount of repeated data. Therefore, the correspondence between the physical register and the memory address can be updated synchronously each time data is written into the current physical register, so as to ensure that in the correspondence between the physical register and the memory address, the memory address corresponding to the current physical register is the address in the memory where the data stored in the current physical register is located.

[0064] In step S303, in the case where the search result is that there is a target physical register corresponding to the target memory address, a data write result that the target data has been written into the target physical register is returned.

[0065] In this step, the correspondence between the physical register and the memory address is searched to determine that there is a target physical register corresponding to the target memory address, that is, it is determined that the target data has been stored in the target physical register before, at this time, it can be directly determined that the target data write instruction has been completed, because the target data has been written into the target physical register, and a data write result is returned. That is, the data write result is used to indicate that the target data has been successfully written into the target physical register.

[0066] It should be noted that when the target data to be written is matrix data, the instruction processing method provided by the present application can also be used to determine whether there is a target physical register that has stored the target data based on the established correspondence between the physical register and the memory address, and if there is, a data write result that the target data has been written into the target physical register can also be directly returned.

[0067] In the embodiment of the present application, the corresponding relationship between the physical register and the memory address is established, the target data write instruction is received, the target memory address where the target data to be written into the physical register is carried in the target data write instruction, the target physical register corresponding to the target memory address is searched based on the corresponding relationship between the physical register and the memory address in response to the target data write instruction, and the data write result that the target data has been written into the target physical register is returned in the case that the target physical register corresponding to the target memory address is found. Thus, the subsequent processing can be directly performed by using the target physical register in the case that the target physical register storing the data of the target memory address is found, and the data of the target memory address does not need to be written into the physical register again, so that the technical effect of reducing the power consumption and time of the processor executing the data write instruction is achieved, and the technical problem of large power consumption and long time consumption of the multiple data write actions in the process that the processor executes the data write instruction multiple times is solved.

[0068] As an optional embodiment, before the target physical register corresponding to the target memory address is searched based on the corresponding relationship between the physical register and the memory address in response to the data write instruction, the method further includes: receiving one or more data write instructions, wherein the one or more data write instructions respectively carry the memory addresses where the data to be written into the physical register is located; writing the data into the physical register in response to the one or more data write instructions; and establishing the corresponding relationship between the physical register where the data is written and the corresponding memory address based on the one or more data write instructions.

[0069] Optionally, the corresponding relationship between the physical register where the data is written and the memory address where the data is located can be established before the target physical register is searched based on the corresponding relationship between the physical register and the memory address. The processor can write the data into the physical register according to the received one or more data write instructions, and establish the corresponding relationship between the physical register where the data is written and the memory address where the data is located. The one or more data write instructions are used to write the specified data from the memory into the physical register, and each data write instruction carries the memory address where the data to be written into the physical register is located. Then, the specified data can be copied from the memory into the corresponding physical register according to the memory address where the data is located in the data write instruction. After the data is written into the physical register, a mapping table can be established to record the corresponding relationship between the physical register and the memory address. The mapping table is very important for the subsequent data processing process, and the processor can quickly find the physical register related to a specific memory address through the mapping table.

[0070] Through this embodiment, the instruction processing method can effectively receive and execute the data write instruction before executing the data write operation, and establish the correspondence between the physical register and the memory address. This not only improves the efficiency of data processing, but also provides convenience for subsequent data access and operation.

[0071] When the present optional embodiment is applied in the matrix data processing process, the correspondence between the memory address where the matrix data is located and the physical register where the matrix data is written can be established. Therefore, when the matrix data needs to be written into the physical register later, the correspondence can be used to find out whether the matrix data to be written has been written into a physical register before, and if so, the matrix data does not need to be written again, saving the energy consumption of repeated writing of the matrix data and improving the processing efficiency of the matrix data.

[0072] As an optional embodiment, in response to the target data write instruction, based on the correspondence between the physical register and the memory address, it is found out whether there is a target physical register corresponding to the target memory address, comprising: determining a target physical register group from the plurality of physical register groups according to the target memory address; and matching the target memory address with the memory addresses corresponding to the physical registers included in the target physical register group to find out whether there is a target physical register corresponding to the target memory address.

[0073] Optionally, since a plurality of physical registers are generally provided in the processor to store data, it would be tedious, time-consuming and energy-consuming to use the traversal method to find out whether there is a target physical register in the plurality of physical registers. At this time, all the physical registers capable of storing data can be grouped according to certain rules to obtain a plurality of physical register groups, and then it is found out whether there is a target physical register in the target physical register group. In this way, the search range can be narrowed down to the target physical register group, and it is not necessary to search all the physical registers capable of storing data, so that the time consumption can be reduced and the energy consumption can be lowered.

[0074] In order to ensure that if there is a target physical register, the target physical register must be in the target physical register group, and if there is no target physical register in the target physical register group, there cannot be a target physical register in other physical registers, the grouping rule of the physical registers can be set in relation to the memory addresses corresponding to the physical registers, that is, the physical registers can be grouped according to the memory addresses corresponding to the physical registers respectively, or in other words, after the physical registers are grouped, the memory addresses corresponding to the data capable of being stored by each group of physical registers are limited within a certain range.

[0075] As an optional embodiment, the target physical register group is determined from the target memory address, comprising: obtaining a number of groups of the plurality of physical registers; determining an index of a cache block where the target memory address is located; and determining the target physical register group according to the index and the number of groups.

[0076] Optionally, the target physical register group can be located according to the number of groups of the plurality of physical registers and the index of the cache block where the target memory address is located. Correspondingly, when storing data in the registers, the physical register group that can store the data can be found according to the memory address and the number of groups, so that when searching for the target physical register where the target data is stored, the target physical register group can be determined according to the target memory address and the number of groups.

[0077] Specifically, all the registers in the plurality of physical registers are divided into M groups, and when the matrix coprocessor assigns a physical register number to each data write instruction to store data, the following rules need to be followed: the new physical register assigned must come from a specific group of the M groups, and the calculation of the group number is related to the target memory address included in the data write instruction.

[0078] Therefore, when searching for whether the target physical register exists, the target physical register group can be located according to the index of the cache block where the target memory address is located and the number of groups.

[0079] When the optional embodiment is applied in the matrix operation process, FIG. 5 is a schematic diagram of a physical matrix register heap according to the optional embodiment of the present application, as shown in FIG. 5, the physical matrix register heap (the plurality of physical registers) includes K physical registers, and each row of each register can write data. All the registers in the physical matrix register heap are divided into M groups, and each group contains N registers. Here, M*N=K needs to be met. The values of M and N depend on the specific hardware implementation. When the matrix coprocessor assigns a physical register number to each matrix load instruction, the new physical register assigned must come from a specific group of the M groups in the physical matrix register heap, and the calculation of the group number is related to the memory address carried in the matrix load instruction.

[0080] As an optional embodiment, the target physical register group is determined according to the index and the number of groups, comprising: taking the index modulo the number of groups to obtain a modulo value; and taking the modulo value as the group number of the target physical register group to determine the target physical register group.

[0081] Optionally, the index of the cache block where the target memory address is located is taken modulo the number of groups, and the obtained modulo value is the group number of the target physical register group. It should be noted that the method of determining the modulo value as the group number of the target physical register group based on the modulo operation is only an example, and the method of determining the group number of the target physical register group based on other operations also belongs to the present application.

[0082] The memory address carried by the matrix loading instruction usually includes a base address and a stride. The matrix loading instruction loads data at different addresses in the memory into each of the (RLEN / 32) rows of the physical matrix register (equivalent to a physical register), respectively. The memory address corresponding to the data loaded by each row of the physical matrix register is related to the base address and the stride. Specifically, the starting memory address corresponding to the data loaded by the rth row of the physical matrix register is calculated as “base address + r*stride”, and r takes 0 to (RLEN / 32)-1. When the present optional embodiment is applied in the matrix operation process, the index of the cache block where the base address of the matrix loading instruction is located is taken modulo the number of groups, and the obtained modulo value is the group number of the physical register group.

[0083] As an optional embodiment, the method further includes establishing a mapping between the target physical register and a target architecture register. The data write instruction further includes the number of the target architecture register to be loaded with the target data, and the target architecture register is visible to software.

[0084] It should be noted that in the actual data processing process, the physical register is not directly visible to software, but is mapped to an architecture register to be visible to software. Therefore, the data write instruction carries the number of the architecture register, and the processor selects a physical register to establish a mapping relationship with the architecture register, so that the software can access the data in the physical register.

[0085] In the scenario of applying the present optional embodiment in matrix calculation, the architecture register is a register that can be directly accessed by the matrix instruction. Each architecture register is a two-dimensional structure and includes RLEN*(RLEN / 32) bits, where (RLEN / 32) is the number of rows of a matrix register, and RLEN is the number of bits of each row. The number of architecture registers can be 8, numbered m0-m7. Of course, the number of architecture registers can be set according to actual needs, and can also be 16.

[0086] The matrix coprocessor maintains a physical matrix register file (multiple physical registers) internally, which includes K matrix registers, where the size of K depends on the specific hardware implementation, but is at least greater than the number of architectural registers. During program execution, the matrix coprocessor selects 8 registers from the K register space in the physical matrix register file (22) as the mapping of the 8 architectural registers m0-m7. The mapping relationship is recorded by a renaming mapping table. The table has 8 table entries, each corresponding to an architectural register, and each table entry records the physical register number in the physical matrix register file to which the current architectural register is mapped. The above process of establishing the mapping relationship between the architectural registers and the physical registers is also referred to as the register renaming strategy.

[0087] The above mapping relationship can be dynamically adjusted during program execution. That is, whenever a new matrix instruction is issued from the CPU core to the matrix coprocessor, if the matrix instruction contains the number md of the destination architectural register, where md is a number between m0-m7, the matrix coprocessor will specify a new physical register mapping for the architectural register md, and update the new physical register number in the renaming mapping table. It should be noted that the above renaming mapping table and the correspondence between the physical registers and the memory addresses mentioned in the present application are not consistent. The renaming mapping table establishes the correspondence between the architectural registers and the physical registers.

[0088] After determining the target physical register, the mapping relationship between the target physical register and the target architectural register in the data write instruction can be established, and the renaming mapping table is updated, so that the software can access the data in the physical register.

[0089] As an optional embodiment, in the case where the target physical register includes multiple rows, the target memory address includes a target base address and a target address stride, where the target base address is the starting address in the memory where the target physical register writes data, and the target address stride is the difference between the memory addresses corresponding to two adjacent rows in the target physical register. The base address corresponding to the target physical register matches the target base address, and the address stride corresponding to the target physical register matches the target address stride.

[0090] This optional embodiment provides the format of the target memory address in the matrix load instruction (equivalent to the data write instruction) when processing matrix data. The memory address carried by the matrix load instruction usually includes a base address and a stride. The matrix load instruction will load data at different addresses in the memory for each row in the (RLEN / 32) rows of the matrix register. The starting memory address corresponding to the data loaded by the rth row of the matrix register is calculated as "base address + r*stride", where r takes 0 to (RLEN / 32)-1.

[0091] In this case, when determining the target physical register matching the target memory address, it is determined that the target base address also matches, and the target address step also matches. Further, the matching is the same, when the target base address in the target memory address is the same as the base address corresponding to a certain physical register, and the target address step is also the same as the address step corresponding to the physical register, it is determined that the physical register is the target physical register.

[0092] As an optional embodiment, the method further comprises: in the case that the lookup result is that there is no target physical register corresponding to the target memory address, determining a backup physical register; writing the target data at the target memory address into the backup physical register, and returning a data write result that the target data has been written into the backup physical register.

[0093] Optionally, if no target physical register corresponding to the target memory address is found in the correspondence between the physical registers and the memory addresses, only a backup physical register can be re-determined to store the data at the target memory address, and after the target data is written into the backup physical register, a data write result that the target data has been written into the backup physical register is returned.

[0094] Specifically, in the plurality of physical registers, the backup physical register can be determined in the following manner: according to the target memory address, a corresponding target physical register group is found, and the backup physical register is determined in the physical registers included in the target physical register group. Since the physical register needs to establish a mapping relationship with the architectural register to be visible to software, when determining the backup physical register, whether an architectural register is being mapped onto a physical register is also considered. If an architectural register is being mapped onto a certain physical register, the physical register cannot be used as a backup physical register.

[0095] The register state information can be set to mark the current state of the physical matrix register, and the backup physical register is selected according to the register state information. A physical matrix register can be in one of the following three states:

[0096] Mapping state: a certain architectural register (m0-7) is currently being mapped onto the physical register.

[0097] Cache state: no architectural register (m0-7) is currently being mapped onto the physical register, but the destination register of a matrix load instruction has been mapped onto the physical register, and the data loaded in the register is currently consistent with the latest data at the corresponding address in the memory.

[0098] Idle state: in addition to the above two cases, the physical register is in an idle state.

[0099] The register state information corresponding to each physical register can also be recorded in the correspondence between the physical register and the memory address (i.e., the physical matrix register state table). That is, FIG. 6 is a schematic diagram of a physical matrix register state table according to an optional embodiment of the present application. As shown in FIG. 6, the correspondence between the physical register and the memory address (i.e., the physical matrix register state table) includes three types of information: base address, stride, and register state information. Among them, the two pieces of information of base address and stride are used to record the memory access base address and stride value of a matrix load instruction. Specifically, if the destination matrix register of a matrix load instruction is mapped to a physical matrix register numbered pmd, when the instruction is executed, not only the data in the memory will be loaded into the physical matrix register numbered pmd, but also the base address and stride information of the instruction will be written into the correspondence between the physical register and the memory address corresponding to the position numbered pmd, and the register state corresponding to the pmd number will be adjusted to the mapping state.

[0100] As a specific embodiment, FIG. 7 is a schematic diagram of an instruction processing method according to an optional embodiment of the present application. As shown in FIG. 7, first, the matrix coprocessor will judge the type of the currently executed matrix instruction. Among them, the matrix instruction is roughly divided into two categories: one is a matrix operation instruction; and the other is a matrix memory instruction. The matrix operation instruction generally specifies 2-3 matrix registers from the architecture registers m0-m7 as the source operand, and after completing the operation under a certain rule (such as floating point / integer matrix multiplication and accumulation operation) on these data, writes the obtained result into a destination matrix register specified from m0-m7.

[0101] The matrix memory instruction is divided into a matrix load instruction and a matrix store instruction. The matrix load instruction generally has three pieces of information, which are: the base address of the memory access, the stride of the memory access, and the matrix register number md to be loaded. The matrix load instruction will load the data in the memory at different addresses for each row in the (RLEN / 32) rows of the matrix register, respectively. Among them, the calculation method of the starting address of the data corresponding to the rth row of the matrix register in the memory is "base address+r*stride", and r takes 0 to (RLEN / 32)-1. Similarly, the matrix store instruction also has three pieces of information, which are: the base address of the memory access, the stride of the memory access, and the matrix register number ms to be stored. The behavior of the matrix store instruction is: write each row in the (RLEN / 32) rows of the matrix register numbered ms to different addresses in the memory, respectively. Among them, the calculation method of the starting address of the rth row in the memory is "base address+r*stride", and r takes 0 to (RLEN / 32)-1.

[0102] Secondly, if the matrix coprocessor judges that a matrix load instruction is executed, before allocating a new physical register mapping for the destination matrix register of the instruction, the index of the cache block where the base address of the matrix load instruction is located (i.e. Cacheline index) is taken modulo M (%M means taken modulo M), and then the physical matrix register state table needs to be queried to check the information of the N physical registers in the (Cacheline index %M)th group, including: base address, stride, register state.

[0103] At this time, there are two cases:

[0104] Case 1: If it is found that there is a register numbered pmdst0 in the N registers, whose register state is cache state, and its base address and stride are exactly the same as the memory access base address and stride of the current matrix load instruction, then the destination matrix register of the instruction is mapped to the physical register pmdst0. This case is called "cache hit". After that, the instruction will be sent to the matrix memory unit for execution, but considering that the data required by the matrix load instruction has been confirmed to exist in the pmdst0 number physical register, the matrix memory unit can directly determine that the instruction has completed execution, and does not need to access the shared cache again.

[0105] Case 2: Otherwise, the destination matrix register of the instruction is mapped to any one of the physical registers pmdst1 in the (Cacheline index %M)th group in the cache state or idle state. After that, the instruction will be sent to the matrix memory unit for execution, and the matrix memory unit will obtain data from the shared cache between the CPU and the matrix coprocessor according to the memory address of the instruction, and load it into the physical register pmdst1.

[0106] If the matrix coprocessor judges that a matrix load instruction is not executed, the physical matrix register state table is queried, a register number pmdst2 in the cache state or idle state is selected as the physical register number of the instruction, and the required data is read from the physical matrix register heap and sent to the matrix operation unit or memory unit for execution, and finally the operation result is written back to the register numbered pmdst2 in the physical matrix register heap.

[0107] The scheme is provided with a physical matrix register state table for a physical matrix register stack, which records the state of each physical register and the memory address information of the data source. Therefore, the physical matrix register stack of the matrix coprocessor can be used as a mapping of the architecture register and a mapping of the memory space, serving as a data cache. The scheme makes full use of the space of the physical register, uses the part not mapped by the architecture register as a data cache, and provides an opportunity for data multiplexing. The matrix loading instruction hitting the cache does not need to access the external storage unit, saving the external memory bandwidth. Moreover, the architecture register and the data cache of the scheme are mapped in a unified physical register stack. When the matrix loading instruction hitting the cache is executed, no data movement is needed, and only the mapping relationship of the architecture register to the physical register needs to be modified, reducing power consumption, hardware implementation complexity, and execution delay of the matrix loading instruction.

[0108] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0109] It should be noted that for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the action sequence described, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0110] From the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, or network device, etc.) execute the method described in each embodiment of the present application.

[0111] Example 2

[0112] According to the embodiments of the present application, an instruction processing device for implementing the above instruction processing method is also provided. FIG. 8 is a structural block diagram of the instruction processing device according to Embodiment 2 of the present application. As shown in FIG. 8, the device comprises:

[0113] The receiving module 81 is configured to receive a target data write instruction, wherein the target data write instruction carries a target memory address of target data to be written into a physical register.

[0114] The responding module 82, connected with the receiving module 81, is configured to, in response to the target data write instruction, find whether there is a target physical register corresponding to the target memory address based on the correspondence between the physical register and the memory address.

[0115] The returning module 83, connected with the responding module 82, is configured to return a data write result that the target data has been written into the target physical register in the case that the finding result is that there is the target physical register corresponding to the target memory address.

[0116] It should be noted that the above receiving module 81, responding module 82 and returning module 83 correspond to steps S301 to S303 in Embodiment 1, and the above modules have the same instances and application scenarios as the corresponding steps, but are not limited to the above disclosed contents of Embodiment 1. It should be noted that the above modules or units can be hardware components or software components stored in a memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b, …, 102n), and the above modules can also be a part of the device and can run in the computer terminal 10 provided in Embodiment 1.

[0117] It should be noted that the preferred embodiments involved in the above embodiments of the present application have the same scheme, application scenario and implementation process as Embodiment 1, but are not limited to the scheme provided in Embodiment 1.

[0118] Embodiment 3

[0119] The embodiments of the present application can provide an electronic device, which can be any one of the electronic devices in the electronic device group. Alternatively, in the present embodiment, the above electronic device can also be replaced by a terminal device such as a mobile terminal.

[0120] Alternatively, in the present embodiment, the above electronic device can be located in at least one network device of the plurality of network devices of the computer network.

[0121] In the present embodiment, the above computer terminal can execute the program code in the method.

[0122] Optionally, FIG. 9 is a structural block diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 9, the electronic device can include one or more (only one is shown in the figure) processors 102, a memory 104, a storage controller, and a peripheral interface, wherein the peripheral interface is connected with a radio frequency module, an audio module, and a display.

[0123] The memory can be used to store software programs and modules, such as program instructions / modules corresponding to the methods and devices in the embodiments of the present application. The processor executes various functions and data processing by running the software programs and modules stored in the memory, i.e., implements the methods in the above embodiments. The memory can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory can further include a memory remotely arranged with respect to the processor, which can be connected to the terminal through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0124] The processor can call information and applications stored in the memory through the transmission device to perform the following steps: receiving a target data write instruction, wherein the target data write instruction carries a target memory address of target data to be written in a physical register; in response to the target data write instruction, based on the correspondence between the physical register and the memory address, searching whether there is a target physical register corresponding to the target memory address; in the case that the searching result is that there is a target physical register corresponding to the target memory address, returning a data write result that the target data has been written into the target physical register.

[0125] Optionally, the processor can further execute program codes of the following steps: before the step of, in response to the data write instruction, based on the correspondence between the physical register and the memory address, searching whether there is a target physical register corresponding to the target memory address, the method further includes: receiving one or more data write instructions, wherein the one or more data write instructions respectively carry memory addresses of data to be written in the physical register; in response to the one or more data write instructions, writing data into the physical register; establishing a correspondence between the physical register in which the data is written based on the one or more data write instructions and the corresponding memory address.

[0126] Optionally, the processor can further execute program codes of the following steps: in response to the target data write instruction, based on the correspondence between the physical registers and the memory addresses, finding whether there is a target physical register corresponding to the target memory address, including: determining a target physical register group from the plurality of physical register groups according to the target memory address; and matching the target memory address with the memory addresses corresponding to the physical registers included in the target physical register group to find whether there is a target physical register corresponding to the target memory address.

[0127] Optionally, the processor can further execute program codes of the following steps: determining a target physical register group from the plurality of physical register groups according to the target memory address, including: obtaining a number of groupings of the plurality of physical registers; determining an index of a cache block where the target memory address is located; and determining the target physical register group according to the index and the number of groupings.

[0128] Optionally, the processor can further execute program codes of the following steps: determining the target physical register group according to the index and the number of groupings, including: taking a modulus of the index with the number of groupings to obtain a modulus value; and taking the modulus value as a group number of the target physical register group to determine the target physical register group.

[0129] Optionally, the processor can further execute program codes of the following steps: the method further includes: establishing a mapping between the target physical register and a target architectural register, wherein the data write instruction further includes a number of the target architectural register to be loaded with the target data, and the target architectural register is visible to software.

[0130] Optionally, the processor can further execute program codes of the following steps: in the case that the target physical register includes multiple rows, the target memory address includes a target base address and a target address step, wherein the target base address is a starting address in the memory where the target physical register writes data, the target address step is a difference between memory addresses corresponding to two adjacent rows in the target physical register, the base address corresponding to the target physical register matches the target base address, and an address step corresponding to the target physical register matches the target address step.

[0131] Optionally, the processor can further execute program codes of the following steps: the method further includes: in the case that the finding result is that there is no target physical register corresponding to the target memory address, determining a backup physical register; writing the target data at the target memory address into the backup physical register, and returning a data write result that the target data has been written into the backup physical register.

[0132] By adopting the embodiment of the application, a scheme for instruction processing is provided. A corresponding relationship between a physical register and a memory address is established, a target data write instruction is received, the target data write instruction carries a target memory address where target data to be written into a physical register is located, a target physical register corresponding to the target memory address is searched based on the corresponding relationship between the physical register and the memory address in response to the target data write instruction, and a data write result that the target data has been written into the target physical register is returned in a case where the searching result is that the target physical register corresponding to the target memory address exists. Thus, the target physical register is directly used for subsequent processing in a case where the target physical register storing the data of the target memory address is found, and the data of the target memory address does not need to be written into the physical register again, so that the technical effect of reducing power consumption and time of a processor executing a data write instruction is achieved, and the technical problem of large power consumption and long time consumption of multiple data write actions in the process that the processor executes the data write instruction multiple times is solved.

[0133] Those skilled in the art can understand that the structure shown in the figure is only schematic, and the electronic device can also be a terminal device such as a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a Mobile Internet Device (MID), a PAD, etc. The figure does not limit the structure of the above-mentioned electronic device. For example, the electronic device can further include more or fewer components (such as a network interface, a display device, etc.) than those shown in the figure, or have a different configuration from that shown in the figure.

[0134] Those skilled in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by instructing the related hardware of the terminal device through a program, and the program can be stored in a computer readable storage medium, and the storage medium can include a flash disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, etc.

[0135] Embodiment 4

[0136] The embodiment of the application further provides a computer readable storage medium. Optionally, in the embodiment, the above-mentioned computer readable storage medium can be used to save the program code executed by the method provided in the above-mentioned embodiment.

[0137] Optionally, in the embodiment, the above-mentioned storage medium can be located in any one of the electronic devices in the group of electronic devices in the computer network, or in any one of the mobile terminal in the group of mobile terminals.

[0138] Optionally, in the embodiment, the computer readable storage medium is configured to store program code for performing the following steps: receiving a target data write instruction, wherein the target data write instruction carries a target memory address where target data to be written into a physical register; in response to the target data write instruction, searching for whether there is a target physical register corresponding to the target memory address based on the correspondence between the physical register and the memory address; and in the case that the searching result is that there is the target physical register corresponding to the target memory address, returning a data write result that the target data has been written into the target physical register.

[0139] Optionally, the computer readable storage medium is further configured to store program code for performing the following steps: before searching for whether there is a target physical register corresponding to the target memory address based on the correspondence between the physical register and the memory address in response to the data write instruction, the method further comprises: receiving one or more data write instructions, wherein the one or more data write instructions respectively carry memory addresses where data to be written into the physical register; in response to the one or more data write instructions, writing the data into the physical register; and establishing the correspondence between the physical register where the data is written based on the one or more data write instructions and the corresponding memory address.

[0140] Optionally, the computer readable storage medium is further configured to store program code for performing the following steps: in response to the target data write instruction, searching for whether there is a target physical register corresponding to the target memory address based on the correspondence between the physical register and the memory address, comprises: determining a target physical register group from a plurality of physical register groups according to the target memory address; and matching the target memory address with memory addresses corresponding to physical registers included in the target physical register group to search for whether there is a target physical register corresponding to the target memory address.

[0141] Optionally, the computer readable storage medium is further configured to store program code for performing the following steps: determining a target physical register group from a plurality of physical register groups according to the target memory address, comprises: obtaining a grouping number of the plurality of physical register groups; determining an index of a cache block where the target memory address is located; and determining the target physical register group according to the index and the grouping number.

[0142] Optionally, the computer readable storage medium is further configured to store program code for performing the following steps: determining the target physical register group according to the index and the grouping number, comprises: taking a modulus of the index with the grouping number to obtain a modulus value; and taking the modulus value as a group number of the target physical register group to determine the target physical register group.

[0143] Optionally, the computer readable storage medium is further configured to store program code for performing the following step: the method further comprises: establishing a mapping between the target physical register and a target architecture register, wherein the data write instruction further comprises a number of the target architecture register to be loaded with the target data, and the target architecture register is visible to software.

[0144] Optionally, the computer readable storage medium is further configured to store program code for performing the following step: in a case where the target physical register comprises multiple rows, the target memory address comprises a target base address and a target address step, wherein the target base address is a starting address of the target physical register to write data in the memory, and the target address step is a difference between memory addresses corresponding to two adjacent rows in the target physical register, the base address corresponding to the target physical register matches the target base address, and the address step corresponding to the target physical register matches the target address step.

[0145] Optionally, the computer readable storage medium is further configured to store program code for performing the following step: the method further comprises: in a case where the lookup result is that there is no target physical register corresponding to the target memory address, determining a backup physical register; writing the target data at the target memory address into the backup physical register, and returning a data write result that the target data has been written into the backup physical register.

[0146] Embodiment 5

[0147] The embodiment of the present application further provides a computer program product. Optionally, the computer program product can include a computer program, and the computer program is executed by a processor to implement the method provided by the above embodiment.

[0148] Embodiment 6

[0149] The embodiment of the present application further provides a computer program product. Optionally, the computer program product can include a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium can be used to store a computer program. The computer program is executed by a processor to implement the method provided by the above embodiment.

[0150] Embodiment 7

[0151] The embodiment of the present application further provides a computer program. Optionally, the computer program is executed by a processor to implement the method provided by the above embodiment.

[0152] The above sequence numbers of the embodiments of the present application are only for description, and do not represent advantages or disadvantages of the embodiments.

[0153] In the above-described embodiments of the present application, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0154] In several embodiments provided in the present application, it should be understood that the disclosed technical contents can be implemented by other ways. Among them, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division way, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or modules shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, which can be electrical or other forms.

[0155] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0156] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above integrated unit can be realized in the form of hardware or in the form of software functional unit.

[0157] The integrated unit, if realized in the form of software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part of the prior art that makes a contribution or the whole or part of the technical solutions can be embodied in the form of software product, which is stored in a storage medium and includes a plurality of instructions for making a computer device (which can be a personal computer, a server or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic or optical disk and various program code storage media.

[0158] The above is only the preferred embodiment of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. A method for processing instructions, comprising: receiving a target data write instruction, wherein the target data write instruction carries a target memory address of target data to be written into a physical register; in response to the target data write instruction, searching for a target physical register corresponding to the target memory address based on a correspondence between physical registers and memory addresses; in a case where the searching result is that there is a target physical register corresponding to the target memory address, returning a data write result that the target data has been written into the target physical register.

2. The method of claim 1, wherein, Before the searching for the target physical register corresponding to the target memory address based on the correspondence between the physical registers and the memory addresses in response to the data write instruction, the method further comprises: receiving one or more data write instructions, wherein the one or more data write instructions respectively carry memory addresses of data to be written into physical registers; in response to the one or more data write instructions, writing the data into the physical registers; establishing the correspondence between the physical registers and the corresponding memory addresses based on the data written by the one or more data write instructions.

3. The method of claim 1, wherein, The searching for the target physical register corresponding to the target memory address based on the correspondence between the physical registers and the memory addresses in response to the target data write instruction comprises: determining a target physical register group from a plurality of physical register groups according to the target memory address; matching the target memory address with a memory address corresponding to a physical register included in the target physical register group to search for whether there is the target physical register corresponding to the target memory address.

4. The method of claim 3, wherein, The determining the target physical register group from the plurality of physical register groups according to the target memory address comprises: obtaining a number of groupings of the plurality of physical register groups; determining an index of a cache block where the target memory address is located; determining the target physical register group according to the index and the number of groupings.

5. The method of claim 4, wherein, The determining the target physical register group according to the index and the number of groupings comprises: taking a modulus of the index with the number of groupings to obtain a modulus value; determining the target physical register group by taking the modulus value as a group number of the target physical register group.

6. The method of claim 1, wherein, The method further comprises establishing a mapping between the target physical register and a target architectural register, wherein the data write instruction further comprises a number of the target architectural register where the target data is to be loaded, and the target architectural register is visible to software.

7. The method of claim 1, wherein, in a case where the target physical register comprises a plurality of rows, the target memory address comprises a target base address and a target address step, wherein the target base address is a starting address in memory where the target physical register writes data, the target address step is a difference between memory addresses corresponding to two adjacent rows in the target physical register, a base address corresponding to the target physical register matches the target base address, and an address step corresponding to the target physical register matches the target address step.

8. The method of any one of claims 1 to 7, wherein, further comprising: determining a backup physical register in a case that the lookup result is that there is no target physical register corresponding to the target memory address; writing target data at the target memory address into the backup physical register, and returning a data write result that the target data has been written into the backup physical register. 9.An instruction processing apparatus, comprising: a receiving module configured to receive a target data write instruction, wherein the target data write instruction carries a target memory address of target data to be written into a physical register; a responding module configured to, in response to the target data write instruction, look up whether there is a target physical register corresponding to the target memory address based on a correspondence between physical registers and memory addresses; a returning module configured to, in a case that the lookup result is that there is a target physical register corresponding to the target memory address, return a data write result that the target data has been written into the target physical register. 10.An electronic device, comprising: a memory storing an executable program; a processor configured to run the program, wherein the program, when executed, performs the instruction processing method of any one of claims 1 to 8.

11. A computer readable storage medium comprising a stored executable program, wherein, controlling the device where the storage medium is located to perform the instruction processing method of any one of claims 1 to 8 when the executable program is executed. 12.A computer program product comprising a computer program which, when executed by a processor, implements the instruction processing method of any one of claims 1 to 8.

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