Information processing method and apparatus, device, and storage medium

Abstract

According to embodiments of the present disclosure, provided are an information processing method and apparatus, a device, and a storage medium. The method comprises: determining a target processing layer from among a plurality of processing layers of a graph neural network, wherein a processing procedure corresponding to the target processing layer comprises a plurality of sub-processing procedures independent of each other; splitting the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing procedures; using a plurality of processing devices to respectively process the plurality of sub-processing procedures corresponding to the plurality of sub-layers; and using a plurality of output results of processing of the plurality of processing devices in a summary layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

Description

Information processing method, apparatus, device, and storage medium

[0001] The present application claims priority to the Chinese patent application No. 202410733370.X, filed on June 6, 2024, entitled “Information processing method, apparatus, device, and storage medium”, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The example embodiments of the present disclosure generally relate to the field of computer, and in particular, to an information processing method, apparatus, device, and computer readable storage medium. BACKGROUND

[0003] Multi-GPU inference refers to an inference process based on a model in the field of deep learning and machine learning, where the inference process can be a process of using a trained model to make predictions or classifications on new data. The trained model can be a graph neural network (GNN) or the like. How to improve the inference efficiency is a focus problem. SUMMARY

[0004] In a first aspect of the present disclosure, an information processing method is provided. The method comprises: determining a target processing layer from a plurality of processing layers of a graph neural network, a processing process corresponding to the target processing layer comprising a plurality of sub-processing processes independent of each other; splitting the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing processes; processing the plurality of sub-processing processes corresponding to the plurality of sub-layers by a plurality of processing devices respectively; and processing a plurality of output results of the plurality of processing devices in a summary layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

[0005] In a second aspect of the present disclosure, an apparatus for information processing is provided. The apparatus comprises: a first determining module configured to determine a target processing layer from a plurality of processing layers of a graph neural network, a processing process corresponding to the target processing layer comprising a plurality of sub-processing processes independent of each other; a splitting module configured to split the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing processes; a first processing module configured to process the plurality of sub-processing processes corresponding to the plurality of sub-layers by a plurality of processing devices respectively; and a second processing module configured to process a plurality of output results of the plurality of processing devices in a summary layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

[0006] In a third aspect of the present disclosure, an electronic device is provided. The device includes at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor. The instructions, when executed by the at least one processor, cause the device to perform the method of the first aspect.

[0007] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium has stored thereon computer- executable instructions that are executable by a processor to implement the method of the first aspect.

[0008] In a fifth aspect of the present disclosure, a computer program product is provided. The computer program product is tangibly stored in a computer storage medium and includes computer-executable instructions that, when executed by a device, cause the device to perform the method of the first aspect.

[0009] It is to be understood that the details set forth herein are by way of example and not intended to limit the scope of the embodiments of the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description, from the drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other features, aspects, and advantages of embodiments of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals denote like elements, and wherein:

[0011] FIG. 1 shows a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

[0012] FIG. 2 shows a flowchart of a process of information processing according to some embodiments of the present disclosure;

[0013] FIG. 3 shows an example graph of a graph convolution network according to some embodiments of the present disclosure;

[0014] FIG. 4A shows an example graph of a processing procedure corresponding to a target processing layer according to some embodiments of the present disclosure;

[0015] FIG. 4B shows an example graph of a processing procedure based on multiple sub-layers and a summary layer according to some embodiments of the present disclosure;

[0016] FIG. 4C shows another example graph of a processing procedure based on multiple sub-layers and a summary layer according to some embodiments of the present disclosure;

[0017] FIG. 5 shows a schematic structural block diagram of an apparatus for information processing according to certain embodiments of the present disclosure;

[0018] FIG. 6 shows a block diagram of an electronic device capable of implementing embodiments of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0020] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0021] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0023] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0024] Conventionally, a common graph convolutional network is often in a single-card inference mode, an independent data multi-card inference mode, and a memory-optimized multi-card inference mode during inference. However, these inference modes have different problems, such as slow inference speed and large workload of processing devices in the single-card inference mode, and only independent processing of mutually independent data in the independent data multi-card inference mode, and an unsatisfactory processing result for data with strong correlation such as graph structure.

[0025] Embodiments of the present disclosure provide a scheme for information processing. According to the scheme, a target processing layer can be determined from a plurality of processing layers of a graph neural network, a processing process corresponding to the target processing layer including a plurality of sub-processing processes independent of each other; the target processing layer is split into a plurality of sub-layers corresponding to the plurality of sub-processing processes; a plurality of processing devices are used to process the plurality of sub-processing processes corresponding to the plurality of sub-layers, respectively; and a plurality of output results of the plurality of processing devices are processed in a summary layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

[0026] Based on such a manner, compared with one processing device processing a processing process corresponding to the target processing layer, embodiments of the present disclosure can use a plurality of processing devices to process a plurality of sub-processing processes corresponding to a plurality of sub-layers, respectively, and each processing device processes a simpler processing process, which can effectively reduce the workload of the processing device. In addition, each processing device can process a simpler processing process in parallel, which reduces the inference time and improves the inference efficiency.

[0027] Example Environment

[0028] FIG. 1 shows a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. As shown in FIG. 1, the example environment 100 can include an electronic device 110.

[0029] In the example environment 100, the electronic device 110 includes a plurality of processing devices. The processing device can be a graphics processing unit (GPU). One GPU can process inference corresponding to one processing layer in a graph neural network 120.

[0030] In some embodiments, the electronic device 110 can split a target processing layer in the graph neural network 120 into a plurality of sub-layers, and insert a summary layer corresponding to the plurality of sub-layers behind the plurality of sub-layers, the summary layer being used to summarize output results of the plurality of sub-layers to determine a target output result for the target processing layer, i.e., the output result obtained based on the first graph structure and the target processing layer is the same as the output result obtained based on the first graph structure, the plurality of sub-layers, and the summary layer. The graph neural network 120 can be deployed on the electronic device 110, and can also be deployed on other devices, which will not be described here.

[0031] In some embodiments, the electronic device 110 can be any type of mobile terminal, fixed terminal, or portable terminal including a mobile handset, a tablet computer, a laptop computer, a notebook computer, a netbook computer, a smartbook, a media tablet, a palmtop computer, a portable gaming terminal, a VR / AR device, a Personal Communication System (PCS) terminal, a personal navigation device, a Personal Digital Assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an electronic book device, a game device, or any combinations of these, including accessories and peripherals of these devices, or any combinations thereof. In some embodiments, the electronic device 110 can also support any type of interface to the target user (such as "wearable" circuitry, etc.).

[0032] The electronic device 110 can also be a standalone physical server, a server cluster or distributed system of multiple physical servers, a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content distribution networks, and basic cloud computing services such as big data and artificial intelligence platforms, etc. The electronic device 110 may, for example, include a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, etc.

[0033] It should be understood that the structure and function of the various elements in the environment 100 are described for illustrative purposes only, without implying any limitation on the scope of the present disclosure.

[0034] Some example embodiments of the present disclosure will be described below with continued reference to the drawings.

[0035] Example Interaction

[0036] FIG. 2 illustrates a flowchart of a process 200 of information processing, according to some embodiments of the present disclosure. The process 200 can be implemented at the electronic device 110. The process 200 is described below with reference to FIG. 1.

[0037] At block 210, the electronic device 110 can determine a target processing layer from a plurality of processing layers of a graph neural network, a processing process corresponding to the target processing layer including a plurality of sub-processing processes independent of each other.

[0038] In some embodiments, the graph neural network can be any suitable deep learning model for processing graph structure. The graph structure mainly includes nodes and edges, and the core idea of the graph neural network is to enable each node to receive and send information from its neighbor nodes through a mechanism of message passing (or aggregation), so that each node can capture and integrate the information of its neighborhood in the graph structure, thereby learning a comprehensive node representation. The neighbor nodes are other nodes connected to the node, and the two nodes connected by an edge in the graph structure.

[0039] In some embodiments, the graph neural network can include a plurality of processing layers, and each processing layer can correspond to a respective processing process.

[0040] In some embodiments, the electronic device 110 can determine a target processing layer from the plurality of processing layers of the graph neural network, where the processing process corresponding to the target processing layer includes a plurality of sub-processing processes independent of each other. The plurality of sub-processing processes are aggregated based on a predetermined rule to obtain the processing process corresponding to the target processing layer. The target processing layer can also be referred to as a parallel layer. The processing layers of the graph neural network other than the parallel layer can be referred to as non-parallel layers, i.e., layers that do not include a plurality of sub-processing processes independent of each other.

[0041] For example, if the processing process corresponding to a layer is y = x, then the layer does not include a plurality of sub-processing processes independent of each other, and thus the layer is a non-parallel layer. If the processing process corresponding to a layer is z = a * x + c * y, then the layer includes at least two sub-processing processes independent of each other, and thus the layer is a parallel layer, where the two sub-processing processes are z1 = a * x and z2 = a * x, and z1 and z2 can be aggregated by addition to obtain z.

[0042] In some embodiments, in order to improve inference efficiency, the time consumption of the target processing layer is greater than the maximum time consumption of the plurality of sub-processing processes and the time consumption corresponding to the aggregation.

[0043] In some embodiments, for a processing layer F in a graph neural network, if given an input G(N, E), the electronic device 110 can split the input G(N, E) into G_0(N_0, E_0), G_1(N_1, E_1)... G_n(N_n, E_n) according to a rule, i.e., the processing process corresponding to the processing layer F includes multiple processing processes that are independent of each other. If it can be determined that there is a layer M that is independent of G(N, E) such that F(G(N, E)) = M(F(G_0(N_0, E_0)), F(G_1(N_1, E_1)),... (G_n(N_n, E_n))), and T(F(G)) < max{T(F(G_i)), i = {0, 1,.., n}} + T(M), where T(F(G)) is the time consumption of the processing process F(G) corresponding to the target processing layer G, T(F(G_i)), i = {0, 1,.., n} is the time consumption corresponding to each processing process that is independent of each other, and T(M) is the time consumption corresponding to the aggregation, the electronic device 110 can determine that the processing layer F is the target processing layer.

[0044] In some embodiments, the electronic device 110 can determine a plurality of candidate combinations associated with a plurality of sub-processing processes, each candidate combination including a plurality of candidate sub-layers and a candidate aggregation layer. For example, if the processing process corresponding to the target processing layer is z = a * y * (x + b), the electronic device 110 can determine at least candidate combination 1 and candidate combination 2, where candidate combination 1 can include two candidate sub-layers and a candidate aggregation layer, the processing process corresponding to one of the candidate sub-layers can be x + b, the processing process corresponding to the other candidate sub-layer can be a * y, and the processing process corresponding to the candidate aggregation layer can be multiplying the processing results corresponding to the two candidate sub-layers. Candidate combination 2 can include two candidate sub-layers, the processing process corresponding to one of the candidate sub-layers can be a * y * x, the processing process corresponding to the other candidate sub-layer can be a * y * b, and the processing process corresponding to the candidate aggregation layer can be adding the processing results corresponding to the two candidate sub-layers.

[0045] In order to improve the efficiency of inference, the electronic device 110 can determine a target combination from the plurality of candidate combinations based on time consumption information corresponding to the plurality of candidate combinations.

[0046] In some embodiments, the target time consumption corresponding to the target combination is less than a threshold value.

[0047] In other embodiments, the processing time corresponding to the target processing layer can be equal to the sum of the total processing time corresponding to multiple sub-layers in the target combination and a predetermined time value, wherein the predetermined time value is much smaller than the processing time corresponding to the target processing layer, and the total processing time corresponding to multiple sub-layers is the sum of the processing times corresponding to each sub-layer, i.e., T(F(G)) = sum{T(F(G_i)),i = {0,1,..,n}} + ET, where T(F(G)) is the processing time of the processing F(G) corresponding to the target processing layer G, T(F(G_i)),i = {0,1,..,n} is the processing time corresponding to each independent processing, and ET is the predetermined time value.

[0048] In some other embodiments, the target time corresponding to the target combination can also be the one with the least time among all candidate combinations.

[0049] In some embodiments, the electronic device 110 may determine multiple candidate sub-layers included in the target combination as multiple sub-layers corresponding to multiple sub-processes. The electronic device 110 may also determine a candidate summarizing layer corresponding to the target combination as a summarizing layer corresponding to the multiple sub-layers.

[0050] In box 220, electronic device 110 can split the target processing layer into multiple sub-layers corresponding to multiple sub-processes.

[0051] In some embodiments, during the training phase of a graph neural network, the electronic device 110 can split the target processing layer into multiple sub-layers corresponding to multiple sub-processes, that is, the electronic device 110 can split the target processing layer in the graph neural network into these multiple sub-layers before training the graph neural network.

[0052] In other embodiments, during the inference phase of the graph neural network, the electronic device 110 can split the target processing layer into multiple sub-layers corresponding to multiple sub-processes. That is, the electronic device 110 can first train the graph neural network instead of splitting the target processing layer in the graph neural network into multiple sub-layers corresponding to multiple sub-processes, and then perform inference based on the split graph neural network during the inference phase of the graph neural network.

[0053] Figure 3 shows an example diagram of graph convolutional networks of some embodiments of the present disclosure, and will now be described with reference to Figure 3.

[0054] Taking Figure 3 as an example, the electronic device 110 can split the parallelizable layer in the graph neural network into multiple sub-layers. For example, for the parallelizable layer 310, the electronic device 110 can split the parallelizable layer 310 into sub-layers 311, 312 and 313.

[0055] The electronic device 110 can insert a summary layer behind the split sub-layers, such as inserting a summary layer 320 behind the sub-layer 311, the sub-layer 312, and the sub-layer 313, to support that the summary layer 320 can determine the target output result for the parallelizable layer 310 based on the output results of the sub-layer 311, the sub-layer 312, and the sub-layer 313.

[0056] For the non-parallelizable layer, the electronic device 110 can not split it, such as the non-parallelizable layer 330 is not split.

[0057] At block 230, the electronic device 110 can use multiple processing devices to process multiple sub-processes corresponding to multiple sub-layers, respectively.

[0058] In some embodiments, the multiple processing devices include multiple graphic processing units (GPUs). The multiple processing devices can be driven in a manner that each process manages one processing device, or in a manner that one process manages all processing devices.

[0059] In some embodiments, the electronic device 110 can split the first graph structure to be input to the target processing layer into multiple sub-graph structures based on the multiple sub-layers and the summary layer in the target combination.

[0060] FIG. 4A shows an example of a processing process corresponding to a target processing layer of some embodiments of the present disclosure, and FIG. 4B shows an example of a processing process based on multiple sub-layers and a summary layer of some embodiments of the present disclosure. Now, FIG. 4A and FIG. 4B are described.

[0061] As shown in FIG. 4A, the first graph structure input to the target processing layer 410 is 420, and the processing process corresponding to each node in the first graph structure 420 by the target processing layer 410 is: U i =∑j∈[0,1,2,3],j≠iE ij ×N i , where N i is the information corresponding to the node i, and E ij is the information of the edge connecting the node i and the node j. The first graph structure 420 includes four nodes, N0, N1, N2, and N3, and any two nodes in the four nodes have a connection relationship, such as an edge E01 between N0 and N1 and an edge E12 between N1 and N2, and so on. The electronic device 110 can use the target processing layer 410 and the first graph structure 420 to obtain a graph structure 430 (target output result), where U0=E 01 ×N0+E 02 ×N0+E 03 ×N0, U1=E 01 ×N1+E 12×N1+E 13 ×N1, U2 = E 02 ×N2+E 12 ×N2+E 23 ×2, U3 = E 03 ×N3+E 13 ×N3+E 23 ×N3.

[0062] As an example of FIG. 4B, the electronic device 110 can split the first graph structure 420 into two sub-graph structures, such as a sub-graph structure 440 and a sub-graph structure 441, where the sub-graph structure 440 only contains N0, N1, N2, N3, edge E01, edge E03, and edge E12. The sub-graph structure 441 only contains N0, N1, N2, N3, edge E02, edge E23, and edge E13.

[0063] The electronic device 110 can use multiple processing devices to process multiple sub-processing processes corresponding to multiple sub-layers, where one sub-layer corresponds to one sub-graph structure.

[0064] As an example of FIG. 4B, the electronic device 110 can split the target processing layer 410 into a sub-layer 450 and a sub-layer 451. The electronic device 110 can input the sub-graph structure 440 into the sub-layer 450, use one processing device to process the sub-processing process corresponding to the sub-layer 450, to obtain a graph structure 460. The electronic device 110 can input the sub-graph structure 441 into the sub-layer 451, use one processing device to process the sub-processing process corresponding to the sub-layer 451, to obtain a graph structure 461.

[0065] In some embodiments, for any target sub-layer in the multiple sub-layers, the second graph structure to be output into the target sub-layer is obtained after marking the target marker information in the first graph structure to be input into the target processing layer, where the target marker information is used to represent the information of the target graph structure to be processed in the target sub-layer. In some embodiments, the first graph structure includes nodes and edges. The information of the nodes and edges included in each second graph structure is the same as the information of the nodes and edges included in the first graph structure, except that the target marker information is marked in the second graph structure, where the target marker information is used to indicate the nodes to be processed and / or the edges to be processed, to indicate that after the second graph structure is input into the sub-layer, the sub-layer can determine to perform reasoning based on the nodes to be processed and / or the edges to be processed.

[0066] As shown in FIG. 4C, the first graph structure 420 includes four nodes, N0, N1, N2, and N3, and any two nodes in the four nodes have a connection relationship, such as an edge E01 between N0 and N1, an edge E12 between N1 and N2, and the like. The electronic device 110 can determine two second graph structures, such as the graph structure 470 and the graph structure 471 in FIG. 4C. The graph structure 470 and the graph structure 471 both include the information that N0, N1, N2, N3, and any two nodes in the four nodes have a connection relationship. In the graph structure 470, the information of N0, N1, N2, N3, the edge E01, the edge E03, and the edge E12 can be set with an identifier 1, to indicate that the information is input to the nodes or the edges to be processed in the sub-layer 450. In the graph structure 471, the information of N0, N1, N2, N3, the edge E02, the edge E23, and the edge E13 can be set with an identifier 1, to indicate that the information is input to the nodes or the edges to be processed in the sub-layer 451.

[0067] The electronic device 110 can use a plurality of processing devices to process a plurality of sub-processing processes corresponding to a plurality of sub-layers, and one sub-layer corresponds to one second graph structure.

[0068] As shown in FIG. 4C, the electronic device 110 can split the target processing layer 410 into the sub-layer 450 and the sub-layer 451. The electronic device 110 can input the graph structure 470 to the sub-layer 450, and use a processing device to process the sub-processing process corresponding to the sub-layer 450 to obtain the graph structure 460. The electronic device 110 can input the graph structure 471 to the sub-layer 451, and use a processing device to process the sub-processing process corresponding to the sub-layer 451 to obtain the graph structure 461.

[0069] At block 240, the electronic device 110 can process a plurality of output results of a plurality of processing devices in a summary layer corresponding to a plurality of sub-layers to determine a target output result for the target processing layer.

[0070] In some embodiments, the electronic device 110 can insert a summary layer corresponding to a plurality of sub-layers behind the plurality of sub-layers, so that the electronic device 110 can receive output results respectively corresponding to the plurality of sub-layers by using the summary layer corresponding to the plurality of sub-layers, and determine a target output result for the target processing layer based on the output results respectively corresponding to the plurality of sub-layers.

[0071] As shown in FIG. 4B, the electronic device 110 can input the graph structure 461 and the graph structure 460 to the summary layer 480 to obtain the graph structure 430, which is the same as the output result obtained by directly inputting the graph structure 410 to the target processing layer 420.

[0072] In some embodiments, in order to accurately determine whether the result output by the summary layer is consistent with the output result of the target processing layer, the electronic device 110 can insert a cache module in the summary layer, so as to check whether the result output by the summary layer for the same data is consistent during single-card and multi-card reasoning, to determine the data consistency of multi-card reasoning. This cache module can be replaced by end-to-end result verification, or can be removed when deploying the split graph convolutional network later.

[0073] The present disclosure can effectively improve the reasoning efficiency and reduce the reasoning time by splitting the target processing layer into multiple sub-layers and inserting a summary layer to obtain the target output result of the target processing layer. The following describes a specific embodiment.

[0074] Taking an example in which the time consumption of each addition and multiplication is 1, the first graph structure includes 100 vertices, and each vertex is connected to each other, that is, there are a total of 4950 edges in the first graph structure. If the target processing layer is not split, since each edge is calculated twice, N multiplications on each vertex need to be calculated N-1 times of addition, then the electronic device 110 can determine that the total time consumption based on the target processing layer is: 4950*2+(4950*2-100)=19700. If the electronic device 110 splits the target processing layer into two sub-layers, and each sub-layer only needs to process half of the edges, and the summary layer also uses addition as an example, the electronic device 110 can determine that the total time consumption based on the two sub-layers and the summary layer is: 4950÷2*2+(4950÷2-100)+100=9900.

[0075] Based on such a manner, compared with a processing device processing a processing process corresponding to the target processing layer, the embodiments of the present disclosure can utilize multiple processing devices to respectively process multiple sub-processing processes corresponding to multiple sub-layers, and each processing device processes a simpler processing process, which can effectively reduce the workload of the processing device. In addition, each processing device can process a simpler processing process in parallel, which reduces the reasoning time consumption and improves the reasoning efficiency.

[0076] Example apparatus and device

[0077] Embodiments of the present disclosure also provide a corresponding apparatus for implementing the above method or process. FIG. 5 shows a schematic structural block diagram of an apparatus 500 for information processing according to certain embodiments of the present disclosure. The apparatus 500 can be implemented as or included in the electronic device 110 as discussed above. Each module / component in the apparatus 500 can be implemented by hardware, software, firmware, or any combination thereof.

[0078] As shown in FIG. 5, the apparatus 500 includes a first determining module 510 configured to determine a target processing layer from a plurality of processing layers of a graph neural network, a processing procedure corresponding to the target processing layer including a plurality of sub-processing procedures independent of each other; a splitting module 520 configured to split the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing procedures; a first processing module 530 configured to process the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by using a plurality of processing devices; and a second processing module 540 configured to process a plurality of output results of the plurality of processing devices in an aggregation layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

[0079] In some embodiments, the splitting module 520 is specifically configured to determine a plurality of candidate combinations associated with the plurality of sub-processing procedures, each candidate combination including a plurality of candidate sub-layers; determine a target combination from the plurality of candidate combinations based on time consumption information corresponding to the plurality of candidate combinations; and determine the plurality of candidate sub-layers included in the target combination as the plurality of sub-layers corresponding to the plurality of sub-processing procedures.

[0080] In some embodiments, each candidate combination further includes a candidate aggregation layer, and the apparatus 500 further includes a second determining module configured to determine the candidate aggregation layer corresponding to the target combination as the aggregation layer corresponding to the plurality of sub-layers.

[0081] In some embodiments, a target time consumption corresponding to the target combination is less than a threshold value.

[0082] In some embodiments, the first processing module 530 is specifically configured to split a first graph structure to be input to the target processing layer into a plurality of sub-graph structures based on the plurality of sub-layers and the aggregation layer; and process the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by using the plurality of processing devices, one sub-layer corresponding to processing one sub-graph structure.

[0083] In some embodiments, the first processing module 530 is specifically configured to determine a plurality of second graph structures to be input to the plurality of sub-layers based on processing procedures corresponding to the plurality of sub-layers and the aggregation layer, wherein for any target sub-layer in the plurality of sub-layers, a second graph structure to be output to the target sub-layer is obtained after marking target marking information in the first graph structure to be input to the target processing layer, the target marking information being used to represent information of a target structure graph to be processed in the target sub-layer; and process the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by using the plurality of processing devices, one sub-layer corresponding to processing one second graph structure.

[0084] In some embodiments, the first graph structure includes nodes and edges, and the target marking information is used to indicate nodes to be processed and / or edges to be processed.

[0085] In some embodiments, the splitting module 520 is specifically configured to split the target processing layer into a plurality of sub-layers corresponding to a plurality of sub-processing processes in a training phase of the graph neural network; or split the target processing layer into a plurality of sub-layers corresponding to a plurality of sub-processing processes in an inference phase of the graph neural network.

[0086] In some embodiments, the plurality of processing devices includes a plurality of graphics processors.

[0087] The units included in the apparatus 500 can be implemented in various ways, including software, hardware, firmware, or any combination thereof. In some embodiments, one or more units can be implemented using software and / or firmware, e.g., machine-executable instructions stored on a storage medium. In addition to or alternatively, some or all of the units in the apparatus 500 can be implemented at least in part by one or more hardware logic components. As examples and not by way of limitation, exemplary types of hardware logic components that can be used include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0088] FIG. 6 illustrates a block diagram of an electronic device 600 in which one or more embodiments of the disclosure can be implemented. It should be understood that the electronic device 600 illustrated in FIG. 6 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. The electronic device 600 illustrated in FIG. 6 can be used to implement the electronic device 110 illustrated in FIG. 1.

[0089] As shown in FIG. 6, the electronic device 600 is in the form of a general electronic device. The components of the electronic device 600 can include, but are not limited to, one or more processors or processor(s) 610, memory 620, storage 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processor(s) 610 can be a real or virtual processor and is capable of performing various processing according to programs stored in the memory 620. In a multi-processor system, multiple processors perform computer-executable instructions in parallel to improve the parallel processing capability of the electronic device 600.

[0090] The electronic device 600 typically includes a plurality of computer storage media. Such media can be any available media that is accessible by the electronic device 600 and includes both volatile and nonvolatile media, removable and non-removable media. The memory 620 can be volatile (such as register, cache, RAM), non-volatile (such as ROM, EEPROM, flash memory), or some combination of the two. The storage device 630 can be a removable or non-removable media, and can include machine-readable media, such as flash drives, magnetic disks, or any other media that can be used to store information and / or data (e.g., training data for training) and that can be accessed by the electronic device 600.

[0091] The electronic device 600 can further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in FIG. 6, a disk drive for reading from or writing to a removable, non- volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk (e.g., a CD-ROM) can be provided. In such instances, each drive can be connected to the bus (not shown) by one or more data media interfaces. The memory 620 can include a computer program product 625 having one or more program modules configured to carry out the various methods or actions of the various embodiments of the present disclosure.

[0092] The communication unit 640 enables communications with other electronic devices over a communication medium. Additionally, the functionality of the components of the electronic device 600 can be implemented in a single computing cluster or a plurality of computer machines that are capable of communicating with one another over a communication connection. As such, the electronic device 600 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network nodes in the networking environment.

[0093] The input device 650 can be one or more input devices, such as a mouse, a keyboard, a trackball, etc. The output device 660 can be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 600 can also communicate with one or more external devices (not shown) such as a storage device, a display device, etc. through the communication unit 640, as needed, one or more devices that enable a user to interact with the electronic device 600, or any devices (e.g., a network card, a modem, etc.) that enable the electronic device 600 to communicate with one or more other electronic devices. Such communication can be carried out via an input / output (I / O) interface (not shown).

[0094] According to an example implementation of the present disclosure, a computer readable storage medium is provided having computer executable instructions stored thereon, where the computer executable instructions are executed by a processor to implement the method described above. According to an example implementation of the present disclosure, a computer program product is also provided that is tangibly stored on a non-transitory computer readable medium and includes computer executable instructions, where the computer executable instructions are executed by a processor to implement the method described above.

[0095] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0096] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium. The instructions stored on the computer readable storage medium can be used to program a computer, a programmable data processing apparatus, and / or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0097] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0098] The computer program product of the second implementation can include a computer readable storage medium. The computer readable storage medium can include instructions. The instructions can include one or both of: instructions for causing a computer to enable a user equipment device to receive a configuration message from a base station, the configuration message comprising a configuration of a plurality of search space sets for a plurality of downlink control channel candidates; and instructions for causing a computer to enable a user equipment device to monitor the plurality of downlink control channel candidates in accordance with the configuration of the plurality of search space sets.

[0099] Various implementations of the disclosure have been described in detail above. The foregoing description is exemplary and explanatory only, and is not intended to be exhaustive or to limit various implementations of the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings without departing from the scope and spirit of the disclosure. It is intended that the scope of the disclosure be limited only by the claims and the equivalents thereof. The use of the terms "including," "containing," "comprising," "having," "in involving," "portions," "elements," "components," "steps," "phases," "processes," "operations," "steps," "stages," "procedures," "methods," "mechanisms," "devices," "systems," "apparatuses," "units," "means," "units," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems," "apparatuses," "units," "means," "devices," "systems

Claims

1. An information processing method comprising: determining a target processing layer from a plurality of processing layers of a graph neural network, a processing procedure corresponding to the target processing layer comprising a plurality of sub-processing procedures independent of each other; splitting the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing procedures; processing the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by a plurality of processing devices; and processing a plurality of output results of the plurality of processing devices in a summary layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

2. The method of claim 1, wherein splitting the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing procedures comprises: determining a plurality of candidate combinations associated with the plurality of sub-processing procedures, each candidate combination comprising a plurality of candidate sub-layers; determining a target combination from the plurality of candidate combinations based on time consumption information corresponding to the plurality of candidate combinations; and determining the plurality of candidate sub-layers included in the target combination as the plurality of sub-layers corresponding to the plurality of sub-processing procedures.

3. The method of claim 2, wherein each candidate combination further comprises a candidate summary layer, the method further comprising: determining the candidate summary layer corresponding to the target combination as the summary layer corresponding to the plurality of sub-layers.

4. The method of claim 2, wherein a target time consumption corresponding to the target combination is less than a threshold value.

5. The method of claim 1, wherein processing the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by a plurality of processing devices comprises: splitting a first graph structure to be input to the target processing layer into a plurality of sub-graph structures based on the plurality of sub-layers and the summary layer; and processing the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by the plurality of processing devices, one sub-layer corresponding to processing one sub-graph structure.

6. The method of claim 1, wherein processing the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by a plurality of processing devices comprises: determining a plurality of second graph structures to be input to the plurality of sub-layers based on processing procedures corresponding to the plurality of sub-layers and the summary layer, wherein for any target sub-layer in the plurality of sub-layers, a second graph structure to be output to the target sub-layer is obtained after marking target marker information in a first graph structure to be input to the target processing layer, the target marker information being used to represent information to be processed of the target graph structure in the target sub-layer; and processing the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by the plurality of processing devices, one sub-layer corresponding to processing one second graph structure.

7. The method of claim 6, wherein the first graph structure comprises nodes and edges, and the target marker information is used to indicate nodes to be processed and / or edges to be processed.

8. The method of claim 1, wherein splitting the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing procedures comprises: ​ ​ ​ In a training phase of the graph neural network, the target processing layer is split into the multiple sub-layers corresponding to the multiple sub-processing procedures. Or In an inference phase of the graph neural network, the target processing layer is split into the multiple sub-layers corresponding to the multiple sub-processing procedures.

9. The method of claim 1, wherein the plurality of processing devices comprises a plurality of graphics processors.

10. An apparatus for information processing, comprising: a first determining module configured to determine a target processing layer from a plurality of processing layers of a graph neural network, a processing procedure corresponding to the target processing layer comprising a plurality of sub-processing procedures independent of each other; a splitting module configured to split the target processing layer into a plurality of sub-layers corresponding to the plurality of sub-processing procedures; a first processing module configured to process the plurality of sub-processing procedures corresponding to the plurality of sub-layers respectively by a plurality of processing devices; and a second processing module configured to process a plurality of output results of the plurality of processing devices in a summary layer corresponding to the plurality of sub-layers to determine a target output result for the target processing layer.

11. An electronic device, comprising: at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, cause the electronic device to perform the method according to any one of claims 1-9.

12. A computer-readable storage medium having computer-executable instructions stored thereon that are executable by a processor to implement the method according to any one of claims 1-9.

13. A computer program product tangibly stored in a computer storage medium and comprising computer-executable instructions that, when executed by a device, cause the device to perform the method according to any one of claims 1-9. ​

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