Method for manufacturing semiconductor structure, and semiconductor structure

Abstract

A method for manufacturing a semiconductor structure, and a semiconductor structure. The method comprises: providing a substrate, wherein the substrate is provided with active pillars arranged at intervals in both a first direction and a second direction, the first direction and the second direction are both parallel to a surface of the substrate, the first direction is perpendicular to the second direction, a first dielectric layer is provided between active pillars, and the first dielectric layer is at least flush with the active pillars; forming word line structures, wherein the word line structures surround the active pillars and extend in the first direction, and a plurality of word line structures are arranged at intervals in the second direction; removing at least part of the first dielectric layers to form first openings; forming contact structures, wherein the contact structures at least partially fill the first openings; and forming capacitor structures, wherein the capacitor structures are electrically connected to the contact structures.

Description

Method for manufacturing semiconductor structure and semiconductor structure

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese Patent Application No. 202410732590.0, filed on June 6, 2024, entitled "Method for Manufacturing Semiconductor Structure and Semiconductor Structure", the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a method for manufacturing semiconductor structure and semiconductor structure. BACKGROUND

[0004] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory, compared with static memory, DRAM memory has the advantages of simple structure, low manufacturing cost and high capacity density. With the development of semiconductor industry, semiconductor devices are becoming highly integrated, i.e. miniaturization. Highly integrated semiconductor devices are changing from planar channel transistors to vertical channel transistors (VCT).

[0005] However, in the manufacturing process of vertical channel transistors, the manufacturing process of semiconductor memory devices is still complex and the yield is low. How to improve the yield of semiconductor memory devices and simplify the manufacturing process of semiconductor memory devices is a technical problem to be solved at present. SUMMARY

[0006] The present disclosure provides a method for manufacturing semiconductor structure and semiconductor structure, which at least has the advantages of improving the yield of semiconductor memory devices and simplifying the manufacturing process of semiconductor memory devices.

[0007] According to some embodiments of the present disclosure, the present disclosure provides a method for manufacturing semiconductor structure, comprising:

[0008] providing a substrate, the substrate having active pillars spaced apart along a first direction and a second direction, the first direction and the second direction being parallel to a surface of the substrate, the first direction and the second direction being perpendicular, the active pillars having a first dielectric layer therebetween, the first dielectric layer being at least flush with the active pillars;

[0009] forming word line structures, the word line structures surrounding the active pillars and extending along the first direction, the plurality of word line structures being spaced apart along the second direction;

[0010] removing at least part of the first dielectric layer to form a first opening;

[0011] forming a contact structure, the contact structure at least partially filling the first opening;

[0012] forming a capacitor structure, the capacitor structure electrically connected to the contact structure.

[0013] In some embodiments, the first opening sidewall exposes a portion of the active pillar, and the first opening bottom exposes a portion of the first dielectric layer.

[0014] In some embodiments, the method further comprises: performing a first processing process on the portion of the active pillar exposed by the first opening sidewall to expand the exposed portion of the active pillar to form an active pillar protrusion, performing a second processing process on the active pillar protrusion to form an initial contact structure, the initial contact structure partially filling the first opening, and the second opening being formed between adjacent initial contact structures.

[0015] In some embodiments, the method further comprises: forming a second dielectric layer, the second dielectric layer filling the second opening and covering the initial contact structure, removing a portion of the second dielectric layer and a portion of the initial contact structure, the remaining initial contact structure serving as the contact structure, a top dimension of the contact structure being greater than a bottom dimension of the contact structure, and forming a capacitor structure on the contact structure, the capacitor structure electrically connected to the contact structure.

[0016] In some embodiments, the first opening is formed by removing a portion of the first dielectric layer and a portion of the active pillar, the first opening sidewall exposing a portion of the first dielectric layer, and the first opening bottom exposing a portion of the active pillar.

[0017] In some embodiments, the contact structure at least partially filling the first opening specifically comprises: forming the contact structure, the contact structure filling the first opening; and the contact structure comprising a first metal layer and a second metal layer, the first metal layer covering a bottom of the first opening; and the second metal layer filling the first opening.

[0018] In some embodiments, the first opening is formed by removing a portion of the dielectric layer and a portion of the active pillar specifically comprises: using an etching gas to form the first opening by controlling an etching angle.

[0019] In some embodiments, the first opening is formed by removing a portion of the dielectric layer and a portion of the active pillar specifically comprises: using a first etching process to remove only a portion of the active pillar, and using a second etching process to remove a portion of the active pillar and a portion of the dielectric layer to form the first opening.

[0020] In some embodiments, the removing the portion of the medium layer and the portion of the active pillar to form the first opening specifically comprises: forming a photoresist layer on the first medium layer, the photoresist layer having a third opening, the third opening having a size greater than a top size of the active pillar; etching the first medium layer with the third opening until the active pillar is exposed to form a first initial opening, continuing to etch the portion of the active pillar with the first initial opening to form a second initial opening, a projection of the second initial opening on the substrate surface being located within a projection of the first initial opening on the substrate surface, the first initial opening and the second initial opening jointly forming the first opening.

[0021] In some embodiments, the first opening has a size difference between a top size of the first opening and a bottom size of the first opening, the top size of the first opening being greater than the bottom size of the first opening, and the size difference being not less than 6 nm.

[0022] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, comprising:

[0023] a substrate, the substrate having active pillars spaced apart along a first direction and a second direction, the first direction and the second direction being parallel to a surface of the substrate, the first direction and the second direction being perpendicular, the active pillars having a first medium layer therebetween, the first medium layer being at least flush with the active pillars;

[0024] a word line structure, the word line structure surrounding the active pillars and extending along the first direction, a plurality of the word line structures being spaced apart along the second direction;

[0025] a contact structure, the contact structure being electrically connected to at least the active pillars;

[0026] a capacitor structure, the capacitor structure being electrically connected to the contact structure.

[0027] In some embodiments, the contact structure has a size difference between a top size of the contact structure and a bottom size of the contact structure, the top size of the contact structure being greater than the bottom size of the contact structure.

[0028] In some embodiments, the size difference is not less than 6 nm.

[0029] In some embodiments, the contact structure is obtained by performing a first processing process and a second processing process on the active pillar, and a side wall outer edge of the contact structure is arc-shaped.

[0030] In some embodiments, the contact structure further comprises a second medium layer between the contact structures.

[0031] In some embodiments, a side wall outer edge of the contact structure is linear, the contact structure comprises a first metal layer and a second metal layer, the first metal layer being connected to the active pillar, and the second metal layer being located on the first metal layer.

[0032] The semiconductor structure manufacturing method and the semiconductor structure provided by the embodiments of the present disclosure can form a first opening by removing at least part of the first dielectric layer, the top size of the first opening is larger than the bottom size, form a contact structure in the first opening, and electrically connect the contact structure with the capacitor structure, so that the forming process of the contact structure is simplified, the contact window is relatively large due to the relatively large contact structure, and the semiconductor yield is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are shown by way of illustration in the drawings and are not limiting of the embodiments provided herein, unless otherwise specified; the drawings comprise schematic illustrations of embodiments of the disclosure. As will be realized, the drawings are provided for not as a definition of the limits of the embodiments disclosed, for which references are to be made to the appended claims and their equivalents except where explicitly specified that a particular drawing is to be considered a part of the specification. It is noted that for clarity and ease of illustration, drawings made in accordance with well-known principles of drawing methodology can not necessarily be made to scale.

[0034] FIG. 1 schematically shows a top view of a semiconductor structure manufacturing method and a semiconductor structure substrate according to the present disclosure;

[0035] FIGS. 2A-2G are process flow diagrams of one embodiment of a semiconductor structure forming method according to the present disclosure;

[0036] FIGS. 3A-3G are process flow diagrams of another embodiment of a semiconductor structure forming method according to the present disclosure;

[0037] FIGS. 4A-4F are process flow diagrams of yet another embodiment of a semiconductor structure forming method according to the present disclosure;

[0038] FIGS. 5A-5H are process flow diagrams of still another embodiment of a semiconductor structure forming method according to the present disclosure;

[0039] FIG. 6A is an energy spectrum test diagram of an initial contact structure in one embodiment of the present disclosure.

[0040] FIG. 6B is a structural schematic diagram of one embodiment of a semiconductor structure according to the present disclosure.

[0041] FIG. 7A is a transmission electron microscope diagram of a contact structure in one embodiment of the present disclosure.

[0042] FIG. 7B is a structural schematic diagram of another embodiment of a semiconductor structure according to the present disclosure.

[0043] FIG. 8 is a structural schematic diagram of still another embodiment of a semiconductor structure according to the present disclosure. DETAILED DESCRIPTION

[0044] As can be known from the background art, in the manufacturing process of vertical channel transistors, the manufacturing process of semiconductor memory devices is still relatively complex and the yield is relatively low. How to improve the yield of semiconductor memory devices and simplify the manufacturing process of semiconductor memory devices is a technical problem to be solved at present.

[0045] The present disclosure provides a semiconductor structure preparation method and a semiconductor structure thereof. The method includes removing at least part of the first dielectric layer to form a first opening, the top size of the first opening being larger than the bottom size, and forming a contact structure in the first opening, and electrically connecting the contact structure with a capacitor structure. The formation process of the contact structure is simplified, and the capacitor contact structure is relatively large, which increases the contact window, thereby improving the semiconductor yield.

[0046] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0047] FIG. 1 schematically shows a top view of a semiconductor structure preparation method and a semiconductor structure substrate thereof according to the present disclosure.

[0048] FIGS. 2A-2G are process flow diagrams of a specific embodiment of a semiconductor structure formation method according to the present disclosure.

[0049] Referring to FIGS. 1-2A, the semiconductor structure preparation method includes providing a substrate 10 having active pillars 20 spaced apart along a first direction X and a second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 10, the first direction X and the second direction Y being perpendicular, the active pillars 20 having a first dielectric layer 301 therebetween, the first dielectric layer 301 being at least flush with the active pillars 20.

[0050] The substrate further includes forming word line structures 40 surrounding the active pillars 20 and extending along the first direction X, the plurality of word line structures 40 being spaced apart along the second direction Y; the word line structure 40 further includes a word line isolation layer 401 and a word line metal layer 402.

[0051] Then, as shown in FIG. 2B, part of the first dielectric layer 301 is removed to form a first opening 501, the method of removing the first dielectric layer 301 including dry etching; the first opening 501 sidewall exposes part of the active pillar 20, and the first opening 501 bottom exposes part of the first dielectric layer 301.

[0052] Then, as shown in FIGS. 2C-2D, a contact structure 901 is formed to at least partially fill the first opening 501; that is, the contact structure 901 does not completely fill the first opening 501, and the contact structure 901 partially occupies the space of the first opening 501. Before forming the contact structure 901, a first processing process is performed on the exposed part of the active pillar 20 on the sidewall of the first opening 501 to expand the exposed part of the active pillar 20 to form an active pillar protrusion 201. The first processing process can be an epitaxy (EPI) processing process. The active pillar 20 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), etc. The specific selection can be made as needed. When the active pillar 20 is silicon, it can be single-crystal silicon or polycrystalline silicon. The epitaxy processing process can be used to epitaxially grow the active pillar 20 exposed on the sidewall of the first opening. As shown in FIG. 2C, the size of the active pillar protrusion 201 formed after the epitaxy processing process has a trend of first increasing and then decreasing from the top to the bottom. Specifically, it can be spherical, elliptical, or spindle-shaped. FIG. 2C only takes the spherical shape as an example. Then, as shown in FIG. 2D, a second processing process is performed on the active pillar protrusion 201 to form an initial contact structure 901. The second processing process further includes first depositing cobalt, nickel, or cobalt-nickel alloy on the active pillar protrusion 201, and then performing a heat treatment to make the active pillar protrusion 201 react with the cobalt, nickel, or cobalt-nickel alloy to form the initial contact structure 901. The material of the initial contact structure 901 can be cobalt silicide, nickel silicide, or cobalt-nickel silicide. The size of the initial contact structure 901 has a trend of first increasing and then decreasing from the top to the bottom. Specifically, it can be spherical, elliptical, or spindle-shaped. FIG. 2D only takes the spherical shape as an example. The adjacent initial contact structures 901 form a second opening 502. Because the initial contact structure 901 does not completely fill the first opening 501, the initial contact structure 901 only partially occupies the space of the first opening 501. The unoccupied interval of the first opening 501 forms the second opening 502.

[0053] Then, as shown in FIG. 2E, a second dielectric layer 302 is formed to fill the second opening 502 and cover the initial contact structure 901. Then, as shown in FIG. 2F, part of the second dielectric layer 302 and part of the initial contact structure 901 are removed to expose the initial contact structure 901. Then, part of the second dielectric layer 302 and part of the initial contact structure 901 are further removed to make the remaining initial contact structure 901 form a contact structure 902. The top size of the contact structure 902 is greater than the bottom size of the contact structure 902. The greater top size of the contact structure 902 can provide a larger contact area, further improving the yield and performance of the semiconductor structure.

[0054] Then, as shown in FIG. 2G, a capacitor structure 70 is formed on the contact structure 902, and the capacitor structure 70 is electrically connected with the contact structure 902. FIG. 2G only schematically shows the capacitor structure 70. The specific capacitor structure 70 can be a double-sided capacitor or a single-sided columnar capacitor. The capacitor structure 70 can include an upper electrode, a lower electrode, and a dielectric layer. The capacitor structure 70 can further include a support structure 80, which includes a first support structure 801 and a second support structure 802.

[0055] The above method can form a vertical channel transistor (VCT), and the contact structure 901 as a capacitor contact structure provides a larger contact area, so that the yield and performance of the semiconductor structure are improved.

[0056] FIGS. 3A-3G are process flow diagrams of another specific embodiment of the semiconductor structure forming method of the present disclosure;

[0057] In the above embodiment, the active pillar protrusion is generated by epitaxy and the active pillar protrusion is subjected to a second processing process, so that the active pillar protrusion forms an initial contact structure. After further etching processing, the remaining initial contact structure serves as a contact structure. The top size of the contact structure is larger than the bottom size, so that the contact area of the contact structure is increased, and the yield and performance of the semiconductor structure are further improved. However, the epitaxial growth process is relatively slow and the process is relatively complex. In the following embodiments, a method with a simpler process and shorter process time will be specifically introduced.

[0058] In combination with FIGS. 1 and 3A, a substrate 10 is provided, which has active pillars 20 spaced apart along a first direction X and a second direction Y. The first direction X and the second direction Y are both parallel to the surface of the substrate 10, and the first direction X and the second direction Y are perpendicular to each other. The active pillars 20 have a first dielectric layer 301 therebetween, which is flush with the active pillars 20.

[0059] The substrate 10 further includes a word line structure 40 formed therein. The word line structure 40 surrounds the active pillars 20 and extends along the first direction X. The word line structure 40 is spaced apart along the second direction Y. The word line structure 40 further includes a word line isolation layer 401 and a word line metal layer 402.

[0060] Then, as shown in FIGS. 3B-3C, part of the first dielectric layer 301 and part of the active pillars 20 are removed to form a first opening 501. The first opening 501 has a sidewall that exposes part of the first dielectric layer 301, and a bottom that exposes part of the active pillars 20.

[0061] Specifically, as shown in FIG. 3B, a first etching process is used to remove part of the active pillar 20 to form a first initial opening 501', a sidewall of the first initial opening 501' exposes part of the first dielectric layer 301, and a bottom of the first initial opening 501' exposes part of the active pillar 20. The first etching process can be a dry etching process, and the etching gas can be carbon tetrafluoride (CF4).

[0062] Specifically, as shown in FIG. 3C, a second etching process is used to continue etching on the basis of the first initial opening, to remove part of the active pillar 20 at the bottom and part of the dielectric layer 301 at the sidewall, so as to form a first opening 501. The depth of the first opening 501 is greater than that of the first initial opening 501', and the top size of the first opening 501 is greater than the bottom size of the first opening 501. The second etching process can be a dry etching process, and the etching gas can be a mixture of carbon tetrafluoride (CF4) and trifluoromethane (CHF3). The second etching process not only continues to etch at the bottom of the first initial opening 501', but also expands the hole at the sidewall. In a specific embodiment, the second etching process expands the hole at the left and right sides of the first initial opening 501' by at least 3 nm, that is, the size difference between the top size of the first opening 501 and the bottom size of the first opening 501 is not less than 6 nm.

[0063] The first etching process and the second etching process make the top size of the first opening 501 larger, which facilitates the subsequent filling to form a contact structure, makes the subsequent contact structure easier to fill, and prevents the generation of bubbles in the contact structure to affect the device structure. In addition, the larger top size of the first opening 501 also makes the top size of the subsequently formed contact structure larger, so as to increase the contact area and further improve the yield and performance of the semiconductor structure.

[0064] Then, as shown in FIGS. 3D-3F, a contact structure 60 is formed to fill the first opening 501. The contact structure includes a first metal layer 601 and a second metal layer 602. The first metal layer 601 covers the bottom of the first opening 501. The second metal layer 602 fills the first opening 501. Specifically, as shown in FIG. 3D, the first metal layer 601 is first formed at the bottom of the first opening 501. The first metal layer 601 only covers the bottom of the first opening 501 and does not completely fill the first opening 501. Then, as shown in FIG. 3E, a second initial metal layer 602' is formed to fill the first opening 501 and cover the first dielectric layer 301. Then, as shown in FIG. 3F, part of the second initial metal layer 602' is removed, so that the remaining second initial metal layer 602' serves as the second metal layer 602, and the second metal layer 602 is flush with the first dielectric layer.

[0065] The first dielectric layer 301 can be silicon nitride, silicon oxynitride, silicon carbon nitride, etc. Since the first dielectric layer 301 has a certain etching selectivity with the active pillars 20, only part of the active pillars 20 is removed in the first etching process, and part of the active pillars 20 is continuously removed and part of the first dielectric layer 301 is expanded and removed to form the first opening 501 in the second etching process, and the contact structure 60 is formed in the first opening 501. Since the process of forming the first opening 501 and the process of filling the first opening 501 are relatively easy to control and the process is simple, the formation process of the entire semiconductor structure is simplified and the process time is shortened.

[0066] Then, as shown in FIG. 3G, the capacitor structure 70 is formed, and the capacitor structure 70 is electrically connected with the contact structure 60. FIG. 3G only schematically shows the capacitor structure 70. Specifically, the capacitor structure 70 can be a double-sided capacitor or a single-sided pillar-shaped capacitor. The capacitor structure 70 can include an upper electrode (not shown in the figure), a lower electrode (not shown in the figure), and a dielectric layer (not shown in the figure). The capacitor structure 70 can further include a support structure 80, which includes a first support structure 801 and a second support structure 802.

[0067] FIGS. 4A-4F are process flow diagrams of another specific embodiment of the semiconductor structure formation method of the present disclosure;

[0068] As shown in FIG. 4A, different from other embodiments, the first dielectric layer 301 also covers the active pillars 20. In combination with FIG. 1 and FIG. 4A, a substrate 10 is provided, and the substrate 10 has active pillars 20 spaced apart along a first direction X and a second direction Y. The first direction X and the second direction Y are both parallel to the surface of the substrate 10, and the first direction X and the second direction Y are perpendicular to each other. The active pillars 20 have a first dielectric layer 301 therebetween, and the first dielectric layer 301 covers the active pillars 20.

[0069] As shown in FIG. 4B, part of the first dielectric layer 301 and part of the active pillars 20 are etched to form the first opening 501. Specifically, a mixed etching gas of carbon tetrafluoride (CF4) and trifluoromethane (CHF3) can be used to form the first opening 501 by controlling the etching angle. For example, the etching angle can be formed by first vertically etching for a certain period of time and then changing the etching bias to continue etching. As shown in FIG. 4A, since the first dielectric layer 301 exists on the top of the active pillars, the depth of the first opening 501 can be deeper and the size of the top of the first opening 501 can be wider during the etching process to form the first opening 501. That is, the size of the top of the subsequently formed contact structure is also larger, so that the contact resistance is reduced and the performance of the semiconductor device is improved.

[0070] Then, as shown in FIGS. 4C-4E, a contact structure 60 is formed to fill the first opening 501; the contact structure 60 includes a first metal layer 601 and a second metal layer 602, the first metal layer 601 covers the bottom of the first opening 501; the second metal layer 602 fills the first opening 501. Specifically, as shown in FIG. 4C, the first metal layer 601 is formed on the bottom of the first opening 501, the first metal layer 601 only covers the bottom of the first opening 501 and does not completely fill the first opening 501; then, as shown in FIG. 4D, a second initial metal layer 602' is formed, the second initial metal layer 602' fills the first opening 501 and covers the first dielectric layer 301; then, as shown in FIG. 4E, part of the second initial metal layer 602' is removed, so that the remaining second initial metal layer 602' serves as the second metal layer 602, and the second metal layer 602 is flush with the first dielectric layer.

[0071] Then, as shown in FIG. 4F, a capacitor structure 70 is formed, the capacitor structure 70 is electrically connected to the contact structure 60. FIG. 4F only schematically shows the capacitor structure 70, specifically, the capacitor structure 70 can be a double-sided capacitor or a single-sided columnar capacitor, the capacitor structure 70 can include an upper electrode (not shown in the figure), a lower electrode (not shown in the figure) and a dielectric layer (not shown in the figure); between the capacitor structures 70, a support structure 80 can also be included, the support structure 80 includes a first support structure 801 and a second support structure 802.

[0072] FIGS. 5A-5H are process flow diagrams of another specific embodiment of the semiconductor structure forming method of the present disclosure;

[0073] In combination with FIG. 1 and FIG. 5A, a substrate 10 is provided, the substrate 10 has active pillars 20 spaced apart along a first direction X and a second direction Y, the first direction X and the second direction Y are both parallel to the surface of the substrate 10, the first direction X and the second direction Y are perpendicular, the active pillars 20 have a first dielectric layer 301 therebetween, the first dielectric layer 301 covers the active pillars 20. A photoresist layer 30 is formed on the active pillars 20.

[0074] Then, as shown in FIG. 5B, the photoresist layer 30 is developed to form a third opening 503, the opening size of the third opening 503 is greater than the top size of the active pillar 20.

[0075] Then as shown in FIGS. 5C-5D, the first dielectric layer 301 is etched with the third opening 503 until the active pillar 20 is exposed to form a first initial opening 5011, and the first initial opening 5011 is further etched to form a second initial opening 5012, the projection of the second initial opening 5012 on the surface of the substrate 10 is within the projection of the first initial opening 5011 on the surface of the substrate 10, and the first initial opening 5011 and the second initial opening 5012 together form the first opening 501. As shown in FIG. 5C, the size of the first initial opening 5011 is equal to the size of the top of the active pillar 20, and the size of the first initial opening 5011 is D1 and the size of the top of the active pillar 20 is D2. As shown in FIG. 5D, the first initial opening 5011 is further etched to form the second initial opening 5012, and the portion above the dashed line in FIG. 5D is the first initial opening 5011 and the portion below the dashed line is the second initial opening 5012, and the first initial opening 5011 and the second initial opening 5012 together form the first opening 501.

[0076] Then as shown in FIGS. 5E-5G, the contact structure 60 is formed to fill the first opening 501, and the contact structure 60 includes a first metal layer 601 and a second metal layer 602, the first metal layer 601 covers the bottom of the first opening 501, and the second metal layer 602 fills the first opening 501. As shown in FIG. 5E, the first metal layer 601 is first formed on the bottom of the first opening 501, and the first metal layer 601 only covers the bottom of the first opening 501 and does not completely fill the first opening 501. Then as shown in FIG. 5F, a second initial metal layer 602' is formed to fill the first opening 501 and cover the first dielectric layer 301. Then as shown in FIG. 5G, part of the second initial metal layer 602' is removed, so that the remaining second initial metal layer 602' serves as the second metal layer 602, and the second metal layer 602 is flush with the first dielectric layer. The top size of the contact structure 60 is greater than the bottom size of the contact structure 60, and the top size of the contact structure 60 is at least 6 nm greater than the bottom size of the contact structure 60. The larger top size facilitates subsequent filling of the contact structure, making it easier to fill the contact structure and preventing the formation of air bubbles in the contact structure that can affect the device structure. In addition, the larger top size of the contact structure increases the contact area, further improving the yield and performance of the semiconductor structure.

[0077] Then, as shown in FIG. 5H, a capacitor structure 70 is formed, and the capacitor structure 70 is electrically connected with the contact structure 60. FIG. 5H only schematically shows the capacitor structure 70. Specifically, the capacitor structure 70 can be a double-sided capacitor or a single-sided columnar capacitor. The capacitor structure 70 can include an upper electrode (not shown in the figure), a lower electrode (not shown in the figure), and a dielectric layer (not shown in the figure). The capacitor structure 70 can further include a support structure 80, which includes a first support structure 801 and a second support structure 802.

[0078] FIG. 6A is an energy dispersive spectrometer (EDS) of the initial contact structure in an embodiment of the present disclosure. As shown in FIG. 6A, the size of the initial contact structure 901 has a trend of first increasing and then decreasing from top to bottom. Specifically, the initial contact structure 901 can be spherical, oval, or fusiform. FIG. 6A only takes the spherical shape as an example. The second dielectric layer 302 is filled between adjacent initial contact structures 901, and covers the initial contact structure 901.

[0079] FIG. 6B is a structural schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 6B, the semiconductor structure according to an embodiment of the present disclosure includes a substrate 10 having active pillars 20 arranged at intervals along a first direction X and a second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 10, the first direction X and the second direction Y being perpendicular, and the active pillars 20 having a first dielectric layer 301 therebetween, the first dielectric layer 301 being flush with the active pillars 20; the substrate 10 further includes word line structures 40 surrounding the active pillars 20 and extending along the first direction X, the word line structures 40 being arranged at intervals along the second direction Y; the word line structures 40 further include a word line isolation layer 401 and a word line metal layer 402. The semiconductor structure further includes contact structures 902 electrically connected to the active pillars 20, and capacitor structures 70 electrically connected to the contact structures 902. The capacitor structures 70 can further include support structures 80 including a first support structure 801 and a second support structure 802. The top size of the contact structures 902 is different from the bottom size of the contact structures 902, the top size of the contact structures 902 being greater than the bottom size of the contact structures 902, and the difference between the top size and the bottom size being not less than 6 nm. The top size of the contact structures 902 is greater than the bottom size of the contact structures 902, so that the contact structures 902 can provide a larger contact area, further improving the yield and performance of the semiconductor structure. The initial contact structures 901 shown in FIG. 6A are obtained by performing a first processing process and a second processing process on the active pillars 20, and the contact structures 902 shown in FIG. 6B are obtained by removing part of the initial contact structures 901, the side wall outer edge of the contact structures 902 being arc-shaped, and the contact structures 902 being semicircular as shown in the figure, and the contact structures further including a second dielectric layer 302.

[0080] FIG. 7A is a transmission electron microscope image of a contact structure according to an embodiment of the present disclosure. As shown in FIG. 7A, the contact structures 60 are electrically connected to the active pillars 20, the top size of the contact structures 60 being greater than the bottom size of the contact structures 60, the top size of the contact structures 60 being different from the bottom size of the contact structures 60, and the difference between the top size and the bottom size being greater than 6 nm, and the contact structures 60 shown in FIG. 7A being inverted trapezoidal.

[0081] FIG. 7B is a structural schematic diagram of another embodiment of the semiconductor structure of the present disclosure. In combination with FIG. 1 and FIG. 7B, the semiconductor structure of the embodiment of the present disclosure includes a substrate 10, the substrate 10 has active pillars 20 arranged at intervals along a first direction X and a second direction Y, the first direction X and the second direction Y are both parallel to the surface of the substrate 10, the first direction X and the second direction Y are perpendicular, and the active pillars 20 have a first dielectric layer 301 therebetween, the first dielectric layer 301 is flush with the active pillars 20; the substrate 10 further includes word line structures 40, the word line structures 40 surround the active pillars 20 and extend along the first direction X, and a plurality of word line structures 40 are arranged at intervals along the second direction Y; the word line structures 40 further include a word line isolation layer 401 and a word line metal layer 402. The semiconductor structure of the present disclosure further includes a contact structure 60, the contact structure 60 is electrically connected to the active pillars 20; the contact structure 60 includes a first metal layer 601 and a second metal layer 602, the first metal layer 601 is electrically connected to the active pillars 20, and the second metal layer 602 is located on the first metal layer; and further includes a capacitor structure 70, the capacitor structure 70 is electrically connected to the contact structure 60. The support structure 80 can also be included between the capacitor structure 70, the support structure 80 includes a first support structure 801 and a second support structure 802. The top size of the contact structure 60 and the bottom size of the contact structure 60 have a size difference, the top size of the contact structure 60 is greater than the bottom size of the contact structure 60, and the size difference is not less than 6 nm. The top size of the contact structure 60 is greater than the bottom size of the contact structure 60, and the top size of the contact structure 60 is greater than the bottom size, so that the contact structure 60 can provide a larger contact area, further improving the yield and performance of the semiconductor structure. The outer edge of the sidewall of the contact structure 60 is linear, and the size of the contact structure 60 gradually decreases from top to bottom, and the contact structure 60 is an inverted trapezoid.

[0082] FIG. 8 is a structural schematic diagram of another embodiment of the semiconductor structure of the present disclosure.

[0083] FIG. 7B is a structural schematic diagram of another embodiment of the semiconductor structure of the present disclosure. In combination with FIG. 1 and FIG. 8, the semiconductor structure of the embodiment of the present disclosure includes a substrate 10, the substrate 10 has active pillars 20 arranged at intervals along a first direction X and a second direction Y, the first direction X and the second direction Y are both parallel to the surface of the substrate 10, the first direction X and the second direction Y are perpendicular, and the active pillars 20 have a first dielectric layer 301 therebetween, the first dielectric layer 301 is flush with the active pillars 20; the substrate 10 further includes word line structures 40, the word line structures 40 surround the active pillars 20 and extend along the first direction X, and a plurality of word line structures 40 are arranged at intervals along the second direction Y; the word line structure 40 further includes a word line isolation layer 401 and a word line metal layer 402. The semiconductor structure of the present disclosure further includes a contact structure 60, the contact structure 60 is electrically connected with the active pillar 20; the contact structure 60 includes a first metal layer 601 and a second metal layer 602, the first metal layer 601 is electrically connected with the active pillar 20, and the second metal layer 602 is located on the first metal layer; and further includes a capacitor structure 70, the capacitor structure 70 is electrically connected with the contact structure 60. The support structure 80 can be included between the capacitor structure 70, the support structure 80 includes a first support structure 801 and a second support structure 802. The top size of the contact structure 60 and the bottom size of the contact structure 60 have a size difference, the top size of the contact structure 60 is greater than the bottom size of the contact structure 60, and the size difference is not less than 6 nm. The top size of the contact structure 60 is greater than the bottom size of the contact structure 60, and the top size of the contact structure 60 is greater than the bottom size, so that the contact structure 60 can provide a larger contact area, further improving the yield and performance of the semiconductor structure. The outer edge of the contact structure sidewall is in a stepped shape.

[0084] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and detail without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, Comprising: providing a substrate (10) having active pillars (20) spaced apart along a first direction (X) and a second direction (Y), the first direction (X) and the second direction (Y) being parallel to a surface of the substrate (10), the first direction (X) and the second direction (Y) being perpendicular, the active pillars (20) having a first dielectric layer (301) therebetween, the first dielectric layer (301) being at least flush with the active pillars (20); forming word line structures (40) surrounding the active pillars (20) and extending along the first direction (X), a plurality of the word line structures (40) being spaced apart along the second direction (Y); removing at least part of the first dielectric layer (301) to form first openings (501); forming contact structures (60) at least partially filling the first openings (501); forming capacitor structures (70) electrically connected with the contact structures (60).

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first openings (501) have sidewalls exposing part of the active pillars (20) and bottoms exposing part of the first dielectric layer (301).

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: Further comprising: performing a first processing on the part of the active pillars (20) exposed by the sidewalls of the first openings (501) to swell the exposed part of the active pillars (20) to form active pillar protrusions (201), and performing a second processing on the active pillar protrusions (201) to form initial contact structures (901) partially filling the first openings (501) and having second openings (502) between adjacent ones of the initial contact structures (901).

4. The method of producing a semiconductor structure according to claim 3, wherein Further comprising: forming a second dielectric layer (302) filling the second openings (502) and covering the initial contact structures (901), removing part of the second dielectric layer (302) and part of the initial contact structures (901), the remaining initial contact structures (901) serving as the contact structures (60), the contact structures (60) having a top dimension greater than a bottom dimension, and forming the capacitor structures (70) on the contact structures (60) and electrically connected with the contact structures (60).

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Removing part of the first dielectric layer (301) and part of the active pillars (20) to form first openings (501) having sidewalls exposing part of the first dielectric layer (301) and bottoms exposing part of the active pillars (20).

6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: Forming the contact structure (60) which at least partially fills the first opening (501), specifically comprising: forming the contact structure (60) which fills the first opening (501); the contact structure (60) comprises a first metal layer (601) and a second metal layer (602), the first metal layer (601) covers the bottom of the first opening (501); the second metal layer (602) fills the first opening (501).

7. The method of claim 5, wherein the step of forming the semiconductor structure is performed by a method comprising: Part of the first dielectric layer (301) and part of the active pillar (20) are removed to form a first opening (501), specifically comprising: using etching gas to form the first opening (501) by controlling the etching angle.

8. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The part of the first dielectric layer (301) and part of the active pillar (20) are removed to form a first opening (501), specifically comprising: using a first etching process to remove only part of the active pillar (20), using a second etching process to remove part of the active pillar (20) and part of the first dielectric layer (301) to form the first opening (501).

9. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The part of the first dielectric layer (301) and part of the active pillar (20) are removed to form a first opening (501), specifically comprising: forming a photoresist layer (30) on the first dielectric layer (301), the photoresist layer (30) has a third opening (503), the size of the third opening (503) is greater than the top size of the active pillar (20); etching the first dielectric layer (301) with the third opening (503) until the active pillar (20) is exposed to form a first initial opening (5011), continuing to etch part of the active pillar (20) with the first initial opening (5011) to form a second initial opening (5012), the projection of the second initial opening (5012) on the surface of the substrate (10) is located within the projection of the first initial opening (5011) on the surface of the substrate (10), the first initial opening (5011) and the second initial opening (5012) together constitute the first opening (501).

10. The method of fabricating a semiconductor structure according to any one of claims 5-9, wherein, The top size of the first opening (501) and the bottom size of the first opening (501) have a size difference, the top size of the first opening (501) is greater than the bottom size of the first opening (501), and the size difference is not less than 6nm.

11. A semiconductor structure, characterized by Comprise: A substrate (10) having active pillars (20) spaced apart along a first direction (X) and a second direction (Y), the first direction (X) and the second direction (Y) are parallel to the surface of the substrate (10), the first direction (X) and the second direction (Y) are perpendicular, the first dielectric layer (301) between the active pillars (20), the first dielectric layer (301) is at least flush with the active pillars (20); Word line structures (40) surrounding the active pillars (20) and extending along the first direction (X), a plurality of the word line structures (40) being spaced apart along a second direction (Y); Contact structures (60) electrically connected to at least the active pillars (20); Capacitor structures (70) electrically connected to the contact structures (60). A top dimension of the contact structures (60) is different from a bottom dimension of the contact structures (60), the top dimension being larger than the bottom dimension.

12. The semiconductor structure of claim 11, wherein, The difference is not less than 6 nm.

13. The semiconductor structure of claim 11, wherein, The contact structures (60) are obtained by a first processing and a second processing of the active pillars (20), the contact structures (60) having an arc-shaped outer edge of a sidewall.

14. The semiconductor structure of claim 13, wherein, The contact structures (60) further comprise a second dielectric layer (302) therebetween.

15. The semiconductor structure of claim 11, wherein, The contact structures (60) have a linear outer edge of a sidewall, the contact structures (60) comprising a first metal layer (601) and a second metal layer (602), the first metal layer (601) being connected to the active pillars (20), the second metal layer (602) being on the first metal layer (601).

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