Data computation verification apparatus and data computation verification method for chip, and chip

Abstract

A data computation verification apparatus and data computation verification method for a chip, and a chip. The data computation verification apparatus for a chip comprises: a buffer, configured for caching a computation task and setting an index identifier for the computation task; a computation core, configured for performing the computation task and correspondingly acquiring a computation result, the computation result being bound to the index identifier corresponding to the computation task; and a verification module, configured for correspondingly determining a target task from among the computation tasks according to the index identifier, and verifying the computation result on the basis of the target task. The technical solution of the embodiments of the present application can prevent false determinations resulting from an incorrect correspondence between a computation task and a computation result during a computation task update phase, thereby avoiding loss of computational power and improving verification accuracy while ensuring that a computation core can sustain continuous computation.

Description

Data computation verification device, data computation verification method and chip

[0001] The present application claims priority from the Chinese patent application No. 2024107217126 entitled "Data computation verification device, data computation verification method and chip of chip" filed on June 4, 2024 with the China Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of chips, in particular to a data computation verification device, a data computation verification method and a chip of chip. BACKGROUND

[0003] In the related art, after the computing core of the chip completes the computation of the task and outputs the computation result, the verification module verifies the computation result with the task to ensure the validity of the computation result. However, there is a delay in the data path of the task issued to each computing core. When the chip issues a new task, if the computing core is outputting the computation result of the previous task, it will be judged that the computation result does not match the current new task. At this time, the valid computation result may be misjudged as an error, resulting in a loss of computing power. SUMMARY

[0004] The present application provides a data computation verification device, a data computation verification method and a chip of chip to solve the problems in the related art. The technical solutions are as follows:

[0005] As an aspect of the present application, the present application provides a data computation verification device of chip, comprising: a buffer area for caching a computation task and setting an index identifier for the computation task; a computing core for computing the computation task and correspondingly obtaining a computation result, the computation result being bound to the index identifier corresponding to the computation task; and a verification module for correspondingly determining a target task from the computation task according to the index identifier, and verifying the computation result based on the target task.

[0006] In one embodiment, the data computation verification device further comprises: a first multiplexer comprising at least one first input end, a first output end and a first control end, the first input end being configured to input the computation task in the buffer area, the first output end being configured to output the target task, and the first control end being configured to input the index identifier corresponding to the computation result.

[0007] In one embodiment, the data computation verification device further comprises: a second multiplexer comprising at least one second input end, a second output end and a second control end, the second input end being configured to input the computation task in the buffer area, the second output end being connected to the computing core, and the second control end being configured to input the index identifier corresponding to the computation task.

[0008] In an embodiment, the data computing and verifying apparatus further comprises a pre-computing module configured to pre-compute the computing task and obtain a pre-computed result corresponding to the computing task, the pre-computed result being bound to the index identifier corresponding to the computing task, and the pre-computed result being configured to be sent to the computing core.

[0009] In an embodiment, the computing task comprises a first task and a second task, the index identifiers of the first task and the second task corresponding to a first index and a second index respectively, the first task being a latest computing task of the computing core, and the second task being a previous computing task of the first task.

[0010] In an embodiment, the computing task further comprises a third task, the index identifier of the third task being a third index, and the third task being a previous computing task of the second task.

[0011] In an embodiment, the data computing and verifying apparatus further comprises a packaging module configured to package the computing result and the target task if the computing result is determined to be valid.

[0012] As another aspect of the embodiments of the present application, the embodiments of the present application provide a chip data computing and verifying method, comprising: buffering a computing task, setting an index identifier for the computing task; computing the computing task and obtaining a computing result corresponding to the computing task, the computing result being bound to the index identifier corresponding to the computing task; determining a target task from the computing task according to the index identifier; and verifying the computing result based on the target task.

[0013] In an embodiment, the chip data computing and verifying method further comprises: pre-computing the computing task and obtaining a pre-computed result corresponding to the computing task, the pre-computed result being bound to the index identifier corresponding to the computing task; and computing the pre-computed result and obtaining the computing result corresponding to the computing task, the computing result being bound to the index identifier corresponding to the computing task.

[0014] In an embodiment, the computing task comprises a first task and a second task, the index identifiers of the first task and the second task corresponding to a first index and a second index respectively, the first task being a latest computing task of the computing core, and the second task being a previous computing task of the first task; and the chip data computing and verifying method comprises: computing the first task and the second task, obtaining a first computing result with the first index and a second computing result with the second index; determining a target task from the first task and the second task according to the first index or the second index; and verifying the first computing result or the second computing result based on the target task.

[0015] In an embodiment, the computing task further includes a third task, an index of the third task is a third index, and the third task is a previous computing task of the second task; the data computing verification method of the chip includes: computing the third task to obtain a third computing result with the third index; determining a target task from the first task, the second task and the third task according to the first index or the second index or the third index; and verifying the first computing result or the second computing result or the third computing result based on the target task.

[0016] In an embodiment, the data computing verification method of the chip further includes: after the second computing result with the second index is completely verified, the second task is cleared.

[0017] In an embodiment, after receiving a new round of latest computing task, the new round of latest computing task is updated as the first task, and the first task of the previous round is updated as the second task.

[0018] In an embodiment, in a case where the target task matches the computing result, it is determined that the computing result is valid.

[0019] In an embodiment, in a case where it is determined that the computing result is valid, the computing result and the target task are packaged and submitted.

[0020] As another aspect of the embodiments of the present application, the embodiments of the present application provide a chip including the data computing verification device of the chip according to any one of the above embodiments.

[0021] The technical solutions of the embodiments of the present application can effectively avoid misjudgment caused by the error of the correspondence between the computing task and the computing result in the computing task updating stage, so that the computing core can continue to compute, the loss of computing power can be avoided, and the accuracy of verification is improved.

[0022] The above summary is merely intended to illustrate the present application and is not intended to limit in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be apparent from the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0023] In the drawings, like numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, the emphasis instead being placed on the relations between various parts and on the principles of the application. It should be understood that these drawings are only intended to depict some embodiments of the application and should not be considered to limit the scope of the application in any way.

[0024] FIG. 1 shows a data computing verification schematic diagram of a chip according to an embodiment of the related art.

[0025] Figure 2 shows a data calculation verification schematic diagram of a chip according to another embodiment of the related art.

[0026] Figure 3 shows a flowchart of a data calculation verification method of a chip according to an embodiment of the present application.

[0027] Figure 4 shows an architecture schematic diagram of a data calculation verification device of a chip according to an embodiment of the present application.

[0028] Figure 5 shows a data calculation verification schematic diagram of a data calculation verification device of a chip according to an embodiment of the present application.

[0029] Figure 6 shows a data calculation verification schematic diagram of a data calculation verification device of a chip according to another embodiment of the present application.

[0030] Reference signs: 400: data calculation verification device of a chip; 410: verification module; 420: buffer area; 430: first multiplexer; 440: second multiplexer; 450: pre-calculation module; 460: packing module; 470: calculation core. DETAILED DESCRIPTION

[0031] In the following, only certain exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0032] The following terms are used herein

[0033] Computing power: refers to the computing ability of a high-performance computing chip to achieve target result output by processing information data (i.e. tasks).

[0034] Calculation core: refers to a basic calculation unit within a high-performance computing chip to complete a certain specific calculation.

[0035] Verification module: an internal module of a high-performance computing chip to complete verification with an initial task before target result output.

[0036] Verification error rate: the calculation error rate of a calculation core detected by a verification module, i.e. the ratio of error calculation output number in a period to all calculation output number in the period.

[0037] In the related art, computing power and accuracy are important indicators for measuring the performance of high-performance computing chips. In order to improve computing power, the multi-core computing array in the chip usually transmits and processes the same set of tasks in the form of multicast or broadcast. After the computing core completes the calculation of the task and outputs the calculation result, the verification module verifies the calculation result with the task. The verification can be that the verification module recalculates the task to output the verification result, and compares whether the verification result and the calculation result are consistent, so as to ensure the validity of the calculation result. In the chip with multiple computing cores, in order to improve the computing power, the update of the task is non-handshake and non-back pressure, that is, the update of the task does not need to wait for the response of the computing core. Due to the delay of the task on the data path of each computing core, when the chip receives a new task, if the computing core is outputting the calculation result of the previous task, it will be judged that the calculation result does not match the current new task.

[0038] FIG. 1 shows a data calculation verification schematic diagram of a chip in an embodiment of the related art. As shown in FIG. 1, the chip uses a single verification module. After the computing core completes the calculation of task 1 and outputs the calculation result of task 1, the verification module is used to verify the current task and the calculation result of task 1. In the case that the chip does not receive a new task, the current task is task 1, and the correspondence between the current task and the calculation result is correct. The verification module can recalculate task 1 or perform other verification calculation on task 1 to obtain a verification result. In the case that the verification result of task 1 matches the calculation result of task 1, the verification passes.

[0039] FIG. 2 shows a data calculation verification schematic diagram of a chip in another embodiment of the related art. As shown in FIG. 2, in the case that the chip receives a new task, the current task is updated to task 2, and at this time the correspondence between the current task and the calculation result is incorrect. Because task 2 is different from task 1, the calculation result of task 2 does not match the calculation result of task 1, so the verification will most likely fail. However, the calculation result corresponding to task 1 is most likely correct in the calculation verification, so the verification can pass at this time. If the calculation result of task 1 is determined to be invalid according to task 2 at this time, it will cause a loss of computing power.

[0040] In view of the above problems, the following two solutions are usually used:

[0041] The first kind is to ignore the detection error result. Since the time interval of task update accounts for a small proportion in the total working time of the computing core, the probability of the computing core outputting the calculation result of the previous task in the task update interval is relatively small. This scheme does not consider the impact of misjudgment and directly discards all detection error results. However, in the case of discarding the effective calculation result as an error, it will cause direct computing power loss. Moreover, the increase of the error rate will also affect the subsequent work configuration, such as adjusting the voltage or working frequency of the computing core, but at this time the actual error rate of the computing core may be within the normal range and there is no need to adjust the working configuration. The wrong working configuration may thus cause indirect computing power loss.

[0042] The second kind is to suspend the calculation of the computing core in the new task update stage. This scheme can ensure that the computing core will not continue to calculate the previous task and will not output the calculation result of the previous task within the time interval from when the chip receives the new task to when the new task is loaded into the computing core. Although this scheme reduces the error rate, suspending the computing core will cause waste of calculation time, and the computing power of the computing core is zero during the suspension period.

[0043] The above task can be a neural network calculation task, a hash function calculation task, or a large model data calculation task. Those skilled in the art can select any information data requiring calculation and verification in the prior art and apply it to the technical scheme of the present application.

[0044] FIG. 3 shows a flowchart of a data calculation and verification method of a chip according to an embodiment of the present application. As shown in FIG. 3, the data calculation and verification method of the chip includes:

[0045] Step S301: cache the calculation task and set an index identifier for the calculation task;

[0046] Step S302: calculate the calculation task and correspondingly obtain the calculation result, the calculation result being bound to the index identifier corresponding to the calculation task;

[0047] Step S303: determine the target task from the calculation task according to the index identifier;

[0048] Step S304: verify the calculation result based on the target task.

[0049] Exemplarily, when the chip receives a computing task, the computing task can be cached to the buffer. For example, the buffer can have a plurality of data slots, each data slot has a fixed index identifier, and the index identifiers of the plurality of data slots are all different. After the computing task is sent to the chip, it is directly stored in one of the data slots of the buffer, and the index identifier corresponding to the data slot is used. Among them, the number of computing tasks is less than or equal to the number of data slots. For example, the computing task in the buffer can be one, at this time one of the plurality of data slots is occupied, and the remaining data slots are not occupied. Alternatively, the computing task in the buffer can be multiple, and the multiple computing tasks are cached to different data slots, and the index identifiers corresponding to any two computing tasks are different.

[0050] Optionally, in the case that the target task matches the computing result, it is determined that the computing result is valid.

[0051] Exemplarily, the computing core is used to calculate the computing task and correspondingly obtain the computing result. The computing result is bound to the index identifier corresponding to the computing task. After the computing core completes the calculation of the computing task, the computing result and the index identifier corresponding to the computing task are sent to the verification module. The verification module determines the target task from the computing task according to the index identifier, and then verifies the computing result based on the target task. Since the computing result is the result of the target task, the correspondence between the computing result and the target task is correct, and an effective data calculation verification result can be obtained. In the case that the data calculation verification result is that the target task matches the computing result, it is determined that the computing result is valid. In the case that the data calculation verification result is that the target task does not match the computing result, it is determined that the computing result is invalid.

[0052] According to the data calculation verification method of the chip, the target task is correspondingly determined from the computing task through the index identifier, and the computing result is verified based on the target task, which can ensure that the correspondence between the target task and the computing result is correct, effectively avoid misjudgment due to the incorrect correspondence between the computing task and the computing result in the computing task updating stage, thereby avoiding the loss of computing power and improving the accuracy of verification while ensuring that the computing core can continue to calculate.

[0053] Optionally, the data calculation verification method of the chip can further include: pre-computing a computing task and correspondingly obtaining a pre-computing result, the pre-computing result being bound to an index identifier corresponding to the computing task; and calculating the pre-computing result and correspondingly obtaining a computing result, the computing result being bound to the index identifier corresponding to the computing task.

[0054] Exemplarily, the computing task is sent to the chip and directly stored in one of the data slots of the buffer, and the index corresponding to the data slot is set. The pre-computation module obtains the computing task from the buffer according to the index and pre-computes the computing task, and obtains the pre-computation result. The pre-computation result is bound to the index corresponding to the computing task. The pre-computation module can send the pre-computation result and the index to the computing core. In the case that the pre-computation result and the index are sent to the computing core, the computing core computes the pre-computation result and obtains the computing result. The computing result is bound to the index corresponding to the computing task. The verification module determines the target task from the computing task according to the index, and then verifies the computing result based on the target task. Since the computing result is the result of the target task, the corresponding relationship between the computing result and the target task is correct, and an effective data computation verification result can be obtained.

[0055] When computing neural network computing tasks, hash function computing tasks, large model data computing tasks and other information data, it may be necessary to uniformly pre-compute the initial task, and then synchronously send the pre-computation result to multiple computing cores for parallel computation. The pre-computation module plays a role in pre-computing and pre-processing data.

[0056] In this embodiment, compared with the related art, the pre-computation module and the buffer, the computing core, and the verification module and the computing core, the buffer pass the index. In the case of obtaining the target task, the target task is obtained from the computing task in the buffer through the index, rather than directly passing the computing task between modules. In addition to effectively avoiding the loss of computing power and the increase of verification error rate in the computing task update stage, the data transmission between modules in the chip is optimized and simplified, the storage of the computing task is avoided, the data consistency of each module is ensured, and the reliability of the chip is improved.

[0057] Optionally, the computing task includes a first task and a second task, and the index of the first task and the second task corresponds to a first index and a second index, respectively. The first task is the latest computing task of the computing core, and the second task is the previous computing task of the first task. The data computation verification method of the chip includes: computing the first task and the second task, obtaining the first computing result with the first index and the second computing result with the second index; determining the target task from the first task and the second task according to the first index or the second index; verifying the first computing result or the second computing result based on the target task.

[0058] In one example, the first task is sent to the chip and buffered in one of the data slots of the buffer, and the first index corresponding to the data slot is used. After the core completes the calculation of the first task, the first calculation result and the first index are sent to the verification module. In the case where the chip does not receive a new task, i.e., the latest calculation task is not updated, only one set of tasks (i.e., the first task) in the chip is processed, and the index identification transmitted to the core and the index identification output by the core are both the first index. The verification module obtains the first task from the calculation tasks in the buffer according to the first index, and then verifies the first calculation result based on the first task. In the case where the first task matches the first calculation result, it is determined that the first calculation result is valid. In the case where the first task does not match the first calculation result, it is determined that the first calculation result is invalid.

[0059] In another example, in the case where the chip receives a new task, i.e., the latest calculation task is updated, the updated latest calculation task is recorded as the first task, and the previous calculation task of the latest calculation task is recorded as the second task. At this time, at least two sets of calculation tasks (i.e., the first task and the second task) in the chip are processed. The calculation result output by the core is the second calculation result, and the index identification output by the core is the second index. The pre-calculation module pre-calculates the first task and correspondingly obtains the first pre-calculation result, which is bound to the first index. The index identification transmitted by the pre-calculation module to the core is the first index. Since the index identification output by the core is the second index, the verification module can determine the second task as the target task from the first task and the second task according to the second index, and verify the second calculation result based on the target task, so that the calculation task verified with the second calculation result is the second task, and the correspondence between the calculation task and the calculation result is correct. In the case where the second task matches the second calculation result, it is determined that the second calculation result is valid; in the case where the second task does not match the second calculation result, it is determined that the second calculation result is invalid.

[0060] After the pre-calculation module completely sends the first pre-calculation result and the first index to the core, the core can calculate the first pre-calculation result and correspondingly obtain the first calculation result, and transmit the first calculation result and the first index to the verification module. The verification module can determine the first task as the target task according to the first index, and verify the first calculation result based on the target task, so that the calculation task verified with the first calculation result is the first task, and the correspondence between the calculation task and the calculation result is also correct. In the case where the first task matches the first calculation result, it is determined that the first calculation result is valid; in the case where the first task does not match the first calculation result, it is determined that the first calculation result is invalid.

[0061] In the embodiments of the application, it can be ensured that the second calculation result can be checked with the second task in the calculation task updating stage, and the first calculation result can be checked with the first task, so as to ensure the correct correspondence between the calculation result and the calculation task, avoid misjudgment, and further avoid the loss of computing power, and improve the overall computing capability and fault tolerance of the chip.

[0062] Optionally, the calculation task can further include a third task, and the index of the third task is a third index, and the third task is a previous calculation task of the second task. The data calculation checking method of the chip can further include: determining a target task from the first task, the second task and the third task according to the first index or the second index or the third index; and checking the first calculation result or the second calculation result or the third calculation result based on the target task.

[0063] For example, when the first task, the second task and the third task are cached in the buffer, the calculation core first outputs the third calculation result, and the index output by the calculation core is the third index. The pre-calculation module pre-calculates the second task and correspondingly obtains the second pre-calculation result, and the second pre-calculation result is bound to the second index, so the index transmitted by the pre-calculation module to the calculation core is the second index. The buffer sends the latest calculation task, i.e. the first task, and the first index to the pre-calculation module. Since the index output by the calculation core is the third index, the checking module can determine the third task as the target task from the first task, the second task and the third task according to the third index, and check the third calculation result based on the third task, so that the correspondence between the calculation task and the calculation result is correct. In the case where the third task matches the third calculation result, it is determined that the third calculation result is valid; in the case where the third task does not match the third calculation result, it is determined that the third calculation result is invalid.

[0064] After the pre-calculation module completely sends the second pre-calculation result and the second index to the calculation core, the calculation core calculates the second pre-calculation result and correspondingly obtains the second calculation result, and transmits the second calculation result and the second index to the checking module. The checking module can determine the second task as the target task according to the second index, and check the second calculation result based on the target task. In the case where the second task matches the second calculation result, it is determined that the second calculation result is valid; in the case where the second task does not match the second calculation result, it is determined that the second calculation result is invalid.

[0065] After the first task and the first index are completely sent to the pre-computation module in the buffer, the pre-computation module pre-computes the first task and correspondingly obtains a first pre-computation result. The first pre-computation result is bound to the first index, so the pre-computation module can deliver the first pre-computation result and the first index to the computing core. After the pre-computation module completely sends the first pre-computation result and the first index to the computing core, the computing core can compute the first pre-computation result and correspondingly obtain a first computation result. The first computation result and the first index are delivered to the verification module. The verification module can determine that the first task is a target task according to the first index, and verify the first computation result based on the target task, so that the computing task for verifying the first computation result is the first task, and the correspondence between the computing task and the computation result is correct. In the case that the first task matches the first computation result, it is determined that the first computation result is valid; in the case that the first task does not match the first computation result, it is determined that the first computation result is invalid.

[0066] The embodiments of the present application take three computing tasks, i.e., the first task, the second task and the third task, as an example for illustration. It is obvious for those skilled in the art to understand that the scheme can be applied to technical solutions of other numbers of computing tasks, for example, the fourth task, the fifth task, the sixth task, etc., which also falls within the protection scope of the present application.

[0067] In the embodiment, by verifying the first computation result or the second computation result or the third computation result based on the target task, it can further avoid misjudgment due to the incorrect correspondence between the computing task and the computation result in the computing task updating stage, so as to avoid the loss of computing power and further improve the accuracy of verification in the case that the computing core can continue to compute.

[0068] Optionally, the data computation verification method of the chip can further include: after the second computation result with the second index is completely verified, the second task is cleared. In this way, the verified computing task can be cleared in time, so as to reduce the memory occupation and release the memory space.

[0069] Exemplarily, in a case where the first task, the second task and the third task are buffered in the buffer, the calculation core first outputs a calculation result as the third calculation result, and an index output by the calculation core is the third index. The checking module can determine the third task as the target task from the first task, the second task and the third task according to the third index, and check the third calculation result based on the third task. After the checking, the third task can be cleared. After the pre-calculation module completely sends the second pre-calculation result and the second index to the calculation core, the calculation core calculates the second pre-calculation result and correspondingly obtains the second calculation result, and the second calculation result and the second index are transmitted to the checking module. The checking module can determine the second task as the target task according to the second index, and check the second calculation result based on the target task. After the checking, the second task can be cleared.

[0070] Optionally, after receiving the new round of latest calculation task, the new round of latest calculation task is updated as the first task, and the first task of the previous round is updated as the second task. In this way, it can be ensured that in the case of processing multiple calculation tasks, it will not fall into a chaotic state, and the calculation and checking can be performed according to a clear order and priority, improving the data processing efficiency, avoiding waste of resources and redundant operations. Moreover, continuous management and updating of the calculation task can be realized, ensuring the smooth progress of the calculation and checking process, thereby improving the stability and reliability of data calculation and checking.

[0071] Optionally, the data calculation and checking method of the chip can further include: in a case where the calculation result is determined to be valid, the calculation result and the target task are packaged and submitted.

[0072] Exemplarily, the packaged calculation result and target task can be submitted to other modules to realize corresponding functions. For example, in a case where the chip is an artificial intelligence (AI) chip, the packaged calculation result and target task can be submitted to a central processing unit (CPU) to perform next step calculation and the like; in a case where the chip is a computing power chip, the packaged calculation result and target task can be submitted to a host.

[0073] The data calculation and checking device 400 of the chip according to the second aspect of the present application is described below in combination with FIG. 4-FIG. 6.

[0074] FIG. 4 shows a schematic diagram of an architecture of a data computing and checking apparatus 400 of a chip according to an embodiment of the present application. As shown in FIG. 4, the data computing and checking apparatus 400 of the chip includes a checking module 410, a buffer 420, and a computing core 470. The buffer 420 is configured to buffer a computing task and set an index identifier for the computing task. The computing core 470 is configured to compute the computing task and obtain a computing result corresponding to the computing task, the computing result being bound to the index identifier of the computing task. The checking module 410 is configured to determine a target task from the computing task according to the index identifier, and check the computing result based on the target task.

[0075] For example, when the chip receives a computing task, such as a first task, the first task can be written into the buffer 420, and the first task can be temporarily stored in the buffer 420. The buffer 420 can set an index identifier for the first task as a first index. The first index is transmitted between the buffer 420 and the pre-computing module, between the pre-computing module and the computing core 470, between the computing core 470 and the checking module 410, and between the checking module 410 and the buffer 420. When the first task is needed, the first task can be obtained from the buffer 420 by using the first index.

[0076] For example, the number of computing tasks in the buffer 420 can be greater than or equal to 2. The computing tasks can be stored in data slots of the buffer 420. For example, the number of data slots can be 2-4 (including the end values). When the data slots are full of computing tasks, the data content in the data slots can be overwritten. For example, when the number of computing tasks is two, the two computing tasks are different, such as a first task and a second task. The pre-computing module can pre-compute the first task, the computing core 470 can compute the second task and output a second computing result, and the checking module 410 can check the second task and the second computing result. When the number of computing tasks is three, the computing task pre-computed by the pre-computing module, the computing task computed by the computing core, and the computing task checked by the checking module 410 can all be different, which satisfies various use scenarios of different computing tasks in the chip. Of course, in another case, at the same time, the pre-computing module can pre-compute one or more computing tasks, the computing core can compute one or more computing tasks, and the checking module can check one or more computing tasks, and all the computing tasks correspond to different index identifiers.

[0077] According to the data calculation verification device 400 of the chip, on one hand, the corresponding relationship between the target task and the calculation result can be ensured to be correct, and misjudgment caused by incorrect corresponding relationship between the calculation task and the calculation result in the calculation task updating stage can be effectively avoided, so that the computing power loss can be avoided and the accuracy of verification can be improved in the case that the calculation core can continue to calculate. On the other hand, the calculation task only needs to be stored in the buffer 420, so that multiple storage of the calculation task is avoided, and in the case that the calculation task is large-bit-width data, the data consistency of the calculation task at each module can be ensured, and the reliability of the chip is further improved.

[0078] FIG. 5 shows a data calculation verification schematic diagram of a data calculation verification device of a chip according to an embodiment of the present application, and FIG. 6 shows a data calculation verification schematic diagram of a data calculation verification device of a chip according to another embodiment of the present application. Optionally, referring to FIGS. 5 and 6, the data calculation verification device 400 can further include a pre-calculation module 450, the pre-calculation module 450 pre-calculates the calculation task and correspondingly obtains a pre-calculation result, the pre-calculation result is bound with the index identifier corresponding to the calculation task, and the pre-calculation result is used to be sent to the calculation core 470.

[0079] Therefore, the pre-calculation module 450 can pre-calculate the calculation task, so as to output the pre-calculation result to the calculation core 470, so that the calculation core 470 can calculate the pre-calculation result and then output the calculation result of the calculation task. Moreover, the index identifier is transmitted between the pre-calculation module 450 and the buffer 420 and the calculation core 470, and between the verification module 410 and the calculation core 470 and the buffer 420, the calculation task is obtained from the buffer 420 by using the index identifier in the case that the calculation task is needed, instead of directly transmitting the calculation task between the modules, so that the data transmission between the modules in the chip is optimized and simplified, multiple storage of the calculation task is avoided, the data consistency of each module is ensured, and the reliability of the chip is improved.

[0080] Optionally, referring to FIGS. 5 and 6, the data calculation verification device 400 can further include a first multiplexer 430, the first multiplexer 430 includes at least one first input end, a first output end and a first control end, the first input end is used to input the calculation task in the buffer 420, the first output end is used to output the target task, and the first control end is used to input the index identifier corresponding to the calculation result.

[0081] Thus, by setting the first multiplexer 430, the index identifier output by the verification module 410 can be input into the first multiplexer 430 through the first control end, and the first multiplexer 430 can select a target task corresponding to the index identifier from at least one computing task according to the index identifier and output from the first output end to the verification module 410, so that the verification module 410 can verify the computing result based on the target task, thereby avoiding misjudgment due to the incorrect correspondence between the computing task and the computing result in the computing task updating stage, and improving the verification accuracy.

[0082] Optionally, as shown in FIGS. 5 and 6, the data computing verification apparatus 400 further includes a second multiplexer 440, the second multiplexer 440 includes at least one second input end, a second output end and a second control end, the second input end is used to input the computing task in the buffer 420, the second output end is connected with the computing core 470, and the second control end is used to input the index identifier corresponding to the computing task.

[0083] In this embodiment, by setting the second multiplexer 440, the latest computing task is cached to the buffer 420 and is correspondingly set with an index identifier, and the pre-computing module 450 also receives the index identifier, the index identifier output by the pre-computing module 450 can be input into the second multiplexer 440 through the second control end, the second multiplexer 440 can select a computing task corresponding to the index identifier from at least one computing task according to the index identifier and output from the second output end to the pre-computing module 450, so that the pre-computing module 450 can pre-compute the computing task and output the pre-computed result to the computing core 470, and the computing task can not need to be stored in the pre-computing module 450, thereby further ensuring the data consistency of each module.

[0084] Optionally, the computing task includes a first task and a second task, and the index identifiers of the first task and the second task are a first index and a second index respectively; the first task is the latest computing task of the computing core, and the second task is a previous computing task of the first task.

[0085] In one example, the first task is sent to the chip and buffered in one of the data slots of the buffer, and the first index corresponding to the data slot is used. After the core completes the calculation of the first task, the first calculation result and the first index are sent to the verification module. In the case where the chip does not receive a new task, i.e., the latest calculation task is not updated, only one set of tasks (i.e., the first task) in the chip is processed, and the index identifier transmitted to the core and the index identifier output by the core are both the first index. The verification module obtains the first task from the calculation tasks in the buffer according to the first index, and then verifies the first calculation result based on the first task. In the case where the first task matches the first calculation result, it is determined that the first calculation result is valid. In the case where the first task does not match the first calculation result, it is determined that the first calculation result is invalid.

[0086] In another example, in combination with FIG. 6, in the case where the chip receives a new task, i.e., the latest calculation task is updated, the updated latest calculation task is denoted as the first task, and the previous calculation task of the latest calculation task is denoted as the second task. At this time, at least two sets of calculation tasks (i.e., the first task and the second task) in the chip are processed. The calculation result output by the core 470 is the second calculation result, and the index identifier output by the core 470 is the second index. The pre-calculation module 450 pre-calculates the first task and correspondingly obtains the first pre-calculation result, which is bound to the first index. The index identifier transmitted by the pre-calculation module 450 to the core 470 is the first index. Since the index identifier output by the core 470 is the second index, the verification module 410 can determine the second task as the target task from the first task and the second task according to the second index, and verify the second calculation result based on the target task, so that the calculation task verified with the second calculation result is the second task, ensuring the correct correspondence between the calculation task and the calculation result. In the case where the second task matches the second calculation result, it is determined that the second calculation result is valid; in the case where the second task does not match the second calculation result, it is determined that the second calculation result is invalid.

[0087] After the pre-calculation module 450 completely sends the first pre-calculation result and the first index to the core 470, the core 470 can calculate the first pre-calculation result and correspondingly obtain the first calculation result, and transmit the first calculation result and the first index to the verification module 410. The verification module 410 can determine the first task as the target task according to the first index, and verify the first calculation result based on the target task, so that the calculation task verified with the first calculation result is the first task, and the correct correspondence between the calculation task and the calculation result can also be ensured. In the case where the first task matches the first calculation result, it is determined that the first calculation result is valid; in the case where the first task does not match the first calculation result, it is determined that the first calculation result is invalid.

[0088] In the embodiments of the application, it can be ensured that the second calculation result can be checked with the second task in the calculation task updating stage, and the first calculation result can be checked with the first task, so as to ensure the correct correspondence between the calculation result and the calculation task, avoid misjudgment, and further avoid the loss of computing power, and improve the overall computing capability and fault tolerance of the chip.

[0089] Optionally, the calculation task can further include a third task, and the index of the third task is a third index, and the third task is a previous calculation task of the second task.

[0090] For example, when the first task, the second task and the third task are cached in the buffer, the calculation result output by the calculation core 470 is the third calculation result, and the index output by the calculation core 470 is the third index. The pre-calculation module 450 pre-calculates the second task and correspondingly obtains the second pre-calculation result, and the second pre-calculation result is bound with the second index, so the index transmitted by the pre-calculation module 450 to the calculation core 470 is the second index. The buffer 420 sends the latest calculation task, i.e., the first task, and the first index to the pre-calculation module 450. Since the index output by the calculation core 470 is the third index, the checking module 410 can determine the third task as the target task from the first task, the second task and the third task according to the third index, and check the third calculation result based on the third task, so that the correspondence between the calculation task and the calculation result is correct. In the case that the third task matches the third calculation result, it is determined that the third calculation result is valid; in the case that the third task does not match the third calculation result, it is determined that the third calculation result is invalid.

[0091] After the pre-calculation module 450 completely sends the second pre-calculation result and the second index to the calculation core 470, the calculation core 470 calculates the second pre-calculation result and correspondingly obtains the second calculation result, and transmits the second calculation result and the second index to the checking module 410. The checking module 410 can determine the second task as the target task according to the second index, and check the second calculation result based on the target task. In the case that the second task matches the second calculation result, it is determined that the second calculation result is valid; in the case that the second task does not match the second calculation result, it is determined that the second calculation result is invalid.

[0092] After the first task and the first index are completely sent to the pre-computation module 450 in the buffer 420, the pre-computation module 450 pre-computes the first task and correspondingly obtains a first pre-computation result. The first pre-computation result is bound to the first index, so the pre-computation module 450 can deliver the first pre-computation result and the first index to the computing core 470. After the pre-computation module 450 completely sends the first pre-computation result and the first index to the computing core 470, the computing core 470 can compute the first pre-computation result and correspondingly obtain a first computation result. The first computation result and the first index are delivered to the verification module 410. The verification module 410 can determine the first task as a target task according to the first index, and verify the first computation result based on the target task, so that the computing task for verifying the first computation result is the first task, and the correspondence between the computing task and the computation result is correct. In the case that the first task matches the first computation result, it is determined that the first computation result is valid; in the case that the first task does not match the first computation result, it is determined that the first computation result is invalid.

[0093] The embodiments of the present application take three computing tasks, i.e., the first task, the second task and the third task, as an example for illustration. It is obvious for those skilled in the art to understand that the scheme can be applied to technical solutions of other numbers of computing tasks, for example, the fourth task, the fifth task, the sixth task, etc., which also falls within the protection scope of the present application.

[0094] Optionally, as shown in FIG. 5 and FIG. 6, the chip data computation verification apparatus 400 further includes a packaging module 460. The packaging module 460 is configured to package the computation result and the target task in the case that the computation result is determined to be valid. The packaged computation result and target task can be submitted to subsequent modules to realize corresponding functions. For example, in the case that the chip is an artificial intelligence chip, the packaged computation result and target task can be submitted to a central processing unit, so as to perform next step computation and the like. In the case that the chip is a computing power chip, the packaged computation result and target task can be submitted to a host.

[0095] According to the third aspect of the embodiments of the present application, the chip includes the apparatus 400 according to any of the above-mentioned second aspect embodiments.

[0096] According to the chip of the embodiments of the present application, the misjudgment caused by the incorrect correspondence between the computing task and the computation result in the case that the computing task is updated can be effectively avoided, so as to improve the overall computing power and fault tolerance of the chip while ensuring that the computing core can continuously compute.

[0097] In the above-described embodiments, all or part can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, all or part generates the processes or functions according to the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium.

[0098] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0099] In addition, the terms "first", "second", etc. are used only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0100] Any process or method descriptions or descriptions in flow charts or otherwise described herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for implementing specific logic functions or steps in the process. And the scope of the preferred embodiments of the present application includes additional implementation in which the functions can be performed in different order, including substantially concurrently or in reverse order, according to the functions involved, as will be understood by those skilled in the art.

[0101] The logic and / or steps represented in the flow chart or otherwise described herein, for example, can be considered as a list of executable instructions for implementing the logic function, which can be specifically embodied in any computer-readable medium for use by an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor, or other system that can take instructions from an instruction execution system, apparatus or device, or in conjunction with these instructions execution system, apparatus or device.

[0102] It should be understood that each part of the present application can be realized by hardware, software, firmware or a combination thereof. In the above embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above-mentioned embodiment methods can be completed by a program instructing the relevant hardware, which can be stored in a computer readable storage medium and includes one or a combination of the steps of the embodiment methods when executed.

[0103] In addition, each functional unit in each embodiment of the present application can be integrated in one processing module, or each unit can be physically present separately, or two or more units can be integrated in one module. The above-mentioned integrated module can be realized in the form of hardware or in the form of a software functional module. The above-mentioned integrated module, if realized in the form of a software functional module and sold or used as an independent product, can also be stored in a computer readable storage medium. The storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0104] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data computation check device for a chip, characterized by comprising: The device comprises: a buffer for buffering a computing task and setting an index identifier for the computing task; a computing core for computing the computing task and correspondingly obtaining a computing result, the computing result being bound to the index identifier corresponding to the computing task; a checking module for correspondingly determining a target task from the computing task according to the index identifier, and checking the computing result based on the target task. Further comprising:

2. The apparatus of claim 1, wherein, a first multiplexer comprising at least one first input end, a first output end and a first control end, the first input end being used for inputting the computing task in the buffer, the first output end being used for outputting the target task, and the first control end being used for inputting the index identifier corresponding to the computing result. Further comprising:

3. The apparatus of claim 1, wherein, a second multiplexer comprising at least one second input end, a second output end and a second control end, the second input end being used for inputting the computing task in the buffer, the second output end being connected to the computing core, and the second control end being used for inputting the index identifier corresponding to the computing task. Further comprising:

4. The apparatus of claim 1, wherein, a pre-computing module for pre-computing the computing task and correspondingly obtaining a pre-computing result, the pre-computing result being bound to the index identifier corresponding to the computing task, and the pre-computing result being used for sending to the computing core.

5. The device according to claim 1, wherein: the computing task comprises a first task and a second task, the index identifiers of the first task and the second task correspond to a first index and a second index respectively, the first task is a latest computing task of the computing core, and the second task is a previous computing task of the first task.

6. The device according to claim 5, wherein: the computing task further comprises a third task, the index identifier of the third task is a third index, and the third task is a previous computing task of the second task. Further comprising:

7. The apparatus of claim 1, wherein, a packing module for packing the computing result and the target task in a case where the computing result is determined to be valid.

8. A data computing and checking method of a chip, comprising: buffering a computing task and setting an index identifier for the computing task; computing the computing task and correspondingly obtaining a computing result, the computing result being bound to the index identifier corresponding to the computing task; correspondingly determining a target task from the computing task according to the index identifier; checking the computing result based on the target task. Further comprising:

9. The method of claim 8, wherein, pre-computing the computing task and correspondingly obtaining a pre-computing result, the pre-computing result being bound to the index identifier corresponding to the computing task; computing the pre-computing result and correspondingly obtaining the computing result, the computing result being bound to the index identifier corresponding to the computing task.

10. The method according to claim 8, wherein: the computing task comprises a first task and a second task, the index identifiers of the first task and the second task correspond to a first index and a second index respectively, the first task is a latest computing task of the computing core, and the second task is a previous computing task of the first task. ​ calculating the first task and the second task to obtain a first calculation result with the first index and a second calculation result with the second index; determining the target task from the first task and the second task according to the first index or the second index; verifying the first calculation result or the second calculation result based on the target task.

11. The method of claim 10, wherein, the calculation task further comprises a third task, the third task having an index identified as a third index, the third task being a previous calculation task of the second task; calculating the third task to obtain a third calculation result with the third index; determining the target task from the first task, the second task and the third task according to the first index, the second index or the third index; verifying the first calculation result, the second calculation result or the third calculation result based on the target task.

12. The method of claim 10, wherein, further comprising: after verifying the second calculation result with the second index completely, clearing the second task.

13. The method of claim 10, wherein, after receiving a new round of latest calculation task, updating the new round of latest calculation task as the first task and updating the first task of the previous round as the second task.

14. The method of claim 8, wherein, in a case where the target task matches the calculation result, determining that the calculation result is valid.

15. The method of claim 14, wherein, further comprising: in a case where it is determined that the calculation result is valid, packaging and submitting the calculation result and the target task.

16. A chip, characterized by an apparatus according to any one of claims 1-7.

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