Memory swapping method, storage medium, and electronic device

Abstract

Disclosed in the present application are a memory swapping method, a storage medium, and an electronic device. The method comprises: acquiring labeled data corresponding to a target process, wherein the labeled data is obtained by means of the target process performing memory category labeling on a plurality of memory blocks in a virtual architecture; on the basis of the labeled data, determining memory mark information corresponding to the virtual architecture, wherein the memory mark information is used for representing memory swapping priorities corresponding to the plurality of memory blocks; and using the memory mark information to select, from among the plurality of memory blocks, a memory block to be swapped for memory swapping. The present application solves the technical problems in the related art of low memory swapping flexibility, a high data transmission risk and poor system resource utilization caused by difficulty in determining memory space that does not support swapping.

Description

[0001] The application relates to the technical field of computers, in particular to a memory exchange method, a storage medium and an electronic device. Background technology In an operating system, the memory used by a process can support a direct memory access (DMA) operation without the intervention of a central processing unit (CPU), and on this basis, in order to ensure data consistency, the virtual memory used by the process needs to be read into physical memory before the DMA operation is performed. In an application scenario, the memory address corresponding to the virtual memory used by the process is dynamically changed, and in order to achieve the reading of the virtual memory used by the process into the physical memory before the DMA operation is performed, in a traditional operating system, the virtual memory used by the kernel space is usually set to be unable to be swapped, and the small page memory used by the user state process is limited to be swapped out by using a lock mark (such as a VM LOCK). The swap function in some current operating systems is also limited to swapping the small page memory. However, the above-mentioned memory swapping limiting scheme cannot accurately distinguish which memory does not support space swapping, which leads to a high risk of system data transmission errors, poor data access efficiency and safety. In addition, the above-mentioned memory space swapping limiting scheme has poor flexibility, thereby leading to poor resource utilization of the whole system. In view of the above problems, no effective solution has been proposed. The application embodiment provides a memory exchange method, a storage medium and an electronic device, which at least solve the technical problems of low memory exchange flexibility, high data transmission risk and poor system resource utilization caused by the fact that the related art cannot determine the memory space that does not support swapping. According to one aspect of the application embodiment, a memory exchange method is provided, which comprises: obtaining tag data corresponding to a target process, wherein the tag data is obtained by performing memory classification tagging on a plurality of memory blocks in a virtual architecture by the target process; determining memory mark information corresponding to the virtual architecture based on the tag data, wherein the memory mark information is used to represent the memory exchange priority level of the plurality of memory blocks; and selecting a to-be-swapped memory block from the plurality of memory blocks for memory exchange by using the memory mark information.According to another aspect of the embodiments of the present application, a memory exchange method is provided, comprising: obtaining a memory exchange request through a first application programming interface, wherein the request data carried in the memory exchange request comprises: tag data corresponding to a target process, wherein the tag data is obtained by performing memory category tagging on a plurality of memory blocks in a virtual architecture by the target process; and returning a memory exchange response through a second application programming interface, wherein the response data carried in the memory exchange response comprises: a memory exchange processing result, wherein the memory exchange processing result is obtained by performing memory exchange processing on a memory block to be exchanged in the plurality of memory blocks by using memory marking information, and the memory marking information is determined based on the tag data, and the memory marking information is used to represent a memory exchange priority level corresponding to the plurality of memory blocks. According to another aspect of the embodiments of the present application, a computer readable storage medium is provided, comprising a stored program, wherein the computer readable storage medium controls a device where the computer readable storage medium is located to perform any one of the memory exchange methods described above when the program runs. According to another aspect of the embodiments of the present application, an electronic device is provided, comprising: a memory, storing an executable program; and a processor, configured to run the program, wherein the program performs any one of the memory exchange methods described above when the program runs. According to another aspect of the embodiments of the present application, a computer program product is provided, comprising a computer program, wherein the computer program implements any one of the memory exchange methods described above when executed by a processor. In the embodiments of the present application, the tag data corresponding to the target process is obtained, wherein the tag data is obtained by performing memory category tagging on the plurality of memory blocks in the virtual architecture by the target process; further, the memory marking information corresponding to the virtual architecture is determined based on the tag data, wherein the memory marking information is used to represent the memory exchange priority level corresponding to the plurality of memory blocks; and the memory block to be exchanged is selected from the plurality of memory blocks by using the memory marking information to perform memory exchange. Therefore, the embodiments of the present application achieve the purpose of performing memory exchange priority tagging on the plurality of memory blocks in the virtual architecture and further implementing memory exchange, thereby achieving the technical effects of improving memory exchange flexibility, improving system data security and resource utilization, and further solving the technical problems of low memory exchange flexibility, high data transmission risk and poor system resource utilization caused by the fact that the related art cannot determine the memory space that does not support exchange. It is easy to note that the general description above and the detailed description below are only for illustrating and explaining the embodiments of the present application, and do not constitute limitations on the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS The drawings described herein are used to provide further understanding of the embodiments of the present application, constitute a part of the embodiments of the present application, and the illustrative embodiments of the present application and the description thereof are used to explain the embodiments of the present application, and do not constitute undue limitations on the embodiments of the present application.In the drawings: Fig. 1 shows a hardware structure diagram of a computer terminal (or mobile device) configured to implement a memory exchange method; Fig. 2 shows a schematic diagram of an embodiment of a computer terminal (or mobile device) as a sending terminal or a receiving terminal; Fig. 3 is a flow chart of a memory exchange method according to Embodiment 1 of the present application; Fig. 4 is a flow chart of a memory exchange method according to Embodiment 2 of the present application; Fig. 5 is a structural schematic diagram of a memory exchange device according to Embodiment 3 of the present application; Fig. 6 is a structural schematic diagram of another memory exchange device according to Embodiment 3 of the present application; Fig. 7 is a structural block diagram of an electronic device according to Embodiment 4 of the present application. DETAILED DESCRIPTION In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the scope of protection of the present application. It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product, or device. First, some nouns or terms appearing in the description of the embodiments of the present application are subject to the following interpretation: Direct Memory Access (DMA) is a data transmission method in a computer system, which allows external devices (such as network adapters, hard disk controllers, graphics cards, etc.) to directly access data in the system memory without passing through the Central Processing Unit (CPU) byte by byte. In a virtual architecture, DMA operation generally refers to DMA operation in a virtualized computing environment, which can improve data transmission efficiency and system performance, and reduce CPU load.In a virtual architecture, there is a virtualization layer between a virtual machine (VM) and physical hardware, which is usually managed by a virtual machine monitor (VMM). When an application or an operating system on the virtual machine needs to perform a DMA operation, actual DMA transmission can involve coordination and conversion between the virtualization layer and the underlying physical hardware. Memory swapping is an operating system memory management technique used to move infrequently used memory pages to a swap space on a disk when system memory is insufficient, to release physical memory for use by other programs. Memory swapping can provide an extended memory mechanism when system memory is insufficient, to avoid performance degradation or crashes. However, due to the slow speed of disk access, memory swapping can also cause system performance degradation, so the memory pages used for memory swapping should be carefully selected, and memory swapping should only be performed when necessary. Kernel mode and user mode in an operating system refer to two different permission levels when a CPU executes instructions. In kernel mode, the CPU can execute all instructions of the operating system kernel, and can directly access all hardware resources and memory of the system. Kernel mode has higher permissions and can execute privileged instructions, such as modifying global memory mapping, controlling interrupt processing, and the like. In user mode, the CPU can only execute a restricted instruction set and cannot directly access hardware resources and memory of the system, and must access through interfaces provided by the operating system. Applications or user processes running in user mode are strictly limited and cannot directly operate hardware or access critical resources of the system. The operating system protects and manages system resources by switching between kernel mode and user mode. When an application needs to perform a system call or access a restricted resource, the CPU switches from user mode to kernel mode, allowing the operating system kernel to complete the corresponding operation; and when the operating system completes, the CPU returns from kernel mode to user mode to continue executing the code of the application. This switching is implemented by special instructions of the CPU and hardware support. Embodiment 1 According to the embodiments of the present application, a memory swapping method embodiment is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown. The method embodiment provided by the embodiment of the present application can be executed in a mobile terminal, a computer terminal, or a similar computing device.Fig. 1 shows a hardware structure diagram of a computer terminal (or mobile device) configured to implement the memory swapping method. As shown in Fig. 1, the computer terminal 10 (or mobile device 10) can include one or more processors 102 (the processor 102 can include, but is not limited to, a microcontroller unit (MCU) or a field programmable gate array (FPGA) and the like processing device), a memory 104 configured to store data, and a transmission device 106 configured to have a communication function. In addition, the computer terminal 10 can also include a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which can be included as one of the ports of the computer bus), a network interface, a cursor control device (such as a mouse, a touchpad, etc.), a keyboard, a power supply and / or a camera. Those skilled in the art can understand that the structure shown in Fig. 1 is only schematic, which does not limit the structure of the above-mentioned electronic device. For example, the computer terminal 10 can include more or fewer components than those shown in Fig. 1, or have a different configuration from that shown in Fig. 1. It should be noted that the one or more processors 102 and / or other data processing circuits can be referred to as "data processing circuits" herein. The data processing circuit can be embodied in whole or in part as software, hardware, firmware or any combination thereof. In addition, the data processing circuit can be a single independent processing module, or any one of the other elements combined into the computer terminal 10 (or mobile device) in whole or in part. As referred to in the embodiments of the present application, the data processing circuit serves as a processor control (for example, selection of a variable resistance terminal path connected to an interface). The memory 104 can be configured to store software programs and modules of application software, such as program instructions / data storage devices corresponding to the memory swapping method in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the above-mentioned memory swapping method. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, a flash memory, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the computer terminal 10 through a network.Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is configured to connect to the network via a network interface to receive or send data. The network can include a wired and / or wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network interface controller (NIC) that can connect to other network devices through a base station to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module configured to communicate with the Internet wirelessly. The display shown in FIG. 1 can be a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 (or mobile device). The hardware structure diagram shown in FIG. 1 can be used as an exemplary diagram of the computer terminal 10 (or mobile device) and as an exemplary diagram of the server. In one example, FIG. 2 shows a schematic diagram of an embodiment in which the computer terminal (or mobile device) shown in FIG. 1 is used as a sending terminal or a receiving terminal. As shown in FIG. 2, the computer terminal 10 (or mobile device) can be connected to one or more servers (e.g., a security server, a resource server, a game server, etc.) via a data network connection or an electronic connection. In one example, the computer terminal 10 (or mobile device) can be any mobile computing device. The data network connection can be a local area network connection, a wide area network connection, an Internet connection, or other types of data network connections. The computer terminal 10 (or mobile device) can be configured to connect to a network service executed by a server (e.g., a security server) or a group of servers 20. The network service is a network-based user service, such as a social network, a cloud resource, an email, an online payment, or other online applications. In the above-described operating environment, the memory exchange method shown in FIG. 3 is provided.Figure 3 is a flow chart of a memory swapping method according to Embodiment 1 of the present application. As shown in Figure 3, the memory swapping method comprises: step S31, obtaining marking data corresponding to a target process, wherein the marking data is obtained by marking a plurality of memory blocks in a virtual architecture by the target process according to memory categories; step S32, determining memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent memory swapping priority levels of the plurality of memory blocks; and step S33, selecting a memory block to be swapped from the plurality of memory blocks for memory swapping by using the memory marking information. The target process is a user process in a computer system, and the target process can be one or more. The plurality of target processes can include user state processes and / or kernel state processes. The virtual architecture refers to a virtualized computing environment created on physical computing resources by using virtualization technology, and the physical computing resources at least include physical memory. The plurality of memory blocks can be virtual memory blocks divided from a memory space of the virtual architecture, and each virtual memory block can include one or more memory pages. The virtualized computing environment can run different operating systems and application programs. The virtualized computing environment can improve the utilization, flexibility and reliability of computing resources in the system, and at the same time, reduce hardware cost and management cost. The virtualization technology includes virtual machine technology and containerization technology. During system operation, each target process can mark virtual memory blocks in the virtual architecture according to memory categories to obtain marking data. According to the marking data, memory category marks marked on the memory blocks by the target process can be determined, and the memory category marks are used to determine memory swapping priority levels of the memory blocks. It should be noted that the marking data can include data of marking at least one memory block in the plurality of memory blocks by the plurality of target processes. Usually, one target process can mark a plurality of memory blocks, and different target processes can also mark the same memory block. Based on the marking data, memory marking information is determined, and then memory swapping priority levels of each memory block in the virtual architecture are determined. The memory swapping priority levels can represent strictness of participation of the memory blocks in memory swapping. For example, a memory swapping priority level of a memory block locked in the memory and prohibited from being swapped out is lower than a memory swapping priority level of a memory block that can be swapped out only when a condition is met, and the memory swapping priority level of the memory block that can be swapped out only when the condition is met is lower than a memory swapping priority level of a memory block that can be swapped out.Further, after determining the memory mark information corresponding to the virtual architecture, the system responds to the memory swap request, selects a memory block to be swapped from the plurality of memory blocks according to the memory swap priority, and uses the memory block to be swapped for memory swap operation. In this way, the memory block with a higher memory swap priority can be used for memory swap first, and the memory block to be swapped out will not be used for memory swap, thereby enhancing the flexibility of system memory swap, reducing the risk of data transmission, and improving the utilization rate of system memory resources. In the embodiments of the present application, the target process corresponding marking data is obtained, wherein the marking data is obtained by marking the memory category of the plurality of memory blocks in the virtual architecture by the target process; further based on the marking data, the memory mark information corresponding to the virtual architecture is determined, wherein the memory mark information is used to represent the memory swap priority of the plurality of memory blocks; and the memory mark information is used to select a memory block to be swapped from the plurality of memory blocks for memory swap. In this way, the present application achieves the purpose of marking the memory swap priority of the plurality of memory blocks in the virtual architecture and further implementing memory swap, thereby achieving the technical effects of improving memory swap flexibility, improving system data security and resource utilization, and further solving the technical problems of low memory swap flexibility, high data transmission risk and poor system resource utilization caused by the difficulty of related technologies to determine the memory space that does not support swap. Taking the Linux system as an example, the memory swap (swap) mechanism in the Linux system is a mechanism for expanding memory using free hard disk space. When the physical memory page in the main memory (such as Random Access Memory, RAM) is insufficient, the swap mechanism can move the memory page that is not frequently used by the user process to the hard disk to free up space for other pages, and this process is called page swap out (swap out). When the user process uses this part of the memory page again, the page swap in (swap in) of these memory pages will be triggered. In the Linux system, not all memory pages can be used for memory swap, and usually only the first part of the memory page of the user space can be used for memory swap, and the second part of the memory page does not support being used for memory swap. For example, the first part of the memory page includes: the memory page allocated to the user process (such as the memory page in the heap, stack and data segment that is not locked, etc.). The second part of the memory page includes: the memory page currently used by the process in the kernel space (such as kernel code page, key kernel data structure, etc.), input / output device mapping memory region, current use region of special hardware (such as graphics card, network card, etc.), and memory page for DMA operation.Therefore, in the system operation, the second part of memory pages which do not support memory exchange need to be locked in the memory to avoid these memory pages being swapped out.

[0002] DMA operation involves hardware devices directly reading and writing data from physical memory (without the need for CPU processing), so when hardware devices transmit data through DMA operation, they usually operate in the buffer area allocated for DMA operation, which is usually required to be "locked" in memory, not supported to be swapped to the disk, that is, this part of the buffer area is used to be able to be tracked by the kernel Fixed physical address, so that the hardware device can directly transmit data. Because the hardware device needs to directly access the physical address of the memory page when performing DMA operation, if the memory page is swapped to the disk, the hardware device will not be able to directly access, thereby causing data transmission failure. Further, after the DMA operation performed by the hardware device is completed, the buffer area allocated for the DMA will be released (i.e., unlocked) from memory, thereby allowing the operating system to page swap the part of memory as needed. Based on this, in order to improve the efficiency of DMA operation in the operating system, a special memory allocation technique (for example, the preset allocator in the Linux system) is used to obtain a memory page suitable for DMA transmission, and these memory pages will be specially managed to ensure the efficiency and safety of DMA operation. According to the above technical solution of the embodiment of the present application, in the virtual architecture, a virtualization layer is inserted between the operating system and the physical device, which is used to identify which memory in the virtual architecture can be used for device DMA operation. In addition, because the memory page in the virtual architecture supports being swapped (such as swap out, swap in, etc.) for the virtualization layer, in order to avoid the part of memory used for device DMA operation being swapped out, the above technical solution of the embodiment of the present application can also mark the memory category of a plurality of memory blocks in the virtual architecture, so that the virtualization layer can realize real-time perception of device memory information, reduce the risk of memory swapping error, and guarantee the data consistency of the system. The following further introduces other optional schemes of the above method steps provided by the embodiment of the present application. In the embodiment of the present application, a plurality of memory marking types corresponding to a plurality of memory types in the virtual architecture are defined. For example, the plurality of memory types include: a first type, reserved memory (Reserved, abbreviated as RSVD memory); a second type, DMA memory; a third type, DEV device usage but not DMA memory; a fourth type, hot (HOT) memory; and a fifth type, normal random access memory (Normal Random Access Memory, abbreviated as NRAM memory).The memory exchange strictness of the above plurality of memory types is different, for example, the first type of memory (RSVD memory) and the second type of memory (DMA memory) strictly do not support memory exchange, the fifth type of memory (NRAM memory) supports memory exchange, and the third type and the fourth type of memory can support memory exchange under certain conditions. Based on this, among the above plurality of memory types, the memory tag value corresponding to the first type is the largest, and the memory tag value corresponding to the fifth type is the smallest, that is, the memory tag value corresponding to the first type to the fifth type gradually decreases. Embodiments of the present application perform memory type tagging on the memory blocks in the virtual architecture based on the plurality of memory tag types corresponding to the plurality of memory types, and determine the memory exchange priority of the memory blocks according to the tagging result (for example, the smaller the memory tag value of a certain memory block, the higher the priority of determining the memory block as a memory block to be exchanged in memory exchange). In an optional embodiment, the memory exchange method further includes the following method steps: dividing the memory space of the virtual architecture based on a first granularity to obtain a plurality of first memory pages corresponding to the first granularity; dividing the memory space of the virtual architecture based on a second granularity to obtain a plurality of second memory pages corresponding to the second granularity, wherein the first granularity is smaller than the second granularity; based on a third granularity, aggregating the plurality of first memory pages and segmenting the plurality of second memory pages to obtain a plurality of memory blocks, wherein the third granularity is greater than the first granularity and smaller than the second granularity. In the above optional embodiment, the first granularity, the second granularity and the third granularity represent a plurality of division scales when dividing the memory space. For example, the first granularity can be set to 4kB, the second granularity can be set to 2MB, and the third granularity can be set to 128kB. oIn an application scenario, the target number of first memory pages can be aggregated according to the scene requirements, and the third granularity is determined according to the target number and the first granularity. For example, 32 4kB memory pages are aggregated, and the third granularity is set to 128kB. As an exemplary embodiment, hybrid granularity is used in memory swapping in a lightweight virtual architecture, that is, 4kB and 2MB memory pages are considered. In order to consider the above two granularities in the memory swapping process while maintaining a small metadata overhead, 32 4kB memory pages are aggregated to obtain a 128kB memory block. In an application scenario, a 2MB memory page can be divided into 128kB memory blocks, and the system performs memory tagging on these 128kB memory blocks, that is, 128kB is used as the memory tagging granularity, and in addition, 128kB can be used as the memory basic unit for memory swapping (that is, 32 4kB memory blocks aggregated in a 128kB memory block are simultaneously swapped in or out as a whole), or a 2MB memory page can be directly used as the memory basic unit for memory swapping. That is, according to the embodiments of the present application, memory swapping with a hybrid of the second granularity and the third granularity can be achieved. In an optional embodiment, the memory marking information includes a first array; based on the tagging data, the memory marking information corresponding to the virtual architecture is determined, including the following method steps: constructing the first array, wherein the array elements of the first array include a plurality of first structure bodies corresponding to a plurality of memory blocks; using the tagging data to determine a target memory address and a memory category identifier, wherein the target memory address is used to determine a target memory block in the plurality of memory blocks, and the memory category identifier is used to represent the tagged memory category of the target memory block; and updating the first structure body corresponding to the target memory block in the first array according to the target memory address and the memory category identifier. Further, in order to perform memory category tagging on the memory blocks of the third granularity, an item structure body (that is, the first structure body) is defined for each memory block of the third granularity, and each item structure body is used to record the default mark (denoted as def), the current mark (denoted as cur), and the tagging number of the memory block. Based on the memory marking value of the current mark recorded in the item structure body corresponding to each memory block of the third granularity, the memory swapping priority of the plurality of memory blocks can be determined. Through the first array corresponding to the plurality of memory blocks in the memory marking information, the memory marking information of each memory block in the plurality of memory blocks can be determined conveniently and quickly, and in an application scenario, the memory swapping priority of a certain memory block can be determined by querying the array elements of the first array in real time.In an alternative embodiment, the memory tag information further comprises a second array; and the memory swapping method further comprises the following method steps: creating the second array, wherein the array elements of the second array comprise a plurality of second structures corresponding to a plurality of second memory pages, and the second structure corresponding to a target second memory page in the plurality of second memory pages comprises a second tag value and the first structures corresponding to the partial memory blocks contained in the target second memory page; updating the first structures in the second array using the updated first array; and for the second structure corresponding to the target second memory page, determining the maximum value in the first tag values corresponding to the partial memory blocks as the second tag value corresponding to the second structure. In addition, a node structure (i.e., the second structure) is defined for each of the above-mentioned second memory pages, and each node structure contains a plurality of item structures, for example, a 2MB memory block can contain 16 128kB memory blocks, and the node structure corresponding to each 2MB memory block contains the corresponding 16 item structures. In addition, the node structure (i.e., the second structure) corresponding to each 2MB memory block can also record the memory tag type with the maximum memory tag value recorded in the item structures corresponding to the 16 128kB memory blocks contained in the 2MB memory block. Further, after the target process performs memory tagging on the virtual architecture through the tagging interface and updates the first array corresponding to the target process, the virtualization layer of the virtual architecture can be transferred through a virtual machine call instruction (VM call) based on the tagging information in the first array to update the second array. Specifically, the node structure corresponding to the target memory block in the second array is updated according to the item structure corresponding to the target memory block in the first array. Further, after the second array is updated, a memory swapping decision is made for each memory block according to the first tag value (i.e., the historical maximum tag value) recorded in the second array corresponding to each memory block to determine whether each memory block supports being swapped out (swap out). According to the above method steps of the embodiments of the present application, based on the node structure corresponding to the above-mentioned second memory page and the item structure corresponding to the third granularity memory block, the management of most large memory pages (such as 2MB memory pages) in the application scenario can be adapted, and the management of small memory pages (such as 4kB) can also be considered.In an optional embodiment, the first structure corresponding to the target memory block in the first array is updated according to the target memory address and the memory category identifier, including the following method steps: determining the target memory block from the plurality of memory blocks according to the target memory address; determining the target marker value corresponding to the memory category identifier according to the memory exchange priority rule, wherein the memory exchange priority rule is used to determine the association between the memory exchange priority level corresponding to the memory category identifier and the target marker value; and updating the first structure corresponding to the target memory block by using the target marker value. In the above optional embodiment, the memory exchange priority rule can be preset according to the application scenario requirement. For example, the memory exchange priority rule can be: the larger the memory marker value, the lower the memory exchange priority. As an exemplary embodiment, in a virtual architecture, the memory blocks are marked from the process dimension, that is, the memory type marking is performed by taking the guest physical address as the key. In the embodiment of the present application, the process marks the memory blocks of the third granularity. For each process, a first array is established, and the marking data in the first array includes the structure (denoted as cfg) for recording the memory marker corresponding to all virtual address spaces (i.e., gfn space, which is a memory block in this example) of the virtual architecture. The structure cfg corresponding to a memory block in the first array of each process is used to record the marking type and the marking times of the process on the memory block. It should be noted that when the above memory block is a memory block of the second granularity (i.e., a 2MB memory block), the structure cfg corresponding to the memory block in the above first array can be a node structure; when the above memory block is a memory block of the third granularity, the structure cfg corresponding to the first array can be an item structure. It should be noted that in the process of marking the memory blocks of the virtual architecture, in order to save storage space, the size of the structure cfg in the first array corresponding to each process can be optimized and adjusted, for example, the structure cfg is limited to 8 bytes. In addition, for each process, the first array is created when the memory blocks of the virtual architecture are marked for the first time, and the first array corresponding to the process is destroyed when the process exits. Further, in an application scenario, multiple processes can mark the same memory block, and the marking values can be different, therefore, a second array is established for the plurality of memory blocks of the virtual architecture. The second array includes the marking data corresponding to a plurality of second memory pages. The second array will record the marking type and the marking times of the plurality of processes in the guest on the plurality of memory blocks (here, the memory blocks are of the third granularity).For example, multiple processes mark the same memory block, and finally the item structure corresponding to the memory block records the marking times of the multiple processes, and records the memory marking type with the maximum marking value (denoted as cur attr) in the current marking of the item structure among the multiple marking of the same memory block by the multiple processes. The array elements of the second array include node structures corresponding to multiple second memory pages, and each node structure also records the memory marking type with the maximum marking value (denoted as max attr) in the current marking (cur) of the multiple item structures contained therein. It can be easily understood that the first array is used to record the marking information of multiple memory blocks marked by a single process, and the second data is used to record the marking information of multiple memory blocks marked by multiple processes. The array elements of the first array include item structures corresponding to multiple memory blocks, and the array elements of the second data include node structures corresponding to multiple memory blocks. Based on the array elements in the first array, memory marking of the virtual architecture can be implemented at the first granularity or the second granularity. Based on the array elements in the second array, memory marking of the virtual architecture can be implemented at the first granularity, the second granularity or the third granularity. In an optional embodiment, the first structure includes a first marking value and a marking time; the first structure corresponding to the target memory block is updated by using a target marking value, including the following method steps: in response to a first condition being met, updating the marking time and updating the first marking value to the target marking value, wherein the first condition includes: the marking time is greater than or equal to zero, the marking time is less than a first threshold, and the target marking value is greater than the first marking value; in response to a second condition being met, updating the marking time, wherein the second condition includes: the marking time is less than the first threshold, and the target marking value is less than or equal to the first marking value. In the above optional embodiment, the target process can be a user process. In an application scenario, in order to facilitate the memory type marking of the user process, an input / output control (input / output control, abbreviated as ioctl) interface for user marking is provided. The user process can select a marking operation (also referred to as a pin operation) or an unmarking operation (also referred to as an unpin operation) through the ioctl interface. That is, the user process calls the above ioctl interface to pass "a certain virtual address space (that is, a memory block) needs to be marked with a certain memory type" to the virtualization layer of the virtual architecture. In an exemplary application scenario, the user process may frequently call the ioctl interface for marking, which increases the system overhead. Based on this, a filtering link is included in the provided ioctl interface.Since the same memory block can also be tagged by the same process or different processes, frequent tagging of the same memory block with the same memory type also increases system overhead. In the above filtering link, the tagging data of multiple processes on the same memory block is counted, and at each tagging, it is determined whether the memory tag value corresponding to the current tagging is greater than the historical maximum tag value of the memory block recorded in the first data and / or the second data. If yes, the historical maximum tag value of the current record is updated to the memory tag value of the current tagging. If no, the tagging operation of the current tagging is ignored. In an optional embodiment, the first structure further includes a tagging operation flag bit. The target memory block corresponding to the first structure is updated using the target tag value, including the following method steps: in response to one of the first condition, the second condition and the third condition being met, the tagging operation flag bit is determined as a first value, wherein the first value is used to determine that the tagging operation is performed on the target memory block according to the first tag value, and the third condition includes: the tagging number is equal to the first threshold value, and the target tag value is greater than the first tag value; in response to the fourth condition being met, the tagging operation flag bit is determined as a second value, wherein the second value is used to determine that the tagging operation on the target memory block is skipped, and the fourth condition includes: the tagging number is equal to the first threshold value, and the target tag value is less than or equal to the first tag value. As an exemplary embodiment, the above tagging operation flag bit is used to determine whether to perform the tagging operation. The tagging operation flag bit is the first value (for example, the value is 1), which indicates that the tagging operation is performed; the tagging operation flag bit is the second value (for example, the value is 0), which indicates that the tagging operation is performed. Specifically, if the current operation of the user process on the target memory block is the tagging binding operation, the data in the structure corresponding to the target memory block (such as the item structure and / or the node structure) is judged and processed as follows:

[0003] (1) If the tagging number corresponding to the target memory block is zero, the tagging level is directly recorded, the tagging number is incremented (i.e. tagging number = tagging number + 1), and the tagging operation flag bit is set to the first value, so that the system performs the current tagging operation;

[0004] (2) If the tagging number corresponding to the target memory block is not zero and the target tag value corresponding to the current tagging operation is greater than the first tag value (i.e. the historical maximum tag value) recorded at present, the first tag value is updated to the target tag value, the tagging number is incremented, and the tagging operation flag bit is set to the first value;

[0005] (3) If the number of marking times corresponding to the target memory block is nonzero, the target marking value corresponding to the current marking operation is less than or equal to the first marking value recorded at present (i.e., the historical maximum marking value), and the number of marking times does not reach the preset first threshold (denoted as PIN MAX), then the number of marking times is incremented, and the marking operation flag bit is set to the first value;

[0006] (4) If the number of marking times corresponding to the target memory block is nonzero, the target marking value corresponding to the current marking operation is greater than the first marking value recorded at present (i.e., the historical maximum marking value), and the number of marking times reaches PIN MAX, then the marking operation flag bit is set to the first value.

[0007] (5) If the number of marking times corresponding to the target memory block is nonzero, the target marking value corresponding to the current marking operation is less than or equal to the first marking value recorded at present (i.e., the historical maximum marking value), and the number of marking times reaches PIN MAX, then the marking is skipped to avoid the problem of large system overhead caused by frequent marking. In an optional embodiment, the first structure further includes an unmarking operation flag bit; the memory exchange method further includes the following method steps: in response to an unmarking instruction, performing unmarking update on the first array according to the number of marking times, a second threshold, and a third threshold, wherein the second threshold is used to determine whether to update the first marking value and the number of marking times according to the unmarking instruction, and the third threshold is used to determine whether to update the unmarking operation flag bit. As an exemplary embodiment, the unmarking operation flag bit is used to determine whether to perform the corresponding unmarking operation (i.e., removing the mark already marked on the target memory block) in response to the unmarking instruction. The unmarking operation flag bit is the third value (e.g., taking the value 1) indicating that the unmarking operation is performed; the unmarking operation flag bit is the fourth value (e.g., taking the value 0) indicating that the unmarking operation is skipped. Specifically, when receiving the unmarking instruction triggered by the process for the target memory block, it is determined whether to perform unmarking update on the unmarking operation flag bit according to the number of marking times corresponding to the target memory block, the preset second threshold, and the third threshold. The second threshold can be a high-frequency marking number (denoted as PIN HIGH), i.e., when the number of marking times of the target memory block is greater than the second threshold, it is considered that high-frequency marking is performed on the target memory block. The third threshold can be a preset upper limit of the number of marking times (denoted as PIN MAX) oGenerally, the third threshold is greater than the second threshold. Specifically, if the target memory block corresponds to a number of tags that does not reach the high-frequency tag number PIN HIGH, the number of tags is decremented (i.e., the number of tags = the number of tags - 1), and the tag operation flag is set to the third value, so that the system performs the untag operation corresponding to the current untag instruction. If the target memory block corresponds to a number of tags that reaches the high-frequency tag number PIN HIGH but does not reach the upper limit of the number of tags PIN MAX, the number of tags is decremented, and the tag operation flag is set to the fourth value, so that the system skips the untag operation to avoid frequent and meaningless changes in the properties of the target memory block. If the target memory block corresponds to a number of tags that reaches the upper limit of the number of tags PIN MAX, the update of the number of tags can be skipped, and the tag operation flag is set to the fourth value, so that the system keeps the property information of the target memory block unchanged. In an optional embodiment, the memory exchange method further includes the following method steps: filtering out array elements in the first array whose first tag value is greater than a fourth threshold, and updating the first array, wherein the fourth threshold is a tag value corresponding to the direct access memory category. In the process of performing a tag operation by a user process, after calling the corresponding tag interface, the tag interface updates the tag data in the first array corresponding to the user process, and updates the item structure corresponding to a plurality of memory blocks. Further, if the user process is currently performing a bind pin operation on a target memory block, it is determined whether the bind pin operation is used to retain the target memory block in the physical memory. Specifically, if the first tag value (i.e., the historical maximum tag value) corresponding to the target memory block is greater than or equal to the tag value (i.e., the fourth threshold) corresponding to the DMA memory, it indicates that the target memory block needs to be retained in the physical memory. After updating the number of tags of the target memory block, it is determined whether the number of tags of the target memory block has reached a preset number of tag threshold (denoted as CNT MAX). If the number of tags is greater than or equal to the number of tag threshold CNT MAX, it indicates that the target memory block is frequently used for device operations, and the benefits of dynamic pin and unpin operations on the target memory block are not large, so the last tag mark of the target memory block can be retained, i.e., the tag update of the target memory block in the current tag process is skipped. Further, if the user process is currently performing an unbind unpin operation on the target memory block, it is determined whether the number of tags of the target memory block is greater than the number of tag threshold CNT MAX. If the number of tags is greater than or equal to the number of tag threshold CNT MAX, the last tag mark of the target memory block can also be retained.According to the above, when the user-mode process performs the binding pin operation or the unbinding unpin operation on the target memory block, if the number of tags of the target memory block is less than the tag number threshold CNT MAX, the tag of the target memory block is considered to be updated, that is, whether the first tag value is updated is determined according to the size relationship between the target tag value corresponding to the current tagging operation and the first tag value corresponding to the target memory block. According to the above method steps of the embodiment of the present application, a cache filtering layer is added in the process of tagging of each target process, and the cache filtering layer filters according to the specified memory exchange priority (that is, part of the memory with a tag value greater than the DMA memory tag value) to improve the memory tagging efficiency. In an optional embodiment, the memory exchange method further includes the following method steps: in response to the target process being a kernel-mode process, calling a kernel-mode tagging interface to perform kernel-mode tagging on the target memory block corresponding to the target process, determining initial tag information, performing tagging update on the initial tag information based on the tagging data, and generating memory tag information. In the above optional embodiment, if the target process is a kernel-mode process, in a virtual architecture, the kernel-mode process will actively call the exposed kernel-mode tagging interface to implement the corresponding binding pin operation and / or unbinding unpin operation. As an exemplary embodiment, for the DMA operation corresponding to the kernel-mode process, the kernel-mode tagging interface is called to perform memory tagging. Generally, there is also a unified DMA interface in the virtual architecture. In addition, for a plurality of operation functions corresponding to the DMA operation, a wrapping function can be added to the plurality of operation functions to automatically implement the above binding pin operation and / or unbinding unpin operation. For example, in an application scenario, before the kernel-mode process calls a user-mode tagging interface (an interface for implementing the binding pin operation), the kernel-mode tagging interface is first called once to perform tagging. Similarly, before the kernel-mode process calls a user-mode untagging interface (an interface for implementing the unbinding unpin operation), the kernel-mode untagging interface is first called once to perform untagging. According to the above method steps of the embodiment of the present application, for the user-mode process and the kernel-mode process, the corresponding tagging interface calling mode is adopted to complete the memory tagging of the virtual architecture, thereby implementing the binding or unbinding of the memory block, and further facilitating the memory exchange process of the virtual architecture. In an optional embodiment, the memory tag information is used to select a to-be-exchanged memory block from a plurality of memory blocks for memory exchange, including the following method steps: selecting the to-be-exchanged memory block from the plurality of memory blocks according to a preset tag threshold and the first tag value and the second tag value in the memory tag information; and performing memory exchange processing on the to-be-exchanged memory block based on the address of the to-be-exchanged memory block in the memory space of the virtual architecture.According to the optional embodiment, the memory blocks with the first mark value greater than the preset mark threshold are selected from the plurality of memory blocks, the memory block with a higher memory swap priority is selected as the to-be-swapped memory block from the partial memory blocks according to the first mark value and the second mark value, and the to-be-swapped memory block is further subjected to the memory swap processing according to the address corresponding to the to-be-swapped memory block. In an application scenario, after an unpin operation is performed on a certain memory block, the memory block may be swapped out (swap out), at this time, the pages corresponding to the memory block in the physical memory are all cleared, therefore, before a pin operation is performed on a target memory block in a virtual architecture, a read operation can be performed on the target memory block, at this time, if the target memory block has indeed been swapped out, a page fault exception of a virtualization layer of the virtual architecture will be triggered, and the virtualization layer will actively swap in the pages corresponding to the target memory block, the above steps can ensure that the target memory block is in the physical memory when the pin operation is performed on the target memory block, and reduce the running risk of the system and improve the system stability. Based on the above method steps of the embodiment of the present application, the memory currently used by the virtualization layer, the memory corresponding to the kernel code segment, and the memory corresponding to the key data structure can be marked as RSVD memory by pre-setting the memory mark type, and the above memory is prohibited from being used for memory swap. By pre-setting the memory mark type, the memory currently used by the device-related process can also be marked as DEV memory, so as to reduce the memory swap priority of the memory, and the mark of the memory can also be dynamically updated to the mark of DMA memory in the system running, so as to ensure that the memory related to the DMA operation is retained in the physical memory. In summary, after the memory of the operating system is correctly marked, the memory swap method provided by the embodiment of the present application can preferentially perform memory swap on the memory block in the virtual architecture which is not marked, and further, the memory block with a higher memory swap priority is preferentially selected from the memory block marked for memory swap according to the first mark value and the second mark value, thereby, the embodiment of the present application can realize memory elasticity on the basis of ensuring the system performance and running correctness, and improve the system resource utilization. It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for the user to select authorization or refusal.It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the action sequence described, because according to the present application, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application. Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, and of course it can also be realized by hardware. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk) and includes a number of instructions to make an end device (which can be a mobile phone, a computer, a server, or a network device) execute the methods described in various embodiments of the present application. Embodiment 2 In the operating environment as in Embodiment 1, the present application provides another memory exchange method as shown in FIG. 4. FIG. 4 is a flowchart of a memory exchange method according to Embodiment 2 of the present application, as shown in FIG. 4, the memory exchange method comprises: step S41, obtaining a memory exchange request through a first application programming interface, wherein the request data carried in the memory exchange request includes: target process corresponding marking data, wherein the marking data is obtained by the target process performing memory category marking on a plurality of memory blocks in a virtual architecture; step S42, returning a memory exchange response through a second application programming interface, wherein the response data carried in the memory exchange response includes: memory exchange processing result, the memory exchange processing result is obtained by performing memory exchange processing on a plurality of memory blocks to be exchanged by using memory marking information, the memory marking information is determined based on the marking data, and the memory marking information is used to represent the memory exchange priority level corresponding to the plurality of memory blocks. According to the above method steps, a method for implementing a memory exchange cloud service is provided, and the method runs on a cloud server.The cloud server obtains a memory exchange request issued by a service invoker through a first application programming interface, executes a memory exchange process based on current memory tagging data corresponding to a memory space of a virtual architecture carried by the memory exchange request, to obtain a memory exchange processing result. Further, the cloud server returns a memory exchange response to the service invoker through a second application programming interface, to provide the memory exchange processing result to the service invoker. The first application programming interface and the second application programming interface can be the same application programming interface or different application programming interfaces. In an optional embodiment, interface parameters in the first application programming interface and the second application programming interface can include, but are not limited to, an interface global identifier, an interface signature key, an interface timestamp, an interface request identifier, a system call credential identifier, and the like. The first application programming interface can use a GET (get) or POST (post) method as an interface request method to obtain a file processing request. The second application programming interface can use a JSON (JavaScript Object Notation) format to feed back a file processing response. The target process is a user process in a computer system, and the target process can be one or more. The target process can include a user mode process and / or a kernel mode process. The virtual architecture refers to a virtualized computing environment created on physical computing resources by using a virtualization technology. The physical computing resources at least include physical memory. The plurality of memory blocks can be virtual memory blocks divided from a memory space of the virtual architecture. Each virtual memory block can include one or more memory pages. The virtualized computing environment can run different operating systems and application programs. The virtualized computing environment can improve the utilization, flexibility, and reliability of computing resources in the system, and reduce hardware costs and management costs. The virtualization technology includes a virtual machine technology and a container technology. During system operation, each target process can tag a memory category of a virtual memory block in the virtual architecture to obtain tagging data. According to the tagging data, a memory category tag of the target process on the memory block can be determined, and the memory category tag is used to determine a memory exchange priority of the memory block. It should be noted that the tagging data can include data of tagging at least one memory block in a plurality of memory blocks by a plurality of target processes. Usually, one target process can tag a plurality of memory blocks, and different target processes can tag the same memory block. Based on the tagging data, memory tag information is determined, and a memory exchange priority of each memory block in the virtual architecture is determined.The memory exchange priority level can represent the strictness of the memory block participating in the memory exchange. For example, the memory exchange priority level of the memory block locked in the memory and prohibited from being swapped out is lower than the memory exchange priority level of the memory block that meets the condition to be swapped out, and the memory exchange priority level of the memory block that meets the condition to be swapped out is lower than the memory exchange priority level of the memory block that can be swapped out. Further, after determining the memory tag information corresponding to the virtual architecture, the system responds to the memory exchange request, selects a to-be-swapped memory block from the plurality of memory blocks according to the memory exchange priority level, and uses the to-be-swapped memory block for the memory exchange operation. Therefore, the memory block with a higher memory exchange priority level can be used for memory exchange first, and the memory block prohibited from being swapped out will not be used for memory exchange, thereby enhancing the flexibility of system memory exchange, reducing the risk of data transmission, and improving the utilization rate of system memory resources. In the embodiment of the present application, the memory exchange request is obtained through a first application programming interface, wherein the request data carried in the memory exchange request includes: the marking data corresponding to the target process, wherein the marking data is obtained by the target process marking the memory categories of the plurality of memory blocks in the virtual architecture; and the memory exchange response is returned through a second application programming interface, wherein the response data carried in the memory exchange response includes: the memory exchange processing result, the memory exchange processing result is obtained by using the memory tag information to process the to-be-swapped memory block in the plurality of memory blocks, the memory tag information is determined based on the marking data, and the memory tag information is used to represent the memory exchange priority level corresponding to the plurality of memory blocks. Therefore, the present application achieves the purpose of marking the memory exchange priority of the plurality of memory blocks in the virtual architecture and further implements memory exchange, thereby achieving the technical effects of improving memory exchange flexibility, improving system data security and resource utilization, and further solving the technical problems of low memory exchange flexibility, high data transmission risk, and poor system resource utilization caused by the difficulty of related technologies to determine the memory space that does not support exchange. It should be noted that the preferred embodiments of the present embodiment can refer to the related description in Embodiment 1, which will not be repeated here.Figure 5 is a structural schematic diagram of a memory exchange device according to Embodiment 3 of the present application. As shown in Figure 5, the device comprises: an obtaining module 501 configured to obtain marking data corresponding to a target process, wherein the marking data is obtained by marking memory categories of a plurality of memory blocks in a virtual architecture by the target process; a determining module 502 configured to determine memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent memory exchange priority levels corresponding to the plurality of memory blocks; and an exchanging module 503 configured to select a memory block to be exchanged from the plurality of memory blocks based on the memory marking information to perform memory exchange. Optionally, the memory exchange device comprises, in addition to all the above-mentioned modules, a dividing module 504 (not shown in the figure) configured to: divide a memory space of the virtual architecture based on a first granularity to obtain a plurality of first memory pages corresponding to the first granularity; divide the memory space of the virtual architecture based on a second granularity to obtain a plurality of second memory pages corresponding to the second granularity, wherein the first granularity is smaller than the second granularity; and aggregate the plurality of first memory pages and divide the plurality of second memory pages based on a third granularity to obtain the plurality of memory blocks, wherein the third granularity is greater than the first granularity and smaller than the second granularity. Optionally, the memory marking information comprises a first array; the determining module 502 is further configured to: construct the first array, wherein array elements of the first array comprise a plurality of first structure bodies corresponding to the plurality of memory blocks; determine a target memory address and a memory category identifier based on the marking data, wherein the target memory address is used to determine a target memory block in the plurality of memory blocks, and the memory category identifier is used to represent a marked memory category of the target memory block; and update the first structure body corresponding to the target memory block in the first array based on the target memory address and the memory category identifier. Optionally, the determining module 502 is further configured to: determine the target memory block from the plurality of memory blocks based on the target memory address; determine a target marking value corresponding to the memory category identifier based on a memory exchange priority rule, wherein the memory exchange priority rule is used to determine an association between a memory exchange priority level corresponding to the memory category identifier and the target marking value; and update the first structure body corresponding to the target memory block based on the target marking value.Optionally, the first structure includes a first mark value and a mark number; the determining module 502 is further configured to: in response to a first condition being met, updating the mark number, and updating the first mark value to a target mark value, wherein the first condition includes: the mark number being greater than or equal to zero, the mark number being less than a first threshold, and the target mark value being greater than the first mark value; in response to a second condition being met, updating the mark number, wherein the second condition includes: the mark number being less than the first threshold, and the target mark value being less than or equal to the first mark value. Optionally, the first structure further includes a mark operation flag; the determining module 502 is further configured to: in response to one of the first condition, the second condition and a third condition being met, determining the mark operation flag as a first value, wherein the first value is used to determine that a mark operation is performed on the target memory block according to the first mark value, and the third condition includes: the mark number being equal to the first threshold, and the target mark value being greater than the first mark value; in response to a fourth condition being met, determining the mark operation flag as a second value, wherein the second value is used to determine that the mark operation is skipped on the target memory block, and the fourth condition includes: the mark number being equal to the first threshold, and the target mark value being less than or equal to the first mark value. Optionally, the first structure further includes an unmark operation flag; the determining module 502 is further configured to: in response to an unmark instruction, performing unmark updating on the first array according to the mark number, a second threshold and a third threshold, wherein the second threshold is used to determine whether the first mark value and the mark number are updated according to the unmark instruction, and the third threshold is used to determine whether the unmark operation flag is updated. Optionally, the memory exchange apparatus further includes a filtering module 505 (not shown in the figure) configured to: filtering out an array element with a first mark value greater than a fourth threshold in the first array, and updating the first array, wherein the fourth threshold is a mark value corresponding to a direct access memory category. Optionally, the memory mark information further includes a second array; the memory exchange apparatus further includes a marking module 506 (not shown in the figure) configured to: creating the second array, wherein an array element of the second array includes a plurality of second structures corresponding to a plurality of second memory pages, a second structure corresponding to a target second memory page in the plurality of second memory pages includes a second mark value and a first structure corresponding to a part of memory blocks, and the part of memory blocks are memory blocks contained in the target second memory page; updating the first structure in the second array by using the updated first array; and for the second structure corresponding to the target second memory page, determining a maximum value in the first mark value corresponding to the part of memory blocks as the second mark value corresponding to the second structure.Optionally, the exchange module 503 is further configured to: select the memory block to be exchanged from the plurality of memory blocks according to the preset marking threshold and the first marking value and the second marking value in the memory marking information; and perform memory exchange processing on the memory block to be exchanged based on an address of the memory block to be exchanged in the memory space of the virtual architecture. Optionally, in addition to the above modules, the memory exchange apparatus further comprises: a kernel state marking module 506 (not shown in the figure) configured to: in response to the target process being a kernel state process, perform kernel state marking on the target memory block corresponding to the target process by calling a kernel state marking interface, determine initial marking information, perform marking update on the initial marking information based on the marking data, and generate the memory marking information. It should be noted that the above obtaining module 501, determining module 502, and exchange module 503 correspond to steps S31 to S33 in Embodiment 1, and the three modules have the same instances and application scenarios as the corresponding steps, but are not limited to the content disclosed in Embodiment 1. It should be noted that the above modules or units can be hardware components or software components stored in a memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b, …, 102n), or can be a part of the apparatus and can run in the computer terminal 10 provided in Embodiment 1. According to the embodiments of the present application, an apparatus embodiment configured to implement the memory exchange method in Embodiment 2 is further provided. FIG. 6 is a structural schematic diagram of another memory exchange apparatus according to Embodiment 3 of the present application. As shown in FIG. 6, the apparatus comprises: an obtaining module 601 configured to obtain a memory exchange request through a first application programming interface, wherein the request data carried in the memory exchange request comprises: marking data corresponding to a target process, wherein the marking data is obtained by the target process performing memory category marking on a plurality of memory blocks in a virtual architecture; and a responding module 602 configured to return a memory exchange response through a second application programming interface, wherein the response data carried in the memory exchange response comprises: a memory exchange processing result, the memory exchange processing result being obtained by performing memory exchange processing on a memory block to be exchanged in the plurality of memory blocks by using memory marking information, the memory marking information being determined based on the marking data, and the memory marking information being used to represent memory exchange priority levels corresponding to the plurality of memory blocks. It should be noted that the above obtaining module 601 and responding module 602 correspond to steps S41 to S42 in Embodiment 2, and the two modules have the same instances and application scenarios as the corresponding steps, but are not limited to the content disclosed in Embodiment 2.It should be noted that the above modules or units can be hardware components or software components stored in the memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b, …, 102n), or the modules can be run in the computer terminal 10 provided in Embodiment 1 as part of the device. It should be noted that the preferred embodiments of the present embodiment can refer to the related description in Embodiment 1 or Embodiment 2, which will not be repeated here. Embodiment 4 also provides an electronic device according to the embodiments of the present application, which can be any one of the computer terminal devices in the computer terminal group. Alternatively, in the present embodiment, the above electronic device can also be replaced by a terminal device such as a mobile terminal. Alternatively, in the present embodiment, the above electronic device can be located in at least one network device of a plurality of network devices of a computer network. In the present embodiment, the above electronic device can execute program codes of the following steps in the memory exchange method: obtaining the marking data corresponding to the target process, wherein the marking data is obtained by the target process marking the memory categories of a plurality of memory blocks in a virtual architecture; determining the memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent the memory exchange priority levels corresponding to the plurality of memory blocks; and selecting the to-be-exchanged memory block from the plurality of memory blocks for memory exchange by using the memory marking information. Alternatively, FIG. 7 is a structural block diagram of an electronic device according to Embodiment 4 of the present application, as shown in FIG. 7, the electronic device 70 can include one or more (only one is shown in the figure) processors 702, a memory 704, a storage controller 706, and a peripheral interface 708, wherein the peripheral interface 708 is connected with a radio frequency module, an audio module, and a display. The memory 704 can be configured to store software programs and modules, such as program instructions / modules corresponding to the memory exchange method and device in the embodiments of the present application, and the processor executes the software programs and modules stored in the memory, thereby executing various functional applications and data processing, that is, implementing the above memory exchange method. The memory 704 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 704 can further include a memory remotely arranged with respect to the processor, which can be connected to the electronic device 70 through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and a combination thereof.The processor 702 can call information and application programs stored in the memory through the transmission device to execute the following steps: obtaining marking data corresponding to a target process, wherein the marking data is obtained by marking a plurality of memory blocks in a virtual architecture with memory categories by the target process; determining memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent memory exchange priority levels corresponding to the plurality of memory blocks; and selecting a memory block to be exchanged from the plurality of memory blocks for memory exchange using the memory marking information. Optionally, the processor 702 can further execute program codes of the following steps: dividing a memory space of the virtual architecture based on a first granularity to obtain a plurality of first memory pages corresponding to the first granularity; dividing the memory space of the virtual architecture based on a second granularity to obtain a plurality of second memory pages corresponding to the second granularity, wherein the first granularity is smaller than the second granularity; and aggregating the plurality of first memory pages and segmenting the plurality of second memory pages based on a third granularity to obtain the plurality of memory blocks, wherein the third granularity is greater than the first granularity and smaller than the second granularity. Optionally, the processor 702 can further execute program codes of the following steps: the memory marking information includes a first array; constructing the first array, wherein array elements of the first array include a plurality of first structures corresponding to the plurality of memory blocks; determining a target memory address and a memory category identifier using the marking data, wherein the target memory address is used to determine a target memory block in the plurality of memory blocks, and the memory category identifier is used to represent a marked memory category of the target memory block; and updating the first structure corresponding to the target memory block in the first array according to the target memory address and the memory category identifier. Optionally, the processor 702 can further execute program codes of the following steps: determining the target memory block from the plurality of memory blocks according to the target memory address; determining a target marking value corresponding to the memory category identifier according to a memory exchange priority rule, wherein the memory exchange priority rule is used to determine an association between a memory exchange priority level corresponding to the memory category identifier and the target marking value; and updating the first structure corresponding to the target memory block using the target marking value. Optionally, the processor 702 can further execute program codes of the following steps: the first structure includes a first marking value and a marking number; in response to a first condition being met, updating the marking number and updating the first marking value to the target marking value, wherein the first condition includes: the marking number is greater than or equal to zero, the marking number is less than a first threshold, and the target marking value is greater than the first marking value; and in response to a second condition being met, updating the marking number, wherein the second condition includes: the marking number is less than the first threshold, and the target marking value is less than or equal to the first marking value.Optionally, the processor 702 can further execute program codes of the following steps: the first structure further includes a marking operation flag bit; in response to one of the first condition, the second condition and the third condition being met, the marking operation flag bit is determined as a first value, wherein the first value is used to determine that the marking operation is performed on the target memory block according to the first mark value, the third condition includes that the marking number is equal to the first threshold value and the target mark value is greater than the first mark value; in response to the fourth condition being met, the marking operation flag bit is determined as a second value, wherein the second value is used to determine that the marking operation is skipped on the target memory block, and the fourth condition includes that the marking number is equal to the first threshold value and the target mark value is less than or equal to the first mark value. Optionally, the processor 702 can further execute program codes of the following steps: the first structure further includes an unmarking operation flag bit; in response to the unmarking instruction, the first array is unmarked and updated according to the marking number, the second threshold value and the third threshold value, wherein the second threshold value is used to determine whether the first mark value and the marking number are updated according to the unmarking instruction, and the third threshold value is used to determine whether the unmarking operation flag bit is updated. Optionally, the processor 702 can further execute program codes of the following steps: the array elements in the first array with the first mark value greater than a fourth threshold value are filtered out, and the first array is updated, wherein the fourth threshold value is a mark value corresponding to the direct access memory category. Optionally, the processor 702 can further execute program codes of the following steps: the memory mark information further includes a second array; the second array is created, wherein the array elements of the second array include a plurality of second structures corresponding to a plurality of second memory pages, the second structure corresponding to a target second memory page in the plurality of second memory pages includes a second mark value and the first structures corresponding to the memory blocks contained in the target second memory page; the first structures in the second array are updated by using the updated first array; for the second structure corresponding to the target second memory page, the maximum value in the first mark values corresponding to the memory blocks is determined as the second mark value corresponding to the second structure. Optionally, the processor 702 can further execute program codes of the following steps: according to the preset mark threshold value and the first mark value and the second mark value in the memory mark information, a to-be-swapped memory block is selected from the plurality of memory blocks; based on the address of the to-be-swapped memory block in the memory space of the virtual architecture, the memory swapping processing is performed on the to-be-swapped memory block. Optionally, the processor 702 can further execute program codes of the following steps: in response to the target process being a kernel process, a kernel marking interface is called to perform kernel marking on the target memory block corresponding to the target process, initial mark information is determined, the initial mark information is marked and updated based on the marking data, and the memory mark information is generated.The processor 702 can call the information and application programs stored in the memory through the transmission device to perform the following steps: obtaining a memory exchange request through a first application programming interface, wherein the request data carried in the memory exchange request includes: tag data corresponding to a target process, wherein the tag data is obtained by the target process performing memory category tagging on a plurality of memory blocks in a virtual architecture; and returning a memory exchange response through a second application programming interface, wherein the response data carried in the memory exchange response includes: a memory exchange processing result, the memory exchange processing result being obtained by performing memory exchange processing on a to-be-exchanged memory block in the plurality of memory blocks by using memory marking information, the memory marking information being determined based on the tag data, and the memory marking information being used to represent a memory exchange priority level corresponding to the plurality of memory blocks. By adopting the embodiment of the present application, an electronic device configured to implement the above memory exchange method is provided. The tag data corresponding to the target process is obtained, wherein the tag data is obtained by the target process performing memory category tagging on a plurality of memory blocks in a virtual architecture; further, based on the tag data, memory marking information corresponding to the virtual architecture is determined, wherein the memory marking information is used to represent a memory exchange priority level corresponding to the plurality of memory blocks; and the to-be-exchanged memory block is selected from the plurality of memory blocks by using the memory marking information for memory exchange. Therefore, the present application achieves the purpose of performing memory exchange priority tagging on the plurality of memory blocks in the virtual architecture and further implementing memory exchange, thereby achieving the technical effects of improving memory exchange flexibility, improving system data security, and improving resource utilization, and further solving the technical problems of low memory exchange flexibility, high data transmission risk, and poor system resource utilization caused by the related technology that cannot determine the memory space that does not support exchange. It can be understood by those skilled in the art that the structure shown in FIG. 7 is only schematic, and the electronic device can also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a mobile Internet device (Mobile Internet Devices, abbreviated as MID), and the like. FIG. 7 does not limit the structure of the above-mentioned electronic device. For example, the electronic device 70 can further include more or fewer components (such as a network interface, a display device, etc.) than those shown in FIG. 7, or have a different configuration from that shown in FIG. 7. It can be understood by those skilled in the art that all or part of the steps in the various methods of the above embodiments can be completed by programs instructing the relevant hardware of the terminal device, and the programs can be stored in a computer-readable storage medium, which can include: a flash disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.Optionally, in the embodiment, the storage medium can be configured to store program codes for implementing the memory swapping method provided in the embodiment 1 or the embodiment 2. Optionally, in the embodiment, the storage medium can be located in any one of computer terminals in a computer terminal group in a computer network, or in any one of mobile terminals in a mobile terminal group. Optionally, in the embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: obtaining marking data corresponding to a target process, wherein the marking data is obtained by marking memory categories of a plurality of memory blocks in a virtual architecture by the target process; determining memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent memory swapping priority levels of the plurality of memory blocks; and selecting to-be-swapped memory blocks from the plurality of memory blocks for memory swapping by using the memory marking information. Optionally, in the embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: dividing a memory space of the virtual architecture based on a first granularity to obtain a plurality of first memory pages corresponding to the first granularity; dividing the memory space of the virtual architecture based on a second granularity to obtain a plurality of second memory pages corresponding to the second granularity, wherein the first granularity is smaller than the second granularity; and aggregating the plurality of first memory pages and segmenting the plurality of second memory pages based on a third granularity to obtain the plurality of memory blocks, wherein the third granularity is larger than the first granularity and smaller than the second granularity. Optionally, in the embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: the memory marking information includes a first array; constructing the first array, wherein array elements of the first array include a plurality of first structure bodies corresponding to the plurality of memory blocks; determining a target memory address and a memory category identifier by using the marking data, wherein the target memory address is used to determine a target memory block in the plurality of memory blocks, and the memory category identifier is used to represent a marked memory category of the target memory block; and updating the first structure body corresponding to the target memory block in the first array according to the target memory address and the memory category identifier. Optionally, in the embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: determining the target memory block from the plurality of memory blocks according to the target memory address; determining a target marking value corresponding to the memory category identifier according to a memory swapping priority rule, wherein the memory swapping priority rule is used to determine an association relationship between a memory swapping priority level corresponding to the memory category identifier and the target marking value; and updating the first structure body corresponding to the target memory block by using the target marking value.Optionally, the processor 702 can further execute program codes for the following steps: the first structure includes a first mark value and a marking number; in response to a first condition being met, updating the marking number and updating the first mark value to a target mark value, wherein the first condition includes: the marking number is greater than or equal to zero, the marking number is less than a first threshold, and the target mark value is greater than the first mark value; in response to a second condition being met, updating the marking number, wherein the second condition includes: the marking number is less than the first threshold, and the target mark value is less than or equal to the first mark value. Optionally, in this embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: the first structure further includes a marking operation flag; in response to one of the first condition, the second condition and a third condition being met, determining the marking operation flag as a first value, wherein the first value is used to determine that a marking operation is performed on the target memory block according to the first mark value, and the third condition includes: the marking number is equal to the first threshold, and the target mark value is greater than the first mark value; in response to a fourth condition being met, determining the marking operation flag as a second value, wherein the second value is used to determine that the marking operation is skipped on the target memory block, and the fourth condition includes: the marking number is equal to the first threshold, and the target mark value is less than or equal to the first mark value. Optionally, in this embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: the first structure further includes an unmarking operation flag; in response to an unmarking instruction, updating the first array according to the marking number, a second threshold and a third threshold, wherein the second threshold is used to determine whether to update the first mark value and the marking number according to the unmarking instruction, and the third threshold is used to determine whether to update the unmarking operation flag. Optionally, in this embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: filtering out array elements in the first array whose first mark value is greater than a fourth threshold, and updating the first array, wherein the fourth threshold is a mark value corresponding to a direct access memory category. Optionally, in this embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: the memory mark information further includes a second array; creating the second array, wherein array elements of the second array include a plurality of second structures corresponding to a plurality of second memory pages, a second structure corresponding to a target second memory page in the plurality of second memory pages includes a second mark value and first structures corresponding to partial memory blocks, and the partial memory blocks are memory blocks included in the target second memory page; updating the first structures in the second array by using the updated first array; for the second structure corresponding to the target second memory page, determining a maximum value in the first mark values corresponding to the partial memory blocks as the second mark value corresponding to the second structure.Optionally, in the embodiment, the computer readable storage medium is configured to store program code for performing the following steps: selecting, from the plurality of memory blocks, a memory block to be exchanged according to a preset marking threshold and first and second marking values in the memory marking information; and performing memory exchange processing on the memory block to be exchanged based on an address of the memory block to be exchanged in the memory space of the virtual architecture. Optionally, in the embodiment, the computer readable storage medium is configured to store program code for performing the following steps: in response to the target process being a kernel-mode process, calling a kernel-mode marking interface to perform kernel-mode marking on a target memory block corresponding to the target process, determining initial marking information, performing marking update on the initial marking information based on the marking data, and generating the memory marking information. Optionally, in the embodiment, the computer readable storage medium is configured to store program code for performing the following steps: obtaining a memory exchange request through a first application programming interface, wherein the request data carried in the memory exchange request includes marking data corresponding to the target process, and the marking data is obtained by performing memory category marking on a plurality of memory blocks in the virtual architecture by the target process; and returning a memory exchange response through a second application programming interface, wherein the response data carried in the memory exchange response includes a memory exchange processing result, the memory exchange processing result is obtained by performing memory exchange processing on a memory block to be exchanged in the plurality of memory blocks by using memory marking information, the memory marking information is determined based on the marking data, and the memory marking information is used to represent memory exchange priority levels corresponding to the plurality of memory blocks. By adopting the embodiment of the application, a computer readable storage medium configured to implement the above memory exchange method is provided. The marking data corresponding to the target process is obtained, wherein the marking data is obtained by performing memory category marking on a plurality of memory blocks in the virtual architecture by the target process; further, based on the marking data, memory marking information corresponding to the virtual architecture is determined, wherein the memory marking information is used to represent memory exchange priority levels corresponding to the plurality of memory blocks; and the memory marking information is used to select a memory block to be exchanged from the plurality of memory blocks for memory exchange. Thus, the application achieves the purpose of performing memory exchange priority marking on the plurality of memory blocks in the virtual architecture and further implementing memory exchange, thereby achieving the technical effects of improving memory exchange flexibility, improving system data security, and improving resource utilization, and further solving the technical problems of low memory exchange flexibility, high data transmission risk, and poor system resource utilization caused by the related art being unable to determine memory spaces that do not support exchange. According to the embodiment of the application, a computer program product is also provided. Optionally, in the embodiment, the computer program product can provide memory exchange services based on the memory exchange method provided in the above embodiment 1 or embodiment 2.Optionally, in the embodiment, the computer program product can be a set of instructions and codes pre-written according to the memory swapping method. The computer program product can run on various computer platforms, including personal computers, servers, mobile devices, etc. Optionally, in the embodiment, the instructions and codes corresponding to the computer program product are used to implement the following method steps: obtaining the marking data corresponding to the target process, wherein the marking data is obtained by marking the memory categories of the plurality of memory blocks in the virtual architecture by the target process; determining the memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent the memory swapping priority levels of the plurality of memory blocks; and selecting the memory block to be swapped from the plurality of memory blocks for memory swapping by using the memory marking information. Through the computer program product, the memory swapping service can be provided in the application scenario involving memory swapping in the virtualized computing environment, so as to achieve the purpose of marking the memory swapping priorities of the plurality of memory blocks in the virtual architecture and further implementing the memory swapping, thereby achieving the technical effects of improving the memory swapping flexibility, improving the system data security and resource utilization, and further solving the technical problems of low memory swapping flexibility, high data transmission risk and poor system resource utilization caused by the difficulty of determining the memory space not supporting swapping in the related art. In the above embodiments of the present application, the descriptions of various embodiments are different from each other, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. In the several embodiments provided in the present application, it should be understood that the disclosed technical contents can be implemented by other means. Among them, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between units or modules, which can be electrical or other forms. The units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme. In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.The integrated unit can be realized in the form of hardware or in the form of a software function unit. If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, the computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes a U disk, a ROM, a RAM, a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes. The above is only the preferred embodiment of the present application, and it should be pointed out that, for ordinary skilled persons in the technical field, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

CLAIM 1. A memory swapping method, comprising: Obtaining marking data corresponding to a target process, wherein the marking data is obtained by performing memory category marking on a plurality of memory blocks in a virtual architecture by the target process; determining memory marking information corresponding to the virtual architecture based on the marking data, wherein the memory marking information is used to represent memory exchange priority levels corresponding to the plurality of memory blocks; and selecting a memory block to be exchanged from the plurality of memory blocks for memory exchange by using the memory marking information.

2. The memory swapping method according to claim 1, wherein, The memory exchange method further includes: dividing a memory space of the virtual architecture based on a first granularity to obtain a plurality of first memory pages corresponding to the first granularity; dividing the memory space of the virtual architecture based on a second granularity to obtain a plurality of second memory pages corresponding to the second granularity, wherein the first granularity is smaller than the second granularity; and aggregating the plurality of first memory pages and segmenting the plurality of second memory pages based on a third granularity to obtain the plurality of memory blocks, wherein the third granularity is greater than the first granularity and smaller than the second granularity.

3. The memory swapping method according to claim 1, wherein, The memory marking information includes a first array. Determining the memory marking information corresponding to the virtual architecture based on the marking data includes: constructing the first array, wherein array elements of the first array include a plurality of first structure bodies corresponding to the plurality of memory blocks; determining a target memory address and a memory category identifier by using the marking data, wherein the target memory address is used to determine a target memory block in the plurality of memory blocks, and the memory category identifier is used to represent a marked memory category of the target memory block; and updating the first structure body corresponding to the target memory block in the first array according to the target memory address and the memory category identifier.

4. The memory swapping method according to claim 3, wherein, Updating the first structure body corresponding to the target memory block in the first array according to the target memory address and the memory category identifier includes: determining a target memory block from the plurality of memory blocks according to the target memory address; Determining a target marking value corresponding to the memory category identifier according to a memory exchange priority rule, wherein the memory exchange priority rule is used to determine an association between the memory exchange priority level corresponding to the memory category identifier and the target marking value; 26 Updating the first structure body corresponding to the target memory block by using the target marking value.

5. The memory swapping method according to claim 4, wherein, The first structure body includes a first marking value and a marking frequency. The target mark value is used to update the first structure corresponding to the target memory block, including: in response to a first condition being met, updating the marking number and updating the first mark value to the target mark value, wherein the first condition includes: the marking number being greater than or equal to zero, the marking number being less than a first threshold, and the target mark value being greater than the first mark value; and in response to a second condition being met, updating the marking number, wherein the second condition includes: the marking number being less than the first threshold, and the target mark value being less than or equal to the first mark value.

6. The memory swapping method according to claim 5, wherein, The first structure further includes a marking operation flag bit; The target mark value is used to update the first structure corresponding to the target memory block, further including: in response to one of the first condition, the second condition and a third condition being met, determining the marking operation flag bit as a first value, wherein the first value is used to determine that a marking operation is performed on the target memory block according to the first mark value, and the third condition includes: the marking number being equal to the first threshold, and the target mark value being greater than the first mark value; and in response to a fourth condition being met, determining the marking operation flag bit as a second value, wherein the second value is used to determine that the marking operation is skipped on the target memory block, and the fourth condition includes: the marking number being equal to the first threshold, and the target mark value being less than or equal to the first mark value.

7. The memory swapping method according to claim 5, wherein, The first structure further includes an unmarking operation flag bit; The memory exchange method further includes: in response to an unmarking instruction, performing unmarking update on the first array according to the marking number, a second threshold and a third threshold, wherein the second threshold is used to determine whether to update the first mark value and the marking number according to the unmarking instruction, and the third threshold is used to determine whether to update the unmarking operation flag bit.

8. The memory swapping method according to any one of claims 5 to 7, wherein, The memory exchange method further includes: filtering out, from the first array, an array element whose first mark value is greater than a fourth threshold, and updating the first array, wherein the fourth threshold is a mark value corresponding to a direct access memory category.

9. The memory swapping method of claim 5, wherein, The memory mark information further includes a second array, and the memory exchange method further includes: creating the second array, wherein an array element of the second array includes a plurality of second structures corresponding to a plurality of second memory pages, a second structure corresponding to a target second memory page in the plurality of second memory pages includes a second mark value and the first structure corresponding to a part of memory blocks, and the part of memory blocks are the memory blocks corresponding to the target mark value in the first array. The memory exchange method further includes: filtering out, from the first array, an array element whose first mark value is greater than a fourth threshold, and updating the first array, wherein the fourth threshold is a mark value corresponding to a direct access memory category. The target second memory page includes a memory block; the first array is updated, and the first structure in the second array is updated; for the second structure corresponding to the target second memory page, the maximum value in the first mark value corresponding to the part of the memory block is determined as the second mark value corresponding to the second structure.

10. The memory swapping method according to claim 9, wherein, The memory exchange method further includes: in response to the target process being a kernel state process, calling a kernel state marking interface to perform kernel state marking on a target memory block corresponding to the target process, determining initial marking information, performing marking update on the initial marking information based on the marking data, and generating the memory marking information.

11. The memory swapping method according to any one of claims 1 to 5, wherein, The memory exchange request carried in the memory exchange request includes: marking data corresponding to a target process, wherein the marking data is obtained by performing memory category marking on a plurality of memory blocks in a virtual architecture by the target process; and a memory exchange response is returned through a second application programming interface, wherein the response data carried in the memory exchange response includes: a memory exchange processing result, the memory exchange processing result is obtained by performing memory exchange processing on a to-be-exchanged memory block in the plurality of memory blocks by using memory marking information, the memory marking information is determined based on the marking data, and the memory marking information is used to represent memory exchange priority levels corresponding to the plurality of memory blocks.

12. A memory swapping method, comprising:

13. A computer readable storage medium, the computer readable storage medium comprising a stored executable program, when the executable program is executed, controlling a device where the computer readable storage medium is located to perform the memory exchange method of any one of claims 1 to 12. A memory, storing an executable program; 14. An electronic device, comprising: A processor, configured to run the program, wherein the program, when executed, performs the memory exchange method of any one of claims 1 to 12.

15. A computer program product, comprising a computer program, the computer program, when executed by a processor, implements the memory exchange method of any one of claims 1 to 12.

15. A computer program product, comprising a computer program, the computer program, when executed by a processor, implements the memory exchange method of any one of claims 1 to 12.

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