Quantum bit array circuit, quantum computer, and method for reading quantum bit

Abstract

The problem to be solved by the present invention is to provide a reading method which eliminates the need for generating a reference current when detecting the number of electrons corresponding to the direction of spin of one electron, and which increases a signal amount and is robust against disturbance noise.　One preferred aspect of the present invention is a quantum bit array circuit comprising a quantum bit array unit and a sense amplifier unit. The quantum bit array unit includes a spin charge conversion part having a first quantum bit transistor and a second quantum bit transistor for reading a quantum bit state, and a third quantum bit transistor for supplying electrons to the first quantum bit transistor. The sense amplifier unit includes a first output transistor and a second output transistor for outputting current according to the number of electrons. The first quantum bit transistor and the second quantum bit transistor are connected via an electron movement pathway. The first quantum bit transistor and the second quantum bit transistor are electrically connected or capacitively coupled to the first output transistor and the second output transistor, respectively. A barrier transistor having a gate electrode for applying voltage for executing a Pauli spin blockade and voltage for executing a classical charge operation is provided between the first quantum bit transistor and the second quantum bit transistor.

Description

Quantum bit array circuit, quantum computer, and quantum bit readout method

[0001] The present invention relates to quantum computing using a quantum bit array chip in which quantum bits are arranged and integrated in an array.

[0002] Quantum computers have been attracting attention in recent years. The miniaturization and performance of semiconductor elements, which have supported the advancement of computers to date, are reaching their limits, making it difficult to significantly improve the performance of conventional classical computers. Quantum computers are one attempt to overcome these limitations through new computational principles and devices. Currently, hardware development is underway in an effort to realize quantum computers, and various methods have been proposed for the qubits, the computing elements at the heart of quantum computers, including superconducting, ion-trap, and silicon types.

[0003] As a silicon-type device that applies semiconductor manufacturing technology, Patent Document 1 discloses a quantum device that includes a transistor structure having a source, a drain, and a gate, one or more quantum dot structures in which charge can be localized, and a quantum bit line that can change the state of charge in the quantum dot structures.

[0004] Furthermore, Patent Document 2 discloses a quantum information processing device that makes it possible to expand quantum bits two-dimensionally using current semiconductor manufacturing methods.

[0005] WO 2021 / 251175 A1 JP 2021-27142 A

[0006] The problem to be solved by the present invention is to provide a readout method that eliminates the need to generate a reference current when detecting the number of electrons corresponding to the spin direction of one electron, increases the signal amount, and is robust against external noise. More detailed problems will be described in the description of the invention.

[0007] a first quantum bit transistor and a second quantum bit transistor connected to each other via an electron transfer path; and a barrier transistor having a gate electrode for applying a voltage for performing Pauli spin blockade and a voltage for performing classical charge manipulation, between the first quantum bit transistor and the second quantum bit transistor.

[0008] Another preferred aspect of the present invention is a quantum computer comprising: a semiconductor device that constitutes the above-described quantum bit array circuit; an analog control device that controls the semiconductor device; a digital control device that controls the analog control device; and a refrigerator that cools the semiconductor device.

[0009] Another preferred aspect of the present invention is a quantum bit readout method for reading out the spin state of an electron in a quantum bit array circuit having a quantum bit array unit and a sense amplifier unit, the method comprising: a first step of arranging a gate electrode in the quantum bit array unit; storing an electron to be read out in a first quantum dot in the quantum bit array unit, and storing an electron having a predetermined ground state in a second quantum dot adjacent to the first quantum dot; a second step of applying a predetermined voltage to the gate electrode to apply a predetermined potential to the quantum dot array unit such that the electron to be read out tunnels into the second quantum dot only when the electron to be read out is in a first ground state; a third step of applying a predetermined voltage to the gate electrode to store one additional electron in the first quantum dot; and a fourth step of differentially reading out the number of electrons in the first quantum dot and the second quantum dot using the sense amplifier unit, thereby reading out the spin state of the electron to be read out.

[0010] When detecting the number of electrons corresponding to the spin direction of one electron, it is possible to eliminate the need to generate a reference current, increase the signal amount, and provide a readout method that is robust against external noise.

[0011] 1 is a conceptual diagram showing a silicon quantum computer; FIG. 1 is a cross-sectional view of a silicon quantum bit structure; FIG. 2 is an explanatory diagram showing a quantum operation method; FIG. 3 is a perspective view showing a silicon quantum bit array structure; FIG. 4 is a circuit diagram of a quantum bit array; FIG. 5 is a circuit diagram of a dynamic resonance frequency changing method; FIG. 6 is an operational waveform diagram of the dynamic resonance frequency changing method; FIG. 7 is a circuit diagram of a spin-charge converter; FIG. 8 is a potential diagram of a spin-charge converter; FIG. 9 is a table showing a conventional spin readout method; FIG. 10 is a system diagram of spin-charge conversion according to an embodiment; FIG. 11 is a table showing a spin readout method according to an embodiment; FIG. 12 is an explanatory diagram showing a control sequence of a spin-charge converter; FIG. 13 is an operational waveform diagram of Pauli spin blockade; FIG. 14 is a plan view showing the layout of a first sense amplifier; FIG. 15 is a circuit diagram of a sense amplifier; FIG. 16 is an operational waveform diagram of a sense amplifier; FIG. 17 is a waveform diagram of a preamplifier current-voltage characteristic; FIG. 18 is an explanatory diagram showing column-direction shuttling control; FIG. 19 is a layout diagram of a second sense amplifier; FIG. 19 is a circuit diagram of a second sense amplifier.

[0012] Each embodiment will be described below with reference to the accompanying drawings. However, the present invention should not be construed as being limited to the following description of the embodiments. Those skilled in the art will readily understand that the specific configuration can be modified without departing from the spirit or scope of the present invention.

[0013] In the configurations of the embodiments described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and redundant explanations may be omitted.

[0014] When there are multiple elements having the same or similar functions, they may be described using the same reference numeral with different subscripts. However, when there is no need to distinguish between multiple elements, the subscripts may be omitted.

[0015] The terms "first," "second," "third," and the like used in this specification are used to identify components and do not necessarily limit the number, order, or content of the components. Furthermore, numbers used to identify components are used in different contexts, and a number used in one context does not necessarily indicate the same configuration in another context. Furthermore, this does not prevent a component identified by a certain number from also serving the function of a component identified by another number.

[0016] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings etc. may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings etc.

[0017] All publications, patents, and patent applications cited herein are incorporated by reference in their entirety.

[0018] As used herein, elements referred to in the singular are intended to include the plural unless the context clearly indicates otherwise.

[0019] In this embodiment, the spin direction information of one electron (or hole; in this specification, the term "electron" is conceptually understood to include holes) is converted into the number of electrons in two quantum dots, making it possible to determine the electron direction based on the difference in the number of electrons. Specifically, a spin-blockade input quantum dot and an output quantum dot are prepared for spin readout, and the output quantum dot contains electrons with a fixed spin direction of either up or down. When the spin direction of the input quantum dot and the spin direction of the output quantum dot are the same (Case 1), electrons do not tunnel from the input quantum dot to the output quantum dot, and one electron each is maintained. On the other hand, when the spin direction of the input quantum dot and the spin direction of the output quantum dot are different (Case 2), electrons tunnel from the input quantum dot to the output quantum dot, resulting in zero electrons in the input quantum dot and two electrons in the output quantum dot.

[0020] In this example, after this operation, one electron is added to the input quantum dot, so that in case 1, the number of electrons in the input quantum dot and the output quantum dot becomes two and one, respectively, and in case 2, they become one and two.

[0021] Therefore, by determining the difference between the number of electrons in the input quantum dot and the number of electrons in the output quantum dot, it is possible to determine whether the operation is in Case 1 or Case 2, and to read out the spin of the calculation result. That is, after converting the number of electrons into a minute current using the SET, the current value is detected using a differential amplifier.

[0022] With this configuration, the spin information of one electron is converted into information about the difference in the number of electrons in the two quantum dots, and the corresponding minute current difference can then be read out using a differential amplifier. This eliminates the need to generate a reference current and doubles the signal amount, enabling readout that is robust against external noise.

[0023] 1 shows the overall configuration of a silicon quantum computer 1000. Quantum bits (Qubits) 102, which are quantum processing devices, are arranged in an array and mounted on a quantum bit array chip (QBA) 101, which is fabricated as a silicon chip.

[0024] QBA101 controls the quantum bits for quantum operations and senses the quantum information of the operation results. The quantum operation pattern, operation timing, bias voltage, and RF signal are supplied to QBA101 by a cryogenic analog control chip CAC (Cryogenic analog chip) 103. This CAC 103 is controlled by a host computer HOST and a digital control chip CDC (Digital control chip) 104 with a bridge function, and receives the operation results performed by QBA101.

[0025] To ensure stable operation of the quantum bits, QBA101 is placed inside the dilution refrigerator DR and operates at an extremely low temperature of around 0.1 K. CAC103, which controls it, is placed inside the dilution refrigerator DR in an environment of around 4 K. The host computer HOST and CDC104 operate at around 300 K (approximately room temperature).

[0026] Figure 2A shows a cross-sectional view of a portion of the silicon quantum bit structure of the Qubit array mounted on the QBA 101. In this QBA, the spin S of a single electron confined within a potential barrier PB formed in a silicon channel C of a MOS structure is used as the Qubit.

[0027] In the silicon quantum bit structure, electrons are trapped directly below the quantum dot control gate (XQ) 201 by increasing the voltage of the quantum dot control gate (XQ) 201 and decreasing the voltage of the interaction control gate (XJ) 202. In other words, the XQ201 gate acts as a quantum dot that can trap electrons, and a quantum bit (Qubit) is formed by trapping one electron inside it.

[0028] Figure 2B illustrates the concept of quantum computation using electromagnetic field irradiation. Qubit computation is controlled by irradiating it with a high-frequency RF signal, as shown in Figure 2B. A magnetic field B is applied to the Qubits in the array, and the precession frequency f S is set to 20.01 GHz for the selected bits and 20 GHz for the unselected bits. When an RF signal with a frequency of 20.01 GHz is irradiated to the entire array, the spin of only the selected bits, whose precession frequency matches the RF frequency, is rotated, allowing quantum operations to be performed.

[0029] Figure 3 is a perspective view showing a schematic example of a silicon quantum bit array structure. In a qubit array, quantum dots are arranged two-dimensionally in the X and Y directions as shown in Figure 3. The first layer of gate wiring in the MOS structure consists of quantum dot control gate lines (XQ) 2022 and interaction control gate lines (XJ) 2021 arranged in multiple rows in the X direction, and the second layer of gate wiring consists of quantum dot control gate lines (YQ) 2032 and interaction control gate lines (YJ) 2031 arranged in multiple rows in the Y direction. XQ 2022 and YQ 2032 control the voltage of the quantum dots (QD), and XJ 2021 and YJ 2031 control the voltage of the potential barrier (PB).

[0030] In this figure, for ease of viewing, the distance between the first layer of gate wiring and the silicon channel C is shown expanded in the Z direction. By adopting such an array structure, large-scale integration of quantum dots and Qubits is realized while suppressing an increase in the total number of wirings. For example, Patent Document 1 discloses a technology using such Qubits.

[0031] This will be explained in detail using the circuit diagram of the Qubit array QBA shown in Figure 4. In this circuit diagram, an initialization region 402 and a sense region 403 are arranged on either side of a central calculation region 401. The array has quantum dot control gate MOSs (gates connected to XQ or YQ) and interaction control gate MOSs (gates connected to XJ) arranged alternately. The silicon channels of the SOI structure are connected in the X direction, enabling electron movement and interaction between quantum dots via transfer gates. In addition, an interaction control gate MOS (gates connected to YJ) is arranged to connect the silicon channel in the Y direction, enabling electron movement and interaction in the Y direction as well.

[0032] The calculation area 401 has 128 MOS transistors used as quantum dots arranged in 8 rows x 16 columns. The initialization area 402 and sense area 403 also have 2 and 4 columns of MOS transistors for quantum dots, respectively. At the end of the array, one side of the silicon channel in both the X and Y directions is commonly connected to the reservoir terminal Nres, and the other side is separated as a DOE / DOS terminal. Although not shown as wiring, RF signal wiring RFQB is arranged on this array using multilayer wiring.

[0033] In this chip, the operations that target a single Qubit include spin rotation around the X axis (Rx) and spin rotation around the Y axis (Ry). These rotate the spin direction that holds the quantum information of the Qubit by 90 degrees around the X and Y axes of the Bloch sphere, respectively. As an example of control when performing Rx / Ry operations, control using a dynamic resonant frequency change method is shown in Figures 5A and 5B.

[0034] Figure 5A shows an array circuit diagram that extracts a portion of the calculation area 401 of the array circuit diagram in Figure 4. Figure 5B shows an example of the operating waveform when operating Qubit qd00 of the array circuit in Figure 5A. First, a static magnetic field is applied to the entire chip, setting the resonant frequency of the precession of the electron spins of all Qubits to 20 GHz.

[0035] When performing calculations, V is applied between terminals XJS1 and XJN1, and between terminals XJN2 and XJS2. L1 -V L2 A voltage of V is applied between terminals YJW0 and YJE0, and between terminals YJE1 and YJW1. L3 -V L4 A voltage of 1 mA is applied from YJW0 to YJE0 and from YJE1 to YJW1. The local magnetic field generated by this current causes the resonant frequency f of the spin precession of electrons in qd00. qd00 However, it increases from 20GHz in standby mode to 20.01GHz.

[0036] In this state, a 20.01 GHz RF signal RFQB is applied to the entire chip with a period of Rabi oscillation t RB If the RF signal is applied for only a quarter of the time, only the electron spins in the qd00 region with the same resonant frequency can be selectively rotated by 90°. If the phase of the RF signal is matched to the phase of the spin precession, rotation around the X axis occurs, and if the phase is shifted by 90°, rotation around the Y axis occurs.

[0037] Finally, the voltages applied between terminals XJN1 and XJS1, between XJN2 and XJS2, between YJW0 and YJE0, and between YJW1 and YJE1 are reversed, and f qd00 After setting the frequency to 19.99 GHz, the system waits for the same period of time to compensate for the phase change of the spin precession. A conventional spin readout method is described in Patent Document 2.

[0038] Figure 6 is a circuit diagram of the spin-charge conversion unit that constitutes part of the sense region 403 in the array circuit diagram of Figure 4. The principle of spin-charge conversion will be explained in a system in which quantum dots qd0, qd1, and qd2 shown in Figure 6 are connected to a single-electron transistor (SET) that serves as a charge sensor. Taking quantum dot qd0 as an example, the energy level of the quantum dot is controlled by electrode XQr0, and the level of the barrier between quantum dot qd1 and the quantum dot is controlled by electrode XJr1.

[0039] The method for converting spin information into charge will be described using the potential diagram of the spin-charge converter shown in Figure 7. Figure 7 shows the quantum dots qd0, qd1, and qd2 shown in Figure 6 and the b-barriers XJr1, XJr2, and XJr3 that are controlled by wiring.

[0040] In Step 0, one electron with spin up is placed in quantum dot qd2, and the target electron whose spin direction is to be read is placed in quantum dot qd0. If the target electron's spin is up (Case 1), in Step 1 the barrier voltage XJr1 is lowered to place the target electron's quantum bit in quantum dot qd1. The potential of quantum dot qd1 is then increased, but because quantum dot qd2 contains an electron with spin up, the Pauli spin blockade effect prevents the electron in qd1 from tunneling to qd2. Therefore, in Step 2 the number of electrons in quantum dot qd2 is maintained at one.

[0041] On the other hand, if the spin of the electron in quantum dot qd0 is downward (Case 2), in Step 1, the barrier voltage XJr1 is lowered to insert a quantum bit into quantum dot qd1, and the potential of quantum dot qd1 is then increased.Since quantum dot qd2 contains electrons with downward spins, the spin blockade effect does not work, and the electron in qd1 can tunnel to qd2.Therefore, in Step 2, the number of electrons in quantum dot qd2 becomes two.

[0042] The conventional readout method is shown in Figure 8. The drain current I of the single electron transistor SET DWhen there is one electron and two electrons in the quantum dot qd2, these become I1 and I2, respectively. In this case, we assume that I2 > I1. The SET current output terminal INT is connected to the positive input of the differential amplifier, and the output terminal of the reference current IREF is connected to the negative input of the differential amplifier. IREF is set to be (I2 + I1) / 2. Since the input terminals of the differential amplifier have parasitic capacitance, a voltage difference is created between the input terminals by precharging the positive and negative input terminals to the same potential and then passing the SET current and reference current for a certain period of time. This is amplified by the differential amplifier, and the readout result is determined.

[0043] In Case 1, when the spin of qd0 is upward, there is one electron in qd2, so the SET current is I1 and smaller than the reference current, so the positive input connected to the INT pin has a higher voltage than the negative input, and the read result is "H". In Case 2, when the spin of qd0 is downward, there are two electrons in qd2, so the SET current is I2 and larger than the reference current, so the positive input connected to the INT pin has a lower voltage than the negative input, and the read result is "L".

[0044] In this case, I2 and I1 are very small currents, ranging from nanoamperes to microamperes, making it difficult to create a reference current. Also, because the generated signal is single-ended, it is difficult to cancel out noise that is carried on the signal.

[0045] Therefore, when detecting the number of electrons corresponding to the spin direction of one electron, it is important to eliminate the need to generate a reference current, increase the signal amount, and provide a readout method that is robust against external noise.

[0046] Figure 9 is a schematic diagram illustrating the principle of the embodiment. A specific explanation will be given using the spin-charge conversion scheme shown in Figure 9. The circuit diagram of the spin-charge conversion unit is the same as Figure 6. The quantum dots (qd) that hold the quantum bits can be constructed using MISFETs (electrostatic effect transistors) through semiconductor processes.

[0047] In Step 0, an electron with an upward spin is placed in the quantum dot qd2. Assume that the quantum dot qd0 contains an electron whose spin direction is to be read out.

[0048] Similar to the operation in Figure 7, in Step 1, an electron in qd0 is moved to qd1. In Step 2, a predetermined voltage is applied to the quantum dot and barrier, utilizing Pauli spin blockade to create a state in which electrons do not tunnel to qd2 when the electron in qd1 has an up-spin, but do tunnel to qd2 when the electron in qd1 has a down-spin. As a result, in Case 1, where the spin of the initial electron in qd0 is up, the number of electrons in qd1 and qd2 is one each. In Case 2, where the spin of the initial electron in qd0 is down, the number of electrons in qd1 and qd2 is zero and two, respectively.

[0049] Then, in Step 3, one new electron is supplied from the quantum dot to the left of quantum dot qd0 and added to qd1. As shown in Step 4, in Case 1 the number of electrons in qd1 and qd2 becomes 2 and 1, respectively, while in Case 2 they become 1 and 2. In the operations from Step 3 onwards, the spin symbol is omitted in order to treat the electron as a classical charge regardless of its spin direction.

[0050] In this example, the potential barrier between the quantum dots qd1 and qd2 can be switched between two types: one that uses the quantum mechanical Pauli exclusion principle to move electrons, and one that uses classical charge manipulation to move electrons while maintaining the number of electrons. Either a voltage that causes Pauli spin blockade or a voltage that causes classical charge manipulation can be applied to the gate electrode of the barrier transistor located between the quantum bit transistors.

[0051] The spin readout method of the embodiment is shown in Figure 10. The drain current I DA, I DB are determined by the number of electrons in the quantum dots qd1 and qd2, and are I1 and I2 when there is one and two electrons in the quantum dots, respectively. As mentioned above, in Case 1, the number of electrons in the quantum dots qd1 and qd2 is two and one, respectively, so (I DA, I DB) = (I2, I1). On the other hand, in Case 2, the number of electrons in the quantum dots qd1 and qd2 is 1 and 2, respectively, so (I DA, I DB )=(I1,I2), where we assume that I2 > I1.

[0052] The current output terminal INB of SET-A and the current output terminal INT of SET-B are connected to the negative and positive inputs of the differential amplifier, respectively. Because the input terminals of the differential amplifier have parasitic capacitance, the positive and negative input terminals are precharged to the same potential, and then current is passed through SET-A and SET-B for a certain period of time, creating a voltage difference between the input terminals. This is amplified by the differential amplifier, and the readout result is determined.

[0053] For case 1, I DA > I DB The voltage of INB is drawn out earlier than INT, and INB < INT, so the result of the differential amplifier is "H". On the other hand, in case 2, I DA < I DB Since INB > INT, the judgment result is "L".

[0054] At this time, I2 and I1 are extremely small currents, ranging from nanoamperes to microamperes, making them generally difficult to detect. However, in this example, complementary signals are created, making it possible to double the signal volume to I2 -I1 compared to conventional methods. Furthermore, a differential signal is generated, enabling differential readout, which makes it possible to cancel common-mode external noise that rides on the signal. This eliminates the need to generate a reference current when detecting the number of electrons corresponding to the spin direction of one electron, increasing the signal volume and providing a readout method that is robust against external noise.

[0055] Figure 11 shows the control sequence during spin-charge conversion in detail. (a) shows the circuit diagram, and (b) shows the potential diagram for electrons over time. Time progresses vertically on the potential diagram. Figure 12 shows the voltage waveforms applied to each gate terminal. Time progresses horizontally, corresponding to the timing of the potential diagram in Figure 11.

[0056] At time=0, the potential of each quantum dot is at a low level (high level VH in terms of gate voltage), and the barrier potential is fixed at a high level (low level VL in terms of gate voltage). A single electron with an up spin is placed in quantum dot qd2, controlled by gate electrode XQr2. The quantum bit (spin up or down) that is the result of the calculation is placed in quantum dot qd0, controlled by gate electrode XQr0. One electron is also placed in the quantum dot controlled by gate electrode XQ16.

[0057] At times 1, 2, and 3, the barrier and dot potentials are controlled as shown in Figure 11, and electrons in qd0 are moved to qd1 by shuttling. At time 4, a predetermined voltage is applied to gates XJr1, XQr1, XJr2, XQr2, and XJr3, causing Pauli spin blockade. As a result, at time 5, one or two electrons remain in qd2, and one or zero electrons remain in qd1. From this point on, electrons are treated as classical charges, so the spin direction is omitted.

[0058] At time = 6-8, one electron is added to qd1, leaving two or one electron. The electron in qd2 is then moved to qd3 by shuttling. At time = 9-14, the electron in qd3 is moved to qd4, and the electron in qd1 is moved to qd3. The number of electrons in qd3 and qd4 can be converted into a SET current and read out using the method shown in Figure 10.

[0059] An example of the arrangement of quantum dots and sense amplifiers in the calculation / shuttle region and spin-charge conversion region is shown in Figure 13. In the calculation / shuttle region CSA, each quantum dot (qd) is coupled by a silicon channel (CHX) in the X direction of the figure, and a single electron in the quantum dot (qd) can be moved in the X direction by shuttling.

[0060] A spin-charge conversion region S / E is provided above each channel CHX, and quantum dots qd1 and qd2 (spin blockade control region SB) that perform the spin blockade described in Figure 11 and quantum dots qd3 and qd4 (charge storage region CS) that store the charge resulting from the conversion are arranged in this region. In this example, these are arranged in four rows, and a sense amplifier SA is placed below them. The sense amplifier SA is equipped with a single-electron transistor (SET) that outputs a current proportional to the number of electrons in the quantum dots qd3 and qd4, and a differential amplifier that receives the output.

[0061] The quantum bit array consists of the calculation / shuttle region CSA and the spin-charge conversion region S / E. In this array, the control signal is commonly connected to all four rows, so the spin-charge conversion operation by the spin blockade operation region SB shown in Figure 11 can be performed simultaneously on all four rows. The converted charge information is then determined by the sense amplifier SA, starting from the bottom row. At this time, the quantum dots qd3 and qd4 in each row are connected by a vertical silicon channel CHY, and by shuttling in the Y direction, the charge can be transferred to the sense amplifier 133.

[0062] The quantum dots qd1 and qd2 are electrically connected or capacitively coupled to two SETs in the sense amplifier 133 via silicon channels CHX and CHY, respectively, allowing for the generation of drain currents from the SETs corresponding to the number of electrons present in the channels of the quantum dots qd1 and qd2. In this embodiment, electrons present in the channels of the quantum dots qd1 and qd2 are transferred to and stored in the quantum dots qd3 and qd4, which are capacitively coupled to two SETs. The difference in drain currents between the two SETs, which corresponds to the number of electrons, is detected by a differential amplifier, allowing the spin state of the quantum bit representing the calculation result in the quantum dot qd0 to be determined.

[0063] FIG. 14 shows a circuit diagram of a sense amplifier SA that converts the minute amount of charge (equivalent to one or two electrons) that has been read out into a current and senses it, and FIGS. 15A and 15B show operation waveforms.

[0064] In Figure 14, the calculated charge is transferred by shuttling from quantum dots qd3 and qd4 in Figure 13 in the Y direction, passes through terminals RDSB and RDST, and is moved to and held at quantum dots qd5 and qd6, whose gates in the preamplifier block are controlled by YQr1.

[0065] As shown in FIG. 15A, YJr2 and YQr2 are set to bias voltages VB5 and VB6, respectively, and YJr3 is activated to VH. The RDOT and RDOB terminals are held at a bias voltage VBA. In this state, in the single-electron transistors (SET-A and SET-B) whose gates are connected to YQr2B and YQr2T, the currents IDA and IDB flowing from the RDOB and RDOT terminals to VSSA are modulated by the number of electrons in qd5 and qd6 due to the Coulomb interaction between SET-A and SET-B and the quantum dots qd5 and qd6. With the gate voltage of SET set to VB6, when there is one electron in qd5 and qd6, the current is I1, and when there are two electrons, the current is I2.

[0066] In this read method, in case 1, (IDA, IDB)=(I2, I1), and in case 2, (IDA, IDB)=(I1, I2).

[0067] Assuming that I2>I1 as shown in the current-voltage characteristics of FIG. 15B, the magnitude relationship between IDA and IDB is read out by a differential amplifier at the subsequent stage.

[0068] The input terminals INT and INB of the differential amplifier are precharged to voltage VPA from node NPA. After deactivating the precharge, the potential of INT and INB is discharged for a certain period of time using the signal current output from the RDOT and RDOB terminals, and the current difference is converted to a voltage difference, which is then compared by a voltage comparator consisting of a differential amplifier and a cross-coupled latch. In case 1, the calculation result is determined to be "H", and in case 2, it is determined to be "L". The cross-coupled latch is activated when SAE is VCC, and at the same time as the voltage comparison, the calculation result is output from the output terminal EXRT to the CAC chip. When SAE is VSS, the output terminal is fixed to VSS.

[0069] Figure 13 shows an example in which four rows of a Qubit array share one sense amplifier, and the spin-to-charge conversion results of the calculation are stored in the two quantum dots on the right. Since the sense amplifier is located at the bottom of the array, after reading out the calculation results of the bottom row of the array, the electrons are sequentially transferred to the bottom of the array, and the sense operation is performed four times.

[0070] Figure 16 shows the charge transfer in the Y direction due to shuttling. (a) is a circuit diagram, and (b) shows the potential of each quantum dot. This figure shows only the circuit on the RDOB side of the circuit in Figure 14, but the calculation results are transmitted in the same way on the RDOT side.

[0071] At Time 0, charges q0 to q3 resulting from spin-charge conversion are accumulated in the quantum dots controlled by gates YQ0 to YQ3. From Time 1 to Time 4, the potential of the YQ gate and the barrier YJ gate is controlled as shown in the figure, and charge q3 is shuttled to the quantum dot controlled by gate YQr1. At Time 5, a current corresponding to q3 flows from RDOB to VSSA in SET-A, and the calculation result is read out by the differential amplifier. After charge q3 is cleared to VSSA at Time 6, the next charge to be read out, q2, is shuttled to the quantum dot controlled by YQr1 at times 7-8. This operation is repeated sequentially, and charges q2 to q0 can be read out by SET-A.

[0072] FIG. 17A shows a second example of the arrangement of quantum dots qd and sense amplifiers SA in the calculation / shuttle area CSA and the spin-charge conversion area S / E.

[0073] Figure 17B shows a circuit diagram of the quantum dots qd and sense amplifiers (preamplifier PA and main amplifier MA) in the calculation / shuttle region CSA and spin-charge conversion region S / E of the second example. In the calculation / shuttle region CSA, each quantum dot qd is connected by a silicon channel in the X direction of the figure, allowing single electrons in the quantum dot to be moved by shuttling. A spin-charge conversion region S / E is provided above each channel, and quantum dots qd1 and qd2, which perform spin blockade as described in Figure 11, and quantum dots qd3 and qd4, which store the charge resulting from the conversion, are located there.

[0074] In this embodiment, one sense amplifier SA is placed in each row of the calculation and shuttling area CSA. Quantum dots qd3 and qd4, which store the charge after spin-charge conversion to be input to the differential amplifier, and SET-A and SET-B, which convert the result into current, are arranged in the Y direction. This method has the advantage of shortening the readout time because there is no need to shuttling electrons in the Y direction during readout.

[0075] By applying the quantum bit array circuit or quantum bit readout method described in Example 1 or Example 2 to the quantum computer system described in FIG. 1, it is possible to eliminate the need to generate a reference current when reading out the quantum operation result, increase the signal amount, and enable readout that is robust against external noise.

[0076] According to the above embodiment, an efficient quantum computer can be realized, which consumes less energy, reduces carbon emissions, prevents global warming, and contributes to the realization of a sustainable society.

[0077] CDC Digital control chip CAC Cryogenic control chip QBA Qubit array chip PB Potential barrier S Electron spin C Silicon channel XJ, XJN, XJS, YJ, YJW, YJE Interaction control gate XQ, XQN, XQS, YQ, YQE, YQW Quantum dot control gate f S spin precession frequency f RF、 f MW RF signal frequency t RFRF signal application time V L1 , V L2 , V B0 , V B1 Bias voltage t RB Rabi oscillation period SET single electron transistor Nres reservoir

Claims

1. A quantum bit array circuit comprising: a quantum bit array section and a sense amplifier section; the quantum bit array section comprises a spin-charge conversion section having a first quantum bit transistor and a second quantum bit transistor for reading out a quantum bit state, and a third quantum bit transistor for supplying electrons to the first quantum bit transistor; the sense amplifier section comprises first and second output transistors for outputting a current according to the number of electrons; the first quantum bit transistor and the second quantum bit transistor are connected via an electron transfer path; the first quantum bit transistor and the second quantum bit transistor are electrically connected or capacitively coupled to the first output transistor and the second output transistor, respectively; and a barrier transistor having a gate electrode for applying a voltage for performing Pauli spin blockade and a voltage for performing classical charge manipulation between the first quantum bit transistor and the second quantum bit transistor.

2. The quantum bit array circuit of claim 1, wherein the first quantum bit transistor is a first MISFET, the second quantum bit transistor is a second MISFET, and the third quantum bit transistor is a third MISFET; the first output transistor is a first SET, and the second output transistor is a second SET; the first MISFET is capacitively coupled to the first SET, and when the number of electrons present in the channel of the first MISFET is one or two, the drain current of the first SET takes first and second values, respectively; the second MISFET is capacitively coupled to the second SET, and when the number of electrons present in the channel of the second MISFET is one or two, the drain current of the second SET takes first and second values, respectively; and the quantum bit array circuit of claim 1, wherein the spin state of the electrons initially in the first MISFET is determined using a difference between the drain currents of the first SET and the second SET.

3. The quantum bit array circuit according to claim 2, wherein the quantum bit array section includes an operation area for performing quantum operations, and the spin state of the electrons in the first MISFIT in the initial state corresponds to a quantum bit that indicates the operation result of the operation area.

4. The quantum bit array circuit according to claim 3, wherein the quantum bit array section includes a channel in a first direction and a channel in a second direction, and quantum dots are arranged in a two-dimensional array, the spin-charge conversion section is arranged at an end of the quantum bit array section in the first direction, the spin-charge conversion section has third and fourth MISFETs provided at intersections of the channel in the first direction and the channel in the second direction, and sense amplifiers are arranged at ends in the second direction of a plurality of spin-charge conversion sections arranged in the second direction.

5. The quantum bit array circuit of claim 4, wherein the sense amplifier comprises a differential amplifier, a first input of the differential amplifier is connected to the drain of the first SET, and a second input of the differential amplifier is connected to the drain of the second SET.

6. The quantum bit array circuit of claim 1, wherein a voltage change applied to the gate electrode of the second quantum bit transistor and the gate electrode of the barrier transistor when performing Pauli spin blockade between the first quantum bit transistor and the second quantum bit transistor is smaller than a voltage change when performing classical charge manipulation.

7. The quantum bit array circuit according to claim 3, wherein the quantum bit array section has a channel in a first direction and a channel in a second direction, quantum dots are arranged in a two-dimensional array, the spin-charge conversion section is arranged at an end in the first direction of the operation area, and one sense amplifier is arranged at the end in the first direction for one row of quantum bits of the operation area.

8. A quantum computer comprising: a semiconductor device constituting the quantum bit array circuit according to claim 1; an analog control device that controls said semiconductor device; a digital control device that controls said analog control device; and a refrigerator that cools said semiconductor device.

9. A quantum bit readout method for reading out the spin state of an electron in a quantum bit array circuit having a quantum bit array section and a sense amplifier section, comprising: a first step of arranging a gate electrode in the quantum bit array section; storing an electron to be read out in a first quantum dot in the quantum bit array section, and storing an electron having a predetermined ground state in a second quantum dot adjacent to the first quantum dot; a second step of applying a predetermined voltage to the gate electrode to apply a predetermined potential to the quantum bit array section such that the electron to be read out tunnels into the second quantum dot only when the electron to be read out is in a first ground state; a third step of applying a predetermined voltage to the gate electrode to store one additional electron in the first quantum dot; and a fourth step of reading out the spin state of the electron to be read out by differentially reading out the number of electrons in the first quantum dot and the second quantum dot using the sense amplifier section.

10. The quantum bit readout method according to claim 9, wherein in the second step, a voltage capable of maintaining the spin state of electrons and causing the Pauli spin blockade effect to appear is applied to the gate electrode.

11. The method for reading a quantum bit according to claim 9, further comprising, after the third step, a transfer step of transferring electrons in the first quantum dot to a third quantum dot and transferring electrons in the second quantum dot to a fourth quantum dot, wherein the third quantum dot is capacitively coupled to a first SET of the sense amplifier unit, and the drain current of the first SET varies depending on the number of electrons in the third quantum dot, and the fourth quantum dot is capacitively coupled to a second SET of the sense amplifier unit, and the drain current of the second SET varies depending on the number of electrons in the fourth quantum dot.

12. The method for reading a quantum bit according to claim 11, wherein the transfer step results in either a state in which the third quantum dot has one electron and the fourth quantum dot has two electrons, or a state in which the third quantum dot has two electrons and the fourth quantum dot has one electron.

13. A method for reading out a quantum bit as set forth in claim 12, wherein in the quantum bit array section, quantum bits can be arranged as a two-dimensional array having a first direction and a second direction; any quantum operation is performed in an operation area of ​​the quantum bit array section; quantum bits having quantum operation results in the operation area are moved in the first direction and transferred to a spin-charge conversion section that executes the first step through the third step; and the quantum operation results converted into charges in the spin-charge conversion section are moved in the second direction in the transfer step and transferred to the third and fourth quantum dots.

14. A method for reading out a quantum bit as described in claim 12, wherein in the quantum bit array section, quantum bits can be arranged as a two-dimensional array having a first direction and a second direction; any quantum operation is performed in an operation area of ​​the quantum bit array section; quantum bits having quantum operation results in the operation area are moved in the first direction and transferred to a spin-charge conversion section that executes the first step through the third step; and the quantum operation results converted into charges in the spin-charge conversion section are moved in the first direction in the transfer step and transferred to the third and fourth quantum dots.

15. The method of reading a quantum bit according to claim 12, wherein the sense amplifier unit has a differential amplifier, a voltage corresponding to the drain current of the first SET is generated at a first input of the differential amplifier, and a voltage corresponding to the drain current of the second SET is generated at a second input of the differential amplifier.

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