device

Abstract

A device having an electrode and a signal application element for applying an electric signal to the electrode, the device (10) being provided, to reduce the need to add a wiring for an inspection purpose, with: a plurality of electrodes (E(i,j)), a plurality of signal application elements (TR(i,j)) for applying an electric signal to each of the plurality of electrodes, and at least one wiring (DL(i)) to which a signal for driving the plurality of signal application elements is applied. The at least one wiring has at least one capacitive coupling unit (C(i,j)) that is capacitively coupled with any one of the plurality of electrodes.

Description

Device

[0001] The present disclosure relates to a device having an electrode and a signal-applying element for applying an electrical signal to the electrode.

[0002] A technique for detecting defective substrates before the formation of self-luminous elements is known (see Patent Document 1). In this technique, a test electrode that is capacitively coupled to the element electrode of the self-luminous elements is added to the substrate of the display device. The test electrode is connected to a test power supply terminal and a voltage is applied. As a result, an electric charge is retained between the element electrode and the test electrode. By measuring the amount of this electric charge, defective substrates can be detected.

[0003] Japanese Patent Application Publication No. 2003-228299

[0004] However, the above-mentioned technique requires additional test electrodes for testing, and therefore additional wiring for applying voltages to the test electrodes. In particular, when a display device has a large number of pixels, a large number of additional wirings are required. The additional wirings complicate the device configuration and, ultimately, the device manufacturing process.

[0005] An aspect of the present disclosure aims to reduce the need for additional wiring for testing in a device having electrodes and signal application elements that apply electrical signals to the electrodes.

[0006] In order to solve the above problem, an apparatus according to one aspect of the present disclosure comprises a plurality of electrodes, a plurality of signal application elements that apply electrical signals to each of the plurality of electrodes, and at least one wiring to which a signal for driving the plurality of signal application elements is applied, wherein the at least one wiring has at least one capacitive coupling portion that is capacitively coupled to one of the plurality of electrodes.

[0007] According to one aspect of the present disclosure, in a device having an electrode and a signal application element that applies an electrical signal to the electrode, the need for additional wiring for testing can be reduced.

[0008] FIG. 1 is a schematic diagram illustrating an example of a device according to embodiment 1 of the present disclosure. FIG. 2 is a cross-sectional view illustrating an example of a cross-sectional state of the device according to embodiment 1 of the present disclosure. FIG. 3 is a timing chart illustrating an example of a temporal change in a signal for inspecting the device according to embodiment 1 of the present disclosure. FIG. 4 is a flowchart illustrating an example of an inspection procedure for inspecting the device according to embodiment 1 of the present disclosure. FIG. 5 is a schematic diagram illustrating a device according to a comparative example. FIG. 6 is a cross-sectional view illustrating a cross-sectional state of the device according to the comparative example. FIG. 7 is a schematic diagram illustrating an example of a device according to embodiment 2 of the present disclosure. FIG. 8 is a timing chart illustrating an example of a temporal change in a signal for inspecting the device according to embodiment 2 of the present disclosure. FIG. 9 is a flowchart illustrating an example of an inspection procedure for inspecting the device according to embodiment 3 of the present disclosure. FIG. 10 is a circuit diagram illustrating an example of a pixel circuit.

[0009] [Embodiment 1] One embodiment of the present disclosure will be described in detail below. Fig. 1 is a schematic diagram illustrating an example of an apparatus 10 according to embodiment 1 of the present disclosure. XYZ coordinates representing the X direction, Y direction, and Z direction are shown on the diagram.

[0010] Fig. 2 is a cross-sectional view illustrating an example of a cross-sectional state of the device 10 according to the first embodiment of the present disclosure. Fig. 2 illustrates the device 10 cut along line A-A in Fig. 1. As illustrated in Fig. 2, the device 10 may have a substrate SUB1 and layers LY1 and LY2, and may be in a state before the substrate SUB2 is attached. This means that, for example, a light-emitting layer of a light-emitting element (for example, an organic light-emitting diode (OLED)) has not yet been formed.

[0011] 1, the device 10 is, for example, a display device. As shown in FIG. 1, the device 10 includes a plurality of pixels P(i, j), a plurality of pixel electrodes E(i, j), a plurality of transistors TR(i, j), a plurality of data lines DL(i), a plurality of gate lines GL(j), a driving and inspection unit 20, and a gate driving unit 31.

[0012] A plurality of pixels P(i,j) are arranged in a matrix in the X and Y directions. A pixel electrode E(i,j) and a transistor TR(i,j) are arranged in each of the plurality of pixels P(i,j). The pixel electrode E(i,j) functions as an electrode E(i,j).

[0013] The transistor TR(i,j) functions as a signal application element that applies an electric signal to the pixel electrode E(i,j) (electrode). The transistor TR(i,j) (signal application element) has a gate terminal, a source terminal, and a drain terminal. The data line DL(i) (wiring) is connected to the source terminal of the transistor TR(i,j), and the gate line GL(j) (second-type wiring) is connected to the gate terminal of the transistor TR(i,j). The pixel electrode E(i,j) is connected to the drain terminal of the transistor TR(i,j).

[0014] The data line DL(i) functions as at least one wiring to which a signal (data signal) for driving the transistor TR(i,j) (signal application element) is applied. The multiple data lines DL(i) (at least one wiring) have at least one capacitive coupling portion C(i,j) that is capacitively coupled to one of the multiple pixel electrodes E(i,j) (electrodes).

[0015] 2, the pixel electrodes E(i,j) (electrodes) are flat electrodes, and the capacitive coupling portions C(i,j) are closely opposed to the flat electrodes C(i,j) in the Z-axis direction. This close proximity means, for example, that the distance between the pixel electrodes E(i,j) and the capacitive coupling portions C(i,j) is in the range of 1.0 to 10.0 μm (for example, 2.5 to 3.5 μm).

[0016] The data line DL(i-1) (at least one wiring) has a portion DLa (wiring body) extending in the Y-axis direction (first direction), and the capacitive coupling portion C(i,j) has a portion DLb extending in a direction (here, the X-axis direction) different from the Y-axis direction (first direction). The capacitive coupling portion C(i,j) shown in Figures 1 and 2 has two portions DLb and a portion DLc extending in the Y-axis direction (first direction).

[0017] The plurality of data lines DL(i) (at least one wiring) includes (1) a data line DL(i) (first wiring) and (2) a data line DL(i-1) (second wiring). (1) A signal (data signal) for driving a transistor TR(i,j) (one signal application element) that applies an electrical signal to a pixel electrode E(i,j) (one electrode) is applied to the data line DL(i) (first wiring). (2) The data line DL(i-1) (second wiring) has one capacitive coupling portion C(i,j) that is capacitively coupled to the pixel electrode E(i,j) (one electrode).

[0018] The data line DL(i) (first wiring) and the data line DL(i-1) (second wiring) are adjacent to each other. That is, the multiple data lines DL(i) (at least one wiring) include a pair of adjacent data lines DL(i-1), DL(i) (a pair of wirings). Here, the set of data lines DL(i), DL(i-1), the set of data lines DL(i+1), DL(i), and the set of data lines DL(i+2), DL(i+1), etc. are adjacent to each other as the first wiring and the second wiring.

[0019] The multiple gate lines GL(j), together with the multiple data lines DL(i) (at least one wiring), function as at least one second-type wiring to which a signal (gate signal) for driving the multiple transistors TR(i, j) (multiple signal application elements) is applied.

[0020] The driving and testing unit 20 includes a signal supplying unit 21, a signal receiving unit 22, a switching control unit 23, and a switching unit SW(i).

[0021] The signal supply unit 21 supplies a test signal (first signal) to a plurality of data lines DL(i) (at least one wiring). The signal receiving unit 22 receives a confirmation signal (second signal) corresponding to the test signal (first signal) supplied from at least one capacitive coupling unit C(i,j) via a plurality of data lines DL(i-1) (at least one wiring). The test signal from the signal supply unit 21 is applied to the transistor TR(i,j) via the data line DL(i). The transistor TR(i,j) injects charge into the pixel electrode E(i,j) in response to the test signal. A confirmation signal corresponding to the injection of charge into the pixel electrode E(i,j) is generated in the capacitive coupling unit C(i,j). The signal receiving unit 22 receives the confirmation signal from the capacitive coupling unit C(i,j) via the data line DL(i-1).

[0022] The switching unit SW(i) switches the connection between the signal supply unit 21 and the signal receiving unit 22 for a plurality of data lines DL(i) (at least one wiring).

[0023] The switching control unit 23 controls the switching unit SW(i). The switching control unit 23 controls the switching unit SW(i) to connect the signal supply unit 21 to one of the pair of data lines DL(i-1), DL(i) (a pair of wirings) (data line DL(i) in FIG. 1), and to connect the signal receiving unit 22 to the other of the pair of data lines DL(i-1), DL(i) (a pair of wirings) (data line DL(i-1) in FIG. 1).

[0024] The signal supply unit 21 is connected to the data line DL(i) via a data buffer DB(i), and the signal reception unit 22 is connected to the data line DL(i) via a sensing buffer SB(i).

[0025] The gate driving unit 31 functions as a selection signal supplying unit and supplies a gate signal (selection signal) to the gate line GL(j) to select a transistor TR(i,j) to be driven from a plurality of transistors TR(i,j) (signal application elements).

[0026] 3 is a timing chart showing an example of temporal changes in signals for testing the device according to the first embodiment of the present disclosure. As shown by M1 in FIG. 3 , the test signal (first signal) for the data lines DL(i) and DL(i+2) changes in signal intensity within a predetermined period (here, 1H period (1 horizontal period)). As shown by M2 in FIG. 3 , the signal intensity of the original data signal is almost constant within about 1H period. By changing the intensity of the test signal (first signal) over time, the intensity of the verification signal also changes over time. As a result, by comparing the waveforms of the test signal and the verification signal, it is possible to easily determine whether the transistor TR(i, j) or the like is good or bad.

[0027] As shown in Figure 3, when the gate signal for gate line GL(j) is in the H state, the following results (1) and (2) are obtained. Note that the dashed lines in Figure 3 represent the confirmation signal W2 that did not appear. (1) The confirmation signal W2(i-1,j) for data line DL(i-1) corresponds to the inspection signal W1(i,j) for data line DL(i). (2) The confirmation signal W2(i+1,j) for data line DL(i+1) corresponds to the inspection signal W1(i+2,j) for data line DL(i+2).

[0028] At this time, it can be determined from result (1) that the transistor TR(i, j) operates normally, and from result (2) that the transistor TR(i+2, j) operates normally.

[0029] 3, when the gate signal of gate line GL(j+1) is in the H state, the following results (1) and (2) are obtained: (1) The verification signal W2(i-1, j+1) of data line DL(i-1) does not correspond to the inspection signal W1(i, j+1) of data line DL(i). (2) The verification signal W2(i+1, j+1) of data line DL(i+1) does not correspond to the inspection signal W1(i+2, j+1) of data line DL(i+2).

[0030] At this time, it can be determined from result (1) that transistor TR(i, j+1) is not operating normally, and from result (2) that transistor TR(i+2, j+1) is not operating normally.

[0031] In this way, the quality of the transistor TR(i,j) can be determined based on the correspondence between the inspection signal W1(i,j) on the data line DL(i) and the confirmation signal W2(i-1,j) on the data line DL(i-1).

[0032] Fig. 4 is a flowchart showing an example of an inspection procedure for inspecting the device according to the first embodiment of the present disclosure. This flowchart corresponds to the timing chart of Fig. 3. Hereinafter, the example of the inspection procedure will be described with reference to Fig. 4.

[0033] (1) Connecting the signal supply unit 21 and the signal receiving unit 22 to the data line DL(i) (Step S11) As shown in FIG. 1, the switching control unit 23 controls the switching unit SW(i) to connect the signal supply unit 21 to every other data line DL(i), DL(i+2), etc., and to connect the signal receiving unit 22 to the remaining data lines DL(i-1), DL(i+1), etc.

[0034] (2) Selection of Gate Line GL(j) (Step S12) The gate driver 31 selects the gate line GL(j) and supplies a gate signal to it. The gate signal is, for example, a substantially constant signal within a 1H period, as shown in FIG.

[0035] (3) Supplying Inspection Signal and Receiving Confirmation Signal (Step S13) In response to the supply of the gate signal to this gate line GL(j), the signal supply unit 21 supplies an inspection signal W1 to the data line DL(i), etc. As shown in Fig. 3, inspection signals W1(i,j), W1(i+2,j), W1(i+4,j)... are supplied to the data lines DL(i), DL(i+2), DL(i+4),... respectively.

[0036] Meanwhile, in response to the supply of the inspection signal W to the data line DL(i), the signal receiving unit 22 receives a confirmation signal W2 from the data line DL(i-1), etc. As shown in Fig. 3, confirmation signals W2(i-1,j), W2(i+1,j), W2(i+3,j)... are received from the data lines DL(i-1), DL(i+1), DL(i+3)..., respectively.

[0037] If the transistor TR(i,j) and the like operate normally, a charge is injected from the transistor TR(i,j) into the pixel electrode E(i,j). As a result of this injection, the signal receiving unit 22 receives a confirmation signal corresponding to the inspection signal via the capacitive coupling unit C(i,j) that is capacitively coupled to the pixel electrode E(i,j) and the data line DL(i-1).

[0038] On the other hand, if the transistor TR(i, j) or the like does not operate normally, the confirmation signal received by the signal receiving unit 22 will be difficult to correspond to the inspection signal, and for example, it will be difficult to find a change in waveform corresponding to the inspection signal.

[0039] As already mentioned, in FIG. 3, it can be determined that the transistors TR(i,j) and TR(i+2,j) are within the normal range from the confirmation signal W2(i-1,j) of the data line DL(i-1) and the confirmation signal W2(i+1,j) of the data line DL(i+1).

[0040] (4) Scanning gate line GL(j) (step S14) Another gate line GL(j) is selected and a gate signal is supplied. In FIG. 3, gate line GL(j+1) is in the H state. In this manner, with gate line GL(j+1) selected, an inspection signal is supplied and a confirmation signal is received. As a result, the state (normal or abnormal) of transistor TR(i, j+1) and the like can be determined.

[0041] As already mentioned, in FIG. 3, it can be determined that the transistors TR(i, j+1) and TR(i+2, j+1) are not within the normal range from the confirmation signal W2(i-1, j+1) of the data line DL(i-1) and the confirmation signal W2(i+1, j+1) of the data line DL(i+1).

[0042] In this manner, the gate line GL(j), gate line GL(j+1), GL(j+2), ... are selected in order, and the inspection signal is supplied and the confirmation signal is received. This process continues until all gate lines GL have been selected (step S15).

[0043] (5) Switching the Connection of the Signal Supply Unit 21 and the Signal Receiving Unit 22 to the Data Line DL(i) (Step S16) From the state in step S11, the connection of the signal supply unit 21 and the signal receiving unit 22 to the data line DL(i) is switched. That is, the signal supply unit 21 is connected to every other data line DL(i-1), DL(i+1), DL(i+3), ..., and the signal receiving unit 22 is connected to the remaining every other data line DL(i), DL(i+2), DL(i+4), ....

[0044] After this switching, steps S12 to S15 are repeated, so that the entire transistor TR(i, j) is inspected.

[0045] As described above, the device according to this embodiment comprises a plurality of electrodes, a plurality of signal application elements that apply electrical signals to each of the plurality of electrodes, and at least one wiring to which a signal for driving the plurality of signal application elements is applied, and the at least one wiring has at least one capacitive coupling portion that is capacitively coupled to one of the plurality of electrodes.

[0046] This makes it possible to test signal application elements (e.g., transistors TR(i, j)) that apply electrical signals to each electrode (e.g., pixel electrodes E(i, j)) without adding wiring for testing within the device.

[0047] 5 is a schematic diagram illustrating an example of the device 10 according to a comparative example of the present disclosure, in which XYZ coordinates representing the X, Y, and Z directions are shown.

[0048] Fig. 6 is a cross-sectional view showing an example of the cross-sectional state of the device 10 according to the comparative example of the present disclosure. Fig. 6 shows the device 10 cut along line B-B in Fig. 5. As shown in Fig. 6, the device 10 may have a substrate SUB1 and layers LY1 and LY2, and may be in a state before the substrate SUB2 is attached.

[0049] 5 and 6, in the device 10 according to the comparative example, the data line DL(i) does not have a capacitive coupling portion C(i,j). As a result, it is necessary to add the capacitive coupling portion C(i,j) and an inspection wiring connected to the capacitive coupling portion C(i,j).

[0050] [Embodiment 2] Another embodiment of the present disclosure will be described below. For ease of explanation, components having the same functions as those described in the above embodiment will be denoted by the same reference numerals, and their description will not be repeated. Figure 7 is a schematic diagram illustrating an example of an apparatus 10 according to embodiment 2 of the present disclosure. XYZ coordinates representing the X, Y, and Z directions are shown on the diagram.

[0051] 2, the device 10 according to the second embodiment of the present disclosure may have the substrate SUB1 and layers LY1 and LY2, and may be in a state before the substrate SUB2 is attached, similar to the first embodiment. This means that, for example, a light-emitting layer of a light-emitting element (for example, an organic light-emitting diode (OLED)) has not been formed.

[0052] 7 , the device 10 includes a plurality of pixels P(i,j), a plurality of pixel electrodes E(i,j), a plurality of transistors TR(i,j), a plurality of data lines DL(i), a plurality of gate lines GL(j), a gate driver 31, a signal supplier 32, and a signal receiver 33.

[0053] The transistor TR(i,j) functions as a signal application element that applies an electrical signal to the pixel electrode E(i,j) (electrode). The transistor TR(i,j) (signal application element) has a gate terminal, a source terminal, and a drain terminal. The gate line GL(j) (wiring) is connected to the gate terminal of the transistor TR(i,j), and the data line DL(i) (second type wiring) is connected to the source terminal of the transistor TR(i,j). The pixel electrode E(i,j) is connected to the drain terminal of the transistor TR(i,j).

[0054] Here, the capacitive coupling portion C(i, j) is arranged on the gate line GL(j+1). That is, the plurality of gate lines GL(j+1) (at least one wiring) has at least one capacitive coupling portion C(i, j) that is capacitively coupled to one of the plurality of pixel electrodes E(i, j) (electrodes). The gate line GL(j) functions as at least one wiring to which a signal (gate signal) for driving the transistor TR(i, j) (signal application element) is applied.

[0055] As in the first embodiment, the pixel electrodes E(i, j) (electrodes) are flat electrodes, and the capacitive coupling portions C(i, j) are closely opposed to the flat electrodes C(i, j) in the Z-axis direction. This close proximity means, for example, that the distance between the pixel electrodes E(i, j) and the capacitive coupling portions C(i, j) is in the range of 1.0 to 10.0 μm (for example, 2.5 to 3.5 μm).

[0056] The gate line GL(j) (at least one wiring) has a portion GLa (wiring body) extending in the X-axis direction (first direction), and the capacitive coupling portion C(i,j) has a portion GLb extending in a direction (here, the Y-axis direction) different from the X-axis direction (first direction). The capacitive coupling portion C(i,j) has two portions GLb and a portion GLc extending in the X-axis direction (first direction).

[0057] The plurality of gate lines GL(j) (at least one line) includes (1) gate line GL(j) (first line) and (2) gate line GL(j+1) (second line). (1) A signal (gate signal) for driving a transistor TR(i,j) (one signal application element) that applies an electrical signal to a pixel electrode E(i,j) (one electrode) is applied to the gate line GL(j) (first line). (2) The gate line GL(j+1) (second line) has one capacitive coupling portion C(i,j) that is capacitively coupled to the pixel electrode E(i,j) (one electrode).

[0058] The gate line GL(j) (first wiring) and the gate line GL(j+1) (second wiring) are adjacent to each other. That is, the plurality of gate lines GL(j) (at least one wiring) includes a pair of adjacent gate lines GL(j) and GL(j+1) (a pair of wirings). Here, the set of gate lines GL(j) and GL(j+1), the set of gate lines GL(j+1) and GL(j+2), and the set of gate lines GL(j+2) and GL(j+3), etc., are adjacent to each other as the first wiring and the second wiring.

[0059] The multiple data lines DL(i), together with the multiple gate lines GL(j) (at least one wiring), function as at least one second-type wiring to which a signal (data signal) for driving the multiple transistors TR(i, j) (multiple signal application elements) is applied.

[0060] The signal supply unit 32 supplies a test signal (first signal) to a plurality of data lines DL(i) (at least one second-type wiring). The signal reception unit 33 receives a confirmation signal (second signal) corresponding to the test signal (first signal) supplied from at least one capacitive coupling unit C(i, j) via a plurality of gate lines GL(j+1) (at least one wiring).

[0061] The gate driver 31 functions as a selection signal supplier, and supplies a gate signal (selection signal) to one (e.g., gate line GL(j)) of a pair of gate lines GL(j), GL(j+1) (a pair of wirings), which selects a transistor TR(i,j) to be driven from among a plurality of transistors TR(i,j) (signal application elements). The signal receiver 33 receives a confirmation signal (second signal) from the other (e.g., gate line GL(j+1)) of the pair of gate lines GL(j), GL(j+1) (a pair of wirings).

[0062] A test signal from the signal supply unit 32 is applied to the transistor TR(i,j) via the data line DL(i). The transistor TR(i,j) injects charge into the pixel electrode E(i,j) in response to the test signal. The capacitive coupling unit C(i,j) generates a confirmation signal corresponding to the charge injection into the pixel electrode E(i,j). The signal receiving unit 33 receives the confirmation signal from the capacitive coupling unit C(i,j) via the gate line GL(j+1).

[0063] 8 is a timing chart showing an example of temporal changes in signals for testing the device according to the second embodiment of the present disclosure. The signal supply unit 32 sequentially selects the data lines DL(i), DL(i+1), etc., and supplies the test signal. The test signal (first signal) has a signal intensity that changes within a predetermined period (here, 1H period * (1 / n), where n is an integer equal to or greater than 2, e.g., the number of data lines DL(i)). Here, multiple data lines DL(i) (e.g., all data lines) are selected within the 1H period, and the test signal (first signal) is supplied. As a result, the quality of multiple transistors TR(i, j) can be determined within the 1H period.

[0064] The supply of gate signals to the gate lines GL(j), GL(j+2)... by the gate driver 31 and the reception of confirmation signals from the gate lines GL(j+1), GL(j+3)... by the signal receiver 33 are alternately performed in a 1H cycle. At this time, gate signals may be simultaneously supplied to every other pair of gate lines GL(j), GL(j+2)..., and confirmation signals may be simultaneously received from every other pair of gate lines GL(j+1), GL(j+3)....

[0065] Assume that the gate driver 31 supplies a gate signal to the gate line GL(j), and the signal receiver 33 receives a verification signal from the gate line GL(j+1). At this time, as shown in FIG. 8 , the verification signal for the gate line GL(j+1) includes waveforms W2(i,j), W2(i+1,j), W2(i+2,j), ..., W2(i+k,j) corresponding to the transistors TR(i,j), TR(i+1,j), TR(i+2,j), ..., TR(i+k,j). By acquiring multiple waveforms W2(i,j+1), ..., W2(i+k,j+1) within a 1H period, it is possible to test multiple transistors TR(i,j), ..., TR(i+k,j).

[0066] 8, the confirmation signal for gate line GL(j+2) includes waveforms W2(i,j+1)...W2(i+k,j+1) corresponding to transistors TR(i,j+1)...TR(i+k,j+1). Since the waveform W2(i+k,j+2) corresponding to transistor TR(i+k,j+1) is not found in this confirmation signal, it is considered that transistor TR(i+k,j+1) is not operating normally.

[0067] Fig. 9 is a flowchart showing an example of an inspection procedure for inspecting an apparatus according to the second embodiment of the present disclosure. This flowchart corresponds to the timing chart of Fig. 8. Hereinafter, the example of the inspection procedure will be described with reference to Fig. 9.

[0068] (1) Selection of Every Other Gate Line GL(j) (Step S21) The gate driver 31 selects every other gate line GL(j), GL(j+2), GL(j+4), ... and supplies a gate signal to each of them. The gate signal is, for example, a signal that is approximately constant over a 1H period. As shown in FIG. 8 , during the first 1H period, a signal that is approximately constant over a 1H period is supplied to the gate lines GL(j), GL(j+2), GL(j+4), ....

[0069] (2) Supplying a Test Signal and Receiving a Confirmation Signal (Step S22) The signal supplying unit 32 selects a data line DL(i) and supplies a test signal to it. At this time, as shown in FIG. 8 , the signal supplying unit 32 may sequentially select a plurality of (e.g., all) data lines DL(i), DL(i+1), ... within a 1H period and supply the test signal to them.

[0070] Meanwhile, the signal receiving unit 33 receives confirmation signals from every other gate line GL(j+1), GL(j+3), GL(j+5), and so on that were not selected in step S21. FIG. 8 shows the confirmation signal from gate line GL(j+1). This confirmation signal includes waveforms W2(i,j+1)...W2(i+k,j+1) corresponding to the test signals of data lines DL(i)...DL(i+k), respectively. Waveforms W2(i,j+1)...W2(i+k,j+1) correspond to transistors TR(i,j)...TR(i+k,j), respectively.

[0071] As a result, transistors TR(i,j)...TR(i+k,j), TR(i,j+2)...TR(i+k,j+2), TR(i,j+4)...TR(i+k,j+4),... can be inspected within a 1H period.

[0072] (3) Selection of Remaining Gate Lines GL(j) (Steps S23, S24) The gate driver 31 selects every other remaining gate line GL(j+1), GL(j+3), GL(j+5), ..., and supplies gate signals to them. As shown in Fig. 8, in the second 1H period, a substantially constant signal is supplied to the gate lines GL(j+1), GL(j+3), GL(j+5), ... during the 1H period.

[0073] 8, the signal supply unit 32 may sequentially select a plurality of (e.g., all) data lines DL(i), DL(i+1), ... during the second 1H period and supply the test signal thereto.

[0074] 8, the verification signal from the gate line GL(j) includes waveforms W2(i,j)...W2(i+k,j) corresponding to the inspection signals of the data lines DL(i)...DL(i+k), respectively. The waveforms W2(i,j)...W2(i+k,j) correspond to the transistors TR(i,j-1)...TR(i+k,j-1), respectively.

[0075] The verification signal from gate line GL(j+2) includes waveforms W2(i,j+2)...W2(i+k,j+2) corresponding to the inspection signals of data lines DL(i)...DL(i+k), respectively. Waveforms W2(i,j+2)...W2(i+k,j+2) correspond to transistors TR(i,j+1)...TR(i+k,j+1), respectively.

[0076] In this manner, the remaining transistors TR(i, j-1)...TR(i+k, j-1), TR(i, j+1)...TR(i+k, j+1), TR(i, j+3)...TR(i+k, j+3),... are inspected, and as a result, the entire transistor TR(i, j) is inspected.

[0077] As described above, the device according to this embodiment comprises a plurality of electrodes, a plurality of signal application elements that apply electrical signals to each of the plurality of electrodes, and at least one wiring to which a signal for driving the plurality of signal application elements is applied, and the at least one wiring has at least one capacitive coupling portion that is capacitively coupled to one of the plurality of electrodes.

[0078] This makes it possible to test signal application elements (e.g., transistors TR(i, j)) that apply electrical signals to each electrode (e.g., pixel electrodes E(i, j)) without adding wiring for testing within the device.

[0079] [Embodiment 3] The device 10 according to embodiment 3 has the same hardware configuration as the device 10 according to embodiment 2. Therefore, a schematic diagram showing the device 10 according to embodiment 3 will be omitted.

[0080] In the third embodiment, similarly to the second embodiment, the plurality of gate lines GL(j) (at least one wiring) includes a plurality of wirings, and the gate driver 31 functions as a selection signal supply unit.

[0081] In the third embodiment, the gate driving unit 31 sequentially selects one wiring from the plurality of wirings and supplies a gate signal (selection signal) for selecting the transistor TR(i,j) to be driven from the plurality of transistors TR(i,j) (signal application elements). The signal receiving unit 33 receives a confirmation signal (second signal) from a wiring (gate line GL(j+1)) adjacent to the first wiring (gate line GL(j)).

[0082] 10 is a flowchart showing an example of an inspection procedure for inspecting an apparatus according to the third embodiment of the present disclosure. Hereinafter, an example of the inspection procedure according to the third embodiment will be described with reference to FIG.

[0083] (1) Selection of Gate Line GL(j) (Step S31) The gate driver 31 selects the gate line GL(j) and supplies a gate signal to it.

[0084] (2) Supplying an inspection signal to the data line DL(i) and receiving a confirmation signal from the gate line GL(j+1) (Step S32) The signal supply unit 32 selects the data line DL(i) and supplies the inspection signal. At this time, the signal supply unit 32 may sequentially select multiple (e.g., all) signal supply units 32 within a 1H period and supply the inspection signal to them.

[0085] The signal receiving unit 33 receives a confirmation signal from the gate line GL(j+1) adjacent to the gate line GL(j) selected in step S31.

[0086] As a result, the transistors TR(i,j) . . . TR(i+k,j) can be inspected within a 1H period.

[0087] (3) Selection of the Next Gate Line GL(j+1) (Step S34) The next gate line GL(j+1) is selected, and then step S32 is executed. That is, the signal supply unit 32 supplies an inspection signal to the data line DL(i), and the signal reception unit 33 receives a confirmation signal from the gate line GL(j+2) adjacent to the gate line DL(i+1).

[0088] As a result, the transistors TR(i, j+1) . . . TR(i+k, j+1) can be inspected within a 1H period.

[0089] As described above, steps S32 and S34 are repeated (step S33) until all gate lines GL(j) are selected (step S33), thereby enabling a complete inspection of the transistors TR(i,j).

[0090] [Modification] In the above, the transistor TR(i,j) is used as the signal application element. However, it is also possible to use an element other than the transistor TR(i,j) or a circuit combining a plurality of elements as the signal application element. For example, a pixel circuit P(i,j) may be used as the signal application element.

[0091] 11 is a circuit diagram showing an example of a pixel circuit P(i,j). This pixel circuit P(i,j) can be used in place of the transistor TR(i,j) in FIG.

[0092] In this pixel circuit P(i,j), the electrode E(i,j) is arranged where the light-emitting portion AL(i,j) would normally be arranged, taking into consideration the possibility that the light-emitting portion AL(i,j) may not be formed in the device 10 at the inspection stage.

[0093] As in the first embodiment, if the data line DL(i) has at least one capacitive coupling portion C(i,j) that capacitively couples with the electrode E(i,j), it becomes possible to supply a test signal from the data line DL(i) to the pixel circuit P(i,j) and receive a confirmation signal from the capacitive coupling portion C(i,j). As a result, it becomes possible to test the pixel circuit P(i,j) without substantially increasing the amount of wiring.

[0094] Here, charges are injected into the electrode E(i,j) from the transistors TR5, TR4, and TR6 of the pixel circuit P(i,j). At this time, the transistor TR4 is driven by the charge accumulated in the capacitor Cst via the data line DL. In this case, the signal on the data line DL does not directly drive the transistor TR4, but the signal applied to the data line DL can be said to be a signal for driving the signal application element (the pixel circuit P(i,j), in particular, the transistor TR4).

[0095] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0096] 10 Device 20 Inspection unit 21, 32 Signal supply unit 22, 33 Signal reception unit 23 Switching control unit 31 Gate driving unit

Claims

1. A device comprising: a plurality of electrodes; a plurality of signal application elements that apply electrical signals to each of the plurality of electrodes; and at least one wiring to which a signal for driving the plurality of signal application elements is applied, wherein the at least one wiring has at least one capacitive coupling portion that is capacitively coupled to any of the plurality of electrodes.

2. The device according to claim 1, wherein the plurality of electrodes are flat electrodes, and the capacitive coupling portion faces the flat electrodes in close proximity.

3. The device according to claim 1 or 2, wherein the at least one wiring has a portion extending in a first direction, and the capacitive coupling portion has a portion extending in a direction different from the first direction.

4. The device according to any one of claims 1 to 3, wherein the at least one wiring includes: a first wiring to which a signal for driving one signal application element that applies an electrical signal to one electrode is applied; and a second wiring having one capacitive coupling portion that capacitively couples with the one electrode.

5. The device of claim 4, wherein the first wiring and the second wiring are adjacent to each other.

6. The device according to any one of claims 1 to 5, further comprising at least one second type wiring to which a signal for driving the plurality of signal applying elements is applied together with the at least one wiring.

7. The device according to claim 6, comprising: a signal supplying section that supplies a first signal to the at least one wiring; and a signal receiving section that receives a second signal that is supplied from the at least one capacitive coupling section via the at least one wiring and corresponds to the first signal.

8. The device according to claim 7, further comprising a switching unit that switches the connection between the signal supply unit and the signal receiving unit for the at least one wiring.

9. The device according to claim 8, wherein the at least one wiring includes a pair of adjacent wirings, and further comprising a switching control unit that controls the switching unit, and the switching control unit controls the switching unit to connect the signal supply unit to one of the pair of wirings and to connect the signal receiving unit to the other of the pair of wirings.

10. The device according to any one of claims 7 to 9, wherein the plurality of signal application elements have gate terminals and source terminals, the wiring is connected to the source terminals, and the second type of wiring is connected to the gate terminals.

11. The device according to claim 6, further comprising: a signal supplying section that supplies a first signal to said at least one second type wiring; and a signal receiving section that receives a second signal that is supplied from said at least one capacitive coupling section via said at least one wiring and corresponds to said first signal.

12. The device according to claim 11, wherein the at least one wiring includes a pair of adjacent wirings, the device comprises a selection signal supplying section that supplies a selection signal to one of the pair of wirings to select a signal application element to be driven from the plurality of signal application elements, and the signal receiving section receives the second signal from the other of the pair of wirings.

13. The device according to claim 11, wherein the at least one wiring includes a plurality of wirings, the device comprises a selection signal supplying section that sequentially selects one wiring from the plurality of wirings and supplies a selection signal that selects a signal application element to be driven from the plurality of signal application elements, and the signal receiving section receives the second signal from a wiring adjacent to the one wiring.

14. The device according to any one of claims 11 to 13, wherein the plurality of signal application elements have gate terminals and source terminals, the wiring is connected to the gate terminals, and the second type of wiring is connected to the source terminals.

15. The device according to any one of claims 7 to 14, wherein the first signal has a signal strength that changes within a predetermined period of time.

16. The device according to any one of claims 1 to 15, wherein the device is a display device.

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