Semiconductor device

Abstract

According to the present invention, damage to a semiconductor chip due to loads in a manufacturing process is prevented.　This semiconductor device includes: wiring pins (34a, 35a) and wiring pins (34b, 35b) which are respectively inserted into first and second wiring holes and which have lower ends that are electrically connected to first and second electrodes, respectively, via a bonding material; and an electrically conductive wiring member (36a). The wiring member (36a) includes: a spacer portion which includes an upper end surface that is joined to an opposing surface of a wiring board at the periphery of a third wiring hole and a lower end surface that is joined to an upper surface of an electrically conductive circuit pattern member of an insulating circuit board (10), and which maintains a prescribed spacing between the opposing surface and the upper surface of the electrically conductive circuit pattern member (13c); and a connecting portion which is formed within the upper end surface of the spacer portion and which is inserted into the third wiring hole. The lower end surface of the wiring member (36a) is joined to the electrically conductive circuit pattern member (13c) in a region of the insulating circuit board (10) between a semiconductor chip (33a1) and a semiconductor chip (33b1).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor device is equipped with various electronic components, such as a semiconductor chip that performs a switching operation and a control circuit that controls the switching operation of the semiconductor chip.

[0003] There are also semiconductor devices that include an insulating circuit board and a printed circuit board. For example, a semiconductor device has been proposed in which the printed circuit board is disposed opposite the insulating circuit board with a spacer portion sandwiched between the front surface of the insulating circuit board, and a pressing portion is disposed on the front surface of the printed circuit board, on the spacer portion with the printed circuit board sandwiched between them (see, for example, Patent Document 1).

[0004] Also, a power semiconductor module has been proposed that includes a housing that houses a semiconductor chip and at least one control pin or guide pin that protrudes outward from the top surface of the housing (see, for example, Patent Document 2).

[0005] International Publication No. 2022 / 244392 Japanese Patent Application Laid-Open No. 2018-195714

[0006] An object of the present invention is to provide a semiconductor device that can prevent damage to a semiconductor chip due to a load during the manufacturing process.

[0007] According to one aspect of the invention, there is provided an insulating circuit board having a conductive circuit pattern member formed on an upper surface thereof, first and second semiconductor chips each having first and second electrodes on their upper surfaces and disposed on the insulating circuit board, a wiring board having an opposing surface facing the upper surface of the insulating circuit board, first to third wiring holes formed in the opposing surface, the first and second wiring holes facing the first and second electrodes, respectively, first and second wiring pins inserted into the first and second wiring holes, respectively, and having lower ends electrically connected to the first and second electrodes via a bonding material, and A semiconductor device is provided, comprising: a conductive wiring member having an upper end surface joined around a third wiring hole and a lower end surface joined to the upper surface of the conductive circuit pattern member of the insulating circuit board, the conductive wiring member having a spacer portion that maintains a predetermined distance between the opposing surface and the upper surface of the conductive circuit pattern member, and a connecting portion formed within the upper end surface of the spacer portion and inserted into the third wiring hole, wherein the lower end surface of the wiring member is joined to the conductive circuit pattern member in a region between the first semiconductor chip and the second semiconductor chip on the insulating circuit board.

[0008] The insulating circuit board may have a rectangular shape in a planar view, the first and second semiconductor chips may be arranged opposite each other across a first center line of the insulating circuit board in a planar view, and the wiring members may be arranged in multiple numbers along the first center line on the conductive circuit pattern member.

[0009] The wiring members may further be arranged in plurality on the conductive circuit pattern member along a second center line that is perpendicular to the first center line in a plan view of the insulating circuit board.

[0010] The conductive circuit pattern member may include a first conductive circuit pattern member extending along the first center line, and a second conductive circuit pattern member and a third conductive circuit pattern member arranged opposite each other across the first conductive circuit pattern member, the first semiconductor chip may be arranged on the second conductive circuit pattern member, the second semiconductor chip may be arranged on the third conductive circuit pattern member, and multiple wiring members may be arranged on the first conductive circuit pattern member along the first center line.

[0011] The conductive circuit pattern member may include a fourth conductive circuit pattern member having a plurality of third semiconductor chips arranged on its upper surface, and a conductive wiring pattern member may be formed on the wiring board, and a current path may be formed between the plurality of third semiconductor chips and the first conductive circuit pattern member, passing through the conductive wiring pattern member and the plurality of wiring members arranged on the first conductive circuit pattern member.

[0012] The connection portion of the wiring member may be pillar-shaped, and the spacer portion of the wiring member may be pillar-shaped and thicker than the connection portion.

[0013] The insulating circuit board may have a rectangular shape in a plan view, the conductive circuit pattern member may include a fifth conductive circuit pattern member having the first semiconductor chip disposed on its upper surface, and a sixth conductive circuit pattern member having the second semiconductor chip disposed on its upper surface, and the wiring members may be arranged in multiple numbers along the boundary line in an edge region of the sixth conductive circuit pattern member that faces the fifth conductive circuit pattern member.

[0014] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0015] The disclosed technique can prevent damage to semiconductor chips due to loads during the manufacturing process. The above and other objects, features, and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, which illustrate preferred embodiments of the present invention by way of example.

[0016] FIG. 1 is a perspective view showing the appearance of a semiconductor device according to an embodiment; FIG. 2 is a side view of a semiconductor module with a sealing member removed; FIG. 3 is a plan view of an insulating circuit board; FIG. 4 is a plan view showing an example of a conductive wiring pattern member formed on a wiring board; FIG. 5 is a diagram showing an example of a circuit configuration of an inverter circuit; FIG. 6 is a perspective view showing the shape of a wiring member; FIG. 7 is a cross-sectional view showing an enlarged mounting region of a wiring pin and a wiring member; FIG. 8 is a diagram showing a comparative example regarding bonding of a wiring pin; FIG. 9 is a flowchart showing a manufacturing process of a semiconductor device; FIG. 10 is a diagram showing a modified example in which a portion of a conductive circuit pattern member of an insulating circuit board is modified; and FIG. 11 is a diagram showing a modified example of the shape of a wiring member.

[0017] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the X-Y plane facing upward (+Z direction) in the semiconductor device shown in the drawings. Similarly, "top" refers to the upward (+Z direction) direction in the semiconductor device shown in the drawings. The terms "back surface" and "bottom surface" refer to the X-Y plane facing downward (-Z direction) in the semiconductor device shown in the drawings. Similarly, the term "bottom" refers to the downward (-Z direction) direction in the semiconductor device shown in the drawings. Similar orientations will be used in other drawings as necessary. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily refer to the vertical direction relative to the ground. In other words, the "top" and "bottom" directions are not limited to the direction of gravity.

[0018] 1 is a perspective view showing the appearance of a semiconductor device according to an embodiment. The semiconductor device 1 includes a semiconductor module 2 and a cooler 3. The semiconductor module 2 and the cooler 3 are bonded together by a bonding material 4.

[0019] The semiconductor module 2 includes a sealing member 5 that seals the insulating circuit board 10 and wiring board 20, which will be described later. The sealing member 5 is molded by a transfer method and seals not only the area between the opposing insulating circuit board 10 and wiring board 20, but also at least the side areas (±X direction and ±Y direction) of the insulating circuit board 10 and wiring board 20 and the top surface area of ​​the wiring board 20. A thermosetting resin is used as the sealing material for the sealing member 5. The thermosetting resin is, for example, an epoxy resin.

[0020] The semiconductor module 2 also includes flat external connection terminals 31a to 31d. The outer ends of the external connection terminals 31a to 31c protrude from the side surface of the sealing member 5 on the +X direction side to form connection terminal portions for connection with an external circuit. Meanwhile, the inner ends of the external connection terminals 31a to 31c are connected to the insulating circuit board 10 inside the sealing member 5. The outer end of the external connection terminal 31d protrudes from the side surface of the sealing member 5 on the −X direction side to form connection terminal portions for connection with an external circuit. Meanwhile, the inner end of the external connection terminal 31d is connected to the insulating circuit board 10 inside the sealing member 5. As will be described later, an inverter circuit is formed inside the semiconductor module 2, and the external connection terminals 31a and 31b correspond to the P terminal of the inverter circuit, the external connection terminal 31c corresponds to the N terminal of the inverter circuit, and the external connection terminal 31d corresponds to the O (Out) terminal for outputting the inverter circuit.

[0021] Furthermore, the semiconductor module 2 includes external connection terminals 32a to 32g. The external connection terminals 32a to 32g are generally columnar and extend in the vertical direction (±Z direction), with their lower ends (inner ends) connected to the wiring board 20 inside the sealing member 5 and their upper ends (outer ends) protruding from the upper surface of the sealing member 5 to serve as connection terminals for connection to an external circuit. The external connection terminals 32a and 32b correspond to gate control terminals of the inverter circuit, the external connection terminals 32c and 32d correspond to auxiliary source terminals of the inverter circuit, and the external connection terminals 32e to 32g correspond to sense signal terminals.

[0022] The cooler 3 has a cooling surface on its upper surface on which the semiconductor module 2 is placed. The bonding material 4 bonds the lower surface of the semiconductor module 2 (more specifically, the lower surface of the metal plate 12 described below) to the cooling surface of the cooler 3. In this way, the bonding material 4 fixes the semiconductor module 2 and the cooler 3 together, and also thermally connects the metal plate 12 of the semiconductor module 2 to the cooler 3.

[0023] The bonding material 4 may be, for example, a brazing material or a thermal interface material. The brazing material may be primarily composed of at least one of a tin alloy, an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy. The thermal interface material may be, for example, an elastomer sheet, an RTV (Room Temperature Vulcanization) rubber, a gel, an adhesive containing a phase change material, or a silicone mixed with ceramics.

[0024] Although not shown, a refrigerant circulates inside the cooler 3, and an inlet and an outlet for the refrigerant are provided on the side or bottom of the cooler 3.

[0025] Fig. 2 is a side view of the semiconductor module with the sealing member removed. Fig. 3 is a plan view of the insulating circuit board. Note that Fig. 2 is a side view of the semiconductor module 2 when viewed in the -Y direction. For ease of explanation, Fig. 3 also shows a state in which wiring pins and wiring members are bonded to the semiconductor chip and conductive circuit pattern member, respectively, on the insulating circuit board 10. In reality, the wiring pins and wiring members are inserted into wiring holes formed in the wiring board 20, and then the lower ends of the wiring pins and wiring members are bonded to the semiconductor chip and conductive circuit pattern member, respectively, on the insulating circuit board 10.

[0026] The semiconductor module 2 includes an insulating circuit board 10 and a wiring board 20. Both the insulating circuit board 10 and the wiring board 20 are rectangular in plan view. The wiring board 20 is disposed with its lower surface facing the upper surface of the insulating circuit board 10 at a predetermined distance (distance D1, described later) from the upper surface of the insulating circuit board 10.

[0027] The insulating circuit board 10 includes an insulating plate 11, a metal plate 12 bonded to the lower surface of the insulating plate 11, and conductive circuit pattern members 13a to 13e formed on the upper surface of the insulating plate 11. The insulating plate 11 and the metal plate 12 are rectangular in plan view. The corners of the insulating plate 11 and the metal plate 12 may be round-chamfered or C-chamfered.

[0028] The insulating plate 11 is made of a material that has insulating properties and excellent thermal conductivity. Such an insulating plate 11 may be made of ceramics or insulating resin. Examples of ceramics include aluminum oxide, aluminum nitride, silicon nitride, and silicon nitride. Examples of insulating resins include paper phenol substrates, paper epoxy substrates, glass composite substrates, and glass epoxy substrates.

[0029] The metal plate 12 is primarily composed of a metal with excellent thermal conductivity. Such a material may be, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, to improve corrosion resistance, the surface of the metal plate 12 may be plated. In this case, the plating material may contain at least one of nickel and tin. The lower surface of the metal plate 12 is also the lower surface of the insulating circuit board 10 and is exposed from the lower surface of the sealing member 5. The lower surface of the metal plate 12 is joined to the cooling surface of the upper surface of the cooler 3 via the joining material 4.

[0030] The conductive circuit pattern members 13a-13e are formed from a copper-containing metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The conductive circuit pattern members 13a-13e are formed on the upper surface of the insulating plate 11 as follows: A metal plate is formed on the upper surface of the insulating plate 11, and the metal plate is then subjected to a process such as etching to obtain the conductive circuit pattern members 13a-13e in a predetermined shape. Alternatively, the conductive circuit pattern members 13a-13e may be pre-cut from a metal plate and then pressure-bonded to the upper surface of the insulating plate 11.

[0031] The conductive circuit pattern member 13a (second conductive circuit pattern member) is electrically connected to the external connection terminal 31a. The external connection terminal 31a is flat, and the lower surface of the −X direction end of the external connection terminal 31a is joined to the upper surface of the +X direction end of the conductive circuit pattern member 13a. Meanwhile, the +X direction end of the external connection terminal 31a protrudes from the sealing member 5 and serves as a connection terminal portion for connection to an external circuit.

[0032] The conductive circuit pattern member 13b (third conductive circuit pattern member) is electrically connected to the external connection terminal 31b. The external connection terminal 31b is flat, and the lower surface of the -X direction end of the external connection terminal 31b is joined to the upper surface of the +X direction end of the conductive circuit pattern member 13b. Meanwhile, the +X direction end of the external connection terminal 31b protrudes from the sealing member 5 and serves as a connection terminal portion for connection to an external circuit. The external connection terminal 31b has the same potential as the external connection terminal 31a. Therefore, the conductive circuit pattern members 13a, 13b also have the same potential.

[0033] The conductive circuit pattern member 13c (first conductive circuit pattern member) is electrically connected to the external connection terminal 31c. The external connection terminal 31c is flat, and the lower surface of the −X direction end of the external connection terminal 31c is joined to the upper surface of the +X direction end of the conductive circuit pattern member 13c. Meanwhile, the +X direction end of the external connection terminal 31c protrudes from the sealing member 5 and serves as a connection terminal portion for connection to an external circuit.

[0034] The conductive circuit pattern member 13d (fourth conductive circuit pattern member) is electrically connected to the external connection terminal 31d. The external connection terminal 31d is flat, and the lower surface of the +X direction end of the external connection terminal 31d is joined to the upper surface of the −X direction end of the conductive circuit pattern member 13d. Meanwhile, the −X direction end of the external connection terminal 31d protrudes from the sealing member 5 and serves as a connection terminal portion for connection to an external circuit.

[0035] The external connection terminals 31a to 31d are formed of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. Furthermore, to improve corrosion resistance, the surfaces of the external connection terminals 31a to 31d may be plated. In this case, the plating material may contain at least one of nickel and tin.

[0036] Semiconductor chips 33a to 33d are mounted on the upper surface of the insulating circuit substrate 10. The semiconductor chips 33a to 33d may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) primarily composed of silicon carbide. Furthermore, these power MOSFETs may incorporate a body diode or SBD (Schottky Barrier Diode) functioning as an FWD (Free Wheeling Diode) within a single chip. Each of these semiconductor chips 33a to 33d includes, for example, an input electrode (drain electrode) as a main electrode on the lower surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the upper surface.

[0037] As described above, this embodiment illustrates a case in which the semiconductor chips 33a to 33d are power MOSFETs primarily composed of silicon carbide. However, as another example, the semiconductor chips 33a to 33d may include switching elements primarily composed of silicon. The switching elements may be, for example, reverse-conducting (RC)-IGBTs (insulated gate bipolar transistors). An RC-IGBT is a semiconductor element in which an IGBT and an FWD are configured in anti-parallel within a single chip. Such semiconductor chips 33a to 33d include, for example, an input electrode (collector electrode) as a main electrode on the bottom surface and an output electrode (emitter electrode) and a control electrode (gate electrode) as main electrodes on the top surface.

[0038] As another example, the semiconductor chips 33a to 33d may each include a pair of switching elements and diode elements made primarily of silicon. The switching elements are, for example, power MOSFETs or IGBTs. The semiconductor chip including the switching elements includes, for example, an input electrode (a drain electrode in a power MOSFET or a collector electrode in an IGBT) as a main electrode on its lower surface, and a gate electrode (a control electrode) and an output electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a main electrode on its upper surface. The diode elements include, for example, SBDs and PiN (P-intrinsic-N) diodes used as FWDs. The semiconductor chip including the diode elements includes, for example, an output electrode (cathode electrode) as a main electrode on its lower surface, and an input electrode (anode electrode) as a main electrode on its upper surface.

[0039] In addition, when each of the semiconductor chips 33a to 33d is a set of a switching element and a diode element, the conductive wiring pattern member of the wiring board 20 and the conductive circuit pattern member of the insulating circuit board 10, which will be described later, are made into pattern members so as to form an inverter circuit including the switching element and the diode element.

[0040] The semiconductor chip 33a is mounted on the upper surface of the conductive circuit pattern member 13a. Although not shown, the input electrodes on the lower surface of the semiconductor chip 33a are electrically connected to the upper surface of the conductive circuit pattern member 13a via solder. This electrically connects the input electrodes on the lower surface of the semiconductor chip 33a and the external connection terminals 31a via the conductive circuit pattern member 13a.

[0041] The semiconductor chip 33b is mounted on the upper surface of the conductive circuit pattern member 13b. Although not shown, the input electrodes on the lower surface of the semiconductor chip 33b are electrically connected to the upper surface of the conductive circuit pattern member 13b via solder. This electrically connects the input electrodes on the lower surface of the semiconductor chip 33b to the external connection terminals 31b via the conductive circuit pattern member 13b.

[0042] The semiconductor chips 33c and 33d are mounted on the upper surface of the conductive circuit pattern member 13d. Although not shown, the input electrodes on the lower surfaces of the semiconductor chips 33c and 33d are electrically connected to the upper surface of the conductive circuit pattern member 13d via solder. This electrically connects the input electrodes on the lower surfaces of the semiconductor chips 33c and 33d to the external connection terminals 31d via the conductive circuit pattern member 13d.

[0043] In this embodiment, four of each of the semiconductor chips 33a to 33d are provided on the insulating circuit board 10. An inverter circuit is configured by combining one of each of the semiconductor chips 33a to 33d.

[0044] Next, a configuration for electrically connecting the conductive circuit pattern members 13a to 13e and the semiconductor chips 33a to 33d on the insulating circuit board 10 to the conductive wiring pattern members formed on the wiring board 20 will be described.

[0045] The output electrodes formed on the upper surfaces of the semiconductor chips 33a to 33d are electrically connected to predetermined conductive wiring pattern members formed on the wiring substrate 20 via wiring pins 34a to 34d, respectively. In this embodiment, as an example, nine wiring pins are arranged for the input electrodes on the upper surfaces of the semiconductor chips 33a to 33d, respectively. Furthermore, the control electrodes formed on the upper surfaces of the semiconductor chips 33a to 33d are electrically connected to predetermined conductive wiring pattern members formed on the wiring substrate 20 via wiring pins 35a to 35d, respectively. The control electrodes may be provided in the center of one side of the upper surfaces of the semiconductor chips 33a to 33d.

[0046] These wiring pins 34a to 34d, 35a to 35d each have a cylindrical shape extending in the vertical direction (±Z direction) and are inserted into wiring holes (through holes) formed in the wiring substrate 20. The upper ends of the wiring pins 34a to 34d, 35a to 35d protrude from the upper surface of the wiring substrate 20. The lower ends of the wiring pins 34a to 34d are electrically connected to output electrodes on the upper surfaces of the semiconductor chips 33a to 33d via bonding material, and the lower ends of the wiring pins 35a to 35d are electrically connected to control electrodes on the upper surfaces of the semiconductor chips 33a to 33d via bonding material. Note that while the wiring pins 34a to 34d, 35a to 35d are shown here as being cylindrical, they may also be shaped like rectangular pillars, polygonal pillars, or star-shaped polygonal pillars, for example.

[0047] Furthermore, wiring members 36a to 36i are disposed on insulating circuit board 10. As will be described in detail below, wiring members 36a to 36i are formed from the same conductive material as wiring pins 34a to 34d and 35a to 35d, and include a cylindrical spacer portion 361 (see FIG. 6) and a connecting portion 362 (see FIG. 6) that is cylindrical and thinner than spacer portion 361 and protrudes above spacer portion 361. The connecting portion 362 of each of wiring members 36a to 36i is inserted into a wiring hole formed in wiring board 20.

[0048] The lower end surfaces of the wiring members 36a to 36c are bonded to the upper surface of the conductive circuit pattern member 13c. The lower end surfaces of the wiring members 36d to 36g are bonded to the upper surface of the conductive circuit pattern member 13d. The lower end surface of the wiring member 36h is bonded to the upper surface of the conductive circuit pattern member 13b. The lower end surface of the wiring member 36i is bonded to the upper surface of the conductive circuit pattern member 13e using a bonding material.

[0049] Conductive circuit pattern member 13c is formed in a region sandwiched between conductive circuit pattern members 13a and 13b, and has a shape extending along a first center line L1 in the ±Y directions of insulating circuit board 10. Wiring members 36a to 36c are arranged along first center line L1.

[0050] On the other hand, wiring members 36d-36g are arranged along a second center line L2 in the ±X directions of insulating circuit board 10. Furthermore, wiring members 36d-36g are arranged along boundary lines 13d1 and 13d2 in the edge region of conductive circuit pattern member 13d along boundary lines 13d1 and 13d2 that face conductive circuit pattern members 13a and 13b. Note that second center line L2 does not have to be exactly in the center of insulating circuit board 10 in the ±X directions, and may be a line near the center.

[0051] The wiring pins 34a to 34d, 35a to 35d and the wiring members 36a to 36i are formed from a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. Furthermore, to improve corrosion resistance, the surfaces of the wiring pins 34a to 34d, 35a to 35d and the wiring members 36a to 36i may be plated. In this case, the plating material may contain at least one of nickel and tin.

[0052] The bonding material used to bond the wiring pins 34a-34d, 35a-35d to the electrodes on the top surface of the semiconductor chip and the wiring members 36a-36i to the conductive circuit pattern members is, for example, solder. The solder components constituting the solder include lead-free solder primarily composed of a predetermined alloy. The predetermined alloy includes tin. Such alloys include, for example, at least one of an alloy consisting of tin-silver, an alloy consisting of tin-silver-copper, an alloy consisting of tin-zinc-bismuth, an alloy consisting of tin-copper, an alloy consisting of tin-silver-indium-bismuth, and an alloy consisting of tin-antimony. Furthermore, such solder components may include additives. Examples of additives include nickel, germanium, cobalt, and silicon. Therefore, the solder components include, for example, tin and at least one of silver, zinc, copper, bismuth, indium, and antimony.

[0053] A sintered body may be used to join the above-mentioned portions. When joining using a sintered body, the sintered material is, for example, a powder containing at least one of silver, iron, copper, aluminum, titanium, nickel, tungsten, and molybdenum.

[0054] Next, the wiring board 20 will be described. The wiring board 20 is, for example, a multilayer printed circuit board (PCB). In the wiring board 20, for example, a wiring layer may be formed on at least one of the upper and lower surfaces of an insulating layer, or multiple insulating layers may be stacked, with a wiring layer also formed on one of the adjacent insulating layers.

[0055] The insulating layer is formed of, for example, an insulating resin. Examples of insulating resins include a paper phenol substrate, a paper epoxy substrate, a glass composite substrate, a glass epoxy substrate, a Teflon (registered trademark) substrate, and a polyimide substrate. The wiring layer is formed of a metal with excellent conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these as a main component.

[0056] 4 is a plan view showing an example of a conductive wiring pattern member formed on a wiring substrate. Here, as an example, the wiring substrate 20 includes, from the top (+Z direction side), an upper insulating layer (not shown), an intermediate insulating layer 21, and a lower insulating layer (not shown). A first wiring layer is formed on the upper surface of the upper insulating layer, a second wiring layer is formed on the upper surface of the intermediate insulating layer 21, a third wiring layer is formed on the lower surface of the intermediate insulating layer, and a fourth wiring layer is formed on the lower surface of the lower insulating layer. As an example, FIG. 4 shows a conductive wiring pattern member of the second wiring layer formed on the upper surface of the intermediate insulating layer 21.

[0057] Conductive wiring pattern members 22a to 22c are formed on the upper surface of the intermediate insulating layer 21. The conductive wiring pattern members 22a to 22c are made of a metal containing copper and having excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these as a main component.

[0058] Furthermore, wiring holes 23a to 23d and 24a to 24d are formed in the wiring substrate 20, penetrating the wiring substrate 20 in the vertical direction (±Z direction).

[0059] Wiring hole 23a is formed at a position facing an output electrode provided on the upper surface of semiconductor chip 33a on insulating circuit board 10. Wiring pin 34a is inserted into wiring hole 23a, and the lower end of wiring pin 34a is electrically connected to the output electrode of semiconductor chip 33a via a bonding material. Wiring hole 24a is also formed at a position facing a control electrode provided on the upper surface of semiconductor chip 33a on insulating circuit board 10. Wiring pin 35a is inserted into wiring hole 24a, and the lower end of wiring pin 35a is electrically connected to the control electrode of semiconductor chip 33a via a bonding material.

[0060] The wiring hole 23a is electrically connected to the conductive wiring pattern member 22a of the intermediate insulating layer 21. This electrically connects the output electrode of the semiconductor chip 33a and the conductive wiring pattern member 22a. On the other hand, the wiring hole 24a is not electrically connected to any of the conductive wiring pattern members of the intermediate insulating layer 21. Although not shown, the wiring hole 24a is electrically connected to another wiring layer of the wiring board 20 (for example, the first wiring layer, which is the top layer), and is electrically connected to the external connection terminal 32a in this wiring layer.

[0061] Wiring hole 23b is formed at a position facing an output electrode provided on the upper surface of semiconductor chip 33b on insulating circuit board 10. Wiring pin 34b is inserted into wiring hole 23b, and the lower end of wiring pin 34b is electrically connected to the output electrode of semiconductor chip 33b via a bonding material. Wiring hole 24b is also formed at a position facing a control electrode provided on the upper surface of semiconductor chip 33b on insulating circuit board 10. Wiring pin 35b is inserted into wiring hole 24b, and the lower end of wiring pin 35b is electrically connected to the control electrode of semiconductor chip 33b via a bonding material.

[0062] The wiring hole 23b is electrically connected to the conductive wiring pattern member 22b of the intermediate insulating layer 21. This electrically connects the output electrode of the semiconductor chip 33b and the conductive wiring pattern member 22b. On the other hand, the wiring hole 24b is not electrically connected to any of the conductive wiring pattern members of the intermediate insulating layer 21. Although not shown, the wiring hole 24b is electrically connected to another wiring layer of the wiring board 20 (for example, the first wiring layer, which is the uppermost layer), and is electrically connected to the external connection terminal 32a in this wiring layer.

[0063] Wiring hole 23c is formed at a position facing an output electrode provided on the upper surface of semiconductor chip 33c on insulating circuit board 10. Wiring pin 34c is inserted into wiring hole 23c, and the lower end of wiring pin 34c is electrically connected to the output electrode of semiconductor chip 33c via a bonding material. Wiring hole 24c is also formed at a position facing a control electrode provided on the upper surface of semiconductor chip 33c on insulating circuit board 10. Wiring pin 35c is inserted into wiring hole 24c, and the lower end of wiring pin 35c is electrically connected to the control electrode of semiconductor chip 33c via a bonding material.

[0064] The wiring hole 23c is electrically connected to the conductive wiring pattern member 22c of the intermediate insulating layer 21. This electrically connects the output electrode of the semiconductor chip 33c and the conductive wiring pattern member 22c. On the other hand, the wiring hole 24c is not electrically connected to any of the conductive wiring pattern members of the intermediate insulating layer 21. Although not shown, the wiring hole 24c is electrically connected to another wiring layer of the wiring board 20 (for example, the first wiring layer, which is the uppermost layer), and is electrically connected to the external connection terminal 32b in this wiring layer.

[0065] Wiring hole 23d is formed at a position facing an output electrode provided on the upper surface of semiconductor chip 33d on insulating circuit board 10. Wiring pin 34d is inserted into wiring hole 23d, and the lower end of wiring pin 34d is electrically connected to the output electrode of semiconductor chip 33d via a bonding material. Wiring hole 24d is also formed at a position facing a control electrode provided on the upper surface of semiconductor chip 33d on insulating circuit board 10. Wiring pin 35d is inserted into wiring hole 24d, and the lower end of wiring pin 35d is electrically connected to the control electrode of semiconductor chip 33d via a bonding material.

[0066] The wiring hole 23d is electrically connected to the conductive wiring pattern member 22c of the intermediate insulating layer 21. This electrically connects the output electrode of the semiconductor chip 33d and the conductive wiring pattern member 22c. On the other hand, the wiring hole 24d is not electrically connected to any of the conductive circuit pattern members of the intermediate insulating layer 21. Although not shown, the wiring hole 24d is electrically connected to another wiring layer of the wiring board 20 (for example, the first wiring layer, which is the uppermost layer), and is electrically connected to the external connection terminal 32b in this wiring layer.

[0067] Furthermore, wiring holes 25a to 25i are formed in the wiring substrate 20, penetrating the wiring substrate 20 in the vertical direction (±Z direction).

[0068] The upper connection portions 362 (see FIG. 6) of the wiring members 36a to 36c are inserted into the wiring holes 25a to 25c, respectively. The wiring holes 25a to 25c are also electrically connected to the conductive wiring pattern member 22c of the intermediate insulating layer 21. As a result, the conductive wiring pattern member 22c is electrically connected to the conductive circuit pattern member 13c of the insulating circuit board 10 and the external connection terminal 31c via the wiring holes 25a to 25c.

[0069] The upper connection portions 362 (see FIG. 6 ) of the wiring members 36d, 36d are inserted into the wiring holes 25d, 25e, respectively. The wiring holes 25d, 25e are electrically connected to the conductive wiring pattern member 22a of the intermediate insulating layer 21. This electrically connects the conductive wiring pattern member 22a to the conductive circuit pattern member 13d of the insulating circuit board 10 and the external connection terminal 31d via the wiring holes 25d, 25e. This configuration also allows the conductive wiring pattern member 22a of the intermediate insulating layer 21 to electrically connect the output electrodes on the upper surface of the semiconductor chip 33a arranged on the conductive circuit pattern member 13a of the insulating circuit board 10 to the input electrodes on the lower surfaces of the semiconductor chips 33c, 33d arranged on the conductive circuit pattern member 13d of the insulating circuit board 10.

[0070] The upper connection portions 362 (see FIG. 6 ) of the wiring members 36f, 36g are inserted into the wiring holes 25f, 25g, respectively. The wiring holes 25f, 25g are electrically connected to the conductive wiring pattern member 22b of the intermediate insulating layer 21. This electrically connects the conductive wiring pattern member 22b to the conductive circuit pattern member 13d and the external connection terminal 31d of the insulating circuit board 10 via the wiring holes 25f, 25g. This configuration also allows the conductive wiring pattern member 22b of the intermediate insulating layer 21 to electrically connect the output electrodes on the upper surface of the semiconductor chip 33b arranged on the conductive circuit pattern member 13b of the insulating circuit board 10 to the input electrodes on the lower surfaces of the semiconductor chips 33c, 33d arranged on the conductive circuit pattern member 13d of the insulating circuit board 10.

[0071] The upper connection portion 362 (see FIG. 6 ) of the wiring member 36h is inserted into the wiring hole 25h. The wiring hole 25h is not electrically connected to any of the conductive wiring pattern members of the intermediate insulating layer 21. Although not shown, the wiring hole 25h is electrically connected to another wiring layer (e.g., the fourth wiring layer, which is the lowest layer) of the wiring board 20 and is electrically connected to the external connection terminal 32g in this wiring layer. Because the lower end of the wiring member 36h is joined to the conductive circuit pattern member 13b of the insulating circuit board 10, the external connection terminal 32g is electrically connected to the input electrode on the underside of the semiconductor chip 33b via the wiring hole 25h and the conductive circuit pattern member 13b. Therefore, the external connection terminal 32g functions as a sense terminal for sensing the voltage at this input electrode (drain electrode).

[0072] The upper connection portion 362 (see FIG. 6 ) of the wiring member 36i is inserted into the wiring hole 25i. The wiring hole 25i is not electrically connected to any of the conductive wiring pattern members of the intermediate insulating layer 21. Although not shown, the wiring hole 25i is electrically connected to another wiring layer (for example, the fourth wiring layer, which is the bottom layer) of the wiring board 20, and is electrically connected to the external connection terminal 32f in this wiring layer.

[0073] External connection terminals 32a to 32f are bonded to the wiring substrate 20. Each of the external connection terminals 32a to 32f is electrically connected to a conductive wiring pattern member of at least one wiring layer included in the wiring substrate 20.

[0074] Although not shown, for example, the external connection terminal 32a is electrically connected to a conductive wiring pattern member formed on the first wiring layer, and this conductive wiring pattern member is electrically connected to the wiring holes 24a and 24b. As a result, the external connection terminal 32a functions as a gate control terminal for inputting control signals to the control electrodes of the semiconductor chips 33a and 33b. Furthermore, for example, the external connection terminal 32b is electrically connected to a conductive wiring pattern member formed on the first wiring layer, and this conductive wiring pattern member is electrically connected to the wiring holes 24c and 24d. As a result, the external connection terminal 32b functions as a gate control terminal for inputting control signals to the control electrodes of the semiconductor chips 33c and 33d.

[0075] Furthermore, the external connection terminal 32c is electrically connected to a conductive wiring pattern member formed on the fourth wiring layer, which in turn is electrically connected to the wiring holes 23a and 23b. As a result, the external connection terminal 32c functions as an auxiliary source terminal connected to the output electrodes (source electrodes) of the semiconductor chips 33a and 33b. Furthermore, the external connection terminal 32d is electrically connected to a conductive wiring pattern member formed on the fourth wiring layer, which in turn is electrically connected to the wiring holes 23c and 23d. As a result, the external connection terminal 32d functions as an auxiliary source terminal connected to the output electrodes (source electrodes) of the semiconductor chips 33c and 33d.

[0076] 5 is a diagram showing an example of the circuit configuration of an inverter circuit. The semiconductor module 2 includes, for example, an inverter circuit as shown in FIG. 5. This inverter circuit includes transistors (MOS-FETs) Q1 and Q2. The transistor Q1 forms the upper arm 37a of a half-bridge circuit, and the transistor Q2 forms the lower arm 37b of the half-bridge circuit. The transistor Q1 corresponds to the semiconductor chips 33a and 33b, and the transistor Q2 corresponds to the semiconductor chips 33c and 33d.

[0077] The drain electrode of transistor Q1 is connected to the P terminal, which constitutes the positive input terminal of the half-bridge circuit. Transistor Q1 corresponds to semiconductor chips 33a and 33b, and the P terminal corresponds to external connection terminals 31a and 31b. As described above, the input electrode (drain electrode) on the underside of semiconductor chip 33a is electrically connected to external connection terminal 31a, which is the P terminal, via conductive circuit pattern member 13a. Furthermore, the input electrode (drain electrode) on the underside of semiconductor chip 33b is electrically connected to external connection terminal 31b, which is the P terminal, via conductive circuit pattern member 13b.

[0078] The source electrode of transistor Q2 is connected to the N terminal, which constitutes the negative input electrode of the half-bridge circuit. Transistor Q2 corresponds to semiconductor chips 33c and 33d, and the N terminal corresponds to external connection terminal 31c. As described above, the output electrode (source electrode) on the top surface of semiconductor chip 33c is electrically connected to the N terminal, or external connection terminal 31c, via wiring pin 34c, conductive wiring pattern member 22c, wiring members 36a to 36c, and conductive circuit pattern member 13c. In addition, the output electrode (source electrode) on the top surface of semiconductor chip 33d is electrically connected to the N terminal, or external connection terminal 31c, via wiring pin 34d, conductive wiring pattern member 22c, wiring members 36a to 36c, and conductive circuit pattern member 13c.

[0079] The source electrode of transistor Q1 and the drain electrode of transistor Q2 are connected at connection point 37c, which is connected to the M terminal, which constitutes the output terminal of the half-bridge circuit. The M terminal corresponds to external connection terminal 31d. As described above, the output electrode (source electrode) on the upper surface of semiconductor chip 33a is electrically connected to the input electrode (drain electrode) on the lower surface of semiconductor chips 33c and 33d and external connection terminal 31d, which is the M terminal, via wiring pin 34a, conductive wiring pattern member 22a, wiring members 36d and 36e, and conductive circuit pattern member 13d. The output electrode (source electrode) on the upper surface of semiconductor chip 33b is electrically connected to the input electrode (drain electrode) on the lower surface of semiconductor chips 33c and 33d and external connection terminal 31d, which is the M terminal, via wiring pin 34b, conductive wiring pattern member 22b, wiring members 36f and 36g, and conductive circuit pattern member 13d.

[0080] The gate electrode of transistor Q1 is connected to gate terminal G1, which is an input terminal for a control signal for switching operation. Gate terminal G1 corresponds to external connection terminal 32a. As described above, the control electrode (gate electrode) on the upper surface of semiconductor chip 33a is electrically connected to external connection terminal 32a, which is gate terminal G1, via wiring pin 35a and a predetermined conductive wiring pattern member (e.g., a conductive wiring pattern member of the first wiring layer) of wiring substrate 20. Similarly, the control electrode (gate electrode) on the upper surface of semiconductor chip 33b is electrically connected to external connection terminal 32a, which is gate terminal G1, via wiring pin 35b and a predetermined conductive wiring pattern member (e.g., a conductive wiring pattern member of the first wiring layer) of wiring substrate 20.

[0081] The gate electrode of transistor Q2 is connected to gate terminal G2, which is an input terminal for a control signal for switching operation. Gate terminal G2 corresponds to external connection terminal 32b. As described above, the control electrode (gate electrode) on the upper surface of semiconductor chip 33c is electrically connected to external connection terminal 32b, which is gate terminal G2, via wiring pin 35c and a predetermined conductive wiring pattern member (e.g., a conductive wiring pattern member of the first wiring layer) of wiring substrate 20. Also, the control electrode (gate electrode) on the upper surface of semiconductor chip 33d is electrically connected to external connection terminal 32b, which is gate terminal G2, via wiring pin 35d and a predetermined conductive wiring pattern member (e.g., a conductive wiring pattern member of the first wiring layer) of wiring substrate 20.

[0082] The source electrode of transistor Q1 is also connected to auxiliary source terminal S1, which corresponds to external connection terminal 32c. The source electrode of transistor Q2 is also connected to auxiliary source terminal S2, which corresponds to external connection terminal 32d.

[0083] The semiconductor device 1 of this embodiment is equipped with eight pairs of transistors Q1 and Q2. Therefore, the semiconductor device 1 includes eight pairs of inverter circuits each including a pair of transistors Q1 and Q2. These inverter circuits are connected in parallel. Although not shown, for example, three semiconductor devices 1 including such parallel inverter circuits may be combined and used. In this case, one semiconductor device 1 generates a U-phase output voltage, another semiconductor device 1 generates a V-phase output voltage, and the remaining semiconductor device 1 generates a W-phase output voltage.

[0084] 6 is a perspective view showing the shape of the wiring members. Since the wiring members 36a to 36i have the same size and shape, they are referred to as "wiring member 36."

[0085] The wiring member 36 includes a lower spacer portion 361 and an upper connection portion 362. The spacer portion 361 includes an upper end surface 361a that is bonded to the periphery of the wiring holes 25a-25i (third wiring holes) on the lower surface (opposing surface) of the wiring board 20, and a lower end surface 361b that is bonded to the upper surfaces of the conductive circuit pattern members 13c-13e of the insulating circuit board 10. The spacer portion 361 maintains a predetermined distance D1 between the lower surface (opposing surface) of the wiring board 20 and the upper surfaces of the conductive circuit pattern members 13c-13e of the insulating circuit board 10. The connection portion 362 is formed within the upper end surface 361a of the spacer portion 361 and is inserted into the wiring holes 25a-25i (third wiring holes).

[0086] In the example of FIG. 6, the spacer portion 361 has a cylindrical shape with a height D1, and the connecting portion 362 has a cylindrical shape that is thinner than the spacer portion 361.

[0087] The wiring member 36 electrically connects the wiring holes formed in the wiring board 20 and the conductive circuit pattern members formed on the insulating circuit board 10, and also maintains a distance D1 between the lower surface (opposing surface) of the wiring board 20 and the upper surface of the conductive circuit pattern members of the insulating circuit board 10. The wiring member 36 can also be called a "wiring pin with spacer" that functions both as a wiring pin and a spacer.

[0088] Furthermore, if the thickness (e.g., diameter) of the connection portion 362 is the same as the thickness (e.g., opening diameter) of the wiring pins 34a to 34d, 35a to 35d, current flows through the spacer portion 361, which is thicker than these, thereby making it possible to improve the heat dissipation effect of the heat generated by the current.

[0089] Fig. 7 is an enlarged cross-sectional view of the mounting area of ​​the wiring pins and wiring members. Fig. 7 is an enlarged cross-sectional view of region A in Fig. 2 taken along line I1-I1 in Fig. 3, and shows the semiconductor chip 33d1, conductive circuit pattern member 13d, wiring pins 34d, 35d, and wiring member 36g. The upper side of Fig. 7 shows the state before bonding between the wiring pins 34d, 35d and semiconductor chip 33d1, and between the wiring member 36g and conductive circuit pattern member 13d, and the lower side of Fig. 7 shows the state after bonding.

[0090] 7, wiring pins 34d, 35d and wiring member 36g are inserted into wiring holes 23d, 24d, and 25g, respectively, of wiring board 20. At this time, upper end surface 361a of spacer portion 361 of wiring member 36g is joined to the lower surface of wiring board 20 (opposing surface 20a facing insulating circuit board 10) around wiring hole 25g.

[0091] Furthermore, a semiconductor chip 33d1 is bonded to the upper surface of the conductive circuit pattern member 13d via bonding material 14a. As a result, the input electrode 33_1 on the lower surface of the semiconductor chip 33d1 is electrically connected to the conductive circuit pattern member 13d via the bonding material 14a. Bonding materials 14b and 14c are disposed on the upper surfaces of the output electrode 33_2 and the control electrode 33_3 of the semiconductor chip 33d1, respectively, and bonding material 14d is disposed on the upper surface of the conductive circuit pattern member 13d in a position facing the wiring member 36g.

[0092] From this state, the wiring board 20 is moved closer toward the insulating circuit board 10 until the lower end surface 361b of the spacer portion 361 of the wiring member 36g abuts against the conductive circuit pattern member 13d. As shown in the lower side of Figure 7, when the wiring board 20 abuts against the lower end surface 361b of the spacer portion 361, the lower ends of the wiring pins 34d and 35d come into contact with the bonding materials 14b and 14c, respectively. However, the lower end surfaces of the wiring pins 34d and 35d do not come into contact with the upper surface of the semiconductor chip 33d1, and a gap is maintained between them.

[0093] Here, a comparative example will be shown in which a wiring pin is used instead of the wiring member 36g in Fig. 7. Fig. 8 is a diagram showing a comparative example relating to the bonding of the wiring pin.

[0094] 8, wiring pins 38 are inserted into wiring holes 25g of wiring board 20 instead of wiring members 36a. Also, as in FIG. 7, bonding materials 14b and 14c are disposed on the surfaces of output electrodes 33_2 and control electrodes 33_3 on the upper surface of semiconductor chip 33d1, respectively. Furthermore, bonding material 14e is disposed on the upper surface of conductive circuit pattern member 13d at a position facing wiring pin 38. Then, from this state, wiring board 20 is moved closer to insulating circuit board 10.

[0095] In this case, the lower end of the wiring pin 38 contacts the bonding material 14e but does not contact the upper surface of the conductive circuit pattern member 13d. Similarly to Fig. 7, the lower ends of the wiring pins 34d and 35d contact the bonding materials 14b and 14c, respectively, but the lower end surfaces of the wiring pins 34d and 35d do not contact the upper surface of the semiconductor chip 33d1. For example, the thickness D2 of the bonding materials 14b and 14c disposed on the semiconductor chip 33d1 is 50 to 400 µm, while the designed distance D3 between the lower end surfaces of the wiring pins 34d and 35d and the upper surface of the semiconductor chip 33d1 is set to 10 to 300 µm.

[0096] However, when the wiring board 20 is brought closer to the insulating circuit board 10, pressure from a jig, for example, may cause a load (stress) downward (in the −Z direction) from the top of the wiring board 20. This load may cause the bottom end surfaces of the wiring pins 34d and 35d to come into contact with the top surface of the semiconductor chip 33d1, and in some cases, cracks may occur, damaging the semiconductor chip 33d1.

[0097] Furthermore, even during the process from when the lower ends of the wiring pins 34d, 35d and the upper surface of the semiconductor chip 33d1 are joined via the bonding materials 14b, 14c, respectively, until sealing is performed with the sealing member 5, a load may be generated downward (in the -Z direction) from the upper side of the wiring substrate 20. In this case as well, the lower end surfaces of the wiring pins 34d, 35d may come into contact with the upper surface of the semiconductor chip 33d1, potentially damaging the semiconductor chip 33d1.

[0098] 7, when wiring member 36g is used, spacer portion 361 of wiring member 36g maintains distance D1 between the lower surface (opposing surface 20a) of wiring board 20 and the upper surface of conductive circuit pattern member 13d of insulating circuit board 10. This reduces the possibility that the lower end surfaces of wiring pins 34d, 35d will come into contact with the upper surface of semiconductor chip 33d1 when a load is applied downward (in the -Z direction) from the upper side of wiring board 20. This reduces the possibility that semiconductor chip 33d1 will be damaged by the application of the load.

[0099] 9 is a flowchart showing the manufacturing process of a semiconductor device. [Step S1] A preparation step is performed to prepare the components of the semiconductor device 1. Examples of the components prepared here include the insulating circuit board 10, wiring board 20, semiconductor chips 33a-33d, wiring pins 34a-34d, 35a-35d, wiring members 36a-36i, and sealing member 5 that constitute the semiconductor module 2, and the cooler 3. Components not listed here may also be prepared as necessary for manufacturing the semiconductor device 1. Manufacturing equipment used in manufacturing the semiconductor device 1 may also be prepared. Examples of manufacturing equipment include a coating device that coats solder and a molding device that seals with a sealing member.

[0100] [Step S2] A module assembly process is performed to assemble the semiconductor module 2. This module assembly process includes, for example, the following steps S2a to S2d.

[0101] (Step S2a) The semiconductor chips 33a to 33d are bonded to the upper surface of the conductive circuit pattern member of the insulating circuit board 10 via the bonding material 14a.

[0102] (Step S2b) In parallel with the process of step S2a, the wiring pins 34a to 34d, 35a to 35d are inserted into and joined to the wiring holes 23a to 23d, 24a to 24d, respectively, of the wiring board 20. Furthermore, the connection portions 362 of the wiring members 36a to 36i are inserted into and joined to the wiring holes 25a to 25i, respectively, of the wiring board 20. At this time, the upper end surfaces 361a of the spacer portions 361 of the wiring members 36a to 36i are joined to the lower surface (opposing surface 20a) of the wiring board 20.

[0103] It should be noted that steps S2a and S2b may be performed before step S2c, and for example, one of steps S2a and S2b may be performed first and the other may be performed later.

[0104] (Step S2c) The wiring board 20 to which the wiring pins 34a to 34d, 35a to 35d and wiring members 36a to 36i are bonded is attached to the insulating circuit board 10 to which the semiconductor chips 33a to 33d are bonded.

[0105] In this process, bonding material 14b is placed on the upper surfaces of output electrodes 33_2 of semiconductor chips 33a to 33d, bonding material 14c is placed on the upper surfaces of control electrodes 33_3 of semiconductor chips 33a to 33d, and bonding material 14d is placed on the upper surface of the conductive circuit pattern member of insulating circuit board 10 at positions facing wiring members 36a to 36i, respectively.

[0106] From this state, the wiring board 20 is moved toward the insulating circuit board 10 until the lower end surfaces 361b of the spacer portions 361 of the wiring members 36a to 36i abut against the upper surfaces of the conductive circuit pattern members of the insulating circuit board 10. When the upper surfaces of the conductive circuit pattern members abut against the lower end surfaces 361b of the spacer portions 361, the spacer portions 361 of the wiring members 36a to 36i maintain a distance D1 between the lower surface (opposing surface 20a) of the wiring board 20 and the upper surfaces of the conductive circuit pattern members of the insulating circuit board 10. Therefore, the lower ends of the wiring pins 34d and 35d contact the bonding materials 14b and 14c, respectively, while being spaced apart from the upper surfaces of the semiconductor chips 33a to 33d. This reduces the possibility that the lower ends of the wiring pins 34d and 35d will collide with the semiconductor chips 33a to 33d and damage the semiconductor chips 33a to 33d.

[0107] As described above, reflow is performed with the upper surfaces of the conductive circuit pattern members abutting against the lower end surfaces 361b of the spacer portions 361 of the wiring members 36a to 36i. The heating melts the bonding materials 14b to 14d, which are then cooled and harden. This bonds the wiring pins 34d and 35d to the upper surfaces of the semiconductor chips 33a to 33d via the bonding materials 14b and 14c, respectively. Furthermore, with the lower end surfaces 361b of the spacer portions 361 of the wiring members 36a to 36i abutting against the upper surfaces of the conductive circuit pattern members of the insulating circuit board 10, the wiring members 36a to 36i and the upper surfaces of the conductive circuit pattern members of the insulating circuit board 10 are bonded by the bonding material 14d.

[0108] Note that step S2b may be included in step S2a. Furthermore, the reflow for bonding the semiconductor chips in step S2a and the reflow for bonding the wiring pins 34a-34d, 35a-35d and wiring members 36a-36i in step S2c may be performed in the same process. In this case, bonding material 14a is placed on the upper surface of the conductive circuit pattern member of the insulating circuit board 10, and the semiconductor chips 33a-33d are placed thereon. Furthermore, bonding materials 14b and 14c are placed on the upper surfaces of the output electrodes 33_2 and control electrodes 33_3 of the semiconductor chips 33a-33d, respectively. Furthermore, bonding material 14d is placed on the upper surface of the conductive circuit pattern member of the insulating circuit board 10 in positions facing the wiring members 36a-36i. From this state, the wiring board 20 is moved toward the insulating circuit board 10 until the lower end faces 361b of the spacer portions 361 of the wiring members 36a to 36i abut the upper faces of the conductive circuit pattern members of the insulating circuit board 10, and reflow is performed.

[0109] (Step S2d) The insulating circuit board 10 and the wiring board 20 are sealed with the sealing member 5. In this step, the insulating circuit board 10 with the wiring board 20 attached is set in the cavity of a predetermined molding device. In the molding device, the molten sealing material in the pod is pressurized by a plunger, and is sent from the pod to a runner and injected into the cavity. The sealing material then hardens, and the insulating circuit board 10 and the wiring board 20 are sealed with the sealing member 5. The region between the insulating circuit board 10 and the wiring board 20 is sealed with the sealing member 5, and at least the side regions (±X direction and ±Y direction) of the insulating circuit board 10 and the wiring board 20 and the upper surface region of the wiring board 20 are also sealed with the sealing member 5.

[0110] [Step S3] The cooler 3 is bonded to the underside of the semiconductor module 2 via a bonding material 4. In this step, for example, the cooler 3 is fixed to a predetermined fixing table, and the semiconductor module 2 is set on the bonding material 4 (for example, a thermally conductive adhesive) applied to the upper surface of the cooler 3. Then, the bonding material 4 is heated, thereby bonding the underside of the semiconductor module 2 and the upper surface of the cooler 3.

[0111] Next, the positions at which the wiring members 36a to 36i are arranged relative to the insulating circuit board 10 will be described.

[0112] In this embodiment, a wiring member is disposed in a region between the first semiconductor chip and the second semiconductor chip on insulating circuit board 10 in plan view.

[0113] For example, the semiconductor chip 33a1 (first semiconductor chip) has an output electrode 33_2 and a control electrode 33_3 (first electrode) on its upper surface, and the semiconductor chip 33b1 (second semiconductor chip) has an output electrode 33_2 and a control electrode 33_3 (second electrode) on its upper surface.

[0114] The wiring substrate 20 is formed with wiring holes 23a and 24a (first wiring holes), wiring holes 23b and 24b (second wiring holes), and wiring hole 25a (third wiring hole). The wiring holes 23a and 24a face the output electrode 33_2 and control electrode 33_3 of the semiconductor chip 33a1, respectively, and the wiring holes 23b and 24b face the output electrode 33_2 and control electrode 33_3 of the semiconductor chip 33b1, respectively. Wiring pins 34a and 35a (first wiring pins) are inserted into the wiring holes 23a and 24a, respectively. The lower end of the wiring pin 34a is electrically connected to the output electrode 33_2 of the semiconductor chip 33a1 via the bonding material 14b. The lower end of the wiring pin 35a is electrically connected to the control electrode 33_3 via the bonding material 14c. Wiring pins 34b and 35b (second wiring pins) are inserted into wiring holes 23b and 24b, respectively. The lower end of wiring pin 34b is electrically connected to output electrode 33_2 of semiconductor chip 33b1 via bonding material 14b. The lower end of wiring pin 35b is electrically connected to control electrode 33_3 via bonding material 14c. A connecting portion 362 of wiring member 36a is inserted into wiring hole 25a. An upper end surface 361a of spacer portion 361 of wiring member 36a is bonded to the lower surface (opposing surface 20a) of wiring board 20, and a lower end surface 361b of spacer portion 361 of wiring member 36a is bonded to conductive circuit pattern member 13c of insulating circuit board 10.

[0115] The lower end surface 361b of the spacer portion 361 of the wiring member 36a is joined to the conductive circuit pattern member 13c in the region between the semiconductor chips 33a1 and 33b1 of the insulating circuit board 10.

[0116] Also, for example, the semiconductor chip 33b2 (first semiconductor chip) has an output electrode 33_2 and a control electrode 33_3 (first electrode) on its upper surface, and the semiconductor chip 33d1 (second semiconductor chip) has an output electrode 33_2 and a control electrode 33_3 (second electrode) on its upper surface.

[0117] The wiring substrate 20 is formed with wiring holes 23b and 24b (first wiring holes), wiring holes 23d and 24d (second wiring holes), and wiring hole 25g (third wiring hole). Wiring holes 23b and 24b face the output electrode 33_2 and control electrode 33_3 of the semiconductor chip 33b1, respectively, and wiring holes 23d and 24d face the output electrode 33_2 and control electrode 33_3 of the semiconductor chip 33d1, respectively. Wiring pins 34b and 35b (first wiring pins) are inserted into the wiring holes 23b and 24b, respectively. The lower end of wiring pin 34b is electrically connected to the output electrode 33_2 of the semiconductor chip 33b2 via bonding material 14a. The lower end of wiring pin 35b is electrically connected to the control electrode 33_3 via bonding material 14b. Wiring pins 34d and 35d (second wiring pins) are inserted into wiring holes 23d and 24d, respectively. The lower end of wiring pin 34d is electrically connected to output electrode 33_2 of semiconductor chip 33d1 via bonding material 14b. The lower end of wiring pin 35d is electrically connected to control electrode 33_3 via bonding material 14c. A connecting portion 362 of wiring member 36g is inserted into wiring hole 25g, and an upper end surface 361a of spacer portion 361 of wiring member 36g is joined to the lower surface (opposing surface 20a) of wiring board 20, and a lower end surface 361b of spacer portion 361 of wiring member 36g is joined to conductive circuit pattern member 13d of insulating circuit board 10.

[0118] The lower end surface 361b of the spacer portion 361 of the wiring member 36g is joined to the conductive circuit pattern member 13d in the region between the semiconductor chip 33b2 and the semiconductor chip 33d1 of the insulating circuit board 10.

[0119] In this way, the wiring member is disposed in the region between the first semiconductor chip and the second semiconductor chip on the insulating circuit board 10 in a plan view. As a result, when a load is applied downward (in the −Z direction) from above the wiring board 20 in the region between the first semiconductor chip and the second semiconductor chip, the distance between the upper surface of the insulating circuit board 10 and the lower surface of the wiring board 20 in that region can be maintained at the same distance as the height of the spacer portion of the wiring member. This reduces the possibility that the lower ends of the first and second wiring pins will collide with the upper surfaces of the first and second semiconductor chips due to the above-mentioned load, causing damage to the first and second semiconductor chips.

[0120] Furthermore, in this embodiment, semiconductor chip 33a1 (first semiconductor chip) and semiconductor chip 33b1 (second semiconductor chip) are disposed opposite each other across first center line L1 of insulating circuit board 10 in a plan view, and multiple wiring members (wiring members 36a-36c) are arranged on conductive circuit pattern member 13c along first center line L1. For example, if multiple wiring members are arranged along sides extending in the ±X directions of the insulating circuit board at positions opposing each other across semiconductor chips 33a1 and 33b1, when a load is applied downward (in the −Z direction) from above wiring board 20 in the region between semiconductor chips 33a1 and 33b1, the strength of that region of wiring board 20 in the downward direction is weak, and this region may bend downward. In this case, there is a possibility that the lower ends of the wiring pins 34a and 35a will collide with the upper surface of the semiconductor chip 33a1, damaging the semiconductor chip 33a1, or that the lower ends of the wiring pins 34b and 35b will collide with the upper surface of the semiconductor chip 33b1, damaging the semiconductor chip 33b1. In contrast, the above-described configuration of the present embodiment in which a plurality of wiring members are arranged along the first center line L1 reduces the possibility of damage to the semiconductor chips 33a1 and 33b1.

[0121] Furthermore, in this embodiment, multiple wiring members (wiring members 36d-36g) are arranged on conductive circuit pattern member 13d along a second center line L2 that is perpendicular to first center line L1 in plan view on insulated circuit board 10. This reduces the possibility of damage to semiconductor chips (e.g., semiconductor chips 33b2 and 33d1) arranged in opposing positions across second center line L2 when a load is applied downward (in the -Z direction) from above wiring board 20 to the region between these chips. Note that second center line L2 does not have to be exactly in the center of insulated circuit board 10 in the ±X directions, and may be a line near the center.

[0122] In this embodiment, the upper surface of the insulating circuit board 10 is formed with a conductive circuit pattern member 13c (first conductive circuit pattern member) extending along the first center line L1, and conductive circuit pattern members 13a and 13b (second and third conductive circuit pattern members) arranged opposite each other with the conductive circuit pattern member 13c sandwiched between them. A semiconductor chip 33a1 (first semiconductor chip) is arranged on the conductive circuit pattern member 13a, and a semiconductor chip 33b1 (second carrier chip) is arranged on the conductive circuit pattern member 13b. Furthermore, multiple wiring members (wiring members 36a to 36c) are arranged on the conductive circuit pattern member 13c along the first center line L1. This reduces the possibility of damage to the semiconductor chips 33a1 and 33b1 when a load is applied downward (in the −Z direction) from above the wiring board 20 in the region between the semiconductor chips 33a1 and 33b1.

[0123] In this embodiment, a conductive circuit pattern member 13d (fourth conductive circuit pattern member) on which a plurality of semiconductor chips 33c, 33d (third semiconductor chips) are arranged is formed on the upper surface of the insulating circuit board 10. A conductive wiring pattern member 22c is formed on the wiring board 20. A current path is formed between the output electrodes 33_2 on the upper surfaces of the semiconductor chips 33c, 33d and the conductive circuit pattern member 13c, passing through the conductive wiring pattern member 22c and the wiring members 36a to 36c. Furthermore, the connection portions 362 of the wiring members 36a to 36c may be columnar, and the spacer portions 361 of the wiring members 36a to 36c may be columnar and thicker than the connection portions 362.

[0124] A large source current flows in the current path between the output electrode (source electrode) 33_2 on the upper surface of the semiconductor chips 33c, 33d and the conductive circuit pattern member 13c (and the external connection terminal 31c), and a large amount of Joule heat is likely to be generated along this current path. In response to this, the conductive wiring pattern member 22c of the wiring board 20 and the conductive circuit pattern member 13c of the insulating circuit board 10 are electrically connected by a plurality of wiring members (wiring members 36a to 36c) that have spacer portions 361 that are thicker than the wiring pins, for example, thereby improving the heat dissipation effect when the source current flows.

[0125] Furthermore, in this embodiment, the upper surface of the insulating circuit board 10 is formed with a conductive circuit pattern member 13b (fifth conductive circuit pattern member) having a semiconductor chip 33b2 (first semiconductor chip) disposed on its upper surface, and a conductive circuit pattern member 13d (sixth conductive circuit pattern member) having a semiconductor chip 33d1 (second semiconductor chip) disposed on its upper surface. Furthermore, a plurality of wiring members (wiring members 36d-36g) are arranged in an edge region of the conductive circuit pattern member 13d along the boundary lines 13d1 and 13d2 that face the conductive circuit pattern member 13b. This reduces the possibility of damage to the semiconductor chips 33b2 and 33d1 when a load is applied downward (in the -Z direction) from above the wiring board 20 in the region between the semiconductor chips 33b2 and 33d1.

[0126] <Modifications of Semiconductor Module> Next, modifications in which the configuration of the semiconductor module 2 is partially modified will be described.

[0127] Fig. 10 is a diagram showing a modified example in which a portion of the conductive circuit pattern member of the insulating circuit board is modified. Like Fig. 3, Fig. 10 shows a state in which wiring pins and wiring members are bonded to the semiconductor chip and conductive circuit pattern member, respectively, on the insulating circuit board 10, for ease of explanation.

[0128] In the insulating circuit board 10 shown in FIG. 10 , the region of the conductive circuit pattern member 13c on the −X direction side extends further in the −X direction. By extending the region of the conductive circuit pattern member 13c in this manner, it becomes possible to bond more wiring members to the conductive circuit pattern member 13c. In the example of FIG. 10 , in addition to the wiring members 36a-36c, wiring members 36j and 36k are bonded to the upper surface of the conductive circuit pattern member 13c. The wiring members 36a-36c, 36j, and 36k are arranged along the first center line L1. Furthermore, the connection portions 362 of the wiring members 36a-36c, 36j, and 36k are inserted into wiring holes formed in the wiring board 20 and electrically connected to the conductive wiring pattern member 22c of the wiring board 20. Therefore, the conductive circuit pattern member 13c is electrically connected to the conductive wiring pattern member 22c via the wiring members 36a-36c, 36j, and 36k.

[0129] As described above, a large source current flows in the current path between the output electrode (source electrode) 33_2 on the upper surface of the semiconductor chip 33c, 33d and the conductive circuit pattern member 13c and the external connection terminal 31c, and therefore a large amount of Joule heat is likely to be generated along this current path. According to the configuration of Figure 10, the conductive circuit pattern member 13c of the insulating circuit board 10 and the conductive wiring pattern member 22c of the wiring board 20 are connected via more wiring members 36a to 36c, 36j, and 36k, so that the heat dissipation effect when the source current flows can be further improved.

[0130] Next, modified examples of the shape of the wiring member will be described with reference to Fig. 11, which shows modified examples of the shape of the wiring member.

[0131] 11A, the connecting portion 362 has a cylindrical shape, while the spacer portion 361 has a rectangular pillar shape. In this manner, as long as the spacer portion 361 is thicker than the connecting portion 362, the cross-sectional shapes of the pillar-shaped spacer portion 361 and the connecting portion 362 can be selected arbitrarily.

[0132] In the wiring member 36 shown in FIG. 11B, the spacer portion 361 includes an upper member 363a and a lower member 363b. Both the upper member 363a and the lower member 363b are columnar (cylindrical in this example), with the upper member 363a being thicker than the lower member 363b. An upper end surface 361a of the upper member 363a is bonded to the peripheries of the wiring holes 25a to 25i on the lower surface (opposing surface 20a) of the wiring substrate 20. The upper member 363a may be a flat member that is circular or polygonal in plan view. In this case, the upper end surface 361a of the flat member is bonded to the peripheries of the wiring holes 25a to 25i on the lower surface (opposing surface 20a) of the wiring substrate 20.

[0133] In the wiring member 36 shown in FIG. 11C , the spacer portion 361 also includes an upper member 364a and a lower member 364b. The lower member 364b is columnar (cylindrical in this case). The lower member 364b may have the same thickness as the connecting portion 362. On the other hand, the upper member 364a has a cut-off top and is inverted cylindrical. That is, the thickness of the upper member 364a gradually decreases from top to bottom. An upper end surface 361a of the upper member 364a is joined to the periphery of the wiring holes 25a-25i on the lower surface (opposing surface 20a) of the wiring substrate 20.

[0134] The wiring member 36 can be fabricated, for example, by cutting a metal material. Alternatively, the wiring member 36 can be fabricated by combining multiple components. For example, the wiring member 36 shown in FIG. 11A includes a columnar member 365a having a height from the top to the bottom of the wiring member 36, and a prismatic member 365b having the same height as the spacer portion 361. A cylindrical through-hole 365c extending in the vertical direction (±Z direction) is formed in the center of the prismatic member 365b. The wiring member 36 is fabricated by inserting the columnar member 365a into the through-hole 365c.

[0135] 11(B), for example, the connection portion 362 and the lower member 363b may be integrally formed as a cylindrical member having a height from the upper end to the lower end of the wiring member 36, and a through-hole 363c may be formed in the center of the upper member 363a. Then, the wiring member 36 is produced by inserting a cylindrical member into the through-hole 363c and joining the upper member 363a and the cylindrical member by welding.

[0136] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0137] REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor module 3 cooler 4 bonding material 5 sealing member 10 insulating circuit board 11 insulating plate 12 metal plate 13a to 13e conductive circuit pattern member 13d1, 13d2 boundary line 14a to 14e bonding material 20 wiring board 20a opposing surface 21 intermediate insulating layer 22a to 22c conductive wiring pattern member 23a to 23d, 24a to 24d, 25a to 25i wiring hole 31a to 31d, 32a to 32g external connection terminal 33a to 33d, 33a1, 33b1, 33b2, 33d1 semiconductor chip 33_1 input electrode 33_2 output electrode 33_3 control electrode 34a to 34d, 35a to 35d, 38 wiring pin 36, 36a to 36k Wiring member 37a Upper arm portion 37b Lower arm portion 37c Connection point 361 Spacer portion 361a Upper end surface 361b Lower end surface 362 Connection portion 363a, 364a Upper member 363b, 364b Lower member 363c, 365c Through hole 365a Cylindrical member 365b Prismatic member A Region D1, D3 Distance D2 Thickness L1 First center line L2 Second center line

Claims

1. An insulating circuit board having a conductive circuit pattern member formed on its upper surface; first and second semiconductor chips each having first and second electrodes on its upper surface and disposed on the insulating circuit board; a wiring board having an opposing surface facing the upper surface of the insulating circuit board, with first to third wiring holes formed in the opposing surface, the first and second wiring holes facing the first and second electrodes, respectively; first and second wiring pins inserted into the first and second wiring holes, respectively, and having lower ends electrically connected to the first and second electrodes via a bonding material; and a conductive wiring member having a spacer portion including an upper end face joined to the periphery of the third wiring hole on the opposing surface of the wiring board and a lower end face joined to the upper surface of the conductive circuit pattern member of the insulating circuit board, maintaining a predetermined distance between the opposing surface and the upper surface of the conductive circuit pattern member, and a connecting portion formed within the upper end face of the spacer portion and inserted into the third wiring hole. the lower end surface of the wiring member is joined to the conductive circuit pattern member in a region between the first semiconductor chip and the second semiconductor chip on the insulating circuit board.

2. The semiconductor device according to claim 1, wherein the insulating circuit board has a rectangular shape in a plan view, the first and second semiconductor chips are arranged opposite each other across a first center line of the insulating circuit board in a plan view, and the wiring members are arranged in multiple rows along the first center line on the conductive circuit pattern member.

3. The semiconductor device according to claim 2, wherein the wiring members are further arranged in plurality on the conductive circuit pattern member along a second center line that is perpendicular to the first center line in a plan view of the insulating circuit board.

4. The semiconductor device described in claim 2, wherein the conductive circuit pattern member includes a first conductive circuit pattern member extending along the first center line, and a second conductive circuit pattern member and a third conductive circuit pattern member arranged opposite each other with the first conductive circuit pattern member in between, the first semiconductor chip is arranged on the second conductive circuit pattern member, the second semiconductor chip is arranged on the third conductive circuit pattern member, and a plurality of the wiring members are arranged on the first conductive circuit pattern member along the first center line.

5. The semiconductor device according to claim 4, wherein the conductive circuit pattern member includes a fourth conductive circuit pattern member having a plurality of third semiconductor chips arranged on its upper surface, a conductive wiring pattern member is formed on the wiring board, and a current path is formed between the plurality of third semiconductor chips and the first conductive circuit pattern member, passing through the conductive wiring pattern member and the plurality of wiring members arranged on the first conductive circuit pattern member.

6. The semiconductor device according to claim 5, wherein the connection portion of the wiring member is pillar-shaped, and the spacer portion of the wiring member is pillar-shaped and thicker than the connection portion.

7. The semiconductor device according to claim 1, wherein the insulating circuit board has a rectangular shape in a plan view, the conductive circuit pattern member includes a fifth conductive circuit pattern member having the first semiconductor chip disposed on its upper surface, and a sixth conductive circuit pattern member having the second semiconductor chip disposed on its upper surface, and the wiring members are arranged in multiple numbers along the boundary line in an edge region of the sixth conductive circuit pattern member that faces the fifth conductive circuit pattern member.

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