Semiconductor device

Abstract

The present invention addresses the problem of improving the ability of a printed circuit board to dissipate heat.　A semiconductor device (10) includes an insulating circuit board and a printed circuit board. A first semiconductor chip is disposed on conductive plates (17b, 17d) of the insulating circuit board, and a second semiconductor chip is disposed on a conductive plate (17e). The printed circuit board has an insulating layer, a first conductive layer conductively connected to an upper surface electrode of the first semiconductor chip and the conductive plate (17e), a second conductive layer conductively connected to an upper surface electrode of the second semiconductor chip and a conductive plate (17c), and an insulating layer disposed between the first conductive layer and the second conductive layer. A cooler is provided on the lower surface of an insulating member (17a) of the insulating circuit board. The conductive plate (17c) extends from the center of the insulating circuit board toward the outer edge so as to be connected to an external terminal (14). The conductive plate (17c) and the second conductive layer of the printed circuit board are connected by conductive members (51, 52).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor device includes a bus bar as a heat dissipation member at a portion connecting a first semiconductor switch element and a second semiconductor switch element (see Patent Document 1). Also, the semiconductor device includes an insulating circuit board to which a conductive pattern member is attached and on which a semiconductor chip is mounted, and a printed circuit board facing the insulating circuit board, and a conductive connecting member of the printed circuit board is connected to the semiconductor chip and the conductive pattern member (see Patent Document 2).

[0003] JP 2017-139380 A International Publication No. 2014 / 103133

[0004] An object of the present invention is to improve the heat dissipation capacity of a printed circuit board.

[0005] To solve the above-mentioned problems, a semiconductor device is provided, comprising: an insulated circuit board having a first conductive plate, a second conductive plate, and a third conductive plate arranged on an insulating member; a first semiconductor chip arranged on the first conductive plate, a first external terminal connected to the first conductive plate, a second semiconductor chip arranged on the second conductive plate, a second external terminal connected to the second conductive plate, a third external terminal connected to the third conductive plate, a first conductive layer conductively connected to an upper surface electrode of the first semiconductor chip and the second conductive plate, a second conductive layer conductively connected to an upper surface electrode of the second semiconductor chip and the third conductive plate, and an insulating layer arranged between the first conductive layer and the second conductive layer, and a printed circuit board arranged opposite the insulated circuit board with the first semiconductor chip and the second semiconductor chip sandwiched therebetween. The semiconductor device also has a cooler on the underside of the insulating member, a third conductive plate extending from the center of the insulating circuit board toward the outer edge, and a conductive member arranged opposite the third conductive plate and connecting the third conductive plate and the second conductive layer.

[0006] The third conductive plate may include a first conductive pattern member having a first width to which the third external terminal is connected, and a second conductive pattern member having a second width smaller than the first width and extending from the center of the insulating circuit board toward the outer edge to a predetermined length.

[0007] The second width may be 2 mm or more and 10 mm or less, and the predetermined length may be 5 mm or more and 60 mm or less.

[0008] The conductive member may include a plurality of conductive pins connecting the third conductive plate and the second conductive layer.

[0009] The center-to-center spacing of the conductive pins may be 1.2 mm or greater.

[0010] The conductive member may include a single conductive block connecting the third conductive plate and the second conductive layer.

[0011] The conductive member may be a conductive inlay embedded in the printed circuit board.

[0012] The insulating circuit board may further include an intermediate conductive member connected to the second conductive plate and located in the middle of the insulating circuit board, and the first conductive layer may be conductively connected to the top electrode of the first semiconductor chip and the second conductive plate through the intermediate conductive member.

[0013] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0014] According to one aspect, it is possible to improve the heat dissipation capability of a printed circuit board. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

[0015] 1 is a plan view showing an example of a chip layout of a semiconductor device; FIG. 2 is a diagram showing an example of a cross section of a semiconductor device; FIG. 3 is a diagram showing an example of a circuit configuration of a semiconductor chip; FIG. 4 is a diagram showing an example of a pattern configuration of a bottom conductive layer; FIG. 5 is a diagram showing an example of a pattern configuration of an inner conductive layer; FIG. 6 is a diagram showing an example of a pattern configuration of an inner conductive layer; FIG. 7 is a diagram showing an example of a pattern configuration of a top layer wiring section; FIG. 8 is a diagram showing an example of an overview of a semiconductor device; FIG. 9 is a diagram showing a first configuration example of a conductive member; FIG. 10 is a diagram showing a second configuration example of a conductive member; FIG. 11 is a diagram showing a third configuration example of a conductive member; FIG. 12 is a diagram showing an example of the shape of a conductive plate; FIG. 13 is a diagram showing an example of a cross section of a semiconductor device of a first reference example; FIG. 14 is a diagram showing an example of a cross section of a semiconductor device of a second reference example; FIG. 15 is a diagram showing the analysis results of Joule heat of a printed circuit board.

[0016] Hereinafter, the present embodiment will be described with reference to the drawings. In the following description, "upper surface" refers to a surface facing upward when viewed from the paper surface. Similarly, "upper" and "upper part" refer to a direction facing upward when viewed from the paper surface. "Lower surface" refers to a surface facing downward when viewed from the paper surface. Similarly, "lower" refers to a direction facing downward when viewed from the paper surface. These directions are used in all drawings. "Upper surface," "upper," "upper part," "lower surface," and "lower" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. Furthermore, in this specification, "connection" means "electrical connection" unless otherwise specified.

[0017] Fig. 1 is a plan view showing an example of a chip layout of a semiconductor device. Fig. 2 is a view showing an example of a cross section of the semiconductor device. Note that Fig. 1 does not show an insulating sealing member and a printed circuit board. Fig. 2 does not show the insulating sealing member.

[0018] The semiconductor device 10 has a modular configuration of a half-bridge circuit including an upper arm portion A and a lower arm portion B. The upper arm portion A of the semiconductor device 10 includes semiconductor chips 11a1, 11b1, 11c1, 11d1, 11a2, 11b2, 11c2, and 11d2 (sometimes collectively referred to as semiconductor chips 11). The lower arm portion B of the semiconductor device 10 includes semiconductor chips 12a1, 12b1, 12c1, 12d1, 12a2, 12b2, 12c2, and 12d2 (sometimes collectively referred to as semiconductor chips 12).

[0019] The semiconductor chip 11 (first semiconductor chip) and the semiconductor chip 12 (second semiconductor chip) may be primarily made of silicon carbide. Such a semiconductor chip is, for example, a power metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, the semiconductor chips 11 and 12 each have a drain electrode as an input electrode on their bottom surfaces, a gate electrode as a control electrode, and a source electrode as an output electrode on their top surfaces.

[0020] The semiconductor chips 11 and 12 may also be composed primarily of silicon. Such a semiconductor chip may include a reverse-conducting (RC)-IGBT that combines the functions of an insulated gate bipolar transistor (IGBT) and a free wheeling diode (FWD). The semiconductor chip has a collector electrode as an input electrode on its bottom surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode on its top surface. In this embodiment, the semiconductor chips 11 and 12 are described as power MOSFETs.

[0021] The semiconductor device 10 includes a heat sink (copper base for heat dissipation) 16, an insulating circuit board 17 provided on the heat sink 16, and a multilayer printed circuit board 18 disposed above the insulating circuit board 17 and facing the insulating circuit board 17 (the multilayer structure of the printed circuit board 18 will be described later). The heat sink 16 is a plate-like member that is substantially rectangular in plan view. The corners of the heat sink 16 may be round-chamfered or C-chamfered.

[0022] The heat sink 16 is made of a metal with excellent heat dissipation properties. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. The surface of the heat sink 16 may be plated to improve corrosion resistance. Examples of plating materials that can be used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0023] An insulating circuit board 17 is connected to the front surface of the heat sink 16 via a bonding material 21, and a cooler 8 is fixed to the rear surface of the heat sink 16. The cooler 8 is, for example, a heat sink with one or more fins or a water-cooled cooling device.

[0024] Insulated circuit board 17 includes insulating member 17a, conductive plates 17b, 17c, 17d, and 17e formed on the front surface of insulating member 17a, and metal plate 17f formed on the back surface of insulating member 17a. Conductive plates 17b and 17d (first conductive plates) are formed on upper arm portion A, and conductive plate 17e (second conductive plate) is formed on lower arm portion B. Conductive plate 17c (third conductive plate) extends from the center toward the outer edge of insulating circuit board 17, and is formed in the center of the region of upper arm portion A on insulating member 17a.

[0025] The insulating member 17a has a rectangular shape in a plan view. The corners of the insulating member 17a may be rounded or chamfered. The insulating member 17a is made of ceramics or a resin material with high thermal conductivity. The ceramic is made of a material containing aluminum oxide, silicon nitride, or aluminum nitride as a main component, for example. The resin material may be an epoxy resin with added filler that has insulating properties and better thermal conductivity than the resin material.

[0026] The conductive plates 17b, 17c, 17d, and 17e are made of a metal with excellent conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. The conductive plates 17b, 17c, 17d, and 17e may be plated to improve their corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0027] The metal plate 17f is formed primarily from a metal with excellent thermal conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. A plating process may be performed to improve the corrosion resistance of the metal plate. Examples of plating materials used in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0028] The semiconductor chips 11a1, 11b1, 11c1, and 11d1 and the external terminal 13a (first external terminal) are mounted on the conductive plate 17b, and the semiconductor chips 11a2, 11b2, 11c2, and 11d2 and the external terminal 13b (first external terminal) are mounted on the conductive plate 17d. The semiconductor chips 12a1, 12b1, 12c1, 12d1, 12a2, 12b2, 12c2, and 12d2 and the external terminal 15 (second external terminal) are mounted on the conductive plate 17e. The external terminal 14 (third external terminal) is mounted on the conductive plate 17c.

[0029] 2 shows a state in which semiconductor chip 11a1 is connected to conductive plate 17b via bonding material 22, and semiconductor chip 11b1 is connected to conductive plate 17b via bonding material 23. Also shown is a state in which semiconductor chip 12a1 is connected to conductive plate 17e via bonding material 24, and semiconductor chip 12b1 is connected to conductive plate 17e via bonding material 25.

[0030] On the other hand, external terminal 13a is connected to conductive plate 17b by a bonding material, and external terminal 13b is connected to conductive plate 17b by a bonding material. Furthermore, external terminal 14 is connected to conductive plate 17c by a bonding material, and external terminal 15 is connected to conductive plate 17e by a bonding material. Solder or a sintered material may be used as the bonding material. Note that external terminals 13a, 13b, 14, and 15 may be connected to the respective conductive plates of insulating circuit board 17 by laser welding or ultrasonic welding.

[0031] The external terminals 13a and 13b are P terminals that serve as positive terminals in the half-bridge circuit, and the external terminal 14 is an N terminal that serves as a negative terminal in the half-bridge circuit. The external terminal 15 is an output terminal of the half-bridge circuit. Bosses p1, p2, p3, and p4 that protrude toward the insulating circuit board 17 are formed at the portions of the external terminals 13a, 13b, 14, and 15 where the bonding material contacts. The bosses p1, p2, p3, and p4 may be formed by pressing when the external terminals 13a, 13b, 14, and 15 are formed. The thickness of the bonding material can be ensured by adjusting the height of the bosses.

[0032] One end of post electrodes 31s, 32s, 33s, and 34s, each consisting of a plurality of electrodes, is connected to the source electrodes of semiconductor chips 11a1, 11b1, 11c1, and 11d1 by a bonding material. The other ends of post electrodes 31s, 32s, 33s, and 34s are connected to printed circuit board 18. One end of post electrodes 31g, 32g, 33g, and 34g is connected to the gate electrodes of semiconductor chips 11a1, 11b1, 11c1, and 11d1 by a bonding material. The other ends of post electrodes 31g, 32g, 33g, and 34g are connected to printed circuit board 18.

[0033] One end of post electrodes 35s, 36s, 37s, and 38s, each consisting of a plurality of electrodes, is connected to the source electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2 by a bonding material. The other ends of the post electrodes 35s, 36s, 37s, and 38s are connected to the printed circuit board 18. Furthermore, one end of post electrodes 35g, 36g, 37g, and 38g is connected to the gate electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2 by a bonding material. The other ends of the post electrodes 35g, 36g, 37g, and 38g are connected to the printed circuit board 18.

[0034] One end of post electrodes 41s, 42s, 43s, and 44s, each consisting of a plurality of electrodes, is connected to the source electrodes of semiconductor chips 12a1, 12b1, 12c1, and 12d1 by a bonding material. The other ends of post electrodes 41s, 42s, 43s, and 44s are connected to printed circuit board 18. One end of post electrodes 41g, 42g, 43g, and 44g is connected to the gate electrodes of semiconductor chips 12a1, 12b1, 12c1, and 12d1 by a bonding material. The other ends of post electrodes 41g, 42g, 43g, and 44g are connected to printed circuit board 18.

[0035] One end of each of post electrodes 45s, 46s, 47s, and 48s, each consisting of a plurality of electrodes, is connected to the source electrodes of each of the semiconductor chips 12a2, 12b2, 12c2, and 12d2 by a bonding material. The other ends of the post electrodes 45s, 46s, 47s, and 48s are connected to the printed circuit board 18. Furthermore, one end of each of post electrodes 45g, 46g, 47g, and 48g is connected to the gate electrodes of each of the semiconductor chips 12a2, 12b2, 12c2, and 12d2 by a bonding material. The other ends of the post electrodes 45g, 46g, 47g, and 48g are connected to the printed circuit board 18.

[0036] 2 shows a state in which one end of the post electrode 31s is connected to the source electrode of the semiconductor chip 11a1 via the bonding material 26, and the other end of the post electrode 31s is connected to the printed circuit board 18. Also shown is a state in which one end of the post electrode 31g is connected to the gate electrode of the semiconductor chip 11a1 via the bonding material 26, and the other end of the post electrode 31g is connected to the printed circuit board 18.

[0037] Furthermore, one end of post electrode 32s is connected to the source electrode of semiconductor chip 11b1 via bonding material 27, and the other end of post electrode 32s is connected to printed circuit board 18. Also, one end of post electrode 32g is connected to the gate electrode of semiconductor chip 11b1 via bonding material 27, and the other end of post electrode 32g is connected to printed circuit board 18.

[0038] Also shown is a state in which one end of a post electrode 41s is connected to the source electrode of the semiconductor chip 12a1 via the bonding material 28, and the other end of the post electrode 41s is connected to the printed circuit board 18. Also shown is a state in which one end of a post electrode 41g is connected to the gate electrode of the semiconductor chip 12a1 via the bonding material 28, and the other end of the post electrode 41g is connected to the printed circuit board 18.

[0039] Furthermore, one end of post electrode 42s is connected to the source electrode of semiconductor chip 12b1 via bonding material 29, and the other end of post electrode 42s is connected to printed circuit board 18. Also, one end of post electrode 42g is connected to the gate electrode of semiconductor chip 12b1 via bonding material 29, and the other end of post electrode 42g is connected to printed circuit board 18.

[0040] The above-mentioned bonding materials 21, 22, 23, 24, 25, 26, 27, 28, and 29 are made of, for example, solder. Lead-free solder is used as the solder. Lead-free solder mainly contains at least one of the following alloys: a tin-silver-copper alloy, a tin-antimony alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. A metal sintered body may be used instead of solder. The material of the metal sintered body is silver, gold, nickel, copper, or an alloy containing at least one of these.

[0041] On the other hand, one ends of conductive members 51 and 52 are connected to conductive plate 17c, and the other ends of conductive members 51 and 52 are connected to printed circuit board 18. Furthermore, one ends of intermediate conductive members 61 and 62 located in the middle between upper arm portion A and lower arm portion B are connected to conductive plate 17e, and the other ends of intermediate conductive members 61 and 62 are connected to printed circuit board 18.

[0042] 2 shows that one end of conductive pin terminal 71 is connected to conductive plate 17b and the other end penetrates and protrudes through printed circuit board 18. Also shown is that conductive pin terminal 72, connected to conductive plate 17d, penetrates and protrudes through printed circuit board 18. Furthermore, each of conductive pin terminals 73, 75, and 76 has one end connected to conductive plate 17e and the other end penetrates and protrudes through printed circuit board 18.

[0043] In semiconductor device 10, insulating circuit board 17 and printed circuit board 18 are connected via the post electrodes, conductive pin terminals, conductive members, and intermediate conductive members described above, providing a three-dimensional wiring structure on the semiconductor chip. With this configuration, printed circuit board 18 is supported above insulating circuit board 17, and semiconductor chips 11 and 12 are electrically connected via conductive layers, described below, formed on printed circuit board 18.

[0044] Semiconductor device 10 is provided with holes h1, h2, h3, h4, h5, h6, and h7 for fixing insulating circuit board 17 and printed circuit board 18 with mounting pins. Holes h1, h2, and h3 are formed in conductive plate 17d. Holes h4, h5, h6, and h7 are formed in conductive plate 17e.

[0045] 3 is a diagram showing an example of the circuit configuration of a semiconductor chip. The diagram shows an example of the configuration of the semiconductor chip 11 of the upper arm portion A and the semiconductor chip 12 of the lower arm portion B. The switching element of the semiconductor chip 11 is composed of a MOSFET 11-1 and a parasitic diode D1 of the MOSFET 11-1. The switching element of the semiconductor chip 12 is composed of a MOSFET 12-1 and a parasitic diode D2 of the MOSFET 12-1.

[0046] The drain electrode of MOSFET 11-1 is connected to the P terminal and the cathode of parasitic diode D1. The gate electrode of MOSFET 11-1 is connected to gate terminal G1. The source electrode of MOSFET 11-1 is connected to the anode of parasitic diode D1, auxiliary source terminal S1, output terminal OUT, the drain electrode of MOSFET 12-1, and the cathode of parasitic diode D2. The gate electrode of MOSFET 12-1 is connected to gate terminal G2. The source electrode of MOSFET 12-1 is connected to the anode of parasitic diode D2, auxiliary source terminal S2, and N terminal.

[0047] Next, the multilayer structure of printed circuit board 18 will be described with reference to Figures 4 to 7. Printed circuit board 18, which is disposed above insulating circuit board 17, has a multilayer structure formed by stacking multiple conductive layers, including a bottom conductive layer, an inner conductive layer, and a top wiring layer, with these layers disposed within insulating layers.

[0048] 4 is a diagram showing an example of the pattern configuration of the bottom conductive layer. The bottom conductive layer L4 is located at the bottom of the printed circuit board 18. On the upper arm side of the bottom conductive layer L4, the conductive layer 141 is connected to post electrodes 31s, 32s, 33s, and 34s connected to the source electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. The conductive layer 141 is also connected to post electrodes 35s, 36s, 37s, and 38s connected to the source electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively. The bottom conductive layer L4 is provided with an upper arm auxiliary source terminal connection portion 1s-4, which is connected to the conductive layer 141.

[0049] The conductive layers 143a, 143b, 143c, and 143d are connected to post electrodes 31g, 32g, 33g, and 34g, respectively, which are connected to the gate electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1. The conductive layers 144a, 144b, 144c, and 144d are connected to post electrodes 35g, 36g, 37g, and 38g, respectively, which are connected to the gate electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2. The lowermost conductive layer L4 is provided with a gate terminal connection portion 1g-4 on the upper arm side.

[0050] On the lower arm side of the bottom conductive layer L4, the conductive layer 142 is connected to post electrodes 41s, 42s, 43s, and 44s that are connected to the source electrodes of the semiconductor chips 12a1, 12b1, 12c1, and 12d1, respectively. The conductive layer 142 is also connected to post electrodes 45s, 46s, 47s, and 48s that are connected to the source electrodes of the semiconductor chips 12a2, 12b2, 12c2, and 12d2, respectively. A lower arm auxiliary source terminal connection portion 2s-4 is provided on the bottom conductive layer L4 and connected to the conductive layer 142.

[0051] Conductive layers 145a, 145b, 145c, and 145d are connected to post electrodes 41g, 42g, 43g, and 44g, respectively, which are connected to the gate electrodes of semiconductor chips 12a1, 12b1, 12c1, and 12d1. Conductive layers 146a, 146b, 146c, and 146d are connected to post electrodes 45g, 46g, 47g, and 48g, respectively, which are connected to the gate electrodes of semiconductor chips 12a2, 12b2, 12c2, and 12d2. A lower arm gate terminal connection portion 2g-4 is provided on the bottom conductive layer L4. Conductive layer 147 is connected to conductive member 51. Conductive layer 142 is connected to conductive member 52 at position pt2. Conductive layer 148a is connected to intermediate conductive member 61, and conductive layer 148b is connected to intermediate conductive member 62.

[0052] 5 and 6 are diagrams showing an example of the pattern configuration of the inner conductive layer. The inner conductive layer L3 shown in FIG. 5 is located between the bottom conductive layer L4 and the inner conductive layer L2 shown in FIG. 6. On the upper arm side of the inner conductive layer L3, the conductive layer 131 (first conductive layer) is connected to post electrodes 31s, 32s, 33s, and 34s connected to the source electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. Furthermore, the conductive layers 134a, 134b, 134c, and 134d are connected to post electrodes 31g, 32g, 33g, and 34g connected to the gate electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. Furthermore, an intermediate conductive member 61 is connected to the conductive layer 131 at position pt3.

[0053] The conductive layer 132 (first conductive layer) is connected to post electrodes 35s, 36s, 37s, and 38s, which are connected to the source electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively. The conductive layers 135a, 135b, 135c, and 135d are connected to post electrodes 35g, 36g, 37g, and 38g, which are connected to the gate electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively. An intermediate conductive member 62 is connected to the conductive layer 132 at position pt4.

[0054] The inner conductive layer L3 is provided with an upper arm side auxiliary source terminal connection portion 1s-3, which is connected to the auxiliary source terminal connection portion 1s-4 shown in Fig. 4. The inner conductive layer L3 is also provided with an upper arm side gate terminal connection portion 1g-3, which is connected to the gate terminal connection portion 1g-4 shown in Fig. 4.

[0055] On the lower arm side of the inner conductive layer L3, the conductive layer 133 (second conductive layer) is connected to post electrodes 41s, 42s, 43s, and 44s connected to the source electrodes of the semiconductor chips 12a1, 12b1, 12c1, and 12d1, respectively. Furthermore, the conductive layer 133 is connected to post electrodes 45s, 46s, 47s, and 48s connected to the source electrodes of the semiconductor chips 12a2, 12b2, 12c2, and 12d2, respectively.

[0056] Conductive layers 136a, 136b, 136c, and 136d are connected to post electrodes 41g, 42g, 43g, and 44g, respectively, which are connected to the gate electrodes of semiconductor chips 12a1, 12b1, 12c1, and 12d1. Conductive layers 137a, 137b, 137c, and 137d are connected to post electrodes 45g, 46g, 47g, and 48g, respectively, which are connected to the gate electrodes of semiconductor chips 12a2, 12b2, 12c2, and 12d2. Conductive member 51 is connected to conductive layer 133 at position pt1, and conductive member 52 is connected to conductive layer 133 at position pt2.

[0057] The inner conductive layer L3 is provided with a lower arm side auxiliary source terminal connection portion 2s-3, which is connected to the auxiliary source terminal connection portion 2s-4 shown in Fig. 4. The inner conductive layer L3 is also provided with a lower arm side gate terminal connection portion 2g-3, which is connected to the gate terminal connection portion 2g-4 shown in Fig. 4.

[0058] The inner conductive layer L2 shown in Fig. 6 is located between the inner conductive layer L3 and the top wiring portion L1 shown in Fig. 7. On the upper arm side of the inner conductive layer L2, the conductive layer 121 (first conductive layer) is connected to post electrodes 31s, 32s, 33s, and 34s connected to the source electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. Furthermore, the conductive layers 124a, 124b, 124c, and 124d are connected to post electrodes 31g, 32g, 33g, and 34g connected to the gate electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. Furthermore, an intermediate conductive member 61 is connected to the conductive layer 121 at position pt3.

[0059] The conductive layer 122 (first conductive layer) is connected to post electrodes 35s, 36s, 37s, and 38s, which are connected to the source electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively. The conductive layers 125a, 125b, 125c, and 125d are connected to post electrodes 35g, 36g, 37g, and 38g, which are connected to the gate electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively. An intermediate conductive member 62 is connected to the conductive layer 122 at position pt4.

[0060] The inner conductive layer L2 is provided with an upper arm auxiliary source terminal connection portion 1s-2, which is connected to the auxiliary source terminal connection portion 1s-3 shown in Fig. 5. The inner conductive layer L2 is also provided with an upper arm gate terminal connection portion 1g-2, which is connected to the gate terminal connection portion 1g-3 shown in Fig. 5.

[0061] On the lower arm side of the inner conductive layer L2, the conductive layer 123 (second conductive layer) is connected to post electrodes 41s, 42s, 43s, and 44s connected to the source electrodes of the semiconductor chips 12a1, 12b1, 12c1, and 12d1, respectively. Furthermore, the conductive layer 123 is connected to post electrodes 45s, 46s, 47s, and 48s connected to the source electrodes of the semiconductor chips 12a2, 12b2, 12c2, and 12d2, respectively.

[0062] Conductive layers 126a, 126b, 126c, and 126d are connected to post electrodes 41g, 42g, 43g, and 44g, respectively, which are connected to the gate electrodes of semiconductor chips 12a1, 12b1, 12c1, and 12d1. Conductive layers 127a, 127b, 127c, and 127d are connected to post electrodes 45g, 46g, 47g, and 48g, respectively, which are connected to the gate electrodes of semiconductor chips 12a2, 12b2, 12c2, and 12d2. Conductive layer 123 is connected to conductive member 51 at position pt1 and to conductive member 52 at position pt2.

[0063] The inner conductive layer L2 is provided with an auxiliary source terminal connection portion 2s-2 on the lower arm side, which is connected to the auxiliary source terminal connection portion 2s-3 shown in Fig. 5. The inner conductive layer L2 is also provided with a gate terminal connection portion 2g-2 on the lower arm side, which is connected to the gate terminal connection portion 2g-3 shown in Fig. 5.

[0064] 7 is a diagram showing an example of a pattern configuration of the uppermost layer wiring portion L1. The uppermost layer wiring portion L1 is located on the uppermost layer of the printed circuit board 18. In the uppermost layer wiring portion L1, a conductive layer is provided on an insulating layer 100.

[0065] On the upper arm side of the top layer wiring unit L1, the conductive layers 101a, 101b, 101c, and 101d are connected to post electrodes 31s, 32s, 33s, and 34s, respectively, which are connected to the source electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. In addition, the conductive layers 102a, 102b, 102c, and 102d are connected to post electrodes 35s, 36s, 37s, and 38s, respectively, which are connected to the source electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively.

[0066] The conductive layer 103 is connected to post electrodes 31g, 32g, 33g, and 34g that are connected to the gate electrodes of the semiconductor chips 11a1, 11b1, 11c1, and 11d1, respectively. Furthermore, the conductive layer 103 is connected to post electrodes 35g, 36g, 37g, and 38g that are connected to the gate electrodes of the semiconductor chips 11a2, 11b2, 11c2, and 11d2, respectively.

[0067] The uppermost layer wiring portion L1 is provided with an auxiliary source terminal connection portion 1s-1 on the upper arm side, which is connected to the auxiliary source terminal connection portion 1s-2 shown in Fig. 6. An auxiliary source terminal (corresponding to the auxiliary source terminal S1 shown in Fig. 3) is connected to the auxiliary source terminal connection portion 1s-1 as an external terminal.

[0068] Furthermore, the top layer wiring portion L1 is provided with a gate terminal connection portion 1g-1 on the upper arm side, and the gate terminal connection portion 1g-1 is connected to the gate terminal connection portion 1g-2 and the conductive layer 103 shown in Fig. 6. In addition, a gate terminal (corresponding to the gate terminal G1 shown in Fig. 3) is connected to the gate terminal connection portion 1g-1 as an external terminal.

[0069] On the lower arm side of the top layer wiring unit L1, the conductive layers 104a, 104b, 104c, and 104d are connected to post electrodes 41s, 42s, 43s, and 44s, respectively, which are connected to the source electrodes of the semiconductor chips 12a1, 12b1, 12c1, and 12d1, respectively. In addition, the conductive layers 105a, 105b, 105c, and 105d are connected to post electrodes 45s, 46s, 47s, and 48s, respectively, which are connected to the source electrodes of the semiconductor chips 12a2, 12b2, 12c2, and 12d2, respectively.

[0070] The conductive layer 106 is connected to post electrodes 41g, 42g, 43g, and 44g that are connected to the gate electrodes of the semiconductor chips 12a1, 12b1, 12c1, and 12d1, respectively. Furthermore, the conductive layer 106 is connected to post electrodes 45g, 46g, 47g, and 48g that are connected to the gate electrodes of the semiconductor chips 12a2, 12b2, 12c2, and 12d2, respectively.

[0071] The uppermost layer wiring portion L1 is provided with an auxiliary source terminal connection portion 2s-1 on the lower arm side, which is connected to the auxiliary source terminal connection portion 2s-2 shown in Fig. 6. An auxiliary source terminal (corresponding to the auxiliary source terminal S2 shown in Fig. 3) is connected to the auxiliary source terminal connection portion 2s-1 as an external terminal.

[0072] Furthermore, the uppermost layer wiring portion L1 is provided with a gate terminal connection portion 2g-1 on the lower arm side, which is connected to the gate terminal connection portion 2g-2 and the conductive layer 106 shown in Fig. 6. Furthermore, a gate terminal (corresponding to the gate terminal G2 shown in Fig. 3) is connected to the gate terminal connection portion 2g-1 as an external terminal.

[0073] On the other hand, the conductive layer 107a is connected to the conductive member 51, and the conductive layer 107b is connected to the conductive member 52. The conductive layer 108a is connected to the intermediate conductive member 61, and the conductive layer 108b is connected to the intermediate conductive member 62.

[0074] The insulating layer 100 of the printed circuit board 18 can be made of an insulating resin. Examples of insulating resins include phenolic resin, epoxy resin, polyimide resin, and glass epoxy resin. Furthermore, each of the conductive layers in the top wiring layer L1, the inner conductive layers L2 and L3, and the bottom conductive layer L4 of the printed circuit board 18 is formed of a metal with excellent conductivity. Examples of such metals include copper, aluminum, and alloys containing at least one of these. The surfaces of the conductive layers may be plated to improve corrosion resistance. Examples of plating materials used in this case include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, and alloys containing at least one of these.

[0075] 8 is a diagram showing an example of the overall appearance of a semiconductor device. The insulating circuit board 17 and printed circuit board 18 mounted on the cooler 8 are fixed by fitting the mounting pins Pn11, Pn12, Pn13, Pn14, Pn15, Pn16, and Pn17 into the holes h1, h2, h3, h4, h5, h6, and h7 shown in FIG. 1, respectively. The insulating circuit board 17 and printed circuit board 18 are then sealed with the insulating sealing member 10a.

[0076] The insulating sealing member 10a may be a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. Epoxy resin is preferable. Furthermore, the insulating sealing member 10a may be an underfill material. The underfill material contains, for example, an epoxy resin as a main component, has a curing temperature of approximately 180°C, and contains a filler material made of an inorganic material. The filler material may be, for example, an inorganic material with high thermal conductivity, such as boron nitride, aluminum nitride, or silicon nitride.

[0077] Here, we will explain the flow of signals through the printed circuit board 18 when current is applied to the semiconductor chips 11 and 12. The conductive layers 131 and 132 (first conductive layers) of the inner conductive layer L3 of the printed circuit board 18 and the conductive layers 121 and 122 (first conductive layers) of the inner conductive layer L2 are conductively connected to the source electrode of the semiconductor chip 11 of the upper arm portion A.

[0078] Furthermore, the conductive layer 131 of the inner conductive layer L3 and the conductive layer 121 of the inner conductive layer L2 are conductively connected to an intermediate conductive member 61 connected to the conductive plate 17e (second conductive plate) of the insulating circuit board 17, and the conductive layer 132 of the inner conductive layer L3 and the conductive layer 122 of the inner conductive layer L2 are conductively connected to an intermediate conductive member 62 connected to the conductive plate 17e of the insulating circuit board 17.

[0079] Therefore, when the semiconductor chip 11 is turned on, the signal output from the source electrode through the drain electrode of the semiconductor chip 11 flows toward the conductive layers 131, 132, 121, and 122 of the printed circuit board 18, and the signal that has flowed through the conductive layers 131, 132, 121, and 122 flows toward the conductive plate 17e through the intermediate conductive members 61 and 62 of the insulating circuit board 17 (source electrode of the semiconductor chip 11 → first conductive layer → second conductive plate via the intermediate conductive member).

[0080] The conductive plate 17e on which the intermediate conductive members 61 and 62 are arranged is connected to the drain electrode of the semiconductor chip 12 of the lower arm portion B. Furthermore, the conductive layer 133 (second conductive layer) of the inner conductive layer L3 of the printed circuit board 18 and the conductive layer 123 (second conductive layer) of the inner conductive layer L2 are conductively connected to the source electrode of the semiconductor chip 12.

[0081] Therefore, the signal that flows from the printed circuit board 18 through the intermediate conductive members 61 and 62 and the conductive plate 17e is input to the drain electrode of the semiconductor chip 12. When the semiconductor chip 12 is turned on, the signal is output from the source electrode through the drain electrode of the semiconductor chip 12, and further flows toward the conductive layers 133 and 123 of the printed circuit board 18 (second conductive plate → drain electrode of the semiconductor chip 12, source electrode → second conductive layer).

[0082] Furthermore, conductive layers 133, 123 of printed circuit board 18 are conductively connected to conductive members 51, 52 which are connected to conductive plate 17c (third conductive plate) of insulating circuit board 17, and external terminal 14 (N terminal) is connected to conductive plate 17c. Therefore, the signal that has flowed through conductive layers 133, 123 of printed circuit board 18 flows toward conductive members 51, 52 of insulating circuit board 17, and the signal that has flowed through conductive members 51, 52 flows to external terminal 14 (second conductive layer → via conductive member, third conductive plate → external terminal (N terminal)).

[0083] In this way, semiconductor device 10 has a configuration in which conductive plate 17c extending from the center toward the outer edge of insulated circuit board 17 is connected to conductive layers 133, 123 of printed circuit board 18 by conductive members 51, 52, and signals flowing through printed circuit board 18 are directed to the conductive plate 17c side of insulated circuit board 17, thereby ensuring a heat dissipation path for printed circuit board 18. This makes it possible to suppress the generation of Joule heat in printed circuit board 18 when semiconductor chips 11, 12 are energized, and makes it possible to improve the heat dissipation capability of printed circuit board 18.

[0084] Next, the shapes of the conductive members 51 and 52 will be described using FIGS. 9 to 11 . Since the conductive members 51 and 52 are the same component, only the conductive member 51 will be described. FIG. 9 illustrates a first configuration example of the conductive members. The conductive member 51-1 of the first configuration example includes a conductive base 51a and multiple conductive pins 51b. The lower surface of the conductive base 51a is connected to the conductive plate 17c, and the conductive pins 51b are connected to the upper surface of the conductive base 51a. The conductive pins 51b are inserted into the printed circuit board 18 and, with respect to the inner conductive layers L3 and L2, are connected to the conductive layer 133 of the inner conductive layer L3 and the conductive layer 123 of the inner conductive layer L2. The center-to-center spacing of the conductive pins 51b is, for example, 1.2 mm or more. The number of conductive pins 51b can be any number depending on the design.

[0085] 10 is a diagram showing a second configuration example of a conductive member. The conductive member 51-2 of the second configuration example includes a conductive base portion 51a and a single conductive block 51c. The lower surface of the conductive base portion 51a is connected to the conductive plate 17c, and the conductive block 51c is connected to the upper surface of the conductive base portion 51a. The conductive block 51c is inserted into the printed circuit board 18 and, with respect to the inner conductive layers L3 and L2, is connected to the conductive layer 133 of the inner conductive layer L3 and the conductive layer 123 of the inner conductive layer L2.

[0086] 11 is a diagram showing a third example of the conductive member. The conductive member of the third example is a conductive inlay 51-3. The conductive inlay 51-3 is embedded in the printed circuit board 18, and with respect to the inner conductive layers L3 and L2, is connected to the conductive layer 133 of the inner conductive layer L3 and the conductive layer 123 of the inner conductive layer L2. The bottom surface of the conductive inlay 51-3 is connected to the conductive plate 17c.

[0087] The conductive members 51, 52 and the intermediate conductive members 61, 62 are made of a metal with excellent conductivity and heat dissipation properties. Examples of such metals include copper, aluminum, or an alloy containing at least one of these. The conductive plates 17b, 17c, 17d, and 17e may be plated to improve their corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0088] Next, the shape of the conductive plate 17c (third conductive plate) will be described with reference to FIG. 12 . FIG. 12 is a diagram illustrating an example of the shape of the conductive plate. The conductive plate 17c includes a first conductive pattern member 17c1 having a first width w1 and to which the external terminal 14 is connected, and a second conductive pattern member 17c2 having a second width w2 smaller than the first width w1 and extending a predetermined length d from the center of the insulating circuit board 17 toward the outer edge. The second width w2 may be 2 mm or more and 10 mm or less. The predetermined length d may be 5 mm or more and 60 mm or less. For example, the second width w2 may be 4 mm, and the predetermined length d may be 28 mm.

[0089] Next, a semiconductor device according to a first reference example will be described with reference to Figures 13 and 14. Figure 13 is a diagram showing an example of a cross section of a semiconductor device according to a first reference example. A semiconductor device 200 according to the first reference example includes a semiconductor chip and an insulating circuit board, and has a wiring structure using wires and a lead frame.

[0090] In semiconductor device 200, heat sink 202 is mounted on the top surface of cooler 201 so that one surface faces the top surface, and insulating circuit board 203 is mounted on the other surface of heat sink 202. Insulating circuit board 203 has insulating member 204, metal plate 205, and conductive plates 206a, 206b, and 206c. Metal plate 205 of insulating circuit board 203 is connected to heat sink 202 via bonding material 207. Semiconductor chip 208 is connected to conductive plate 206b of insulating circuit board 203 via bonding material 209.

[0091] On the other hand, wire 210 is a bonding wire made of aluminum, and connects the upper surface electrode of semiconductor chip 208 and conductive plate 206a. One end of lead frame 211 is connected to the upper surface electrode of semiconductor chip 208 via bonding material 212, and the other end of lead frame 211 is connected to conductive plate 206c via bonding material 213. Insulated circuit board 203 on which semiconductor chip 208 is mounted is sealed with insulating sealing member 214.

[0092] 14 is a diagram showing an example of a cross section of a semiconductor device according to a second embodiment. A semiconductor device 300 according to the second embodiment includes a semiconductor chip and an insulating circuit board, and has a wiring structure using a printed circuit board and pin terminals.

[0093] One surface of heat sink 302 is mounted on the top surface of cooler 301 so as to face the top surface, and insulating circuit board 303 is mounted on the other surface of heat sink 302. Insulating circuit board 303 has insulating member 304, metal plate 305, and conductive plates 306a and 306b. Metal plate 305 of insulating circuit board 303 is connected to heat sink 302 via bonding material 307.

[0094] Semiconductor chip 309a is connected to conductive plate 306a of insulating circuit board 303 via bonding material 308a, and semiconductor chip 311a is further connected via bonding material 310a. Semiconductor chip 309b is connected to conductive plate 306b of insulating circuit board 303 via bonding material 308b, and semiconductor chip 311b is further connected via bonding material 310b.

[0095] Printed circuit board 312 has a multilayer structure in which insulating layers 321 and 322 and conductive layers 331, 332, and 333 are stacked one on top of the other, and is disposed opposite insulating circuit board 303. One end of conductive pin terminals p31 and p32 is connected to an upper surface electrode of semiconductor chip 309a via bonding material 314a, and the other end passes through printed circuit board 312 to be connected to conductive layers 331, 332, and 333. One end of conductive pin terminals p33 and p34 is connected to an upper surface electrode of semiconductor chip 311a via bonding material 315a, and the other end passes through printed circuit board 312 to be connected to conductive layers 331, 332, and 333.

[0096] The conductive pin terminals p35 and p36 have one end connected to the upper surface electrode of the semiconductor chip 309b via the bonding material 314b, and the other end passing through the printed circuit board 312 to be connected to the conductive layers 331, 332, and 333. The conductive pin terminals p37 and p38 have one end connected to the upper surface electrode of the semiconductor chip 311b via the bonding material 315b, and the other end passing through the printed circuit board 312 to be connected to the conductive layers 331, 332, and 333.

[0097] One end of conductive pin terminal p39a is connected to conductive plate 306a via bonding material 318a, and the other end protrudes through printed circuit board 312. One end of conductive pin terminal p39b is connected to conductive plate 306b via bonding material 318b, and the other end protrudes through printed circuit board 312. Insulated circuit board 303 and printed circuit board 312, on which semiconductor chips 309a, 311a, 309b, and 311b are mounted, are sealed with insulating sealing member 340.

[0098] In the semiconductor device 300, the conductive pin terminals p31, p32, p33, p34, p35, p36, p37, p38, p39a, and p39b are connected to the printed circuit board 312 and the insulating circuit board 303, thereby supporting the printed circuit board 312 and further electrically connecting two sets of circuit units through the printed circuit board 312.

[0099] Here, wires and lead frames are used as the wiring structure in the semiconductor device 200 of the first reference example. In the case of such a wiring structure of wires and lead frames, it is necessary to provide a plurality of connection areas such as bonding areas on the insulating circuit board 203 in order to form a circuit, which makes it difficult to miniaturize the device.

[0100] On the other hand, the semiconductor device 300 of the second reference example has a wiring structure that includes a printed circuit board and pin terminals. This eliminates the need to provide multiple connection areas on an insulating circuit board, as is the case with a wiring structure that uses wires and lead frames, enabling high-density packaging and miniaturization of the device.

[0101] However, the printed circuit board 312 placed on top of the semiconductor chip has a structure in which the wiring of each semiconductor chip is aggregated, so when the semiconductor chip is energized, Joule heat increases, the amount of heat generated by the printed circuit board 312 increases, and heat dissipation performance deteriorates.

[0102] In contrast, semiconductor device 10 of the present embodiment is configured such that a heat dissipation pattern member (conductive plate 17c) is provided on insulating circuit board 17, and the heat dissipation pattern member of insulating circuit board 17 is connected to the conductive layer of printed circuit board 18 disposed opposite insulating circuit board 17 by conductive members 51 and 52, thereby dissipating Joule heat generated on printed circuit board 18 to the insulating circuit board 17 side via conductive members 51 and 52. This makes it possible to reduce the size of the device and further improve the heat dissipation capacity of printed circuit board 18.

[0103] 15 is a diagram showing the results of an analysis of Joule heat in a printed circuit board. The temperature in the central portion of the printed circuit board of a semiconductor device before improvement (e.g., semiconductor device 300 of the second reference example) reaches a maximum temperature of 210°C when the semiconductor chip is energized. In contrast, the maximum temperature in the central portion of the printed circuit board 18 of the semiconductor device 10 after improvement has been reduced to 143°C, achieving a temperature reduction of 30%.

[0104] Although the embodiments have been illustrated above, the configuration of each part shown in the embodiments may be replaced with another having a similar function. Furthermore, any other components or steps may be added. Furthermore, any two or more of the configurations (features) of the above-described embodiments may be combined. The above merely illustrates the principles of the present invention. Furthermore, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and applications shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0105] 10 Semiconductor device 11, 11a1, 11b1, 11c1, 11d1, 11a2, 11b2, 11c2, 11d2 Semiconductor chip (upper arm semiconductor chip) 12, 12a1, 12b1, 12c1, 12d1, 12a2, 12b2, 12c2, 12d2 Semiconductor chip (lower arm semiconductor chip) 13a, 13b External terminal (P terminal) 14 External terminal (N terminal) 15 External terminal (output terminal) 16 Heat sink 17 Insulated circuit board 17a Insulating member 17b, 17d Conductive plate (first conductive plate) 17e Conductive plate (second conductive plate) 17c Conductive plate (third conductive plate) 17f Metal plate 18 Printed circuit board 21, 22, 23, 24, 25, 26, 27, 28, 29 Bonding material 31s, 32s, 33s, 34s, 35s, 36s, 37s, 38s Post electrodes (connecting source electrodes of upper arm semiconductor chips) 31g, 32g, 33g, 34g, 35g, 36g, 37g, 38g Post electrodes (connecting gate electrodes of upper arm semiconductor chips) 41s, 42s, 43s, 44s, 45s, 46s, 47s, 48s Post electrodes (connecting source electrodes of lower arm semiconductor chips) 41g, 42g, 43g, 44g, 45g, 46g, 47g, 48g Post electrodes (connecting gate electrodes of lower arm semiconductor chips) 51, 52 Conductive members 61, 62 Intermediate conductive members 71, 72, 73, 74, 75, 76 Conductive pin terminal 8 Cooler 11-1, 12-1 MOSFET 100 Insulating layer 101a, 101b, 101c, 101d, 102a, 102b, 102c, 102d Conductive layer (source electrode connection of upper arm semiconductor chip) 103 Conductive layer (gate electrode connection of upper arm semiconductor chip) 104a, 104b, 104c, 104d, 105a, 105b, 105c, 105d Conductive layer (source electrode connection of lower arm semiconductor chip) 106 Conductive layer (gate electrode connection of lower arm semiconductor chip) 107a, 107b Conductive layer (conductive member connection) 108a, 108b Conductive layer (intermediate conductive member connection) 121, 122 Conductive layer (first conductive layer) 124a, 124b, 124c, 124d, 125a, 125b, 125c, 125d: Conductive layer (gate electrode connection of upper arm semiconductor chip) 123: Conductive layer (second conductive layer)126a, 126b, 126c, 126d, 127a, 127b, 127c, 127d Conductive layer (gate electrode connection of lower arm semiconductor chip) 131, 132 Conductive layer (first conductive layer) 134a, 134b, 134c, 134d, 135a, 135b, 135c, 135d Conductive layer (gate electrode connection of upper arm semiconductor chip) 133 Conductive layer (second conductive layer) 136a, 136b, 136c, 136d, 137a, 137b, 137c, 137d Conductive layer (gate connection of lower arm semiconductor chip) 141 Conductive layer (source electrode connection of upper arm semiconductor chip) 143a, 143b, 143c, 143d, 144a, 144b, 144c, 144d Conductive layer (gate electrode connection of upper arm semiconductor chip) 142 Conductive layer (source electrode connection of lower arm semiconductor chip) 145a, 145b, 145c, 145d, 146a, 146b, 146c, 146d Conductive layer (gate electrode connection of lower arm semiconductor chip) 147 Conductive layer (conductive member connection) 148a, 148b Conductive layer (intermediate conductive member connection) 1s-1, 1s-2, 1s-3, 1s-4 Auxiliary source terminal connection (for upper arm semiconductor chip) 1g-1, 1g-2, 1g-3, 1g-4 Gate terminal connection (for upper arm semiconductor chip) 2s-1, 2s-2, 2s-3, 2s-4 Auxiliary source terminal connection (for lower arm semiconductor chip) 2g-1, 2g-2, 2g-3, 2g-4 Gate terminal connection (for upper arm semiconductor chip) 10a DESCRIPTION OF REFERENCE NUMERALS Insulating sealing member 51-1, 51-2 Conductive member 51-3 Conductive inlay 51a Conductive base portion 51b Conductive pin 51c Conductive block 17c1 First conductive pattern member 17c2 Second conductive pattern member w1 First width w2 Second width d Predetermined length 200 Semiconductor device (first reference example) 201 Cooler 202 Heat sink 203 Insulating circuit board 204 Insulating member 205 Metal plate 206a, 206b, 206c Conductive plate 207, 209, 212, 213 Bonding material 208 Semiconductor chip 210 Wire 211 Lead frame 214 Insulating sealing member 300 Semiconductor device (second reference example) 301 Cooler 302 Heat sink 303 Insulating circuit board 304 Insulating member 305 Metal plate306a, 306b Conductive plates 307, 308a, 308b, 310a, 310b, 314a, 315a, 314b, 315b, 318a, 318b Bonding material 309a, 311a, 309b, 311b Semiconductor chip 312 Printed circuit board 321, 322 Insulating layer 331, 332, 333 Conductive layer 340 Insulating sealing member A Upper arm portion B Lower arm portion h1, h2, h3, h4, h5, h6, h7 Hole p1, p2, p3, p4 Boss D1, D2 Parasitic diode S1, S2 Auxiliary source terminal G1, G2 Gate terminal L1 Top layer wiring portion L2, L3 Inner layer conductive layer L4 Bottom layer conductive layer pt1, pt2: Conductive member connection positions pt3, pt4: Intermediate conductive member connection positions Pn11, Pn12, Pn13, Pn14, Pn15, Pn16, Pn17: Mounting pins p31, p32, p33, p34, p35, p36, p37, p38, p39a, p39b: Pin terminals

Claims

1. An insulated circuit board having a first conductive plate, a second conductive plate, and a third conductive plate arranged on an insulating member; a first semiconductor chip arranged on the first conductive plate; a first external terminal connected to the first conductive plate; a second semiconductor chip arranged on the second conductive plate; a second external terminal connected to the second conductive plate; a third external terminal connected to the third conductive plate; a first conductive layer conductively connected to an upper surface electrode of the first semiconductor chip and the second conductive plate; a second conductive layer conductively connected to an upper surface electrode of the second semiconductor chip and the third conductive plate; and an insulating layer arranged between the first conductive layer and the second conductive layer, the printed circuit board arranged opposite the insulated circuit board with the first semiconductor chip and the second semiconductor chip sandwiched between them; a cooler is provided on the underside of the insulating member; the third conductive plate extends from the center toward the outer edge of the insulated circuit board; and the second conductive layer is arranged opposite the third conductive plate; a conductive member connecting the third conductive plate and the second conductive layer; 2. The semiconductor device of claim 1, wherein the third conductive plate includes a first conductive pattern member having a first width to which the third external terminal is connected, and a second conductive pattern member having a second width smaller than the first width and extending a predetermined length from the center of the insulating circuit board toward the outer edge.

3. The semiconductor device according to claim 2, wherein said second width is 2 mm or more and 10 mm or less, and said predetermined length is 5 mm or more and 60 mm or less.

4. The semiconductor device according to claim 1, wherein said conductive member includes a plurality of conductive pins connecting said third conductive plate and said second conductive layer.

5. The semiconductor device according to claim 4, wherein the center-to-center spacing of said conductive pins is 1.2 mm or more.

6. The semiconductor device according to claim 1, wherein said conductive member includes a single conductive block connecting said third conductive plate and said second conductive layer.

7. The semiconductor device according to claim 1, wherein said conductive member is a conductive inlay embedded in said printed circuit board.

8. The semiconductor device according to claim 1, further comprising an intermediate conductive member connected to said second conductive plate and located in the middle of said insulating circuit board, said first conductive layer being conductively connected to the upper surface electrode of said first semiconductor chip and said second conductive plate through said intermediate conductive member.

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