Light detection device

Abstract

This light detection device includes: a first photoelectric conversion unit; a first charge accumulation unit directly connected to the first photoelectric conversion unit; a first amplification transistor connected to the first charge accumulation unit; a second photoelectric conversion unit; a second charge accumulation unit directly connected to the second photoelectric conversion unit; a second amplification transistor connected to the second charge accumulation unit; and a switch transistor electrically connected between the first charge accumulation unit and the second charge accumulation unit.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] For example, as disclosed in Japanese Patent Application Laid-Open No. 2003-129999, a technique is known in which a transfer transistor for transferring charges from a photodiode to an FD (floating diffusion region) is provided between them.

[0003] JP 2023-129340 A JP 2018-191270 A

[0004] As miniaturization progresses, the transfer path of the transfer transistor may become narrower, and the transfer characteristics may deteriorate.

[0005] One aspect of the present disclosure addresses challenges associated with miniaturization.

[0006] A photodetector according to one aspect of the present disclosure includes a first photoelectric conversion unit, a first charge accumulation unit directly connected to the first photoelectric conversion unit, a first amplification transistor connected to the first charge accumulation unit, a second photoelectric conversion unit, a second charge accumulation unit directly connected to the second photoelectric conversion unit, a second amplification transistor connected to the second charge accumulation unit, and a switch transistor electrically connected between the first charge accumulation unit and the second charge accumulation unit.

[0007] A photodetector according to one aspect of the present disclosure includes a first semiconductor substrate, a first photoelectric conversion unit formed on the first semiconductor substrate, a first charge accumulation unit formed on the first semiconductor substrate and directly connected to the first photoelectric conversion unit in a direction of the substrate thickness, a second photoelectric conversion unit formed on the first semiconductor substrate, a second charge accumulation unit formed on the first semiconductor substrate and directly connected to the second photoelectric conversion unit in a direction of the substrate thickness, and a charge accumulation unit formed on the first semiconductor substrate and positioned between the first photoelectric conversion unit and the second photoelectric conversion unit. the first contact extends from the first charge storage portion to the second semiconductor substrate; and a second contact extends from the second charge storage portion to the second semiconductor substrate, wherein the first contact and the second contact are spaced apart from the separation portion when viewed in plan.

[0008] 1 is a diagram illustrating an example of a schematic configuration of a photodetection device 100 according to an embodiment. FIG. 1 is a diagram illustrating an example of a pixel circuit. FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection element 1. FIG. 3 is a diagram illustrating an example of a schematic configuration of a photodetection element 1. FIG. 4 is a diagram illustrating an example of an arrangement of contacts 6 and the like. FIG. 5 is a diagram illustrating an example of an arrangement of contacts 6 and the like. FIG. 6 is a diagram illustrating an example of four-pixel addition. FIG. 7 is a diagram illustrating an example of four-pixel addition. FIG. 8 is a diagram illustrating an example of eight-pixel addition. FIG. 9 is a diagram illustrating an example of a schematic configuration of a photodetection element 1. FIG. 10 is a diagram illustrating an example of a timing chart. FIG. 11 is a diagram illustrating an example of a noise cancellation circuit. FIG. 12 is a diagram illustrating another example of a noise cancellation circuit. FIG. 13 is a diagram illustrating an example of boost wiring. FIG. 14 is a diagram illustrating an example of a schematic configuration of a photodetection element 1. FIG. 15 is a diagram illustrating an example of a pixel circuit. FIG. 16 is a diagram illustrating an example of a pixel circuit. FIG. 17 is a diagram illustrating an example of a pixel circuit. FIG. 18 is a diagram illustrating an example of a mask member. FIG. 19 is a diagram illustrating another example of a mask member. FIG. 19 is a diagram illustrating another example of a mask member. FIG. 19 is a diagram illustrating an example of a schematic configuration of a photodetection element 1. FIG. 10 is a diagram illustrating an example of a schematic configuration of a trench portion 9 and its periphery. FIG. 11 is a diagram illustrating an example of a schematic configuration of a photodetection element 1. FIG. 12 is a diagram illustrating an example of a cell size design. FIG. 1 is a diagram showing an example of cell size design. FIG. 2 is a diagram showing an example of cell size design. FIG. 3 is a diagram showing an example of a timing chart. FIG. 4 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 5 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit. FIG. 6 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 7 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0010] The present disclosure will be described in the following order: 0. Introduction 1. Embodiment 2. Modifications 2.1 4-pixel addition 2.2 8-pixel addition (4×2-pixel addition) 2.3 Modifications of separation section 2.4 Noise removal 2.5 Boost wiring 2.6 F2F stacking 2.7 Sharing reset transistor 2.8 Variable range of charge storage section 2.9 Countermeasures against dark current 2.10 Well contact arrangement, hole storage layer 2.11 Cell size design 2.12 Hole evacuation 2.13 Others 3. Conclusion 4. Application example to a moving body 5. Application example to an endoscopic surgery system

[0011] 0. Introduction The image sensor of Patent Document 1 includes a transfer transistor provided between a photodiode and an FD. The vertical transfer transistor forms a transfer path to the Si (silicon) surface. In a configuration including such a transfer transistor, as pixels become smaller, the following problems may arise: The transfer path becomes narrower, deteriorating transfer characteristics and degrading low-light image quality. With regard to the design of the saddle point (e.g., threshold voltage) of the transfer transistor, misalignment of impurities leads to increased differences between pixels. The transfer electric field needs to be increased, resulting in a trade-off with Qs (amount of charge that can be stored).

[0012] The disclosed technology addresses at least some of the above-mentioned problems. For example, it suppresses the deterioration of transfer characteristics that accompanies miniaturization. As will be described in detail later, the photodetector is configured not to include a transfer transistor. Furthermore, based on this configuration, further technical features are combined.

[0013] 1. Embodiment FIG. 1 is a diagram illustrating an example of a schematic configuration of a photodetector 100 according to an embodiment. The illustrated photodetector 100 is a solid-state imaging device (also referred to as an image sensor, etc.), and each element is provided within and on a silicon semiconductor substrate, for example. The photodetector 100 includes a photodetector element 1, as well as peripheral circuits and signal lines. Examples of the peripheral circuits are illustrated as a control circuit 101, a vertical drive circuit 102, a column signal processing circuit 103, a horizontal drive circuit 104, and an output circuit 105, each of which is designated by a reference numeral. Examples of the wiring are illustrated as a signal line 106, a signal line 107, and a signal line 108, each of which is designated by a reference numeral. Another element illustrated is a frame memory M1. The frame memory M1 may be provided within a semiconductor chip constituting the photodetector 100, or may be provided outside the chip.

[0014] The photodetector element 1 includes a plurality of pixels 2 (which may also be referred to as a plurality of photodetector sections or a plurality of photodetector cells, etc.). The plurality of pixels 2 are arranged in a two-dimensional array. It can be said that the photodetector element 1 includes a pixel array section. FIG. 1 also shows an XYZ coordinate system for the photodetector element 1. The X-axis direction corresponds to the row direction of the array, for example, the lateral direction (horizontal direction) of the photodetector device 100. The Y-axis direction corresponds to the column direction of the array, for example, the longitudinal direction (vertical direction) of the photodetector device 100. The Z-axis direction corresponds to the front-to-rear direction (up-and-down direction) of the photodetector device 100. The positive Z-axis direction and the negative Z-axis direction are also referred to as the upward and downward directions.

[0015] The photodetector element 1 detects incident light. Unless otherwise specified, the photodetector element 1 detects light traveling from the front to the rear of the photodetector device 100 (toward the negative direction of the Z axis).

[0016] The pixel 2 includes a photoelectric conversion unit. The photoelectric conversion unit generates an electric charge according to the amount of incident light. An example of the photoelectric conversion unit is a photodiode (PD). A circuit is also provided that generates and outputs a voltage signal (pixel signal) according to the amount of electric charge generated in the photoelectric conversion unit. The pixel 2 may be interpreted as including such a circuit, and in this case, the pixel 2 may also be called a pixel circuit.

[0017] The control circuit 101 receives data instructing an input clock, an operation mode, etc., and outputs data such as internal information of the photodetector device 100. The control circuit 101 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 102, the column signal processing circuit 103, the horizontal drive circuit 104, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 101 inputs (supplies) these generated signals to the vertical drive circuit 102, the column signal processing circuit 103, the horizontal drive circuit 104, etc.

[0018] The vertical drive circuit 102 includes, for example, a shift register. The vertical drive circuit 102 is connected to the photodetector elements 1 via a plurality of signal lines 106 (horizontal signal lines) extending in the row direction of the pixels 2. Each signal line 106 extends, for example, for each pixel row, and each signal line 106 may include a plurality of signal lines. The vertical drive circuit 102 supplies a drive signal (for example, a pulse signal) for driving the pixels 2 to a selected signal line 106.

[0019] Driving the pixels 2 by the vertical drive circuit 102 includes driving transistors (FIG. 2) described below. The transistors are driven to output voltage signals (pixel signals) corresponding to the amount of charge generated in the photoelectric conversion units in the pixels 2 to corresponding signal lines 107 among a plurality of signal lines 107 (vertical signal lines) extending in the column direction of the pixels 2.

[0020] The column signal processing circuits 103 are connected to the photodetector elements 1 via signal lines 107. Each signal line 107 may include multiple signal lines. The column signal processing circuits 103 are arranged, for example, for each pixel column, and perform signal processing such as noise removal on pixel signals from one row of pixels 2 for each pixel column. The column signal processing circuits 103 perform signal processing such as CDS (Correlated Double Sampling) to remove fixed pattern noise specific to the pixels 2, signal amplification, and AD (Analog to Digital) conversion. As will be described later, noise removal may include removal of KTC noise, for which a frame memory M1 may be used. A horizontal selection switch (not shown) may be connected between the output stage of the column signal processing circuit 103 and the signal line 107.

[0021] The horizontal drive circuit 104 includes, for example, a shift register. The horizontal drive circuit 104 sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 103 in turn, and causes each of the column signal processing circuits 103 to output a pixel signal to a signal line 108.

[0022] The output circuit 105 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuits 103 through the signal line 108, and outputs the processed signals. For example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. are performed on the pixel signals.

[0023] 2 is a diagram showing an example of a pixel circuit. Two pixels 2 arranged side by side in the row direction of the array are shown as an example. The pixels 2 are referred to as pixel 2-1 and pixel 2-2 in the drawing. When there is no particular distinction between them, they are simply referred to as pixel 2.

[0024] The photoelectric conversion unit included in the pixel 2 is illustrated and referred to as the photoelectric conversion unit 3. As described above, the photoelectric conversion unit 3 generates electric charges according to the amount of incident light. In Fig. 2, the photoelectric conversion unit 3 is illustrated as a photodiode with an anode connected to GND (ground).

[0025] The charge storage unit 4 and a plurality of transistors are exemplified as elements of a circuit (pixel circuit) provided around the photoelectric conversion unit 3. In the following description, when a transistor is connected between two elements, it means that one of the source and drain of the transistor is connected to one element, and the other of the source and drain is connected to the other element. In addition, the photoelectric conversion unit 3, charge storage unit 4, transistor, etc. included in the same pixel 2 are also referred to as the corresponding photoelectric conversion unit 3, charge storage unit 4, transistor, etc.

[0026] The charge accumulation section 4 is configured to include an FD (floating diffusion). The charge accumulation section 4 is directly connected to the corresponding photoelectric conversion section 3. The pixel 2 does not include a transfer transistor such as that used in Patent Document 1, and the charge accumulation section 4 is connected to the photoelectric conversion section 3 without going through such a transfer transistor. The charge generated in the photoelectric conversion section 3 moves from the photoelectric conversion section 3 to the charge accumulation section 4 as it is generated. It can also be said that the charge is automatically transferred from the photoelectric conversion section 3 to the charge accumulation section 4. The charge accumulation section 4 accumulates the charge from the photoelectric conversion section 3 and generates a voltage signal according to the accumulated charge.

[0027] The transistors are exemplified by a reset transistor 51, an amplifier transistor 52, a selection transistor 53, and a switch transistor 54. When there is no need to distinguish between them, they are simply called transistors.

[0028] The reset transistor 51 is connected between the charge storage unit 4 and the power supply node VDD, and discharges the charge stored in the charge storage unit 4 to the power supply node VDD. The letters RST indicating the reset transistor are also shown in the figure.

[0029] The gate electrode of the reset transistor 51 is connected to a corresponding signal line 106. The reset transistor 51 is turned on and off by a control signal from the signal line 106. When the reset transistor 51 is on, the charge in the charge accumulation unit 4 is discharged to the power supply node VDD via the reset transistor 51. The charge in the photoelectric conversion unit 3, which is directly connected to the charge accumulation unit 4, is also discharged.

[0030] The amplifier transistor 52 is connected between a power supply node VDD and the selection transistor 53. The gate of the amplifier transistor 52 is connected to the corresponding charge storage unit 4. The amplifier transistor 52 amplifies and outputs the voltage generated in the corresponding charge storage unit 4. The letters AMP indicating the amplifier transistor are also shown in the figure.

[0031] The selection transistor 53 is connected between the corresponding amplification transistor 52 and a signal line 107. The selection transistor 53 selectively outputs the output voltage of the corresponding amplification transistor 52 to the signal line 107. The letters SEL indicating the selection transistor are also shown.

[0032] The gate electrode of the selection transistor 53 is connected to a corresponding signal line 106. The selection transistor 53 is turned on and off by a control signal from the signal line 106. When the selection transistor 53 is on, the output voltage of the amplification transistor 52 is output to a signal line 107 via the selection transistor 53. This voltage signal can become a pixel signal.

[0033] The switch transistor 54 is electrically connected between two or more charge storage units 4, in other words, between the charge storage units 4 of two or more pixels 2. In the example shown in Fig. 2, the switch transistor 54 is connected between two charge storage units 4 and electrically connects or disconnects them. The letters SW indicating the switch transistor are also shown.

[0034] The switch transistor 54 of pixel 2-1 and the switch transistor 54 of pixel 2-2 are connected in series between the charge storage unit 4 of pixel 2-1 and the charge storage unit 4 of pixel 2-2. That is, the switch transistor 54 of pixel 2-1 is connected between the charge storage unit 4 of pixel 2-1 and the switch transistor 54 of pixel 2-2. The switch transistor 54 of pixel 2-2 is connected between the charge storage unit 4 of pixel 2-2 and the switch transistor 54 of pixel 2-1.

[0035] The gate electrode of the switch transistor 54 is connected to a corresponding signal line 106. The on / off of the switch transistor 54 is controlled by a control signal from the signal line 106. When the switch transistor 54 is on, the charge storage unit 4 of the pixel 2-1 and the charge storage unit 4 of the pixel 2-2 are connected to each other.

[0036] The two charge accumulation units 4 connected via the switch transistor 54 function as a single charge accumulation unit as a whole. The charge present there is the sum of the charges accumulated in the two charge accumulation units 4 (total charge). A signal corresponding to this total charge is output from the signal line 107 via the two amplification transistors 52 and two selection transistors 53 corresponding to the two charge accumulation units 4. This signal is a single signal representing two pixels 2, pixel 2-1 and pixel 2-2. In other words, the switch transistor 54 enables pixel addition (binning). This can also be called RL addition, which adds together the two pixels 2 located on the left and right.

[0037] 2, two pixels 2, pixel 2-1 and pixel 2-2, share one signal line 107. That is, the selection transistor 53 of pixel 2-1 and the selection transistor 53 of pixel 2-2 are both connected to the same signal line 107. The output voltage of the amplification transistor 52 of pixel 2-1 and the output voltage of the amplification transistor 52 of pixel 2-2 are supplied to the common signal line 107 via the corresponding selection transistors 53. The amplification transistor 52 and selection transistor 53 of pixel 2-1 and the amplification transistor 52 and selection transistor 53 of pixel 2-2 are connected in parallel to the signal line 107. Since transistors are connected in parallel to the same signal line 107, the signal output to the signal line 107 can be speeded up.

[0038] 1, for example, pixels 2 having the above-described configuration are arranged in a two-dimensional array in the X-axis direction and the Y-axis direction (arranged in an array) to form a photodetector element 1. Components included in the pixels 2, such as a photoelectric conversion unit 3 and a charge accumulation unit 4, are also arranged in an array. Further details will be described with reference to FIGS. 3 to 7.

[0039] 3 is a diagram showing an example of the schematic configuration of the photodetector element 1. The diagram shows a schematic cross section of part of the photodetector element 1 when viewed from the side (as viewed in the positive Y-axis direction), more specifically, of part of pixels 2-1 and 2-2 arranged side by side in the row direction (X-axis direction) of the array.

[0040] In this example, the photodetector element 1 includes two semiconductor substrates. Components of the photodetector element 1 are formed in or on the semiconductor substrates. The first semiconductor substrate is referred to as semiconductor substrate P1 and is illustrated. The second semiconductor substrate is referred to as semiconductor substrate P2 and is illustrated. The semiconductor substrate P1 and the semiconductor substrate P2 are stacked on top of each other. More specifically, the semiconductor substrate P1 and the semiconductor substrate P2 are attached (bonded) to each other so as to be electrically connected to each other. In the example shown in FIG. 3, the semiconductor substrate P2 and the semiconductor substrate P1 are located in this order in the positive direction of the Z axis.

[0041] The plurality of photoelectric conversion units 3 and the plurality of charge accumulation units 4 described above are formed on a semiconductor substrate P1. Other pixel circuit elements, such as the various transistors previously described with reference to FIG. 2, are formed on a semiconductor substrate P2. Note that in FIG. 3, electrodes 50, which are among the components of the transistors, are illustrated with reference numerals. The electrodes 50 may be, for example, gate or drain / source electrodes of a reset transistor 51 (RST) or an amplification transistor 52 (AMP).

[0042] The semiconductor substrate P1 includes an insulating layer 10 (first insulating layer). The insulating layer 10 may include a conductive member such as wiring. The surface of the semiconductor substrate P1 facing the insulating layer 10 (the surface on the negative Z-axis direction side in this example) is referred to as the surface p1a and is illustrated. Incident light is incident on the surface (back surface) of the semiconductor substrate P1 opposite the surface p1a. In this sense, the photodetector 100 can also be called a back-illuminated photodetector.

[0043] The semiconductor substrate P2 includes an insulating layer 20 (second insulating layer). The insulating layer 20 may include a conductive member such as wiring. The surface of the semiconductor substrate P2 facing the insulating layer 20 (in this example, the surface on the positive Z-axis direction side) is illustrated and referred to as the back surface p2b.

[0044] 3, the semiconductor substrates P1 and P2 are bonded together so that the surface p1a of the semiconductor substrate P1 and the back surface p2b of the semiconductor substrate P2 are in surface contact. The thickness (length in the Z-axis direction) of the insulating layer 10 of the semiconductor substrate P1 is thinner than the thickness of the insulating layer 20 of the semiconductor substrate P2. For example, the insulating layer 20 may include two or more wiring layers, while the insulating layer 10 may include a single wiring layer.

[0045] The illustrated photoelectric conversion unit 3 is a photodiode, and the N-type region thereof is particularly illustrated as the photoelectric conversion unit 3. The photoelectric conversion unit 3 includes a main body 31 and an end portion 32. The end portion 32 is the portion of the photoelectric conversion unit 3 that contacts the charge accumulation unit 4, and in this example, corresponds to the lower end portion (the end portion on the negative Z-axis direction side) of the photoelectric conversion unit 3. The end portion 32 has an impurity concentration different from that of the main body 31, for example, an impurity concentration higher than the impurity concentration of the main body 31. Note that the photoelectric conversion unit 3 may be configured without the end portion 32 (only the main body 31), in which case the main body 31 contacts the charge accumulation unit 4.

[0046] The charge accumulation portions 4 are directly connected to the corresponding photoelectric conversion portions 3 in line in the substrate thickness direction (Z-axis direction). The photoelectric conversion portions 3 (main body 31, end portion 32) and the charge accumulation portions 4 are located in this order in the negative direction of the Z-axis. The charge accumulation portions 4 are formed in a well region of the semiconductor substrate P1. The well region in which the charge accumulation portions 4 are formed is referred to as a well region 40 and is illustrated.

[0047] An optical layer for guiding light to be detected by pixel 2, out of the light incident on the light detection element 1, to the photoelectric conversion unit 3 of that pixel 2, is also formed on the semiconductor substrate P1. Examples of such an optical layer include a filter layer 18 and a lens layer 19 shown in FIG. 3 . The filter layer 18 and the lens layer 19 are provided in this order in the positive direction of the Z axis so as to cover the photoelectric conversion unit 3. The lens layer 19 includes a lens (e.g., an on-chip lens (OCL)) for focusing the incident light on the photoelectric conversion unit 3. The filter layer 18 includes a color filter that transmits light of the color of that pixel 2. Various known materials may be used.

[0048] The photodetector element 1 further includes contacts 6 (e.g., vias) and wiring 7. A portion of the contacts 6 is formed on the semiconductor substrate P1. The remaining portion of the contacts 6 and the wiring 7 are formed on the semiconductor substrate P2. The wiring 7 is included in an insulating layer 20 of the semiconductor substrate P2. Unless otherwise specified, the wiring 7 refers to the wiring connected to the charge accumulation unit 4 via the contacts 6.

[0049] There are a plurality of contacts 6, each extending from a corresponding charge accumulation portion 4 to the semiconductor substrate P2. More specifically, in the example shown in Fig. 3, the contacts 6 extend in the substrate thickness direction (positive direction of the Z axis) so as to connect the charge accumulation portion 4 formed on the semiconductor substrate P1 with the wiring 7 formed on the semiconductor substrate P2.

[0050] The contact 6 passes through the insulating layer 10 of the semiconductor substrate P1. As described above, the thickness of the insulating layer 10 of the semiconductor substrate P1 is thinner than the thickness of the insulating layer 20 of the semiconductor substrate P2. By reducing the thickness of the insulating layer 10, the length of the contact 6 passing through the insulating layer 10 can be shortened.

[0051] The portion of the contact 6 formed on the semiconductor substrate P1 is exposed on the front surface p1a of the semiconductor substrate P1. The portion of the contact 6 formed on the semiconductor substrate P2 is exposed on the back surface p2b of the semiconductor substrate P2. The semiconductor substrates P1 and P2 are stacked so that these portions are in electrical contact (bonded) with each other. When the material of the contact 6 is copper (Cu), this can also be called a Cu-Cu bond.

[0052] The charge storage unit 4 is connected to other elements, such as the reset transistor 51, the amplification transistor 52, and the switch transistor 54, which were previously described with reference to Fig. 2, via the contact 6 and the wiring 7. The contact 6 and the wiring 7 can also be considered as a path (transfer path) for transferring the charge stored in the charge storage unit 4 to the transistor.

[0053] The photodetector element 1 includes an isolation portion for isolating adjacent pixels 2 from one another among the plurality of pixels 2. The isolation portion is formed on a semiconductor substrate P1. In FIG. 3, a P-type region 8 and a trench portion 9 are illustrated as examples of the isolation portion, and are designated by reference numerals. When there is no particular need to distinguish between these, they are simply referred to as isolation portions.

[0054] The separation by the separation unit may include electrical separation and optical separation. For example, if adjacent pixels 2 correspond to different colors, a color mixing suppression effect can be obtained. The separation unit is located between multiple pixels 2, more specifically, between multiple photoelectric conversion units 3 and between multiple charge accumulation units 4.

[0055] The P-type region 8 extends along the upper and side surfaces of the photoelectric conversion unit 3, as well as the side surfaces of the well region 40 in which the charge accumulation unit 4 is formed, so as to cover these surfaces. The trench portion 9 extends from the back surface side (positive Z-axis direction) of the semiconductor substrate P1 to at least the same height as the lower end of the photoelectric conversion unit 3 (the same position in the Z-axis direction). In the example shown in FIG. 3 , the trench portion 9 extends to the same height as the lower end of the charge accumulation unit 4 (to the upper surface of the insulating layer 10). The trench portion 9 is located on the opposite side of the P-type region 8 from the photoelectric conversion unit 3 and the charge accumulation unit 4 (well region 40). The trench portion 9 can also be called a full trench, extending in the height direction (Z-axis direction) of the semiconductor substrate P1 excluding the insulating layer 10, the filter layer 18, and the lens layer 19.

[0056] Between the pixel 2-1 and the pixel 2-2, there are arranged in this order a P-type region 8, a trench portion 9 and another P-type region 8. The adjacent pixels 2-1 and 2-2 are separated from each other by such an isolation portion.

[0057] 4 and 5 are diagrams showing an example of the schematic configuration of the photodetector element 1. Fig. 4 shows a schematic layout of the semiconductor substrate P1 in a plan view (as viewed in the negative direction of the Z axis). Of the elements described above, the photoelectric conversion unit 3, the charge accumulation unit 4, the contact 6, the P-type region 8, and the trench portion 9 are shown. Note that although the photoelectric conversion unit 3 and the charge accumulation unit 4 are located at different positions in the Z axis direction, they are also drawn together for ease of understanding.

[0058] 5 shows a schematic plan view of the layout of the semiconductor substrate P2. Of the elements described above, the reset transistor 51, the amplifier transistor 52, the select transistor 53, the switch transistor 54, the contact 6, and the wiring 7 are shown. The signal line 107 is also shown by a dashed line.

[0059] The layouts in Figures 4 and 5 are merely examples, and any layout can be designed within the scope of realizing the configurations in Figures 2 and 3 described above.

[0060] One of the features is the arrangement of the contacts 6 etc. on the semiconductor substrate P1. The description will be made with reference to FIGS.

[0061] 6 and 7 are diagrams showing examples of the arrangement of the contacts 6, etc. In plan view, at least a portion of the contacts 6 overlaps with the charge storage portion 4. In the example shown in Fig. 6, a portion of the contacts 6 overlaps with the charge storage portion 4, and in the example shown in Fig. 7, the entire contacts 6 overlap with the charge storage portion 4.

[0062] The contact 6 is spaced apart from the P-type region 8. This feature is determined, for example, from the positional relationship between the centers of the photoelectric conversion unit 3 and the contact 6. The center of the photoelectric conversion unit 3 is illustrated as center 3c. The center of the contact 6 is illustrated as center 6c. Note that the center 3c of the photoelectric conversion unit 3 may be the same as the center of the pixel 2.

[0063] The distance from the center 3c of the photoelectric conversion unit 3 to the center 6c of the contact 6 is referred to as distance d1. The distance from the center 3c of the photoelectric conversion unit 3 to the P-type region 8 is referred to as distance d2. The center 6c of the contact 6 is located closer to the center 3c than the P-type region 8. The distance d1 is equal to or less than half of the distance d2 (distance d1≦(distance d2 / 2)). As shown in FIG. 6, the center 6c of the contact 6 may be separated to some extent from the center 3c of the photoelectric conversion unit 3. As shown in FIG. 7, the center 6c of the contact 6 may substantially overlap with the center 3c of the photoelectric conversion unit 3. "Substantially overlapping" includes the center 6c of the contact 6 coinciding with the center 3c of the photoelectric conversion unit 3, and may also include a case where there is a deviation within a range due to manufacturing variations or the like.

[0064] According to the photodetector element 1 described above, by directly connecting the charge storage unit 4 to the photoelectric conversion unit 3, it is possible to eliminate the transfer transistors that have been used in the past. This makes it possible to address issues associated with miniaturization. For example, as mentioned at the beginning, problems that can arise with miniaturization when a transfer transistor is provided are avoided. That is, the transfer path is narrowed, which reduces the transfer characteristics and degrades low-light image quality. With regard to the design of the saddle point (e.g., threshold voltage) of the transfer transistor, it is possible to avoid the deterioration of inter-pixel differences due to misalignment of impurities. There is also no need to increase the transfer electric field, which creates a trade-off with Qs.

[0065] Furthermore, for example, since a barrier (especially a shallow barrier) of the transfer transistor does not occur in principle, transfer can be improved. Even in deep areas, the accumulation period of the photoelectric conversion unit 3 can be used as the transfer period, making it easier to ensure the transfer period. This can improve low-illumination image quality accordingly.

[0066] The charge generated in the photoelectric conversion unit 3 is automatically transferred to the charge storage unit 4, and if the amount of charge is very large, it reaches the power supply node VDD via the charge storage unit 4 (overflow). In principle, blooming does not occur.

[0067] Since there is no need to provide a transfer transistor, there is no need for manufacturing steps for forming the transfer transistor and for forming circuits, wiring, etc. for controlling the transfer transistor, and therefore the number of manufacturing steps can be reduced accordingly.

[0068] Since the switch transistor 54 is provided to connect the plurality of charge storage sections 4 together, it is possible to obtain a signal according to the total charge of the plurality of charge storage sections 4. In other words, pixel addition becomes possible.

[0069] Furthermore, because the photodetector element 1 has a stacked structure of the semiconductor substrates P1 and P2, different design rules (manufacturing processes, etc.) can be used for the semiconductor substrates P1 and P2. This can contribute to improving the performance of the photodetector device 100. For example, since the semiconductor substrate P1 does not require the formation of transistors, it is easier to adopt processes, materials, etc. suitable for suppressing dark current in the photoelectric conversion unit 3 (e.g., photodiodes). By applying finer design rules to the semiconductor substrate P2 than to the semiconductor substrate P1, it becomes possible to shrink the reset transistor 51 to the switch transistor 54, the contact 6, etc., improve the degree of freedom in placement, and improve circuit performance.

[0070] The distance between the contact 6 and the P-type region 8 suppresses dark current that may occur in the charge accumulation unit 4. A transfer path can be formed without being affected by the P-type region 8. This effect becomes easier to obtain as the contact 6 is farther away from the P-type region 8, in other words, as the center 6c of the contact 6 approaches the center 3c of the photoelectric conversion unit 3.

[0071] The thickness of the insulating layer 10 of the semiconductor substrate P1 on which no transistors are formed can be made thinner than the thickness of the insulating layer 20 of the semiconductor substrate P2 on which transistors are formed. By making the insulating layer 10 thinner, the contacts 6 passing through the insulating layer 10 can be made shorter. This suppresses an increase in the capacitance of the charge storage unit 4 that may occur due to the length of the contacts 6, and accordingly increases the conversion efficiency (charge-to-voltage conversion efficiency) of the charge storage unit 4. For example, this can improve image quality in low illumination (dark conditions).

[0072] It is possible to adopt a configuration without the switch transistor 54. Even in this case, the effect of directly connecting the charge accumulation unit 4 to the photoelectric conversion unit 3 can be obtained. The stacked structure of the semiconductor substrates P1 and P2 is not essential. The components of the photodetector element 1 may be formed on a single semiconductor substrate, or conversely, may be formed on three or more semiconductor substrates. Even in this case, the effect of directly connecting the charge accumulation unit 4 to the photoelectric conversion unit 3 can be obtained.

[0073] 2. Modifications Various modifications are possible based on the technology of the above embodiment. Some modifications will be described below.

[0074] In the above embodiment, two-pixel addition has been described as an example, but it is also possible to add more than two pixels. This will be described with reference to FIGS. 8 to 11.

[0075] 2.1 Four-Pixel Addition Figures 8 to 10 are diagrams showing examples of four-pixel addition. Figure 8 shows an example of a pixel circuit. Figure 9 schematically shows an example of the layout of the semiconductor substrate P1. Figure 10 schematically shows an example of the layout of the semiconductor substrate P2.

[0076] Eight pixels 2 are illustrated. The pixels 2 are referred to as pixel 2-1 to pixel 2-8 in the drawing. When no particular distinction is made between them, they are simply referred to as pixel 2.

[0077] The switch transistors 54 are connected between the four charge storage units 4. Specifically, the switch transistors 54 of the pixels 2-1 to 2-4 are connected between the charge storage units 4. The same applies to the pixels 2-5 to 2-8.

[0078] Pixels 2-1 and 2-2 are two pixels 2 arranged side by side in the row direction of the array. Pixels 2-3 and 2-4 are two pixels 2 arranged side by side with pixels 2-1 and 2-3 in the column direction. A pixel signal corresponding to the total charge in the charge storage units 4 of these four pixels 2 is output from signal line 107-0. Four-pixel addition is possible. The same is true for pixels 2-5 to 2-8, and pixel signals corresponding to the total charge in their charge storage units 4 are output from signal line 107-1.

[0079] Furthermore, in this example, pixels 2-1 to 2-4 share one signal line 107-0. The output signals of the amplification transistors 52 of pixels 2-1 to 2-4 are supplied to the common signal line 107-0. The amplification transistors 52 and selection transistors 53 of each of pixels 2-1 to 2-4 are connected in parallel to the signal line 107-0. Since transistors are connected in parallel to the same signal line 107-0, the speed of signal output to the signal line 107-0 can be increased. The same is true for pixels 2-5 to 2-8, which share one signal line 107-1.

[0080] 2.2 8-Pixel Addition (4 x 2-Pixel Addition) Figure 11 is a diagram showing an example of 8-pixel addition. Sixteen pixels 2 are shown divided into four pixel groups, each consisting of four pixels 2. The four pixels 2 that make up each pixel group are shown as pixels 2-1 to 2-4. When no particular distinction is made between them, they are simply referred to as pixels 2. A total of eight pixels 2 included in the two pixel groups are added together. Switch transistors 54 are connected between the charge storage units 4 of the eight pixels 2.

[0081] 11, the switch transistor 54 is connected between the charge storage units 4 of eight pixels 2. A pixel signal corresponding to the total charge of the charge storage units 4 of those eight pixels 2 is output from two signal lines 107-0. Eight-pixel addition is possible.

[0082] 11, the switch transistors 54 are connected between the charge storage units 4 of the eight pixels 2. A pixel signal corresponding to the total charge of the charge storage units 4 of the eight pixels 2 is output from the two signal lines 107-1. Eight-pixel addition is possible.

[0083] 2.3 Modifications of Isolation Portion In the above embodiment, the trench portion 9 is a full trench. However, the trench portion 9 does not have to be a full trench. This will be described with reference to FIGS. 12 and 13.

[0084] 12 and 13 are diagrams showing an example of a schematic configuration of the photodetector element 1. As shown in FIG. 12 , the trench portion 9 is located on the opposite side of the photoelectric conversion portion 3, with the P-type region 8 sandwiched between them. The trench portion 9 extends to a position at the same height as the lower end of the photoelectric conversion portion 3. The P-type region 8 extends below it. The P-type region 8 has a connection portion 8a. The connection portion 8a is connected to another P-type region 8 located on the opposite side of the P-type region 8, with the trench portion 9 sandwiched between them, at the same height (position in the Z-axis direction) as the charge accumulation portion 4. In the separation portion between the pixel 2-1 and the pixel 2-2, the connection portions 8a of the P-type region 8 of the pixel 2-1 and the P-type region 8 of the pixel 2-2 are connected to each other (it can be said that they share one connection portion 8a), thereby connecting the two P-type regions 8 to each other.

[0085] The photodetector element 1 includes a well contact. The well contact 40a is formed below the connection portion 8a so as to be in contact with the well region 40 and the connection portion 8a of the P-type region 8. An electrode 41 extending from the well contact 40a to the semiconductor substrate P2 is also shown. The potential of the well contact 40a can be controlled from the semiconductor substrate P2 via the electrode 41. For example, holes that may accumulate in the well region 40 can be discharged. As described above, the well contact 40a is formed below the connection portion 8a between the P-type regions 8 of the pixel 2-1 and the pixel 2-2, and therefore the well contact 40a is provided in common to these well regions 40.

[0086] 13, one well contact 40a is provided in common to four pixels 2, pixel 2-1 to pixel 2-4. That is, one common well contact 40a is provided for each of four well regions 40. However, this is not limiting, and one common well contact 40a may be provided for any number of well regions 40 greater than or equal to four (an example is shown in FIG. 26, which will be described later). One common well contact 40a may also be provided for each of two or three well regions 40.

[0087] 2.4 Noise Removal The charges accumulated in the charge accumulation unit 4 may include not only charges generated in the photoelectric conversion unit 3 but also noise charges generated in the charge accumulation unit 4. An example of the noise charges is KTC noise charges. In one embodiment, noise removal measures may be taken. For example, a signal corresponding to the noise charges may be removed from a signal corresponding to the charges accumulated in the charge accumulation unit 4. Specific methods will be described below using a frame memory system and a noise cancellation circuit as examples.

[0088] <Frame Memory Method> In the frame memory method, the frame memory M1 in FIG. 1 described above holds the voltage value of a signal corresponding to the noise charge. For example, first, the voltage value of the signal from each pixel 2 during non-exposure (shuttering) is held (temporarily stored) in the frame memory M1 as the voltage value of the noise signal. Then, the voltage value of the noise signal stored in the frame memory M1 is subtracted from the voltage value of the signal from each pixel 2 after exposure. The pixel signal from which the noise has been removed is obtained. These processes may be performed by the column signal processing circuit 103 in FIG. 1 or by any other logic circuit.

[0089] FIG. 14 is a diagram showing an example of a timing chart. Several control signals and voltage signals are shown schematically. In the diagram, the selection transistor 53 (SEL) indicates the on / off state of the selection transistor 53. The reset transistor 51 (RST) indicates the on / off state of the reset transistor 51. The auto-zero (AZ) indicates the auto-zero state of the ADC (Analog-to-Digital Converter) in the column signal processing circuit 103. The ramp waveform of the DAC circuit is a single-slope ramp voltage used in the DAC (Digital-to-Analog Converter). The output voltage indicates the voltage of the signal output from the pixel 2 via the signal line 107.

[0090] At time t1, the selection transistor 53 (SEL) and the reset transistor 51 (RST) are both on. An output voltage according to the amount of charge in the charge storage unit 4 is output in a state where the charge is discharged via the reset transistor 51.

[0091] At time t2, the ramp waveform intersects with the output voltage, and the voltage at that time is detected. This detected output voltage can also be called the output voltage at reset. The ramp waveform of the DAC circuit is adjusted based on this output voltage.

[0092] At time t3, the reset transistor 51 (RST) turns off. Noise occurs, and the output voltage begins to change. At time t4, the Ramp waveform intersects with the output voltage, and the output voltage at that time is detected. This detected output voltage is the voltage at the time of reset plus the voltage of the noise signal. The value of this output voltage is stored in the frame memory M1 as the voltage value of the noise signal.

[0093] At time t5, exposure begins. The selection transistor 53 (SEL) and the reset transistor 51 (RST) are both off. Charges corresponding to the amount of received light are generated in the photoelectric conversion unit 3 and transferred to the charge accumulation unit 4.

[0094] At time t6, signal readout begins. The selection transistor 53 (SEL) is turned on. An output voltage corresponding to the amount of charge accumulated in the charge accumulation unit 4 is output to the signal line 107 via the selection transistor 53. This output voltage includes the voltage of the noise signal. The noise is removed by subtracting the voltage value of the noise signal stored in the frame memory from the voltage value of this output signal.

[0095] For example, noise can be removed by using the frame memory method described above.

[0096] <Noise Cancellation Circuit> The noise cancellation circuit negatively feeds back the voltage of a signal corresponding to the noise charge to the charge accumulation section 4. Two types of circuits will be described with reference to FIGS.

[0097] 15 is a diagram showing an example of a noise cancellation circuit. Of the components of the noise cancellation circuit, an amplifier 55 and a signal line 109 (feedback line) are shown with reference numerals. The illustrated amplifier 55 is an operational amplifier.

[0098] One input terminal (-) of the amplifier 55 is connected to the signal line 107. A reference voltage is input to the other input terminal (+) of the amplifier 55. In this example, the reference voltage is the voltage of the power supply node VDD. The voltage obtained by subtracting the voltage of the signal line 107 from the voltage of the power supply node VDD is input to the amplifier 55.

[0099] The amplifier 55 adds an inverted voltage of the voltage on the signal line 107 to the voltage on the power supply node VDD and outputs the result. The output terminal of the amplifier 55 is connected to a signal line 109. A voltage obtained by superimposing an antiphase voltage of the noise voltage appearing on the signal line 107 on the voltage on the power supply node VDD is supplied to the signal line 109.

[0100] The reset transistor 51 is connected between the signal line 109 and the charge storage unit 4. A voltage having a phase opposite to that of the noise voltage is fed back to the charge storage unit 4 via the reset transistor 51. The noise is cancelled.

[0101] Naturally, the noise cancellation circuit can also be applied to configurations other than the four-pixel addition configuration shown in FIG.

[0102] 16 is a diagram showing another example of a noise cancellation circuit. Of the noise cancellation components, a feedback transistor 56, a capacitor C1, and a capacitor C2 are indicated by reference numerals. The voltage across both ends of the series-connected amplifier transistor 52 and select transistor 53 is adjustable.

[0103] The feedback transistor 56 is connected between the connection point of the amplification transistor 52 and the selection transistor 53 and the reset transistor 51. The capacitor C1 is connected between the connection point of the reset transistor 51 and the feedback transistor 56 and a reference potential node. The reference potential node has a reference potential (e.g., GND potential). The capacitor C2 is connected between the connection point of the reset transistor 51 and the feedback transistor 56 and the charge storage unit 4. By controlling the gate voltage of the feedback transistor 56, the output voltage can be selectively negatively fed back to the reset transistor 51 (RST). This negative feedback cancels noise. For detailed principles, see, for example, Patent Document 2.

[0104] 16 is characterized by the use of capacitors C1 and C2. As described above, the photodetector 100 is configured to include semiconductor substrates P1 and P2. By forming capacitors C1 and C2 on one of the two semiconductor substrates that is suitable for forming capacitors, it becomes easier to realize the noise cancellation circuit.

[0105] 2.5 Boost Wiring In one embodiment, a boost wiring may be provided in parallel with the wiring 7 connected to the charge storage unit 4. This can improve the charge transfer performance from the charge storage unit 4. This will be described with reference to FIG. 17 .

[0106] 17 is a diagram showing an example of boost wiring. The layout of the wiring 7 and its surrounding elements is shown in a plan view (viewed in the negative Z-axis direction). In this example, two boost wirings 11 are provided. The two boost wirings 11 extend parallel to (run parallel to) the wiring 7 at an interval on both sides of the wiring 7, i.e., on opposite sides of the wiring 7.

[0107] The potential of the boost wiring 11 is set so that the wiring 7 is boosted by electrical coupling between the boost wiring 11 and the wiring 7. This increases the shallow transfer electric field in particular, improving charge transfer performance. It also provides a shielding effect against other signal wirings.

[0108] 2.6 F2F Stacking In one embodiment, the semiconductor substrate P1 and the semiconductor substrate P2 may be bonded together so that the surfaces of the semiconductor substrate P1 and the semiconductor substrate P2 are in surface contact with each other (F2F stacking / F2F bonding). This will be described with reference to FIG.

[0109] 18 is a diagram showing an example of the schematic configuration of the photodetector element 1. The surface of the semiconductor substrate P2 facing the insulating layer 20 is shown as the surface p2a. In this example, the semiconductor substrates P1 and P2 are bonded together so that the surface p1a of the semiconductor substrate P1 and the back surface p2b of the semiconductor substrate P2 are in surface contact. The contact 6 passes through the insulating layer 10 of the semiconductor substrate P1 and the insulating layer 20 of the semiconductor substrate P2.

[0110] Even when the semiconductor substrate P1 and the semiconductor substrate P2 are stacked as described above, the same effects as before can be obtained. As the number of stacking options increases, the degree of freedom in designing the layout and the like is improved.

[0111] 2.7 Sharing of Reset Transistor In one embodiment, two or more pixels 2 may share one reset transistor 51 (RST), as will be described with reference to FIG.

[0112] 19 is a diagram showing an example of a pixel circuit. In this example, four pixels 2, pixel 2-1 to pixel 2-4, share one reset transistor 51. A switch transistor 54 is electrically connected between each charge storage unit 4 and the reset transistor 51 so that the charge storage unit 4 of each of the four pixels 2 is commonly connected to one reset transistor 51. The reset transistor 51 is commonly connected to the charge storage unit 4 of each pixel 2 via the switch transistor 54 of each pixel 2. The number of reset transistors 51 can be reduced by the number of reset transistors 51 that are shared, which can contribute to layout area efficiency, etc.

[0113] Not limited to the above example, any number of pixels 2 greater than or equal to two may share one reset transistor 51. That is, the switch transistor 54 may be electrically connected between each of two or more charge storage units 4 and the reset transistor 51 so as to commonly connect two or more charge storage units 4 to the reset transistor 51. The planar layout of the semiconductor substrate P1 and the semiconductor substrate P2 may be changed as appropriate to match the pixel circuit of FIG. 19 . Note that the reset transistor 51 may be shared without going through the switch transistor 54.

[0114] 2.8 Variable Range of Charge Accumulation Unit In one embodiment, the range of the amount of charge that can be stored in the charge accumulation unit 4 may be variable. For example, the potential level of the charge accumulation unit 4 at the time of resetting can be switched. This will be described with reference to FIGS. 20 and 21.

[0115] 20 and 21 are diagrams showing examples of pixel circuits. For ease of explanation, the reset transistor 51 is shown separately from the pixel 2. In this example, four pixels 2, pixel 2-1 to pixel 2-4, share one reset transistor 51.

[0116] Since the pixels 2 are arranged in an array, the reset transistors 51 are also arranged in an array. The position of each reset transistor 51 is distinguished and indicated as (n, m), etc., where n and m correspond to the row number and column number.

[0117] The power supply node of the reset transistor 51 is provided by a signal line 106. Each reset transistor 51 is connected between the corresponding signal line 106 and the corresponding pixel 2. The reset transistors 51 in the same row are connected to the same signal line 106 (power supply node). In the example shown in FIG. 20 , the reset transistor 51 in the nth row is connected to the signal line 106(n) in the nth row. The reset transistor 51 in the n+1th row is connected to the signal line 106(n+1) in the n+1th row.

[0118] The voltage of the signal line 106 to which the reset transistor 51 is connected is referred to as voltage VB and is illustrated schematically as a variable voltage source. Voltage VB can be switched, for example, between a low voltage, which is a relatively low voltage, and a high voltage, which is a relatively high voltage. The voltage of the signal line 106, which is the power supply node of the reset transistor 51, is switched between a low voltage and a high voltage. In the configuration shown in FIG. 20 , the voltage of the power supply node can be switched individually for each row.

[0119] By switching the voltage VB, it is possible to switch the potential level of the charge accumulation unit 4, i.e., the range of the charge accumulation unit 4. The voltage VB may be switched according to the level (illuminance) of incident light. For example, when the level of incident light on the photodetector element 1 is relatively low, the voltage VB is switched to a low voltage to alleviate the electric field around the charge accumulation unit 4, and conversely, when the level of incident light is relatively high, the voltage VB is switched to a high voltage to ensure the range of the charge accumulation unit 4.

[0120] By switching the voltage VB, it is more likely that image quality can be optimized according to illuminance than if not done. Furthermore, by switching the voltage VB for each row, signals from pixels 2 in rows with different voltages VB can be combined. This provides the same effect as combining signals obtained with different exposure periods, such as in HDR combination.

[0121] 21 shows an example of the circuit of each pixel 2. The switch transistor 54 is electrically connected between each charge storage unit 4 and the reset transistor 51 so that the charge storage units 4 of the four pixels 2 are commonly connected to one reset transistor 51. More specifically, in this example, the switch transistor 54 of pixel 2-1 is electrically connected between the charge storage unit 4 of pixel 2-1 and the reset transistor 51. The switch transistor 54 of pixel 2-2 is electrically connected between the charge storage unit 4 of pixel 2-2 and the reset transistor 51. The switch transistor 54 of pixel 2-3 is electrically connected between the charge storage unit 4 of pixel 2-3 and the reset transistor 51. The switch transistor 54 of pixel 2-4 is electrically connected between the charge storage unit 4 of pixel 2-4 and the reset transistor 51.

[0122] 2.9 Dark Current Countermeasures As mentioned above, the charge accumulation unit 4 includes a floating diffusion region (FD). The FD is an N-type region obtained by diffusing impurities into the semiconductor substrate P1, for example. If the FD spreads too much, dark current may increase. In one embodiment, a mask member may be provided to define the FD of the charge accumulation unit 4 (for example, to limit its diffusion). This will be described with reference to FIGS. 22 to 25.

[0123] 22 and 23 are diagrams showing examples of a mask member. The illustrated mask member is a dummy member 12. The dummy member 12 may be provided as, for example, a dummy electrode. An example of a material for the dummy member 12 is polysilicon.

[0124] 22 , in plan view, the dummy member 12 has an annular (ring-shaped) shape that includes the charge accumulation portion 4. The opening exposes the charge accumulation portion 4, while the periphery of the charge accumulation portion 4 is covered by the dummy member 12. As shown in FIG. 23 , the dummy member 12 is provided on the well region 40 so as to cover the well region 40 except for the portion where the charge accumulation portion 4 is formed.

[0125] During manufacturing, a resist 13 is provided to cover the well region 40 and the dummy member 12. In Fig. 23, the resist 13 is shown imaginarily by a dashed line. Ion implantation is performed through openings in the resist 13 to diffuse an N-type region into the well region 40. The range of this diffusion region is limited by the openings in the dummy member 12. It can be said that the diffusion region is formed in self-alignment by the dummy member 12.

[0126] 24 and 25 are diagrams showing another example of a mask member. The illustrated mask member is an electrode material 14. Various known electrode materials may be used. As shown in FIG. 24 , when viewed from above, the electrode material 14 has an annular shape that includes the charge accumulation portion 4 therein. The opening exposes the charge accumulation portion 4, while the other portion is covered by the dummy member 12. As shown in FIG. 25 , the electrode material 14 is provided on the well region 40 so as to cover the well region 40 except for the portion where the charge accumulation portion 4 is to be formed.

[0127] During manufacturing, a resist 13 is provided to cover the well region 40 and the electrode material 14. In Fig. 25, the resist 13 is shown imaginarily by a dashed line. Ion implantation is performed through openings in the resist 13 to diffuse an N-type region into the well region 40. The range of this diffusion region is limited by the openings in the electrode material 14. It can be said that the diffusion region is formed in self-alignment by the electrode material 14.

[0128] For example, by using the mask member as described above, it is possible to define an opening in the diffusion region (i.e., FD (floating diffusion region)) of the charge accumulation portion 4. The diffusion region of the charge accumulation portion 4 is prevented from expanding too much (the diffusion region is shrunk), which increases the possibility of suppressing dark current and further improving conversion efficiency.

[0129] 2.10 Well Contact Arrangement, Hole Accumulation Layer Various modifications are possible regarding the arrangement of the well contact 40a. Some examples will be described below.

[0130] <8-Pixel Sharing> As described above, one well contact 40a may be provided in common for any number of two or more pixels 2. An example will be described with reference to FIG.

[0131] 26 is a diagram showing an example of a schematic configuration of the photodetector element 1. One common well contact 40a is provided for eight pixels 2, pixel 2-1 to pixel 2-8.

[0132] <Hole Accumulation Layer> For example, in the case of a full trench in which the trench portion 9 extends to the same height as the lower end of the charge accumulation portion 4 (well region 40) as shown in FIG. 3 described above, the trench portion 9 may include a hole accumulation layer. This will be described with reference to FIG.

[0133] 27 is a diagram showing an example of a schematic configuration of the trench portion 9 and its periphery. The trench portion 9 includes an electrode layer 91 and an insulating layer 92. Both the electrode layer 91 and the insulating layer 92 extend in the same direction as the extension direction of the trench portion 9 (the Z-axis direction). The insulating layers 92 are a pair of insulating layers 92 located on opposite sides of each other with the electrode layer 91 sandwiched between them in a direction intersecting the extension direction of the trench portion 9 (a direction perpendicular to the extension direction in this example). The insulating layers 92 extend in the same direction as the extension direction of the trench portion 9 (the Z-axis direction in this example).

[0134] A P-type region 8 is located on the opposite side of the insulating layer 92 from the electrode layer 91. The electrode layer 91 and the P-type region 8 form a capacitance. A photoelectric conversion unit 3 is located on the opposite side of the P-type region 8 from the trench portion 9. Although not shown in the figure, a well region 40 ( FIG. 3 ) in which a charge accumulation unit 4 is formed is also located below the photoelectric conversion unit 3 (on the negative Z-axis direction side).

[0135] The electrode layer 91 has a negative potential. For example, a negative bias is supplied to the electrode layer 91 from outside the pixel array portion, and the potential of the electrode layer 91 is fixed to a negative potential. A hole accumulation layer is formed on the surface (side surface) of the trench portion 9 facing the P-type region 8. In this way, the trench portion 9 including the hole accumulation layer is obtained.

[0136] 27, a negative fixed charge film may be formed in the trench portion 9. In this case, the negative fixed charge film functions as a hole accumulation layer.

[0137] <Guard Ring Section> In one embodiment, the well contact 40a may be provided outside the pixel array section. This will be described with reference to FIG.

[0138] 28 is a diagram showing an example of a schematic configuration of a photodetector element 1. The photodetector element 1 includes a guard ring portion 15. The guard ring portion 15 is provided outside the pixel array portion, i.e., outside the array of a plurality of photoelectric conversion portions 3, etc. A well contact 40a is provided in the guard ring portion 15. The well contact 40a does not need to be provided within the pixel array portion (inside the effective pixels).

[0139] Various arrangements of the well contacts 40a are possible, including the above-described arrangement in the guard ring portion 15, thereby improving design freedom. For example, the GND supply capacity and the area efficiency of the layout can be optimized according to the pixel structure, etc.

[0140] 2.11 Cell Size Design The pixel size (cell size) can be designed by connecting the charge storage units 4 of different pixels 2. This will be explained with reference to FIGS.

[0141] 29 to 31 are diagrams showing examples of cell size design. In the example shown in Fig. 29, as in the previous examples, one pixel 2 constitutes one cell. For example, if one pixel 2 has a size of 0.5 μm × 0.5 μm, the cell size is also 0.5 μm × 0.5 μm.

[0142] 30 and 31 , the photodetector element 1 includes wiring 16 for changing the cell size. The wiring 16 connects the pixels 2 to each other so that two or more pixels 2 form one cell. In other words, the wiring 16 connects the charge accumulation units 4 arranged side by side in at least one of the row and column directions of the array. The wiring 16 may be formed on a semiconductor substrate P1.

[0143] 30 , the wiring 16 is connected to the contacts 6 of two charge storage units 4 arranged side by side in the column direction so as to connect the two charge storage units 4 to each other. For example, if one pixel 2 has a size of 0.5 μm×0.5 μm, the cell size is 1.0 μm×0.5 μm (Dual Pixel).

[0144] 31 , the wiring 16 is connected to the contacts 6 of two charge accumulation units 4 arranged side by side in the row direction and two charge accumulation units arranged side by side therewith in the column direction so as to connect them to each other. For example, when one pixel 2 has a size of 0.5 μm×0.5 μm, the cell size is 1.0 μm×1.0 μm.

[0145] For example, by utilizing the wiring 16 formed on the semiconductor substrate P1 as described above, various cell sizes can be designed based on one pixel 2. The degree of freedom in the wiring layout of the semiconductor substrate P1 can be utilized, making design easy. For example, it is only necessary to change the design of one wiring layer of the semiconductor substrate P1, so the cell size can be changed with a small number of steps. Various photodetector elements 1 with different cell sizes can be developed in parallel. The design of the semiconductor substrate P2 can be changed as appropriate depending on the cell size.

[0146] 2.12 Hole Emission When holes are accumulated in the peripheral P-type regions of the photoelectric conversion unit 3 and the charge accumulation unit 4, the potential of those parts rises. For example, the potential of the well region 40 also rises. To deal with this, hole emission control may be performed. One example of this control is to temporarily lower the potential of the power supply node VDD of the reset transistor 51 (RST) while the transistor 51 is on. This will be described with reference to FIG. 32.

[0147] 32 is a diagram showing an example of a timing chart. In the diagram, the power supply node VDD (RST) indicates the voltage of the power supply node VDD to which the reset transistor 51 (RST) is connected. The well region 40 and the charge storage unit 4 schematically indicate their potentials. As an overall trend, holes accumulate over time, and the potential of the well region 40 gradually increases. Control is performed to lower this potential (return it to its original state).

[0148] The reset transistor 51 (RST) is on from time t11 to time t14. The potential of the charge storage unit 4 rises to the potential of the power supply node VDD (RST). The potential of the well region 40 also rises.

[0149] Between time t12 and time t13, which is between time t11 and time t14, the potential of the power supply node VDD (RST) is controlled (for example, pulse controlled) to be temporarily lowered. The potential of the charge storage unit 4 also drops. Holes accumulated in the well region 40 are discharged, and the potential of the well region 40 also drops.

[0150] For example, as described above, holes accumulated in the well region 40 can be discharged, and an increase in the potential of the well region 40 can be suppressed. This is particularly effective when the trench portion 9 includes a hole accumulation layer (FIG. 27) or when there is no well contact 40a. The control described here can be applied to both the shuttering (corresponding to times t1 to t5 in FIG. 14) and the readout (corresponding to time t6 and thereafter in FIG. 14).

[0151] 2.13 Others The above-described embodiments and various modified examples may be combined as appropriate within a range that does not contradict. Furthermore, the above description has been given using an example in which the photodetection device 100 is a solid-state imaging device. However, the photodetection device 100 is not limited to a solid-state imaging device. Another example of the photodetection device 100 is a distance measuring device. The disclosed technology can be applied to various devices that use photodetection, without being limited to this.

[0152] 3. Summary The techniques described above can be specified, for example, as follows. One of the techniques disclosed is a photodetector 100. As described with reference to FIGS. 1 to 32 , etc., the photodetector 100 includes a first photoelectric conversion unit (e.g., the photoelectric conversion unit 3 of pixel 2-1), a first charge accumulation unit (e.g., the charge accumulation unit 4 of pixel 2-1) directly connected to the first photoelectric conversion unit, a first amplification transistor (e.g., the amplification transistor 52 of pixel 2-1) connected to the first charge accumulation unit, a second photoelectric conversion unit (e.g., the photoelectric conversion unit 3 of pixel 2-2), a second charge accumulation unit (e.g., the charge accumulation unit 4 of pixel 2-2) directly connected to the second photoelectric conversion unit, a second amplification transistor (e.g., the amplification transistor 52 of pixel 2-2) connected to the second charge accumulation unit, and a switch transistor 54 electrically connected between the first charge accumulation unit and the second charge accumulation unit.

[0153] According to the photodetector 100 described above, by directly connecting the charge storage unit 4 to the photoelectric conversion unit 3, it is possible to eliminate the transfer transistors that have been used conventionally. This makes it possible to address the various issues associated with miniaturization mentioned above. Furthermore, by connecting two or more charge storage units 4 together with a switch transistor 54, it is possible to obtain a signal corresponding to the total charge of the two or more charge storage units 4. For example, pixel addition becomes possible.

[0154] As described with reference to Figures 8 to 10, etc., the photodetector 100 includes a third photoelectric conversion unit (e.g., photoelectric conversion unit 3 of pixel 2-3), a third charge accumulation unit directly connected to the third photoelectric conversion unit (e.g., charge accumulation unit 4 of pixel 2-3), a fourth photoelectric conversion unit (e.g., photoelectric conversion unit 3 of pixel 2-4), and a fourth charge accumulation unit directly connected to the fourth photoelectric conversion unit (e.g., charge accumulation unit 4 of pixel 2-4), and the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit are arranged in an array, the first photoelectric conversion unit and the second photoelectric conversion unit are arranged side by side in the row direction (X-axis direction), and the third photoelectric conversion unit and the fourth photoelectric conversion unit are arranged side by side in the column direction (Y-axis direction), and the switch transistor 54 may be electrically connected between the first charge accumulation unit, the second charge accumulation unit, the third charge accumulation unit, and the fourth charge accumulation unit. This makes it possible to obtain a signal corresponding to the total charge of the four charge storage sections 4. For example, four-pixel addition becomes possible.

[0155] As described with reference to FIG. 3 and other figures, the photodetector 100 may include a first semiconductor substrate (semiconductor substrate P1) on which the first photoelectric conversion unit, the first charge accumulation unit, the second photoelectric conversion unit, and the second charge accumulation unit are formed, and a second semiconductor substrate (semiconductor substrate P2) on which the first amplification transistor, the second amplification transistor, and the switch transistor 54 are formed. This allows different design rules to be used between the semiconductor substrate P1 on which the photoelectric conversion unit 3 and the charge accumulation unit 4 are formed and the semiconductor substrate P2 on which the amplification transistor 52 and the switch transistor 54 are formed, for example. This can contribute to improving the performance of the photodetector 100.

[0156] The photodetector 100 can also be specified from another perspective. As described with reference to FIGS. 1 to 32 , the photodetector 100 includes a first semiconductor substrate (semiconductor substrate P1), a first photoelectric conversion unit (e.g., the photoelectric conversion unit 3 of pixel 2-1) formed on the first semiconductor substrate, a first charge accumulation unit (e.g., the charge accumulation unit 4 of pixel 2-1) formed on the first semiconductor substrate and directly connected to the first photoelectric conversion unit, arranged in the substrate thickness direction (Z-axis direction), a second photoelectric conversion unit (e.g., the photoelectric conversion unit 3 of pixel 2-2) formed on the first semiconductor substrate, a second charge accumulation unit (e.g., the charge accumulation unit 4 of pixel 2-2) formed on the first semiconductor substrate, arranged in the substrate thickness direction and directly connected to the second photoelectric conversion unit, and a charge accumulation unit (e.g., the charge accumulation unit 4 of pixel 2-2) formed on the first semiconductor substrate. a separation portion located therebetween, a second semiconductor substrate, a first amplification transistor (e.g., amplification transistor 52 of pixel 2-1) formed on the second semiconductor substrate and connected to the first charge accumulation portion, a second amplification transistor (e.g., amplification transistor 52 of pixel 2-2) formed on the second semiconductor substrate and connected to the second charge accumulation portion, a first contact (e.g., contact 6 of pixel 2-1) extending from the first charge accumulation portion to the second semiconductor substrate, and a second contact (e.g., contact 6 of pixel 2-2) extending from the second charge accumulation portion to the second semiconductor substrate, and the first contact and the second contact are spaced apart from the separation portion when viewed in a plan view (when viewed in the negative direction of the Z axis).

[0157] The photodetector 100 described above also eliminates the transfer transistor that was conventionally used by directly connecting the charge accumulation unit 4 to the photoelectric conversion unit 3. This addresses the issues associated with miniaturization. Furthermore, since the contact 6 is located farther away from the isolation unit, dark current that may occur in the charge accumulation unit 4 can be suppressed. A transfer path can be formed without being affected by the isolation unit. Furthermore, different design rules can be used between the semiconductor substrate P1 on which the photoelectric conversion unit 3 and the charge accumulation unit 4 are formed and the semiconductor substrate P2 on which the amplification transistor 52 and the switch transistor 54 are formed. This can contribute to improving the performance of the photodetector 100.

[0158] As described with reference to Figure 6 and the like, in plan view, the distance from the center of the first photoelectric conversion unit (for example, the center 3c of the photoelectric conversion unit 3 of pixel 2-1) to the center of the first contact may be equal to or less than half the distance from the center of the first photoelectric conversion unit to the separation unit, and the distance from the center of the second photoelectric conversion unit (for example, the center 3c of the photoelectric conversion unit 3 of pixel 2-2) to the center of the second contact may be equal to or less than half the distance from the center of the second photoelectric conversion unit to the separation unit (distance d1≦(distance d2 / 2). As described with reference to Figure 7 and the like, in plan view, the center of the first contact may substantially overlap with the center of the first photoelectric conversion unit, and the center of the second contact may substantially overlap with the center of the second photoelectric conversion unit. In this way, as the contact 6 becomes farther away from the separation unit, in other words, as the center 6c of the contact 6 approaches the center 3c of the photoelectric conversion unit 3, the effect of being able to form a transfer path without being affected by the separation unit is more easily obtained.

[0159] 3 and 27 , the isolation portion includes a trench portion 9 extending to the same height (position in the Z-axis direction) as the first charge accumulation portion and the second charge accumulation portion, and the trench portion 9 may include a hole accumulation layer (formed, for example, on the surface of the trench portion 9 on the P-type region 8 side). The trench portion 9 includes an electrode layer 91 extending in the same direction as the extension direction of the trench portion 9 (the Z-axis direction), and a pair of insulating layers 92 positioned on opposite sides of the electrode layer 91 in a direction intersecting the extension direction of the electrode layer 91 (the X-axis direction in the examples of FIGS. 3 and 27 ) and extending in the same direction as the extension direction of the insulating layer 92, and the electrode layer 91 of the trench portion 9 may have a negative potential. In this way, for example, the trench portion 9 of a full trench can be provided with the function of a hole accumulation layer.

[0160] As described with reference to Figures 12 and 13, the isolation portion may include: a first P-type region (e.g., P-type region 8 of pixel 2-1) extending along the side surfaces of the first photoelectric conversion portion and the side surfaces of the first well region (e.g., well region 40 of pixel 2-1) in which the first charge accumulation portion is formed so as to cover these surfaces; a second P-type region (e.g., P-type region 8 of pixel 2-2) extending along the side surfaces of the second photoelectric conversion portion and the side surfaces of the second well region (e.g., well region 40 of pixel 2-2) in which the second charge accumulation portion is formed so as to cover these surfaces; a trench portion 9 located on the opposite side of the first photoelectric conversion portion across the first P-type region and on the opposite side of the second photoelectric conversion portion across the second P-type region; and a connection portion 8a connected between the first P-type region and the second P-type region at the same height as the first charge accumulation portion and the second charge accumulation portion. As described with reference to FIGS. 12, 13, 26, etc., the photodetector 100 includes a third photoelectric conversion unit (e.g., photoelectric conversion unit 3 of pixel 2-3) formed on a first semiconductor substrate, a third charge accumulation unit (e.g., charge accumulation unit 4 of pixel 2-3) formed on the first semiconductor substrate and directly connected to the third photoelectric conversion unit in the substrate thickness direction, a fourth photoelectric conversion unit (e.g., photoelectric conversion unit 3 of pixel 2-4) formed on the first semiconductor substrate, and a fourth photoelectric conversion unit (e.g., photoelectric conversion unit 4 of pixel 2-4) formed on the first semiconductor substrate. The conversion unit may include a fourth charge accumulation unit (e.g., charge accumulation unit 4 of pixel 2-4) directly connected to the conversion unit in a line in the substrate thickness direction, and a well contact 40a commonly connected to a first well region in which the first charge accumulation unit is formed, a second well region in which the second charge accumulation unit is formed, a third well region in which the third charge accumulation unit is formed (e.g., well region 40 of pixel 2-3), and a fourth well region in which the fourth charge accumulation unit is formed (e.g., well region 40 of pixel 2-3). As described with reference to Figures 1 to 5 and 28, the photodetector 100 includes a first photoelectric conversion unit and a second photoelectric conversion unit, and is equipped with a plurality of photoelectric conversion units 3 arranged in an array, a guard ring unit 15 provided outside the array of the plurality of photoelectric conversion units 3 (an array of a plurality of pixels 2), and a well contact 40a connected to a first well region in which a first charge accumulation unit is formed and a second well region in which a second charge accumulation unit is formed, and the well contact 40a may be provided in the guard ring unit 15.For example, various arrangements of such well contacts 40a are possible.

[0161] 3 and other figures, the semiconductor substrate P1 includes a first insulating layer (insulating layer 10), the semiconductor substrate P2 includes a second insulating layer (insulating layer 20), the contact 6 passes through the first insulating layer and extends from the charge storage unit 4 to the semiconductor substrate P2, and the thickness of the first insulating layer (length in the Z-axis direction) may be thinner than the thickness of the second insulating layer. By shortening the contact 6 passing through the first insulating layer, an increase in the capacitance of the charge storage unit 4 can be suppressed.

[0162] 1 to 3 and 22 to 25, the first charge accumulation portion includes a floating diffusion region (FD), the second charge accumulation portion includes a FD, and the photodetector 100 may include a first mask member (e.g., the dummy member 12 or the electrode material 14 of pixel 2-1) provided to define an opening in the floating diffusion region of the first charge accumulation portion, and a second mask member (e.g., the dummy member 12 or the electrode material 14 of pixel 2-2) provided to define an opening in the floating diffusion region of the second charge accumulation portion. This makes it possible to suppress an increase in dark current that may occur, for example, due to excessive spreading of the FD.

[0163] As described with reference to Figures 1 to 3 and Figures 14 to 16, the charges accumulated in the first charge accumulation unit include the charges generated in the first photoelectric conversion unit and the first noise charges generated in the first charge accumulation unit, and the charges accumulated in the second charge accumulation unit include the charges generated in the second photoelectric conversion unit and the second noise charges generated in the second charge accumulation unit. In order to remove the signal corresponding to the first noise charges from the signal corresponding to the charges accumulated in the first charge accumulation unit and also remove the signal corresponding to the second noise charges from the signal corresponding to the charges accumulated in the second charge accumulation unit, the photodetector 100 may include at least one of a frame memory M1 that holds the voltage of the signal corresponding to the first noise charges and the voltage of the signal corresponding to the second noise charges, and a noise cancellation circuit (e.g., amplifier 55, signal line 109, capacitor C1, capacitor C2, etc.) that negatively feeds back the voltage of the signal corresponding to the first noise charges to the first charge accumulation unit and negatively feeds back the voltage of the signal corresponding to the second noise charges to the second charge accumulation unit. Noise (for example, KTC noise) can be removed.

[0164] 19 and other drawings, the photodetector 100 may include a reset transistor 51 connected between the first and second charge accumulation units and a power supply node VDD, and configured to discharge the charges accumulated in the first and second charge accumulation units to the power supply node VDD. The switch transistor 54 may be electrically connected between the first and second charge accumulation units and the reset transistor 51 so as to commonly connect the first and second charge accumulation units to the reset transistor 51. This allows for a reduction in the number of reset transistors 51, which can contribute to layout area efficiency and the like.

[0165] 2 and 20 , the photodetector 100 includes a reset transistor 51 connected between the first charge storage unit 41 and the second charge storage unit 42 and a power supply node, and configured to discharge the charges stored in the first charge storage unit 41 and the second charge storage unit 42 to the power supply node. The voltage VB of the power supply node may be switched between a low voltage and a high voltage. This allows the range (amount of charge that can be stored) of the charge storage unit 4 to be variable. By switching the voltage VB for each row, signals from pixels 2 in rows with different voltages VB can be combined.

[0166] 2 and 32 , the photodetector 100 includes a reset transistor 51 connected between the first charge accumulation unit and the second charge accumulation unit and a power supply node VDD, and configured to discharge the charges accumulated in the first charge accumulation unit and the second charge accumulation unit to the power supply node VDD, and the potential of the power supply node VDD may be temporarily controlled to a low potential (time t12 to time t13) during an on-period (time t11 to time t14) of the reset transistor 51. This allows holes accumulated in the peripheral P-type regions of the photoelectric conversion unit 3 and the charge accumulation unit 4 to be discharged.

[0167] As described with reference to FIG. 18 and other figures, the first semiconductor substrate includes a first insulating layer (insulating layer 10), the second semiconductor substrate includes a second insulating layer (insulating layer 20), and the first and second semiconductor substrates are bonded together so that the surface of the first semiconductor substrate facing the first insulating layer and the surface of the second semiconductor substrate facing the second insulating layer are in surface contact, and the first contact and the second contact may extend through the first insulating layer into the second insulating layer. For example, such an F2F stacking is also possible. The increased number of options for stacking the first and second semiconductor substrates improves the degree of freedom in designing the layout, etc.

[0168] The effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0169] 4. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0170] FIG. 33 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0171] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 33, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0172] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0173] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0174] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0175] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0176] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0177] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0178] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0179] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0180] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 33, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0181] FIG. 34 is a diagram showing an example of the installation position of the imaging unit 12031.

[0182] In FIG. 34, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0183] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0184] 34 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0185] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0186] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0187] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0188] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0189] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the above-described configurations. Specifically, the photodetector 100 ( FIG. 1 , etc.), which is a solid-state imaging device, can be applied to the imaging unit 12031. For example, it may be possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0190] 5. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0191] FIG. 35 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0192] 35 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0193] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0194] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0195] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0196] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0197] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0198] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0199] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0200] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0201] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0202] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0203] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0204] FIG. 36 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0205] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0206] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0207] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0208] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0209] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0210] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0211] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0212] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0213] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0214] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0215] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0216] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0217] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0218] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0219] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0220] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0221] The foregoing describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging unit 11402 of the camera head 11102, among the components described above. Specifically, the photodetector 100 (FIG. 1, etc.), which is a solid-state imaging device, can be applied to the imaging unit 10402. For example, this increases the likelihood of obtaining a clearer image of the surgical site, thereby enabling the surgeon to more reliably confirm the surgical site.

[0222] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0223] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0224] The present technology may also be configured as follows: (1) A photodetector including a first photoelectric conversion unit, a first charge accumulation unit directly connected to the first photoelectric conversion unit, a first amplification transistor connected to the first charge accumulation unit, a second photoelectric conversion unit, a second charge accumulation unit directly connected to the second photoelectric conversion unit, a second amplification transistor connected to the second charge accumulation unit, and a switch transistor electrically connected between the first charge accumulation unit and the second charge accumulation unit. (2) The photodetector device according to (1), comprising: a third photoelectric conversion unit; a third charge accumulation unit directly connected to the third photoelectric conversion unit; a fourth photoelectric conversion unit; and a fourth charge accumulation unit directly connected to the fourth photoelectric conversion unit, wherein the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit are arranged in an array; the first photoelectric conversion unit and the second photoelectric conversion unit are arranged side by side in the row direction; the third photoelectric conversion unit and the fourth photoelectric conversion unit are arranged side by side in the column direction; and the switch transistor is electrically connected between the first charge accumulation unit, the second charge accumulation unit, the third charge accumulation unit, and the fourth charge accumulation unit. (3) The photodetector according to (1) or (2), comprising: a first semiconductor substrate on which the first photoelectric conversion unit, the first charge accumulation unit, the second photoelectric conversion unit, and the second charge accumulation unit are formed; and a second semiconductor substrate on which the first amplification transistor, the second amplification transistor, and the switch transistor are formed.(4) A semiconductor device comprising: a first semiconductor substrate; a first photoelectric conversion unit formed on the first semiconductor substrate; a first charge accumulation unit formed on the first semiconductor substrate and directly connected to the first photoelectric conversion unit, arranged side by side in a substrate thickness direction; a second photoelectric conversion unit formed on the first semiconductor substrate; a second charge accumulation unit formed on the first semiconductor substrate and directly connected to the second photoelectric conversion unit, arranged side by side in a substrate thickness direction; an isolation unit formed on the first semiconductor substrate and located between the first photoelectric conversion unit and the second photoelectric conversion unit; a second semiconductor substrate; a first amplification transistor formed on the second semiconductor substrate and connected to the first charge accumulation unit; a second amplification transistor formed on the second semiconductor substrate and connected to the second charge accumulation unit; a first contact extending from the first charge accumulation unit to the second semiconductor substrate; and a second contact extending from the second charge accumulation unit to the second semiconductor substrate, A photodetector, wherein the first contact and the second contact are spaced apart from the isolation portion in a plan view. (5) The photodetector according to (4), wherein, in a plan view, the distance from the center of the first photoelectric conversion portion to the center of the first contact is equal to or less than half the distance from the center of the first photoelectric conversion portion to the isolation portion, and the distance from the center of the second photoelectric conversion portion to the center of the second contact is equal to or less than half the distance from the center of the second photoelectric conversion portion to the isolation portion. (6) The photodetector according to (4) or (5), wherein, in a plan view, the center of the first contact substantially overlaps the center of the first photoelectric conversion portion, and the center of the second contact substantially overlaps the center of the second photoelectric conversion portion. (7) The photodetector according to any of (4) to (6), wherein the isolation portion includes a trench portion extending to the same height as the first charge accumulation portion and the second charge accumulation portion, and the trench portion includes a hole accumulation layer.(8) The photodetector according to (7), wherein the trench portion includes an electrode layer extending in the same direction as the extension direction of the trench portion, and a pair of insulating layers positioned on opposite sides of the electrode layer in a direction intersecting the extension direction of the electrode layer and extending in the same direction as the extension direction of the electrode layer, and the electrode layer in the trench portion has a negative potential. (9) The photodetector according to any one of (4) to (6), wherein the isolation portion includes: a first P-type region extending along a side surface of the first photoelectric conversion portion and a side surface of a first well region in which the first charge accumulation portion is formed so as to cover these surfaces; a second P-type region extending along a side surface of the second photoelectric conversion portion and a side surface of the second well region in which the second charge accumulation portion is formed so as to cover these surfaces; a trench portion located on the opposite side of the first photoelectric conversion portion across the first P-type region and on the opposite side of the second photoelectric conversion portion across the second P-type region; and a connection portion connected between the first P-type region and the second P-type region at the same height as the first charge accumulation portion and the second charge accumulation portion. (10) The photodetector according to (9), comprising: a third photoelectric conversion unit formed on the first semiconductor substrate; a third charge accumulation unit formed on the first semiconductor substrate and directly connected to the third photoelectric conversion unit in a line-up in the substrate thickness direction; a fourth photoelectric conversion unit formed on the first semiconductor substrate; a fourth charge accumulation unit formed on the first semiconductor substrate and directly connected to the fourth photoelectric conversion unit in a line-up in the substrate thickness direction; and a well contact commonly connected to a first well region in which the first charge accumulation unit is formed, a second well region in which the second charge accumulation unit is formed, a third well region in which the third charge accumulation unit is formed, and a fourth well region in which the fourth charge accumulation unit is formed.(11) The photodetector according to (9), comprising: a plurality of photoelectric conversion units, each including the first photoelectric conversion unit and the second photoelectric conversion unit, arranged in an array; a guard ring unit provided outside the array of the plurality of photoelectric conversion units; and a well contact connected to a first well region in which the first charge accumulation unit is formed and a second well region in which the second charge accumulation unit is formed, wherein the well contact is provided in the guard ring unit. (12) The photodetector according to any of (4) to (11), wherein the first semiconductor substrate includes a first insulating layer, the second semiconductor substrate includes a second insulating layer, the first contact passes through the first insulating layer and extends from the first charge accumulation unit to the second semiconductor substrate, the second contact passes through the first insulating layer and extends from the second charge accumulation unit to the second semiconductor substrate, and a thickness of the first insulating layer is thinner than a thickness of the second insulating layer. (13) The photodetector according to any one of (1) to (12), wherein the first charge accumulation portion includes a floating diffusion region, the second charge accumulation portion includes a floating diffusion region, and the photodetector comprises: a first mask member provided to define an opening in the floating diffusion region of the first charge accumulation portion; and a second mask member provided to define an opening in the floating diffusion region of the second charge accumulation portion.(14) The photodetector according to any one of (1) to (13), wherein the charges accumulated in the first charge accumulation unit include charges generated in the first photoelectric conversion unit and first noise charges generated in the first charge accumulation unit, and the charges accumulated in the second charge accumulation unit include charges generated in the second photoelectric conversion unit and second noise charges generated in the second charge accumulation unit, and the photodetector comprises at least one of: a frame memory that holds a voltage of a signal corresponding to the first noise charges and a voltage of a signal corresponding to the second noise charges in order to remove a signal corresponding to the first noise charges from a signal corresponding to the charges accumulated in the first charge accumulation unit and to remove a signal corresponding to the second noise charges from a signal corresponding to the charges accumulated in the second charge accumulation unit; and a noise cancellation circuit that negatively feeds back the voltage of the signal corresponding to the first noise charges to the first charge accumulation unit and negatively feeds back the voltage of the signal corresponding to the second noise charges to the second charge accumulation unit. (15) The photodetector according to any one of (1) to (14), further comprising a reset transistor connected between the first charge accumulation unit and the second charge accumulation unit and a power supply node, and discharging the charges accumulated in the first charge accumulation unit and the second charge accumulation unit to the power supply node. (16) The photodetector according to any one of (1) to (15), further comprising a reset transistor connected between the first charge accumulation unit and the second charge accumulation unit and a power supply node, and discharging the charges accumulated in the first charge accumulation unit and the second charge accumulation unit to the power supply node, wherein the voltage of the power supply node is switched between a low voltage and a high voltage. (17) The photodetector according to (16), further comprising a switch transistor electrically connected between the first charge accumulation unit and the second charge accumulation unit and the reset transistor so as to commonly connect the first charge accumulation unit and the second charge accumulation unit to the reset transistor.(18) The photodetector according to any one of (1) to (17), further comprising a reset transistor connected between the first charge accumulation unit and the second charge accumulation unit and a power supply node, the reset transistor discharging the charges accumulated in the first charge accumulation unit and the second charge accumulation unit to the power supply node, wherein the potential of the power supply node is temporarily controlled to a low potential during an on-period of the reset transistor. (19) The photodetector according to any one of (1) to (18), wherein the first semiconductor substrate includes a first insulating layer, the second semiconductor substrate includes a second insulating layer, the first semiconductor substrate and the second semiconductor substrate are bonded together so that a surface of the first semiconductor substrate facing the first insulating layer and a surface of the second semiconductor substrate facing the second insulating layer are in surface-to-surface contact, and the first contact and the second contact extend through the first insulating layer into the second insulating layer.

[0225] 1 Photodetector element 10 Insulating layer 11 Boost wiring 12 Dummy member 13 Resist 14 Electrode material 15 Guard ring portion 16 Wiring 18 Filter layer 19 Lens layer 2 Pixel 20 Insulating layer 3 Photoelectric conversion portion 31 Body 32 End portion 3c Center 4 Charge storage portion 40 Well region 40a Well contact 41 Electrode 50 Electrode 51 Reset transistor 52 Amplifying transistor 53 Select transistor 54 Switch transistor 55 Amplifier 56 Feedback transistor 6 Contact 6c Center 7 Wiring 8 P-type region 8a Connection portion 9 Trench portion 91 Electrode layer 92 Insulating layer 100 Photodetector device 101 Control circuit 102 Vertical drive circuit 103 Column signal processing circuit 104 Horizontal drive circuit 105 Output circuit 106 Signal line 107 Signal line 108 Signal line 109 Signal line C1 Capacitor C2 Capacitor M1 Frame memory VB Voltage VDD Power supply node d1 Distance d2 Distance P1 Semiconductor substrate p1a Front surface P2 Semiconductor substrate p2a Front surface p2b Back surface

Claims

1. A photodetector comprising: a first photoelectric conversion unit; a first charge accumulation unit directly connected to the first photoelectric conversion unit; a first amplification transistor connected to the first charge accumulation unit; a second photoelectric conversion unit; a second charge accumulation unit directly connected to the second photoelectric conversion unit; a second amplification transistor connected to the second charge accumulation unit; and a switch transistor electrically connected between the first charge accumulation unit and the second charge accumulation unit.

2. The photodetector according to claim 1, comprising: a third photoelectric conversion unit; a third charge accumulation unit directly connected to the third photoelectric conversion unit; a fourth photoelectric conversion unit; and a fourth charge accumulation unit directly connected to the fourth photoelectric conversion unit; wherein the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit are arranged in an array; the first photoelectric conversion unit and the second photoelectric conversion unit are arranged side by side in the row direction; the third photoelectric conversion unit and the fourth photoelectric conversion unit are arranged side by side in the column direction; and the switch transistor is electrically connected between the first charge accumulation unit, the second charge accumulation unit, the third charge accumulation unit, and the fourth charge accumulation unit.

3. The photodetector according to claim 1, comprising: a first semiconductor substrate on which the first photoelectric conversion unit, the first charge accumulation unit, the second photoelectric conversion unit, and the second charge accumulation unit are formed; and a second semiconductor substrate on which the first amplification transistor, the second amplification transistor, and the switch transistor are formed.

4. A semiconductor device comprising: a first semiconductor substrate; a first photoelectric conversion unit formed on the first semiconductor substrate; a first charge accumulation unit formed on the first semiconductor substrate and directly connected to the first photoelectric conversion unit, arranged side by side in the substrate thickness direction; a second photoelectric conversion unit formed on the first semiconductor substrate; a second charge accumulation unit formed on the first semiconductor substrate and directly connected to the second photoelectric conversion unit, arranged side by side in the substrate thickness direction; an isolation unit formed on the first semiconductor substrate and located between the first photoelectric conversion unit and the second photoelectric conversion unit; a second semiconductor substrate; a first amplification transistor formed on the second semiconductor substrate and connected to the first charge accumulation unit; a second amplification transistor formed on the second semiconductor substrate and connected to the second charge accumulation unit; a first contact extending from the first charge accumulation unit to the second semiconductor substrate; and a second contact extending from the second charge accumulation unit to the second semiconductor substrate, The photodetector device, wherein the first contact and the second contact are spaced apart from the separation portion in a plan view.

5. The photodetector device of claim 4, wherein, when viewed in a plane, the distance from the center of the first photoelectric conversion unit to the center of the first contact is 1 / 2 or less of the distance from the center of the first photoelectric conversion unit to the separation unit, and the distance from the center of the second photoelectric conversion unit to the center of the second contact is 1 / 2 or less of the distance from the center of the second photoelectric conversion unit to the separation unit.

6. The photodetector device according to claim 4, wherein, when viewed in a plane, the center of the first contact substantially overlaps with the center of the first photoelectric conversion element, and the center of the second contact substantially overlaps with the center of the second photoelectric conversion element.

7. The photodetector according to claim 4, wherein the isolation section includes a trench section extending to the same height as the first charge accumulation section and the second charge accumulation section, and the trench section includes a hole accumulation layer.

8. The photodetector device according to claim 7, wherein the trench portion includes an electrode layer extending in the same direction as the extension direction of the trench portion, and a pair of insulating layers positioned on opposite sides of the electrode layer in a direction intersecting the extension direction of the electrode layer and extending in the same direction as the extension direction of the electrode layer, and the electrode layer in the trench portion has a negative potential.

9. The photodetector device of claim 4, wherein the isolation portion includes: a first P-type region extending along the side surfaces of the first photoelectric conversion portion and the side surfaces of the first well region in which the first charge accumulation portion is formed so as to cover these surfaces; a second P-type region extending along the side surfaces of the second photoelectric conversion portion and the side surfaces of the second well region in which the second charge accumulation portion is formed so as to cover these surfaces; a trench portion located on the opposite side of the first P-type region from the first photoelectric conversion portion and on the opposite side of the second P-type region from the second photoelectric conversion portion; and a connection portion connected between the first P-type region and the second P-type region at the same height as the first charge accumulation portion and the second charge accumulation portion.

10. The photodetector according to claim 9, comprising: a third photoelectric conversion unit formed on the first semiconductor substrate; a third charge accumulation unit formed on the first semiconductor substrate and directly connected to the third photoelectric conversion unit and arranged in the substrate thickness direction; a fourth photoelectric conversion unit formed on the first semiconductor substrate; a fourth charge accumulation unit formed on the first semiconductor substrate and directly connected to the fourth photoelectric conversion unit and arranged in the substrate thickness direction; and a well contact commonly connected to a first well region in which the first charge accumulation unit is formed, a second well region in which the second charge accumulation unit is formed, a third well region in which the third charge accumulation unit is formed, and a fourth well region in which the fourth charge accumulation unit is formed.

11. A photodetector as described in claim 9, comprising: a plurality of photoelectric conversion units, each including the first photoelectric conversion unit and the second photoelectric conversion unit, arranged in an array; a guard ring unit provided outside the array of the plurality of photoelectric conversion units; and a well contact connected to a first well region in which the first charge accumulation unit is formed and a second well region in which the second charge accumulation unit is formed, wherein the well contact is provided in the guard ring unit.

12. The photodetector device of claim 4, wherein the first semiconductor substrate includes a first insulating layer, the second semiconductor substrate includes a second insulating layer, the first contact extends through the first insulating layer from the first charge storage portion to the second semiconductor substrate, the second contact extends through the first insulating layer from the second charge storage portion to the second semiconductor substrate, and the thickness of the first insulating layer is thinner than the thickness of the second insulating layer.

13. The photodetector according to claim 1, wherein the first charge accumulation portion includes a floating diffusion region, the second charge accumulation portion includes a floating diffusion region, and the photodetector comprises: a first mask member provided to define an opening in the floating diffusion region of the first charge accumulation portion; and a second mask member provided to define an opening in the floating diffusion region of the second charge accumulation portion.

14. The photodetector according to claim 1, wherein the charges accumulated in the first charge accumulation unit include charges generated in the first photoelectric conversion unit and a first noise charge generated in the first charge accumulation unit, and the charges accumulated in the second charge accumulation unit include charges generated in the second photoelectric conversion unit and a second noise charge generated in the second charge accumulation unit, and the photodetector comprises at least one of: a frame memory that holds the voltage of the signal corresponding to the first noise charge and the voltage of the signal corresponding to the second noise charge, in order to remove the signal corresponding to the first noise charge from the signal corresponding to the charges accumulated in the first charge accumulation unit and to remove the signal corresponding to the second noise charge from the signal corresponding to the charges accumulated in the second charge accumulation unit; and a noise cancellation circuit that negatively feeds back the voltage of the signal corresponding to the first noise charge to the first charge accumulation unit and negatively feeds back the voltage of the signal corresponding to the second noise charge to the second charge accumulation unit.

15. The photodetector according to claim 1, further comprising a reset transistor connected between the first charge storage section and the second charge storage section and a power supply node, for discharging the charges stored in the first charge storage section and the second charge storage section to the power supply node.

16. The photodetector device according to claim 1, further comprising a reset transistor connected between the first charge storage unit and the second charge storage unit and a power supply node, for discharging the charges stored in the first charge storage unit and the charges stored in the second charge storage unit to the power supply node, and the voltage of the power supply node is switched between a low voltage and a high voltage.

17. The photodetector device according to claim 16, wherein the switch transistor is electrically connected between the first charge storage unit and the second charge storage unit and the reset transistor so as to commonly connect the first charge storage unit and the second charge storage unit to the reset transistor.

18. The photodetector device according to claim 1, further comprising a reset transistor connected between the first charge storage section and the second charge storage section and a power supply node, for discharging the charges stored in the first charge storage section and the charges stored in the second charge storage section to the power supply node, and wherein the potential of the power supply node is temporarily controlled to a low potential while the reset transistor is on.

19. The photodetector device of claim 4, wherein the first semiconductor substrate includes a first insulating layer, the second semiconductor substrate includes a second insulating layer, the first semiconductor substrate and the second semiconductor substrate are bonded together so that a surface of the first semiconductor substrate facing the first insulating layer and a surface of the second semiconductor substrate facing the second insulating layer are in surface contact, and the first contact and the second contact extend through the first insulating layer into the second insulating layer.

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