Wiring substrate and method for manufacturing wiring substrate

Abstract

The purpose of the present invention is to provide a wiring substrate in which fine wiring members 50 can be reliably mounted in cavities 35, in proximity to side walls of the cavities, and to provide a method for manufacturing the wiring substrate.　In a wiring substrate 20 on which at least one semiconductor element 40 is mounted, the wiring substrate has a core layer 60. Wiring layers (21, 22) are arranged on a first surface and a second surface of the core layer. At least one through electrode 30 that penetrates from the first surface to the second surface is provided in the core layer.　At least one bottomed cavity 35 is formed in the surface of the core layer on which the semiconductor element is mounted. A fine wiring member 50 is placed in the cavity. Irregularities having a surface roughness Sa of 500 nm or greater are formed on the bottom of the cavity. The presence of the irregularities on the bottom surface of the cavity enables the fine wiring member to be reliably fixed to the wiring substrate.

Description

Wiring board and method of manufacturing the same

[0001] Wiring board and method of manufacturing the same

[0002] In recent years, innovations in semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology have led to rapid advances in the performance of electronic products. Semiconductor technology has achieved nano-level linewidths below the micron level, enabling highly integrated cells with more than 10 million cells per chip, while also achieving various advances in high-speed operation and thermal processing. However, packaging technology has not yet been fully established to keep up with the increasing sophistication of these semiconductor elements, and the performance of final semiconductor products is sometimes limited by packaging technology and its electrical connection technology.

[0003] Ceramic or resin is often used as a material for packaging substrates. Ceramic substrates have high resistance and excellent insulation against direct current, but they have a high dielectric constant, which results in significant energy loss in an alternating current electric field, making them unsuitable for mounting high-performance, high-frequency semiconductor elements. Resin substrates can accommodate high-frequency semiconductor elements, but there is a limit to the wiring pitch that can be formed on the substrate, and warping can occur due to the effects of thermal history, making it difficult to mount high-performance semiconductor elements.

[0004] Meanwhile, in recent years, attention has been focused on technology that applies silicon or glass to high-end packaging substrates. Through-holes are formed in silicon or glass substrates, and conductive materials are attached to the through-holes to form intermediate substrates used between semiconductor elements and motherboards. This shortens the wiring length between the semiconductor elements and motherboard, and results in intermediate substrates with excellent electrical properties.

[0005] For example, Patent Document 1 discloses the following with the aim of providing a packaging substrate having a cavity structure and applicable to high-speed circuits, and a semiconductor device including the same: "A semiconductor device 100 includes a semiconductor element section 30 including semiconductor elements 32, 34, and 36, and a packaging substrate 20 electrically connected to the semiconductor element section. By using a glass substrate as a core for the packaging substrate 20, the semiconductor elements and the motherboard are connected more closely, allowing electrical signals to be transmitted over the shortest possible distance. Electrical characteristics such as signal transmission speed are greatly improved, and the generation of parasitic elements is substantially prevented, thereby further simplifying the insulating film processing process."

[0006] JP 2023-52130 A

[0007] However, in Patent Document 1, in order to fix a component (cavity element) in the cavity, an arc-shaped support portion that connects one end and the other end of the lateral surface of the cavity portion is provided and protrudes into the cavity interior space. The position of the cavity element is fixed by this support portion. However, because the glass substrate is a brittle material, using an arc-shaped support portion that connects one end and the other end may cause cracks or chips when the component is fixed. Furthermore, using an arc-shaped support portion that connects one end and the other end makes it difficult to shorten the distance between the cavity and the through-electrode of the element.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a wiring board that can reliably mount a fine wiring member in a cavity close to its sidewall, and a method for manufacturing the wiring board.

[0009] In order to solve the above problems, one representative multilayer wiring board of the present invention is a wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, and at least one cavity with a bottom formed on the surface of the core layer on which the semiconductor element is mounted, a micro-wiring member placed in the cavity, and an unevenness having a roughness Sa of 500 nm or more formed on the bottom of the cavity.

[0010] Furthermore, one representative method for manufacturing a wiring board of the present invention includes the steps of: irradiating a laser to a portion of a core layer of the wiring board where a through electrode and a portion where a cavity are to be formed, and performing an etching process to form a cavity having irregularities with a roughness Sa of 500 nm or more at the bottom of the through hole and the cavity; and arranging a fine wiring member in the cavity.

[0011] According to the present invention, it is possible to provide a wiring board and a method for manufacturing a wiring board that can reliably mount a micro wiring member in a cavity in a state close to the sidewall of the cavity. Problems, configurations, and effects other than those described above will become apparent from the description of the following embodiments of the invention.

[0012] FIG. 1 is a cross-sectional view of a semiconductor package substrate. FIG. 2A is a plan view of a semiconductor package substrate on which one wiring board is mounted. FIG. 2B is a plan view of a semiconductor package substrate on which multiple wiring boards are mounted. FIG. 3 is a cross-sectional view showing an example of a semiconductor package substrate. FIG. 4 is a cross-sectional view showing the structure of a core layer. FIG. 5A is a diagram illustrating the shape of the bottom of a cavity. FIG. 5B is a diagram illustrating the shape of the bottom of a cavity. FIG. 6 is a diagram illustrating the shape of a sidewall of a cavity. FIG. 7 is a diagram illustrating the inclination angle of a sidewall of a cavity. FIG. 8 is a diagram illustrating the positional relationship between a cavity and a through hole. FIG. 9 is a cross-sectional view illustrating through electrodes and wiring formed in a core layer. FIG. 10 is a cross-sectional view of a semiconductor package substrate according to a second embodiment. FIG. 11 is a cross-sectional view illustrating a third embodiment in which multiple types of cavities are mixed. FIG. 12 is a diagram illustrating a process of eluting a core layer. FIG. 13 is a diagram illustrating a process of performing laser processing on the core layer to form the starting points of through holes and cavities. FIG. 14 is a diagram illustrating the overlap of laser modification and modified portions obtained by etching. FIG. 15 is a diagram illustrating a process for forming through holes and cavities in a core material by etching. FIG. 16 is a diagram illustrating the shape of through holes formed in a core layer. FIG. 17 is a diagram illustrating a process for forming conductor layers in through holes formed in a core layer. FIG. 18 is a diagram illustrating a process for mounting a microwiring member in a cavity portion. FIG. 19 is a diagram illustrating a process for forming a microwiring member and insulating resin layers on the front and back surfaces of a core material. FIG. 20 is a diagram illustrating a process for forming wiring on insulating resin layers formed on the front and back surfaces of a core material. FIG. 21 is a diagram illustrating a process for forming wiring layers and connection terminals. FIG. 22 is a diagram illustrating a process for connecting a semiconductor element and a wiring substrate. FIG. 23 is a diagram illustrating a process for filling an underfill into a connection portion between a semiconductor element and a wiring substrate. FIG. 24 is a diagram illustrating the formation of a protective resin for a semiconductor element. FIG. 25 is a diagram illustrating a laser processing process according to a second embodiment. FIG. 26 is a diagram illustrating an etching process according to the second embodiment. FIG. 27 is a diagram illustrating a laser processing step for forming a through-hole in a cavity portion in a structure that is a modification of the semiconductor package substrate according to the embodiment of the present invention.FIG. 28 is a diagram illustrating an etching step for forming a through hole in a cavity portion in a structure that is a modification of the semiconductor package substrate according to the embodiment of the present invention.

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the embodiments and examples shown below are merely examples of embodiments of the present invention, and the present invention should not be construed as being limited to these embodiments and examples. Note that in the drawings referred to in the embodiments of the present invention, identical or similar symbols (symbols consisting of a number followed by A, B, etc.) are used for identical parts, and repeated explanations may be omitted. Furthermore, explanations of dimensions and ratios in the drawings may differ from actual ratios or may be omitted from some of the configurations for convenience of explanation or notation.

[0014] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0015] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-shaped member or a layer contained in the plate-shaped member is illustrated. The "upper surface" and "lower surface" may also be referred to as the "first surface" and the "second surface."

[0016] Furthermore, "side" refers to the surface or thickness of a layer of a plate-like member or a layer contained in the plate-like member. Furthermore, a portion of the surface and the side surface may be collectively referred to as "end." Furthermore, "side surface of a through hole" refers to the interface on the object that forms the through hole, in the case of a through hole provided in an object. Furthermore, "upper" refers to the vertically upward direction when the plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower," are sometimes referred to as the "positive Z-axis direction" and the "negative Z-axis direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0017] Furthermore, the distance in the Z-axis direction is referred to as "height," and the distance on the XY plane defined by the X-axis and Y-axis directions is referred to as "width." Furthermore, when referring to a layered object, the height is also referred to as "thickness." Furthermore, a "through electrode" refers to a conductive path provided to electrically connect the first and second surfaces of a glass substrate when the glass substrate is used as part of a multilayer wiring board, and does not necessarily have to completely penetrate the glass substrate with a single conductive material. A through electrode is defined as a conductive path that connects the conductive path from the first surface to the conductive path from the second surface. Furthermore, the form of the through electrode may be a filled structure in which the through hole is filled with a conductive material, or a conformal structure in which only the sidewall portion of the through hole is covered with a conductive material.

[0018] Furthermore, "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction. Furthermore, "center" refers to the center, not the peripheral part, of a surface or layer. And "central direction" refers to the direction from the peripheral part of a surface or layer toward the center of the planar shape of the surface or layer.

[0019] Furthermore, when a range of values ​​is expressed as "a range of 3 to 10 ppm / °C," this means a range of 3 ppm / °C or more and 10 ppm / °C or less. The same applies to other ranges of values.

[0020] The unevenness roughness Sa means the average absolute value of the difference in height between each point and the average plane of the surface, and is defined by the following formula. A: 120 μm ２ to 650 μm ２ is.

[0021] The PV value means the difference in height between the highest point (peak) and the lowest point (valley) on the surface. The depth of the depression is defined by the following formula:

[0022] First Embodiment (Semiconductor Package Substrate) First, the structure of a semiconductor package substrate according to the first embodiment will be described with reference to FIG. 1 . FIG. 1 is a cross-sectional view of a semiconductor package substrate mounted on a motherboard 1. A semiconductor package substrate 100 according to an embodiment of the present invention is composed of an FC-BGA substrate 10, a wiring substrate 20, and a semiconductor element 40. The wiring substrate 20 is a wiring substrate for connecting the FC-BGA substrate 10 and the semiconductor element 40, and a micro-wiring member 50 is mounted on the wiring substrate 20. As shown in FIG. 1 , the semiconductor package substrate 100 is mounted on the motherboard 1 and transmits external electrical signals from the motherboard 1 to the semiconductor element 40. Furthermore, the micro-wiring member 50 mounted on the wiring substrate 20 can electrically connect multiple semiconductor elements mounted on the wiring substrate 20 to each other. The semiconductor element 40 may be a CPU, a High Bandwidth Memory (HBM), or the like.

[0023] (Planar Shape of Semiconductor Package Substrate) Next, with reference to Figures 2A and 2B, the planar shape of the semiconductor package substrate 100 on which the semiconductor element 40 and the wiring board 20 are mounted, as viewed from above, will be described. Figure 2A is a plan view of the semiconductor package substrate 100 on which one wiring board is mounted, and Figure 2B is a plan view of the semiconductor package substrate 100 on which multiple wiring boards are mounted. In the semiconductor package substrate 100, as shown in Figures 2A and 2B, at least one semiconductor element 40 is mounted above the wiring board 20, and the semiconductor elements are electrically connected to each other via the wiring board 20. In addition, the semiconductor element 40 is connected to the motherboard 1 via the FC-BGA substrate 10, allowing transmission and reception of electrical signals with the outside.

[0024] (Cross Section of Semiconductor Package Substrate) Next, with reference to FIG. 3 , the cross-sectional structure of the semiconductor package substrate 100 will be described. FIG. 3 is a cross-sectional view of the semiconductor package substrate. In FIG. 3 , the wiring substrate 20 is configured such that a first wiring layer 21 is formed on a first surface, which is the upper surface of a core layer 60, and a second wiring layer 22 is formed on a second surface of the core layer 60. A semiconductor element 40 is mounted above the first wiring layer 21 via an underfill 86. A cavity 35 is formed in the core layer 60, and a micro wiring member 50 is placed inside the cavity 35 via a DAF (Die Attach Film) 51. A through electrode 30 is formed penetrating from the first surface to the second surface of the core layer. The through electrode 30 penetrates the first and second surfaces of the core layer 60 to establish electrical connection, and the micro wiring member 50 is a wiring member for electrically connecting the semiconductor element 40 and is embedded in the cavity 35.

[0025] This allows the multiple semiconductor elements 40 to be electrically connected via the fine wiring member 50 of the wiring substrate 20 and the first wiring layer 21 of the core layer 60, and the fine wiring member 50 is fixed by the insulating resin 85 of the first wiring layer 21 of the core layer 60, in combination with the uneven shape of the bottom of the cavity 35, which will be described later.

[0026] (Cross Section of Core Layer) Next, the structure of the core layer 60 will be described with reference to Fig. 4. Fig. 4 is a cross section of the core layer in a portion where the cavities 35 and through-holes 70 are formed. A plurality of cavities 35 and through-holes 70 are formed in the core layer 60 by laser irradiation or etching, which will be described later. The core layer 60 is made of quartz, alkali-free glass, alkali glass, Al, ２ O ３ , SiO ２ , CaO, MgO, SrO, BaO, ZrO ２It is a composite material containing at least one of the above. As for the main physical properties of the core layer 60, the linear expansion coefficient is in the range of 3 to 10 ppm / °C, and the elastic modulus is 40 GPa or more, preferably about 60 GPa, and the composition ratio can be set appropriately. The thickness T1 of the core layer 60 is in the range of 100 to 1,800 μm, and preferably in the range of 200 to 1,000 μm. However, the thickness T1 of the core layer 60 is not limited to the above range, and the thickness T1 can be set appropriately.

[0027] The depth D1 of the cavity 35 having a bottom formed in the core layer 60 is equal to or greater than the thickness T2 of the microwiring member 50, and the relationship between D1 and T2 is at least D1 > T2 + 5 μm. The relationship between D1 and T2 and the thickness T1 of the core layer 60 is T1 > D1. The depth D1 of the cavity 35 may be set as appropriate as long as it satisfies the relationship D1 > T2 + 5 μm or greater.

[0028] The relationship between the width W1 and depth W2 of the bottomed cavity 35 formed in the core layer 60 and the w1 and w2 of the microwiring member 50 is w1 + 20 μm > W1 > w1 + 3 μm and w2 + 20 μm > W2 > w2 + 3 μm. The width W1 and depth W2 of the cavity 35 may be set appropriately as long as they satisfy the above conditions. If W1 > w1 + 20 μm and W2 > w2 + 20 μm, depressions may occur in the insulating resin 85 when the first wiring layer 21 is formed on the core layer 60, reducing the reliability of wiring formation and significantly reducing the yield of the wiring substrate 20.

[0029] (Unevenness of the Cavity Bottom) Next, the unevenness formed on the bottom of the cavity 35 will be described with reference to FIGS. 5A and 5B. FIG. 5A is a diagram illustrating the unevenness on the bottom of the cavity. The bottom of the cavity 35 with a bottomed structure formed in the core layer 60 has minute unevenness formed thereon, as shown in FIGS. 5A and 5B, and the roughness is preferably Sa: 500 to 1500 nm. The minute unevenness has a periodic structure, with a period in the range of 5.0 to 25 μm. The minute unevenness has the effect of enhancing adhesion with the Die Attach Film (DAF) used when mounting the microwiring member 50. If Sa: 500 nm or less, it becomes difficult to obtain the anchor effect for enhancing adhesion. Furthermore, if Ra: 1500 nm or more, the unevenness on the bottom becomes large, affecting the parallelism when the microwiring member 50 is mounted. Therefore, the roughness is Ra: 500 to 1000 nm, and more preferably in the range of 500 to 800 nm. The roughness may be set appropriately as long as it is within a range that maintains adhesion and the mountability of the micro wiring member 50. The same applies to the period of the minute irregularities, which may be set appropriately as long as it is within the range of 5.0 to 25 μm.

[0030] 5B, the uneven shape of the cavity bottom can also be expressed as a shape in which peaks with a height of 0.25 to 10.0 μm are arranged at a period of 5.0 to 25 μm. The cavity bottom should satisfy the above conditions of Sa, peak shape, etc.

[0031] (Cavity Sidewalls) Next, the irregularities formed on the sidewalls of the cavity 35 will be described with reference to FIG. 6 . FIG. 6( a) is a diagram illustrating the shape of the cavity sidewall. As shown in FIG. 6( a), the sidewalls of the cavity 35 with a bottomed structure formed in the core layer 60 have ridges formed in the vertical and horizontal directions. The PV values ​​of the ridges are 1.2 μm or more and 3.6 μm or less, and the depths of the recesses are in the range of 0.5 μm or more and 4.1 μm or less. These vertical and horizontal ridges form a plurality of approximately rectangular recesses that can be observed with an optical microscope at a magnification of 50x or more. The spacing between the vertical ridges is in the range of 5 μm or more and 20 μm or less, and the spacing between the horizontal ridges is in the range of 2 μm or more and 25 μm or less. FIG. 6( b) is an optical microscope photograph of the upper sidewall of the cavity 35 observed from the top surface of the cavity 35. The ridges of the side walls of the cavity 35 with the bottom structure and the multiple, approximately rectangular recesses have the effect of fixing the fine wiring member 50 and enhancing the adhesion between the insulating resin 85 used in the first wiring layer 21 formed on the core layer 60 and the core layer 60.

[0032] Generally, chemical adhesion treatment is used to ensure adhesion between the core layer 60 and the insulating resin 85, but it has been confirmed that this can result in delamination at the interface due to stress caused by differences in the linear expansion coefficients of the materials used. Forming irregularities within the above numerical range on the sidewall of the bottomed cavity 35 creates an anchor effect, ensuring adhesion between the core layer 60 and the insulating resin 85, and thus ensuring reliability as a wiring substrate. Figure 6(b) is an optical microscope photograph of the sidewall of the cavity 35 viewed from above the z-axis, revealing the fine irregularities that are formed.

[0033] (Angle of Cavity Sidewall) Next, the inclination angle of the cavity sidewall will be described with reference to FIG. 7 . FIG. 7 is a cross-sectional view illustrating the inclination angle of the cavity sidewall. In the wiring substrate 20 according to the embodiment, the inclination angle of the sidewall of the cavity 35 having a bottom structure formed in the core layer 60 is preferably set in the range of 4.5° to 35.5°. The inclination angle of the sidewall of the cavity 35 can be determined based on the relationship between the cavity depth D1 and the opening difference S1 between the top and bottom of the cavity. By setting the inclination angle of the sidewall of the cavity 35 to 4.5° to 35.5°, the distance from the cavity 35 to the nearest through electrode hole can be set to 40 μm to 150 μm. If the sidewall angle of the cavity 35 is set to 30° or more, the distance between the cavity 35 and the through electrode 30 will be 150 μm or more, resulting in wasted area on the wiring substrate 20. For example, the wiring length between the microwiring member 50 and the through electrode 30 increases, and the wiring length of the semiconductor element 40, the FC-BGA substrate 10, the motherboard 1, and the semiconductor package substrate 100 as a whole also increases, resulting in a deterioration in transmission characteristics. Furthermore, if the sidewall angle is 4.5° or less, the process of mounting the microwiring member 50 in the cavity 35 may become difficult. For this reason, the sidewall of the cavity 35 preferably has an inclination angle of 4.5° or more and 35.5° or less, and more preferably 4.5° or more and 15° or less. The inclination angle of the sidewall of the cavity 35 may be set as appropriate as long as it is within the above range.

[0034] Next, the through hole 70 around the cavity 35 will be described with reference to Fig. 8. Fig. 8 is a diagram illustrating the positional relationship between the cavity 35 and the through hole 70, and is a plan view of the core layer viewed from above. As shown in Fig. 8, if the inclination angle of the side wall of the cavity 35 is excessively large, wasted area occurs on the core layer, and the distance from the microwiring member 50 to the through electrode 30 formed in the through hole 70 becomes long.

[0035] (Organic Resin Layer) Next, with reference to FIG. 9 , the through electrodes and wiring formed on the surface of the core layer will be described. FIG. 9 is a cross-sectional view illustrating the through electrodes 30, first wiring layer 21, and second wiring layer 22 formed in the core layer material. In the wiring substrate 20 according to the embodiment, as shown in FIG. 9 , an organic resin layer 80 is formed at each interface between the core substrate 60 and the first wiring layer 21, the second wiring layer 22, and the through electrodes 30, with a thickness of 100 nm or more and 10,000 nm or less. The organic resin layer 80 is formed to cover microcracks occurring in the core layer 60 and has the effect of inhibiting breakage of the core layer 60 and the propagation of the microcracks. It also has the effect of ensuring adhesion between the core layer 60 and the conductor layer. The organic resin layer 80 is, for example, a resin containing at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, and is formed by spin coating, dipping, or the like. If the thickness of the organic resin layer 80 is 100 nm or less, the effect of covering microcracks that occur in the core layer 60 and suppressing the progression of the microcracks is small. Furthermore, if the thickness is 10,000 nm or more, the increased thickness can cause problems with stress. Therefore, the thickness of the organic resin layer 80 is preferably in the range of 100 nm to 10,000 nm, and more preferably in the range of 200 nm to 800 nm. The thickness of the organic resin layer 80 may be set as appropriate within the above range.

[0036] The conductor layers used for the core layer 60, first wiring layer 21, second wiring layer 22, and through electrode 30 may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, etc., but are preferably Cu. The thickness of the wiring may be set as desired. The seed layer for forming the conductor layer may be selected from, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, etc., as long as it is a material that can be formed in the organic resin layer 80. However, Cu is preferred, and its formation method may be an appropriate method such as sputtering, electroless plating, or CVD processing.

[0037] The insulating resin 85 formed on the upper surfaces of the first wiring layer 21 and the second wiring layer 22 formed on the front and back surfaces of the core layer 60 is, for example, at least one resin selected from the group consisting of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, to which fillers such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide have been added. The resin has an elastic modulus of 6 to 15 GPa and a linear expansion coefficient of 11 to 30 ppm / °C, and is preferably a thermosetting resin. Examples of methods for forming the insulating resin layer include spin coating, vacuum pressure pressing, heat pressing, compression molding, and transfer molding. Any suitable method may be used to form the insulating resin layer, as long as it is capable of embedding the microwiring member 50 mounted in the bottomed cavity 35 of the core layer 60. Preferably, the method is a vacuum pressure pressing method, in which heat and pressure are simultaneously applied under vacuum. The processing method is not limited to one, and a combination of methods other than those described above may be used.

[0038] 3, the semiconductor element connection terminals that electrically connect the semiconductor element 40 and the wiring board 20 have a pillar structure, which may be SnAg / Ni, SnAgCu / Ni, SnCu / Ni, SnAg / Cu / Ni, Au / Pd / Ni, Au / Ni, IT, OPS, or the like. The pillars have a diameter in the range of 10 μm to 30 μm, and a period of 20 to 50 μm. The pillar diameter and pitch can be set appropriately according to the structure of the semiconductor element 40 and the connection terminal.

[0039] Furthermore, the core layer 60 used in the wiring substrate 20 is made of glass, and the SiO2 ratio of the glass is in the range of 55% by mass or more and 85.0% by mass or less. If the SiO2 ratio of the glass composition is 55% by mass or less, it becomes difficult to form the cavity structure. Furthermore, if the SiO2 ratio is 85.0% by mass or more, the difference in the linear expansion coefficient between the core layer 60 and the first wiring layer 21 and the second wiring layer 22 becomes large, causing stress, which may lead to warping of the wiring substrate 20 or peeling at the interfaces between the first wiring layer 21, the second wiring layer 22, and the core layer 60, and at the interface between the core layer 60 and the microwiring member 50. Therefore, the SiO2 ratio of the core layer 60 is preferably in the range of 55% by mass or more and 85% by mass or less, and more preferably in the range of 75% by mass or more and 85% by mass or less. Within the above range, the SiO2 ratio of the core layer 60 is preferably in the range of 55% by mass or more and 85% by mass or less. ２ The ratio may be set as appropriate.

[0040] Second Embodiment Next, a second embodiment will be described with reference to FIG. 10 . The second embodiment differs from the first embodiment in that a through electrode is also formed in the region below the cavity 35. In the following description, components identical or equivalent to those in the first embodiment are denoted by the same reference numerals, and their description will be simplified or omitted. In the wiring substrate according to the second embodiment shown in FIG. 10 , the through electrode 30 formed in the core layer 60 and the cavity through electrode 31 formed below the cavity with a bottomed structure have different diameters. If the processed diameter of the through electrode 30 penetrating from the first surface to the second surface of the core layer 60 is Φ1 and the processed diameter of the cavity through electrode 31 formed in the cavity with a bottomed structure is Φ2, then Φ1 > Φ2. By satisfying the diameter of the through electrode Φ1 > Φ2, it is possible to achieve miniaturization of the connection terminals used to electrically connect the microwiring member 50 arranged in the cavity 35 to the outside. As a result of the above, in addition to the micro-wiring member 50, it is possible to mount functional members such as semiconductor elements and capacitors in the cavity 35 having a bottomed structure, thereby enabling the functions of the wiring board 20, i.e., the semiconductor package substrate 100, to be multifunctional.

[0041] Third Embodiment Next, a third embodiment will be described with reference to FIG. 11 . FIG. 11 is a cross-sectional view of a wiring substrate having cavities and through electrodes of various depths on the same substrate. The cavities and through electrodes described in the first and second embodiments can be formed on the same substrate by changing the longitudinal and lateral dimensions and depths of the cavities and the shapes of the through electrodes. The wiring substrate shown in FIG. 11 has a panel size of 510 mm x 515 mm and is a 0.44 mm thick glass panel on which cavities of 70 μm and 200 μm depths are simultaneously formed. FIG. 11( a) shows a portion of the structure described in the second embodiment in which through electrodes are formed at the bottom of the cavity, with the cavity depth being 200 μm. FIG. 11( b) shows a portion of the cavity structure described in the first embodiment in which the cavity depth is 200 μm. 11(c) shows a portion of the cavity structure described in the first embodiment where the cavity depth is 70 μm. By locally changing the intensity of the laser modification and controlling the etching conditions, the depth of these cavities can be made to various dimensions and shapes, even if they are at depths other than those shown in FIG.

[0042] The through electrode in FIG. 11(d) is a so-called X-shaped through electrode with an opening diameter of 60 μm, and can be formed by etching from both sides of the glass substrate. A through hole of this shape is characterized by having its opening diameter smallest near the center of the thickness of the glass panel. The through electrode in FIG. 11(e) and the bottomed hole in FIG. 11(f) are called V-shaped, and the cross section of the through hole is V-shaped. This shape can be created by masking one side of the glass panel and etching from only one side. When etching with one side of the glass panel masked, it is desirable to divide the glass panel into approximately 100 mm x 100 mm pieces before processing.

[0043] <Method for Manufacturing Wiring Board According to Embodiment of the Present Invention> A method for manufacturing wiring board 20 according to an embodiment of the present invention will be described below with reference to FIGS.

[0044] (Creation of Core Layer) Figure 12 is a diagram showing the process of etching a base substrate 61, which serves as the base material for the core layer. When the core material is glass, hydrogen fluoride-based or alkaline etching is performed to adjust the glass thickness. The thickness T1A of the base substrate 61, which serves as the base for the core layer 60, can be appropriately set depending on the application, taking into account the thickness reduction caused by the etching process for forming the through holes. For example, T1A is in the range of 200 to 1,900 μm, and the reduction in thickness of the base substrate due to the formation of the through holes can be in the range of 100 to 1,800 μm.

[0045] (Configuration of through holes and cavities with bottomed structure) Figure 13 is a diagram showing a process of forming laser-modified portions that serve as the starting points of through holes and cavities in core layer 60. Figure 14 shows the structure of the laser-modified portions that serve as the starting points of cavities 35 with bottomed structure, and Figure 15 shows a process of removing through holes 70 and cavities 35 with bottomed structure by etching to form through holes and cavities. Figure 16 is a diagram explaining the cross-sectional shape of through holes 70 formed by etching and the inclination angle of the via.

[0046] (Laser Modification) To form the through-hole 70 and the cavity 35 with a bottomed structure, there is a method in which, for example, laser processing is performed on the base substrate 61 shown in Fig. 12 to form a laser modified portion 75 that will be the starting point of the through-hole 70 and the cavity 35 (a portion where the through-electrode is to be formed, a portion where the cavity is to be formed), and then the laser modified portion 75 is expanded by etching, as shown in Fig. 13. For laser processing, when a femtosecond laser or a picosecond laser is used, it is preferable to use one of the oscillation wavelengths of 1064 nm, 532 nm, and 355 nm. Alternatively, CO ２It is also possible to form the starting points of the through holes 70 and the bottomed cavities 35 by laser processing or electrical discharge machining. Unlike the through holes 70, the bottomed cavities 35 are processed by adjusting the height of the laser-modified portions 75. After laser processing, the core layer 60 is immersed in hydrogen fluoride or a high-concentration alkaline etching solution (e.g., a sodium hydroxide aqueous solution or a potassium hydroxide aqueous solution) to etch the core layer 60 along the starting points of the through holes 11, thereby forming the through holes 11 and the bottomed cavities 35. Generally, etching progresses isotropically in the xy plane, and the rate of etching varies depending on the thickness direction (z-axis direction) of the base substrate 61. Therefore, the cylindrical spaces formed in the core layer 60 after etching become the through holes 70.

[0047] When forming the cavity 35 with a bottomed structure, the laser-modified portion serving as the cavity's starting point is formed by laser processing, and the laser-modified portion 75 is formed so that the through holes 70 overlap after etching, as shown in FIG. 14 . A high overlap rate indicates a high rate at which the through holes 11 overlap with adjacent through holes. FIG. 14(a) shows a case where there are two laser-modified portions, and FIG. 14(b) shows a case where multiple laser-modified portions are formed to form a cavity with a bottomed structure. When forming the cavity 35 with a bottomed structure, it is desirable to process the laser-modified portion 75 at a period of 5 μm or more and 25 μm or less, more preferably in the range of 5 μm or more and 10 μm or less. By processing at the above periodicity, the bottom of the cavity with a bottomed structure has a Sa of 500 to 3000 nm, and the micro-irregularities are periodic at a pitch of 5 to 25 μm. Ridges are formed in the vertical and horizontal directions on the side walls of the cavity 35, and the PV value of the ridges is 1.8 μm or more and 3.6 μm or less, the depth of the recess is 0.5 μm or more and 4.1 μm or less, the spacing between the vertical ridges is in the range of 5 μm or more and 15.5 μm or less, the spacing between the horizontal ridges is in the range of 2 μm or more and 25 μm or less, and the inclination angle can be formed in the range of 1° or more and 30° or less.

[0048] (Cross-sectional Shape of Through Hole) FIG. 16 is an enlarged cross-sectional view of a through hole 70 formed in the core layer 60. FIG. 16(a) shows a cross-sectional view of the through hole 70, and FIG. 16(b) shows the inclination angle of the through hole 70. The method for measuring the inclination angle will be described later. The cross-section of the through hole 70 shown in FIG. 16 was obtained by cleaving (cutting) the base substrate 10A in the thickness direction with a scribe to expose the cross-section (cut surface) of the through hole 70, and analyzing the SEM image observed with a scanning electron microscope (SEM) using image analysis software. As shown in FIG. 16, the through hole 70 has an hourglass shape, and the angle of the side surface of the through hole 70 is inverted upside down with respect to the 50% position, which is the central portion. The shape of the through hole 70 is not limited to the above shape, and any shape can be selected as long as it penetrates the first surface 60a and the second surface 60b of the core layer 60. The shape of the through-hole 70 is an example of a through-hole that can be obtained by laser processing and etching, and the present disclosure is not limited to the above shape.

[0049] The shape of the through hole 70 shown in FIG. 16( a) has a nearly vertically symmetrical structure at the 50% mark on the scale. Regarding the method for measuring the inclination angle of the side surface of the through hole 70, for the section from 5% to 50% distance from the first surface 60a, as shown in FIG. 16( b), a center line TC is drawn perpendicular to the first surface 60a at the center of the opening on the first surface 60a side of the core layer 60. Next, as indicated by arrow A1, the center line TC is translated toward both sides of the through hole 11 until it contacts the point where the diameter of the through hole 11 is at its minimum value. The point of contact is designated as the reference point RP. Then, a tangent line ss is drawn from the reference point RP to the side surface corresponding to each position from 5% to 50% on the scale, and the inclination angle θ of the tangent line ss is measured. This inclination angle θ is designated as the inclination angle at each cross-sectional position from 5% to 50%. The inclination angle θ is defined as positive in the direction in which the diameter of the through hole 11 widens upward. Furthermore, for the section from 50% to 95% distance from the first surface 10a, the center line TC is translated to the reference point RP, and a tangent line ss is drawn on the side surface corresponding to each of the positions from 50% to 95% on the scale. The inclination angle θ of the tangent line ss is then measured, and this inclination angle θ is defined as the inclination angle at each of the cross-sectional positions from 50% to 95%. The inclination angle θ is defined as negative when the diameter of the through hole 11 widens downward. As shown in FIG. 16(b), the inclination angle θ changes sign from positive to negative at the 50% position, and the absolute value of the inclination angle θ is between approximately 14° and 15°.

[0050] (Formation of Through Electrodes) Next, referring to FIG. 17 , a process for forming a conductive layer in the through hole 70 formed in the core layer 60 and forming the through electrode 30 will be described. To form the through electrode 30, an organic resin layer 80 is formed on the surface of the core layer 60. The organic resin layer 80 is, for example, a resin mixture of at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, and is formed by spin coating, immersion treatment, or the like. If the thickness of the organic resin layer 80 is 100 nm or less, the effect of following microcracks generated in the core layer 60 is small, and it becomes difficult to suppress the progression of microcracks. Furthermore, if the thickness is 10,000 nm or more, stress increases with increasing thickness. Therefore, a range of 100 nm or more and 10,000 nm or less is preferable, and even more preferable is a range of 200 nm or more and 800 nm or more. The thickness of the organic resin layer 80 may be set appropriately within the above range.

[0051] After forming the organic resin layer 80 on the core layer 60, a seed layer is formed. Examples of the metal seed layer include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, with Cu being preferred. The formation method can be, for example, electroless plating, whose solution composition includes, for example, copper salts such as copper sulfate and copper chloride, Rossel salt for retaining copper ions, EDTA (ethylenediaminetetraacetic acid), and formalin. The solution composition can be adjusted appropriately depending on the chemical resistance of the insulating resin used. The metal seed layer formed by electroless plating is preferably at least 0.3 μm thick inside the sub-through hole 12. If the thickness is less than 0.3 μm, the coverage of the metal seed layer formed by electroless plating is insufficient, resulting in discontinuous conductive layers formed by electroplating. When the thickness of the metal seed layer formed by electroless plating is 0.3 μm or more, the thickness of the metal seed layer can be set appropriately. A seed layer formation method other than the electroless plating method includes formation by a sputtering method. When forming a seed layer by a sputtering method, for example, Ti, Cu, etc., at least one metal layer made of these materials can be used. The seed layer formation method may be appropriately selected from the above methods.

[0052] (Formation of Wiring) After forming a resist pattern on the core layer 60 on which the seed layer has been formed, the through electrodes 30, the first wiring layer 21, and the second wiring layer 22 are formed by electrolytic plating. Forming the resist pattern by photolithography involves, for example, laminating a dry film resist, drawing a pattern by exposure, and developing it. Forming the resist pattern by photolithography is a process that uses materials generally used in the wiring formation process for FC-BGA. The resist pattern is peeled off after electrolytic plating, and excess seed layer is removed by etching. When forming the resist pattern by photolithography, the bottom of the cavity 35, which has a bottomed structure, is protected with the resist pattern as needed. The through-hole 70 is electroplated to form the through-electrode 30 and wiring, which may be made of metals such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, with Cu being preferred. The plating solution is primarily composed of copper sulfide pentahydrate, sulfuric acid, and chloride ions. To ensure uniformity of the plating film, the through-electrode 30, first wiring 21a1, and second wiring 22b1 are formed using a plating solution containing at least one additive. The through-electrode 30, first wiring 21a1, and second wiring 22b1 are preferably formed to a thickness of at least 2 μm.

[0053] (Mounting of Microwiring Member) Next, with reference to FIG. 18 , the mounting of the microwiring member 50 in the cavity 35 having a bottomed structure formed in the core layer 60 will be described. The microwiring member 50 is mounted in the cavity from the bottomed structure using a die attach film (DAF) material by face-up mounting. The thickness of the DAF material used is at least 5 μm or more and 30 μm or less. If the thickness of the DAF material is 5 μm or less, it becomes difficult to conform to the irregularities of the bottom of the cavity 35 having a bottomed structure. Furthermore, if the thickness of the DAF material is 30 μm or more, the heat and pressure during mounting may cause the DAF material to creep up onto the side and top surfaces of the microwiring member 50. Therefore, the thickness of the DAF material may be set appropriately as long as it is in the range of 5 μm or more and 30 μm or less. Furthermore, when mounting the micro wiring member 50, the wiring pattern formed on the core layer 60 can be used as an alignment mark, allowing for accurate mounting. The shape of the alignment mark of the wiring pattern may be set arbitrarily. When mounting the micro wiring member 50, it is desirable to use a mounting machine that can set the stage temperature to 80°C or higher, the load to 10 N or higher, and has a mounting accuracy of (average + 4σ) ±5 μm or less.

[0054] (Formation of Insulating Resin Layer) Next, the formation of the insulating resin layer will be described with reference to FIG. 19 . After the microwiring member 50 is mounted in the cavity 35, which has a bottomed structure, of the core layer 60, an insulating resin 85 is formed on the front and back surfaces of the core layer 60, as shown in FIG. 19 . The insulating resin 85 is, for example, at least one resin selected from the group consisting of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, to which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added as a filler. The insulating resin 85 is preferably a thermosetting resin having a modulus of elasticity in the range of 6 to 15 GPa and a linear expansion coefficient in the range of 11 to 30 ppm / Deg.C.

[0055] Examples of methods for forming the insulating resin layer include spin coating, vacuum pressure pressing, heat pressing, compression molding, and transfer molding. Any suitable method may be used as long as it is possible to embed the microwiring member 50 mounted in the cavity 35 of the core layer 60, which has a bottomed structure. A vacuum pressure pressing method is preferred, and it is desirable to select a processing method that simultaneously applies heat and pressure under vacuum. The processing method is not limited to one method, and a combination of methods other than those described above may also be used. The microwiring member 50 is sealed in the cavity 35, which has a bottomed structure, by forming the insulating resin 85 on the front and back surfaces of the core layer 60.

[0056] (Formation of Conductive Vias) Next, the formation of conductive vias will be described with reference to Fig. 20. By forming the insulating resin 85 on the front and back surfaces of the core layer 60, conductive vias are formed in the insulating resin 85 to electrically connect with the micro wiring member 50 sealed in the cavity 35 having a bottomed structure. The conductive vias are formed using, for example, a UV laser, CO ２ The vias may be formed by laser via processing using a laser. When a photosensitive insulating resin material is used for the insulating resin 85, photovias may be formed by photolithography. Any suitable means and process may be used as long as the vias are used for electrical connection to the microwiring member 50. For the vias formed in the insulating resin 85, a seed layer is formed, a pattern is formed by photolithography, and then wiring is formed. The seed layer is formed of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, or the like by electroless plating or sputtering. Similarly, the wiring layer is formed of Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, or the like. The metal material for the seed layer and wiring layer is preferably Cu, and they are formed from at least one metal containing Cu.

[0057] (Formation of Wiring Layer and Connection Terminal) Next, with reference to FIG. 21 , the formation of the wiring layer and connection terminal will be described. After forming the insulating resin 85 and wiring including vias on the front and back surfaces of the core layer 60, wiring is formed multiple times as shown in FIG. 21 to form the first wiring layer 21 and the second wiring layer 22. The first wiring layer 21 and the second wiring layer 22 are formed in at least one layer, and the required number of layers are formed. Furthermore, in the first wiring layer 21, semiconductor element connection terminals 23 for electrical connection with the semiconductor element 40 are formed. The semiconductor element connection terminals 23 have a pillar structure, and the structure may be SnAg / Ni, SnAgCu / Ni, SnCu / Ni, SnAg / Cu / Ni, Au / Pd / Ni, Au / Ni, IT, OPS, or the like. The pillars have a diameter in the range of 10 μm to 30 μm, and a period of 20 to 50 μm. The pillar diameter and pitch may be appropriately designed in accordance with the structure of the semiconductor element 40 and the connection terminals.

[0058] (Electrical Bonding with Semiconductor Element) Next, the formation of the wiring layer will be described with reference to FIG. 22 . After the first wiring layer 21 and the second wiring layer 22 are formed on the front and back surfaces of the core layer 60, electrical bonding with the semiconductor element 40 is performed as shown in FIG. 22 . Examples of bonding the semiconductor element 40 to the wiring substrate 20 include a mount reflow method in which the semiconductor element is mounted and then subjected to heat treatment to form a solder bond, and thermal compression bonding (TCB) in which heat and load are simultaneously applied to form a solder bond with the wiring substrate 20. The bonding method for the semiconductor element 40 and the wiring substrate 20 may be selected appropriately depending on the diameter and pitch of the connection terminals of the semiconductor element 40 and the wiring substrate 20. However, if the pitch of the connection terminals is 30 μm or less, using thermal compression bonding (TCB) can reduce connection defects between the semiconductor element 40 and the wiring substrate 20.

[0059] (Underfill) Next, with reference to FIG. 23 , the filling of the underfill will be described. After connecting the semiconductor element 40 and the wiring board 20, as shown in FIG. 23 , an underfill 86 is filled to protect the connection between the semiconductor element 40 and the wiring board 20. The underfill 86 is, for example, at least one resin selected from the group consisting of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, to which a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide is added. The underfill 86 is filled into the bonded portion between the semiconductor element 40 and the wiring board 20 by capillary action. There are two methods for filling the underfill 86: one is by capillary action, and the other is by pre-laying and filling during thermal compression bonding (TCB). When mounting is performed first using Thermal Compression Bonding (TCB), Non-Conductive Paste (NCP) or Non-Conductive Film (NCF) is used. The purpose of both NCP and NCF is to protect the joint between the semiconductor element 40 and the wiring board 20, and the resin composition used is the same. The material and method used for the underfill 86 can be appropriately selected depending on the method for joining the semiconductor element 40 and the wiring board 20.

[0060] (Resin Mold) Next, as shown in FIG. 23 , the outer periphery of the semiconductor element 40 is protected with a mold resin 87. The mold resin may be, for example, at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, to which a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide has been added, and the mold resin is formed by a method such as compression molding or transfer molding. After the mold resin 87 is formed, a grinding process may be performed to reduce the height of the wiring substrate 20, and the wiring substrate 20 may be ground to a desired thickness. The amount of grinding may be appropriately set depending on the thickness of the wiring substrate 20.

[0061] (Manufacturing Method 1 of Second Embodiment) Next, referring to FIGS. 25 and 25, manufacturing method 1 of the second embodiment of the present invention will be described. FIGS. 25 and 26 are views illustrating the process of forming a cavity through-hole 71 in a cavity 35 having a bottomed structure. FIG. 25 illustrates the process of forming a through-hole 70 in the core layer 60 and a laser-modified portion 75 that serves as the starting point of the cavity 35. When forming the laser-modified portion 75 using a femtosecond or picosecond laser, the Z axis of the laser is controlled to control the depth of the laser-modified portion 75, and simultaneously form the through-hole 70 and the laser-modified portion 75 that serves as the starting point of the cavity 35. Thereafter, etching is performed as shown in FIG. 26, thereby enabling the formation of a cavity through-hole 71 in the core layer 60 and the cavity 35 having a bottomed structure. The cavity through-holes 71 formed in the cavity 35 consisting of the core layer 60 and the bottomed structure have different opening diameters, with the through-hole 70 being larger than the cavity through-hole 71, because the laser-modified portions 75 are in contact with the etching solution for different periods of time.

[0062] (Manufacturing Method 2 of Second Embodiment) Next, manufacturing method 2 of the second embodiment will be described with reference to Figures 27 and 27. Figure 27 is a diagram illustrating a process of forming a through-hole 70 and a cavity 35 having a bottomed structure by laser processing and etching in the core layer 60, and then forming a laser-modified portion 75 in the cavity 35 having a bottomed structure by laser processing. Figure 28 is a diagram illustrating a process of etching the laser-modified portion 75 formed in the cavity 35 having a bottomed structure in Figure 27 to form a cavity through-hole 71.

[0063] <Actions and Effects> The above-described manufacturing methods 1 and 2 according to the second embodiment describe the process of forming a cavity through-hole 71 in a cavity 35 having a bottomed structure, and the processes before and after are the same as those in the manufacturing method according to the first embodiment.

[0064] Hereinafter, the detailed contents of the examples and comparative examples in the embodiments will be described using examples and comparative examples. Note that each example shown below is an example of the present invention, and the present invention should not be construed as being limited to these examples.

[0065] <Examples and Comparative Examples According to Embodiments of the Present Invention> In the examples and comparative examples, a cavity 35 having a bottomed structure was formed in the core material of the wiring substrate 20, various processes were performed, and a temperature cycle test was conducted. Table 1 shows the manufacturing conditions and the shape of the cavity 35 having a bottomed structure for the examples and comparative examples. In Examples 1 to 5, the processing pitch of the laser-modified portion was changed to change the roughness, PV, and ridge spacing of the bottom and side of the cavity 35 having a bottomed structure formed by etching. In Comparative Example 1, the laser processing and pitch were set to larger values ​​compared to Examples 1 to 5, and a cavity having a bottomed structure was formed by etching. In Comparative Example 2, a resist pattern was formed on the core material by photolithography, and a cavity 35 having a bottomed structure was formed by etching. The Sa, PV, and irregularity period of the cavity bottom were measured using a white light interferometer (Zygo NeX View NX2) over a 174 x 174 μm area. The results shown in Table 1 indicate that as the laser processing pitch increases, the Sa, PV, unevenness period, PV of the side surface, and ridge spacing of the bottom surface of the cavity 35 increase. Regarding the mountability of the microwiring member 50, the thickness of the DAF material used in the member was 15 μm, while the average PV of the cavity bottom in Comparative Example 1 was 15,000 nm or more, which indicates that mountability was reduced. Similarly, reliability evaluation in a temperature cycle test also showed that the average PV of the bottom was 15,000 nm or more, which made it difficult for the DAF to maintain adhesion and reduced reliability. In Comparative Example 2, in which a resist pattern was formed on the core material by photolithography and then etched, the bottom and side surfaces were smooth, but the distance between adjacent through holes was set wide. Furthermore, reliability evaluation in a temperature cycle test confirmed peeling of the member, resulting in a failure.

[0066] The data in Table 2 shows the results of changing the inclination angle of the sidewall of the cavity 35 by changing the etching rate of the etching solution. Table 2 shows the results of evaluating the transmission characteristics of the microwiring member 50 mounted in the cavity 35 after each mounting process. In Examples 6 to 10, the etching rate was changed to change the inclination angle of the sidewall of the cavity 35, thereby changing the distance between the cavity 35 and the through electrode 30. Comparative Example 3 shows a case where the etching rate was further increased, and Comparative Example 4 shows a case where the processing was performed in the same manner as Comparative Example 2. Regarding the transmission characteristics shown in Table 2, the microwiring member and the through electrode 30 were connected using a semi-additive process (SAP) with a line and space ratio of 5 / 5 μm. The S parameter (S21), which indicates the frequency dependency of the degree of propagation wave relative to the input wave, was used to measure the transmission characteristics. S21 is expressed as the logarithm of the power ratio (transmitted wave power / input wave power), and a smaller absolute value indicates smaller transmission loss. A network analyzer was used to measure the S parameter (S21). Note that, in the evaluation of transmission characteristics, S21 of -2.9 dB or less is deemed unsuitable. From the results shown in Table 2, in Examples 6 to 10, the distance between the through electrode 30 adjacent to the cavity 35 can be set within the range of 20 to 150 μm, and the transmission characteristic S21 is -2.9 dB or less. In Comparative Examples 3 and 4, it is difficult to place the cavity 35 and the through electrode 30 adjacent to each other, and the transmission characteristic S21 is -2.9 dB or more.

[0067] Next, Table 3 shows the results of evaluating adhesion with and without an organic resin layer at the interface between the core material, the through electrode, and the metal wiring layer. In Examples 12 to 14, the thickness of the organic resin layer was varied, and a seed layer was formed using electroless plating and a sputtered seed layer. Then, electrolytic plating was performed, and adhesion was evaluated using a peel test. Comparative Example 5 shows an evaluation performed without forming an organic resin layer. A peel strength of 0.3 kN / m or more was considered acceptable. The results shown in Table 3 confirmed that in each Example in which an organic resin layer was formed, high peel strength was achieved with both electroless plating and a sputtered seed layer. Furthermore, the results of the comparative examples confirmed that without an organic resin layer, the peel strength was 0.3 kN / m or less.

[0068] Table 4 shows the component mounting yield, substrate warpage, and reliability evaluation results in a temperature cycle test for Example 15, which is an embodiment of the present invention, and Comparative Examples 6 and 7. For the evaluations shown in Table 4, a 100 x 100 mm substrate was fabricated and evaluated using the structure shown in Figure 2(a). In Comparative Example 6, as in Comparative Example 1, a resist pattern was formed on the core material by photolithography to form a cavity 35 with a bottomed structure. In Comparative Example 7, a substrate was fabricated and evaluated using the same specifications as in Prior Document 1: Japanese Patent No. 6665375. <Temperature Cycle Test> Test conditions: A cycle consisting of changes in temperature from -55°C, RT (room temperature), to 125°C was defined as one cycle, and each temperature was held for 30 minutes, followed by 1000 cycles. Observation method: resistance measurement (criteria: resistance change rate from initial value is 10% or less) Observation of blistering of substrate (if blistering occurs, evaluate the blister location using a cross section and an ultrasonic flaw detector) As shown in Table 4, by using glass for the core material, it is possible to suppress warpage of the substrate compared to Comparative Example 5. In a reliability evaluation using a temperature cycle test, Comparative Example 6 failed after 700 cycles, whereas Example 15, which is an embodiment of the present invention, was confirmed to have no problems up to 1000 cycles of the temperature cycle test.

[0069] <Actions and Effects> By adjusting the roughness of the bottom and side surfaces of the cavity 35 having a bottomed structure in the core layer 60, it is possible to improve adhesion with the component mounted in the cavity 35. Furthermore, by adjusting the inclination angle of the side surfaces, it is possible to ensure transmission characteristics by reducing the distance to the through electrode 30. Furthermore, it is possible to obtain adhesion by forming an organic resin layer at the interface between the core layer 60, the through electrode 30, and the metal wiring. Therefore, according to the examples of the embodiments of the present invention, the semiconductor package substrate 100 using the wiring substrate 20 can be made highly reliable. According to the embodiments of the present invention and the manufacturing methods and examples of the embodiments of the present invention, it is possible to suppress warpage and provide a highly reliable wiring substrate and a manufacturing method for a wiring substrate.

[0070] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. Note that the present disclosure includes the following aspects.

[0071] Other Embodiments The present disclosure also includes the following aspects: (Aspect 1) A wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, at least one cavity with a bottom formed on the surface of the core layer on which the semiconductor element is mounted, a micro-wiring member placed in the cavity, and an asperity having a roughness Sa of 500 nm or more formed on the bottom of the cavity.

[0072] (Aspect 2) The wiring board according to aspect 1, wherein the roughness Sa of the recesses and projections on the bottom of the cavity is 3000 nm or less.

[0073] (Aspect 3) A wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, at least one cavity with a bottom formed on the surface of the core layer on which the semiconductor element is mounted, a micro-wiring member placed in the cavity, and the bottom of the cavity having unevenness formed by peaks having a height of 0.25 to 10.0 μm at a horizontal interval of 5.0 to 25 μm.

[0074] (Aspect 4) A wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, at least one bottomed cavity formed on the surface of the core layer on which the semiconductor element is mounted, a micro-wiring member placed in the cavity, and the inclination angle of the sidewall of the bottomed cavity is in the range of 4.5° to 35.5°.

[0075] (Aspect 5) The wiring substrate according to any one of Aspects 1 to 4, wherein the sidewalls of the cavity have ridges formed in the vertical and horizontal directions, the PV value of the ridges is 1.2 μm or more and 4.4 μm or less, and the depth of the recess is 0.5 μm or more and 4.1 μm or less.

[0076] (Aspect 6) The wiring board according to any one of Aspects 1 to 5, characterized in that a plurality of substantially rectangular recesses are formed on the sidewall of the cavity by a plurality of vertical ridges and horizontal ridges, and the spacing between the vertical ridges is 5 μm or more and 15.5 μm or less, and the spacing between the horizontal ridges is 2.0 μm or more and 25 μm or less.

[0077] (Aspect 7) The wiring board according to any one of Aspects 1 to 6, wherein the distance between the cavity and the nearest through electrode from the cavity is 20 μm or more and 150 μm or less.

[0078] (Aspect 8) The wiring board according to any one of Aspects 1 to 7, characterized in that an organic resin layer having a thickness of at least 100 nm to 5,000 nm is formed at the interface between the core layer and the wiring layer and at the interface between the core layer and the through electrode.

[0079] (Aspect 9) The material of the core layer is SiO ２ A wiring board according to any one of Aspects 1 to 8, wherein the ratio of the glass is 55% by mass or more and 85.0% by mass or less.

[0080] (Aspect 10) The wiring board according to any one of Aspects 1 to 9, wherein the core layer has cavities formed therein that have different depths.

[0081] (Aspect 11) A method for manufacturing a wiring board having a core layer, wherein wiring layers are disposed on a first surface and a second surface of the core layer, wherein the core layer is provided with at least one through electrode penetrating from the first surface to the second surface, and wherein at least one cavity with a bottom is formed on the surface of the core layer on which a semiconductor element is mounted, the method comprising: irradiating a laser to a portion of the core layer where the through electrode and a portion where the cavity are to be formed, and performing an etching process to form a cavity having irregularities at the bottom of the through hole and the cavity with a roughness Sa of 500 nm or more; and arranging a fine wiring member in the cavity.

[0082] (Aspect 12) The method for manufacturing a wiring substrate according to aspect 11, wherein the etching treatment is a step of etching the core layer with hydrogen fluoride or a high-concentration alkaline etching solution.

[0083] (Aspect 13) A method for manufacturing a wiring substrate according to Aspect 11 or Aspect 12, characterized in that in the process of irradiating the area where the through electrode is to be formed and the area where the cavity is to be formed with a laser, the area where the through electrode is to be formed is entirely modified in the thickness direction of the core layer, and the area where the cavity is to be formed is partially modified in the thickness direction of the core layer.

[0084] (Aspect 14) The method for manufacturing a wiring substrate according to any one of Aspects 11 to 13, wherein in the step of irradiating the areas where the through electrodes and the cavities are to be formed with a laser, a femtosecond laser or a picosecond laser having an emission wavelength of 1064 nm, 532 nm, or 355 nm is used.

[0085] (Aspect 15) A method for manufacturing a wiring substrate according to any one of Aspects 11 to 14, characterized in that in the step of placing a microwiring member in the cavity, the microwiring member is mounted on the bottom of the cavity in a face-up manner using a die attach film, and the thickness of the die attach film is 5 μm or more and 30 μm or less.

[0086] 1: Motherboard 10: FG-BGA 20: Wiring substrate 21: First wiring layer 22: Second wiring layer 23: Semiconductor element connection terminal 30: Through electrode 31: Cavity through electrode 35: Cavity 40: Semiconductor element 50: Fine wiring member 51: DAF 60: Core layer 60a: First surface 60b: Second surface 61: Base substrate 70: Through hole 71: Cavity through hole 75: Laser modified portion 80: Organic resin layer (primer layer) 85: Insulating resin 86: Underfill 87: Molding resin 100: Semiconductor package substrate T1: Thickness of core substrate T2: Thickness of member having fine wiring layer D1: Cavity depth W1: Cavity width, W2: Cavity depth w1: Width of fine wiring layer, w2: Depth of member having fine wiring layer w2 S1: Difference in opening between the top and bottom of the cavity θ: Cavity angle CB: Cavity bottom TC: Center line of TGV SS: Tangent line of TGV

Claims

1. A wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, at least one cavity with a bottom formed on the surface of the core layer on which the semiconductor element is mounted, a fine wiring member placed in the cavity, and an unevenness having a roughness Sa of 500 nm or more formed on the bottom of the cavity.

2. The wiring board according to claim 1, wherein the roughness Sa of the bottom of the cavity is 3000 nm or less.

3. A wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, at least one cavity with a bottom formed on the surface of the core layer on which the semiconductor element is mounted, a micro-wiring member placed in the cavity, and the bottom of the cavity having unevenness formed by peaks with a height of 0.25 to 10.0 μm at a horizontal interval of 5.0 to 25 μm.

4. A wiring board having at least one semiconductor element mounted thereon, the wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, at least one cavity with a bottom formed on the surface of the core layer on which the semiconductor element is mounted, a micro-wiring member placed in the cavity, and the inclination angle of the sidewall of the cavity with a bottom is in the range of 4.5° to 35.5°.

5. The wiring board according to any one of claims 1 to 4, characterized in that ridges are formed in the vertical and horizontal directions on the side walls of the cavity, the PV value of the ridges is 1.2μm or more and 4.4μm or less, and the depth of the recess is 0.5μm or more and 4.1μm or less.

6. A wiring board according to any one of claims 1 to 4, characterized in that a plurality of substantially rectangular recesses are formed on the side walls of the cavity by a plurality of vertical ridges and horizontal ridges, the spacing between the vertical ridges being 5 μm or more and 15.5 μm or less, and the spacing between the horizontal ridges being 2.0 μm or more and 25 μm or less.

7. The wiring board according to any one of claims 1 to 4, characterized in that the distance between the cavity and the nearest through electrode is 20 µm or more and 150 µm or less.

8. A wiring board according to any one of claims 1 to 4, characterized in that an organic resin layer having a thickness of at least 100 nm to 5,000 nm is formed at the interface between the core layer and the wiring layer and at the interface between the core layer and the through electrode.

9. The material of the core layer is SiO ２ 5. The wiring board according to claim 1, wherein the ratio of glass is 55 mass % or more and 85.0 mass % or less.

10. The wiring board according to any one of claims 1 to 4, characterized in that cavities of different depths are formed in the core layer.

11. A method for manufacturing a wiring board having a core layer, wiring layers disposed on a first surface and a second surface of the core layer, the core layer having at least one through electrode penetrating from the first surface to the second surface, and at least one cavity with a bottom formed on the surface of the core layer on which a semiconductor element is mounted, the method comprising: irradiating a laser onto a portion of the core layer where the through electrode and the cavity are to be formed and performing an etching process to form a cavity having irregularities with a roughness Sa of 500 nm or more at the bottom of the through hole and the cavity; and arranging a fine wiring member in the cavity.

12. The method for manufacturing a wiring board according to claim 11, wherein the etching treatment is a process of etching the core layer with hydrogen fluoride or a high-concentration alkaline etching solution.

13. A method for manufacturing a wiring board according to claim 11 or 12, characterized in that in the process of irradiating the area where the through electrode is to be formed and the area where the cavity is to be formed with a laser, the area where the through electrode is to be formed is entirely modified in the thickness direction of the core layer, and the area where the cavity is to be formed is partially modified in the thickness direction of the core layer.

14. A method for manufacturing a wiring board according to claim 11 or 12, characterized in that in the step of irradiating the areas where the through electrodes and cavities are to be formed with a laser, a femtosecond laser or a picosecond laser having an emission wavelength of 1064 nm, 532 nm or 355 nm is used.

15. A method for manufacturing a wiring board as described in claim 11 or 12, characterized in that in the step of placing a fine wiring member in the cavity, the fine wiring member is mounted on the bottom of the cavity in a face-up manner using a die attach film, and the thickness of the die attach film is 5 μm or more and 30 μm or less.

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