Display apparatus and electronic device

Abstract

The purpose of the present invention is to provide a display apparatus and an electronic device capable of improving yield, for example.　This display apparatus includes a pixel circuit including a light emitting element, and a drive transistor connected in series with the light emitting element between a first power supply line and a second power supply line and supplying the light emitting element with a current corresponding to a data signal. A first voltage is supplied to the first power supply line, a second voltage lower than the first voltage is supplied to the second power supply line, and next to a first conductor pattern connected to an anode of the light emitting element, a second conductor pattern is formed that is at a voltage lower than the first voltage at least when the light emitting element emits light.

Description

Display devices and electronic devices

[0001] The present technology relates to a display device and an electronic device.

[0002] A display device having a pixel circuit including a light-emitting element is known. Patent Document 1 listed below discloses a technique for repairing a bright spot or a dark spot defect of a pixel formed at the outermost edge of a pixel region that emits light by using a dummy pixel.

[0003] JP 2015-228361 A

[0004] The technology disclosed in the above-mentioned Patent Document 1 utilizes dummy pixels, and does not disclose a technology for improving yield by devising the layout of pixel circuits.

[0005] An object of the present technology is to provide, for example, a display device and an electronic device that can improve yield.

[0006] The present technology provides, for example, a display device having a pixel circuit including a light-emitting element and a drive transistor connected in series with the light-emitting element between a first power supply line portion and a second power supply line, and supplying a current corresponding to a data signal to the light-emitting element, wherein a first voltage is supplied to the first power supply line, and a second voltage lower than the first voltage is supplied to the second power supply line, and a second conductor pattern is formed adjacent to a first conductor pattern connected to an anode of the light-emitting element, the second conductor pattern having a voltage lower than the first voltage at least when the light-emitting element emits light.

[0007] The present technology relates to, for example, an electronic device having a display device of the present technology.

[0008] FIG. 1 is a diagram showing an example of the configuration of a display device applicable to an embodiment of the present technology. FIG. 2 is a diagram showing an example of the configuration of a pixel circuit. FIG. 3 is a diagram schematically showing an example of a stacked structure of a pixel circuit. FIG. 4A is a diagram showing a portion of a conductor pattern of a third wiring layer (3MT) in a comparative example, and FIG. 4B is a diagram showing a portion of a conductor pattern of a fourth wiring layer (4MT) in the comparative example. FIG. 5 is a diagram showing cross-sectional structures of the third wiring layer and the fourth wiring layer in the comparative example. FIG. 6A is a diagram showing a portion of a conductor pattern of a third wiring layer (3MT) in the first embodiment, and FIG. 6B is a diagram showing a portion of a conductor pattern of a fourth wiring layer (4MT) in the first embodiment. FIG. 7A is a diagram showing a portion of a conductor pattern of a third wiring layer (3MT) in the second embodiment, and FIG. 7B is a diagram showing a portion of a conductor pattern of a fourth wiring layer (4MT) in the second embodiment. FIG. 8 is a diagram showing cross-sectional structures of a third wiring layer and a fourth wiring layer in the second embodiment. FIG. 9 is a diagram showing an example of a configuration of a pixel circuit. FIG. 10 is a diagram showing an example of a configuration of a pixel circuit. FIG. 11 is a diagram showing an example of a configuration of a pixel circuit. FIG. 12 is a diagram showing an example of a configuration of a pixel circuit. FIG. 13 is a diagram showing an example of a configuration of a pixel circuit. FIG. 14 is a diagram showing an example of a configuration of a pixel circuit. FIG. 15 is a diagram showing an example of a configuration of a pixel circuit. FIG. 16 is a diagram showing an example of a configuration of a pixel circuit. FIG. 17 is a diagram showing an example of a configuration of a pixel circuit. FIG. 18 is a perspective view showing an example of the appearance of a head-mounted display. FIG. 19 is a perspective view showing an example of the appearance of another head-mounted display. FIG. 20A is a front view showing an example of the appearance of a digital still camera. FIG. 20B is a rear view showing an example of the appearance of a digital still camera. FIG. 21 is a perspective view showing an example of the appearance of a television device. FIG. 22 is a perspective view showing an example of the appearance of a smartphone. FIG. 23A is a diagram showing an example of the interior of a vehicle from the rear to the front of the vehicle. Fig. 23B is a diagram showing an example of the interior of a vehicle from diagonally rear to diagonally front of the vehicle. Fig. 24 is a diagram showing an example of a layout for forming pixels. Fig. 25 is a diagram showing an example of a layout for forming pixels.FIG. 26A is a plan view showing an example of a layout for forming pixels, and FIG. 26B is a cross-sectional view showing an example of the pixel layout.

[0009] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order. In this specification and the drawings, components having substantially the same function or configuration will be assigned the same reference numerals, and redundant description will be omitted as appropriate. Furthermore, the shapes, sizes, positional relationships, etc. of components shown in each drawing may be exaggerated depending on the content of the description, and reference numerals may be omitted to avoid cluttering the illustrations. <1. Overview of embodiments of the present technology> <2. Comparative example> <3. First embodiment> <4. Second embodiment> <5. Configuration example of pixel circuit> <6. Modified example> <7. Application example>

[0010] 1. Overview of an embodiment of the present technology FIG. 1 is a diagram illustrating an example of a configuration of a display device 1 applicable to an embodiment of the present technology. The display device 1 is a device that displays various information such as images using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described as employing OLEDs as light-emitting elements. The display device 1 is, for example, a display mounted in an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

[0011] The display device 1 has, as circuit blocks, a pixel unit 2, a timing controller 3, a first drive unit 4, and a second drive unit 5. The display device 1 has, for example, these circuit blocks mounted on a substrate. The substrate includes, for example, a semiconductor substrate made of silicon or the like.

[0012] Although not shown here, the pixel section 2 specifically has a plurality of pixels (pixel circuits) PIX arranged in a matrix of m rows and n columns (m and n are natural numbers), forming a pixel area. The pixel arrangement may be other than a matrix. The pixel section 2 is provided with pixels that represent the three primary colors of R (red), G (green), and B (blue), for example, to represent a color image. The color representation of an image is not limited to this, and may be configured to represent, for example, a monochrome (black and white) image. The specific configuration and operation of the pixel PIX will be described later.

[0013] The pixel section 2 also has control lines WSL, DSL, and AZSL extending along the row direction of the pixel array and a signal line SGL extending along the column direction of the pixel array. The control lines WSL, DSL, and AZSL are provided for each pixel row, and the signal line SGL is provided for each pixel column. The control lines WSL, DSL, and AZSL are each connected to an output terminal of the corresponding row of the first drive unit 4 and a group of pixels in the corresponding row. The signal line SGL is each connected to an output terminal of the corresponding column of the second drive unit 5 and a group of pixels in the corresponding column. Specifically, the control line WSL is supplied with a control signal that controls writing of a pixel signal to the pixel PIX, the control line DSL is supplied with a control signal that controls light emission of the pixel PIX, the control line AZSL is supplied with a control signal that appropriately initializes the pixel PIX, and the signal line SGL is supplied with a pixel signal. Specifically, the control signal is a signal that performs control by switching the voltage level (for example, switching between a low voltage and a high voltage). Note that the types of the control lines connected to the first drive unit 4 and the signal lines connected to the second drive unit 5 are changed as appropriate depending on the configuration of the pixels PIX in the pixel unit 2.

[0014] The timing controller 3 controls the drive timing of the first drive unit 4 and the second drive unit 5. The timing controller 3 controls the operations of the first drive unit 4 and the second drive unit 5 based on drive signals input from an external device (e.g., a display controller). The timing controller 3 is connected to the first drive unit 4 and outputs a control signal to the first drive unit 4 that controls the first drive unit 4. The timing controller 3 is also connected to the second drive unit 5 and outputs a control signal to the second drive unit 5 that controls the second drive unit 5.

[0015] The first driving unit 4 generates a shift signal for each pixel row based on a control signal input from the timing controller 3, and generates control signals for driving the control lines WSL, DSL, and AZSL using the generated shift signals, and outputs them to the pixel unit 2. The first driving unit 4 can be configured, for example, as a shift register type circuit having a shift register circuit in its signal input section. However, the first driving unit 4 is not limited to this, and may be configured, for example, as an address decoder type circuit having an address decoder in its signal input section.

[0016] The second driving unit 5 allocates image data input from an external device (e.g., a display controller) to each signal line SGL based on a control signal input from the timing controller 3, converts the allocated image data into pixel signals, and outputs them to the corresponding signal lines SGL of the pixel unit 2. The second driving unit 5 can be configured, for example, with a RAMPDAC circuit that uses a ramp waveform analog signal to generate the pixel signals to be output to the signal lines SGL. However, the second driving unit 5 is not limited to this, and can also be configured, for example, with a voltage follower circuit that has a voltage follower circuit in the output section to the signal line SGL.

[0017] FIG. 2 shows an example configuration of a pixel PIX included in the pixel unit 2. Appropriate body voltages are applied to the bodies of the following transistors. This pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MP12 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14, and the other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of the source and drain is connected to the power supply line VCCP, and the other of the source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of the source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of the source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15.The gate of transistor MP15 is connected to the control line AZSL, one of the source and drain is connected to the other of the source and drain of transistor MP14 and the anode of the light-emitting element EL, the other of the source and drain is connected to the power supply line VSS, the anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP14 and one of the source and drain of transistor MP15, and the cathode is connected to the power supply line Vcath.

[0018] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 (storage capacitor) is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. During the period when transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this manner, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. During the period when transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS. Note that transistors MP12 to MP15 may be transistors using low-temperature polysilicon (LTPS). Furthermore, at least one of transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0019] Thus, this pixel PIX includes a light-emitting element EL. This pixel PIX also includes a transistor MP14 (drive transistor) that is connected in series with the light-emitting element EL between a power supply line VCCP (first power supply line) and a power supply line Vcath (second power supply line) and supplies a current to the light-emitting element EL in accordance with a pixel signal serving as a data signal. A predetermined first voltage is supplied to the power supply line VCCP, and a predetermined second voltage lower than the first voltage is supplied to the power supply line Vcath.

[0020] Here, the layered structure forming the pixel PIX will be described. FIG. 3 is a schematic diagram illustrating an example of the layered structure of the pixel PIX. The pixel PIX has a structure in which four wiring layers 11 to 14 are layered on a semiconductor substrate 10. Specifically, a first wiring layer 11 (1MT), a second wiring layer 12 (2MT), a third wiring layer 13 (3MT), and a fourth wiring layer 14 (4MT) are layered in this order on the semiconductor substrate 10. Each of the wiring layers 11 to 14 forms a conductor pattern made of a conductive material such as aluminum. Each of the wiring layers 11 to 14 is layered via an insulator layer 15 made of an insulating material (e.g., silicon oxide). Each of the wiring layers 11 to 14 is connected via a conductive conduction hole 16 (through-hole) formed in the insulator layer 15. The conduction hole 16 is formed, for example, by filling a through-hole in the insulator layer 15 with a conductor such as tungsten.

[0021] Semiconductor elements (not shown in FIG. 3 ), such as the above-mentioned transistor MP14, are formed on the semiconductor substrate 10. The first wiring layer 11 is stacked on the semiconductor substrate 10 via an insulator layer 15, and is connected to electrodes of the semiconductor elements on the semiconductor substrate 10 via conductive holes 16. The conductor pattern of the fourth wiring layer 14 includes an anode electrode 14A of the light-emitting element EL. An organic layer 17 functioning as a light-emitting layer and a cathode electrode 18 of the light-emitting element EL are stacked in this order on the anode electrode 14A of the light-emitting element EL, thereby forming the light-emitting element EL.

[0022] The display device 1 according to the embodiment of the present technology is characterized by the layout of the pixels PIX. Before describing the layout of the pixels PIX according to the embodiment of the present technology, the layout of the pixels PIX in a comparative example will be described.

[0023] 2. Comparative Example Figures 4 and 5 are diagrams showing an example of the layout of a pixel PIX in a comparative example. Figure 4A shows a portion of the conductor pattern (indicated by dashed hatching) of the third wiring layer 13 (3MT), and Figure 4B shows a portion of the conductor pattern of the fourth wiring layer 14 (4MT). Specifically, Figures 4A and 4B show the conductor pattern around the anode electrode 14A. Figure 5 is a cross-sectional view taken along the cross-sectional line AA-AA in Figure 4 (insulator layer 15 is not shown).

[0024] (Relationship between the Anode Electrode Conductor and the Conductor Pattern on the Same Layer) As shown in FIG. 4B , the conductor Anode, the power supply line VCCP, and the signal line SGL are formed as conductor patterns around the anode electrode 14A in the fourth wiring layer 14. The conductor Anode is connected to the anode electrode 14A of the light-emitting element EL and has the same voltage as the anode electrode 14A of the light-emitting element EL. Note that the conductor Anode in the fourth wiring layer 14 includes the anode electrode 14A. The conductor Anode in the topmost fourth wiring layer 14 is formed large (for example, formed in an island shape and the largest compared to the other layers) because it serves as a base for the light-emitting element EL (as the anode electrode 14A). A power supply line VCCP runs parallel to this conductor Anode. The power supply line VCCP is a power supply line connected to the anode side of the light-emitting element EL. More specifically, the power supply line VCCP is a positive power supply line used for emitting light from the light-emitting element EL in the pixel PIX. Specifically, the conductor Anode of the fourth wiring layer 14 is formed in a rectangular shape, and the power supply line VCCP runs parallel to one long side and three short sides. In other words, the conductor Anode of the fourth wiring layer 14 is surrounded on three of its four sides by the power supply line VCCP. Note that the signal line SGL runs parallel to the other long side.

[0025] (Relationship between the Anode Electrode Conductor and the Underlying Conductor Pattern) As shown in FIGS. 4 and 5 , the conductor patterns include a power supply line VCCP, a power supply line VSS, a signal line SGL, a conductor DRs, and a conductor Anode, which are formed in the lower periphery (third wiring layer 13) of the anode electrode 14A of the fourth wiring layer 14. The power supply line VSS is a negative power supply (a power supply with a lower voltage than the power supply line VCCP) used to initialize the voltage of a predetermined node (in this embodiment, the anode of the light-emitting element EL) in the pixel PIX. The conductor DRs is connected to one of the source and drain electrodes (DRs) of the transistor MP14 (drive transistor) and has the same voltage as that electrode. The conductor connected to the source electrode of the transistor MP14 basically has a lower voltage than the power supply line VCCP, but is applied with a high voltage almost the same as that of the power supply line VCCP during light emission.

[0026] 5, the conductor DRs in the third wiring layer 13 includes a lower electrode 13A of a capacitor C11 (auxiliary capacitance Csub). An upper electrode 13B is laminated on the lower electrode 13A with a capacitance insulating film 13C interposed therebetween, thereby forming the capacitor C11, which is an MIM (Metal Insulator Metal) capacitor. The upper electrode 13B is connected to the power supply line VCCP via a conductive hole 16 and is a conductor having the same voltage as the power supply line VCCP.

[0027] A conductor DRs and an upper electrode 13B are provided below the conductor Anode of the fourth wiring layer 14 (4MT). That is, between the layers, the conductor Anode forming the anode electrode 14A and the conductor pattern DRs are disposed adjacent to each other with the insulator layer 15 interposed therebetween. Also, the conductor Anode forming the anode electrode 14A and the upper electrode 13B (the conductor connected to the power supply line VCCP) are disposed adjacent to each other with the insulator layer 15 interposed therebetween.

[0028] (Problems Caused by Wiring Defects) Here, to reduce the number of wiring layers and thereby miniaturize the pixel PIX, it is necessary to increase the density of the conductor patterns in each of the wiring layers 11 to 14 while taking yield into consideration. As described above, in the layout of the pixel PIX in the comparative example, the conductor Anode and the high-voltage power supply line VCCP run parallel to each other in the fourth wiring layer 14. If these are shorted, the voltage of the anode electrode 14A of the light-emitting element EL will increase, causing the light-emitting element EL to emit light and become a bright spot. Also, with respect to the third wiring layer 13, the high-voltage upper electrode 13B and conductor DRs are disposed below the conductor Anode of the fourth wiring layer 14. If an inter-layer short occurs, the voltage of the anode electrode 14A of the light-emitting element EL will increase, causing the light-emitting element EL to emit light and become a bright spot. These bright spots lead to a decrease in yield. Therefore, in each of the embodiments described below, the pixel PIX layout is devised to improve this yield.

[0029] 3. First Embodiment A layout of a pixel PIX according to a first embodiment of the present technology will be described below. The first embodiment relates to a layout in the same layer as the anode electrode 14A of the light-emitting element EL. Fig. 6 is a diagram showing an example of the layout of the pixel PIX in this embodiment. Fig. 6A shows a part of the conductor pattern of the third wiring layer 13 (3MT), and Fig. 6B shows a part of the conductor pattern of the fourth wiring layer 14 (4MT). Specifically, Figs. 6A and 6B show the conductor patterns around the anode electrode 14A.

[0030] As shown in FIG. 6B , the conductor Anode, the power supply line VCCP, the power supply line (another power supply line) VSS, and the signal line SGL are formed as conductor patterns around the anode electrode 14A in the fourth wiring layer 14. The conductor Anode in the fourth wiring layer 14 includes the anode electrode 14A. A power supply line VSS, which has a voltage lower than that of the power supply line VCCP at least during light emission, runs parallel to the conductor Anode. Specifically, the conductor Anode in the fourth wiring layer 14 is formed in a rectangular shape, and the power supply line VSS runs parallel to one long side and three short sides. In other words, the conductor Anode in the fourth wiring layer 14 is surrounded on three of its four sides by the power supply line VSS. The signal line SGL runs parallel to the other long side. Therefore, the power supply line VCCP is not arranged adjacent to the conductor Anode of the fourth wiring layer 14 in the same layer.

[0031] As described above, in the layout of the pixel PIX in this embodiment, the conductor Anode and the power supply line VSS run parallel to each other in the fourth wiring layer 14. If these are shorted, the voltage of the anode electrode 14A of the light-emitting element EL will be low, causing the light-emitting element EL to not emit light and becoming a dark dot. Dark dots are less visible than bright dots, so the inspection standards for determining defects are less stringent and they are less likely to result in defective products. For example, a bright dot defect will result in a defective product if only one dot is present, but a dark dot defect will not result in a defective product if only one dot is present. In other words, the yield can be improved.

[0032] (Summary of the Present Embodiment) As described above, in the present embodiment, the display device 1 has a pixel PIX including a light-emitting element EL and a transistor MP14 (drive transistor) connected in series with the light-emitting element EL between a power supply line VCCP (first power supply line) and a power supply line Vcath (second power supply line) and supplying a current corresponding to a data signal to the light-emitting element EL. A first voltage is supplied to the power supply line VCCP, and a second voltage lower than the first voltage is supplied to the power supply line Vcath. A power supply line VSS (second conductor pattern) having a voltage lower than the first voltage at least when the light-emitting element EL emits light is formed adjacent to a conductor Anode (first conductor pattern) connected to the anode of the light-emitting element EL. Specifically, the power supply line VSS is formed adjacent to the conductor Anode in the same layer. Furthermore, the power supply line VCCP (third conductor pattern) is not formed adjacent to the conductor Anode in the same layer. As a result, even if the conductor Anode is short-circuited to the power supply line VSS in the same layer, this will not result in a dark spot defect, and the yield can be improved.

[0033] In the pixel PIX shown in Figure 2, in addition to the power supply line VSS, the conductor pattern connected to the gate electrode of transistor MP13 can also be the second conductor pattern. A low-voltage control signal is generally supplied to the gate of Pch transistor MP13 (the light-emission control transistor connected to control line DSL) during light emission. In other words, by arranging a second conductor pattern adjacent to the first conductor pattern, whose voltage is lower than the voltage of the power supply line VCCP at least during light emission, it is possible to improve yield. Note that the term "basically" here also includes cases where a period of high voltage is provided for some purpose, but does not affect light emission.

[0034] In the pixel PIX shown in FIG. 2 , in addition to the power supply line VCCP, the conductor pattern connected to the gate electrode of transistor MP12, the conductor pattern connected to the gate electrode of transistor MP15, or the conductor pattern connected to one of the source and drain electrodes of transistor MP14 can also be the third conductor pattern. A high-voltage control signal is generally supplied to the gates of P-channel transistor MP12 (a write transistor connected to control line WSL) and transistor MP15 (an initialization transistor connected to control line AZSL) during light emission. Furthermore, one of the source and drain electrodes of P-channel transistor MP14 (a drive transistor that controls the current flowing through the light-emitting element EL) is at a high voltage (a voltage approximately equal to the power supply line VCCP) during light emission. In other words, by avoiding the formation of a third conductor pattern adjacent to the first conductor pattern that reaches a voltage equal to or greater than the voltage of the power supply line VCCP during light emission, yield can be improved. The term "basically" here also includes cases where a short period of low voltage is provided for some purpose.

[0035] The first conductor pattern is not limited to the conductor Anode that forms the anode electrode 14A of the light-emitting element EL. For example, it may be a conductor Anode other than that of the fourth wiring layer 14, such as the conductor Anode of the third wiring layer 13. The explanations of the first conductor pattern, the second conductor pattern, and the third conductor pattern are the same in the explanations of the second embodiment and the like, which will be described later.

[0036] 4. Second Embodiment Next, a layout of a pixel PIX according to a second embodiment of the present technology will be described. The second embodiment relates to the layout of the anode electrode 14A of the light-emitting element EL and an adjacent layer. FIGS. 7 and 8 are diagrams showing an example of the layout of the pixel PIX according to the second embodiment. FIG. 7A shows a portion of the conductor pattern of the third wiring layer 13 (3MT), and FIG. 7B shows a portion of the conductor pattern of the fourth wiring layer 14 (4MT). Specifically, FIGS. 7A and 7B show the conductor pattern around the anode electrode 14A. FIG. 8 is a cross-sectional view taken along the cross-sectional line BB-BB in FIG. 7 (the insulator layer 15 is not shown).

[0037] 7 and 8 , the third wiring layer 13, which is the layer adjacent to (specifically, the lower layer of) the anode electrode 14A of the fourth wiring layer 14, has a power supply line VCCP, a power supply line VSS, a signal line SGL, a conductor DRs, and a conductor Anode formed as conductor patterns. The conductor DRs is connected to one of the source and drain electrodes (DRs) of the transistor MP14 (drive transistor) and has the same voltage as that electrode. The conductor Anode is connected to the anode electrode 14A of the light-emitting element EL and has the same voltage as the anode electrode 14A of the light-emitting element EL.

[0038] As shown in FIG. 8 , the conductor DRs in the third wiring layer 13 includes a lower electrode 13A of a capacitor C11 (auxiliary capacitance Csub). An upper electrode 13B is stacked on the lower electrode 13A via a capacitance insulating film 13C, thereby forming the capacitor C11, which is a metal-insulator-metal (MIM) capacitor. The upper electrode 13B is connected to the power supply line VCCP via a conductive hole 16 and is a conductor with the same voltage as the power supply line VCCP. As shown in FIG. 7A , the conductor Anode in the third wiring layer 13 is surrounded on three of its four sides by the power supply line VSS. This makes the third wiring layer 13 less likely to cause bright spot defects even if a short circuit occurs in the same layer.

[0039] As shown in FIG. 7B, a conductor Anode, a power supply line VCCP, and a signal line SGL are formed as conductor patterns around the anode electrode 14A in the fourth wiring layer 14.

[0040] The conductor Anode of the fourth wiring layer 14 (4MT) does not include the power supply line VCCP, nor does it include the conductor DRs or the upper electrode 13B (the conductor connected to the power supply line VCCP), but only the power supply line VSS is provided. That is, between the layers, the conductor Anode forming the anode electrode 14A and the power supply line VSS are adjacently disposed with the insulating layer 15 interposed therebetween. Thus, in the layout of the pixel PIX of this embodiment, the power supply line VSS is disposed below the conductor Anode of the fourth wiring layer 14 in the third wiring layer 13. Even if an interlayer short occurs between these due to a process abnormality (e.g., dust contamination), the voltage of the anode electrode 14A of the light-emitting element EL is reduced, causing the light-emitting element EL to not emit light and resulting in a dark spot. This reduces the likelihood of a defective product compared to a bright spot defect.

[0041] (Summary of the Present Embodiment) As described above, in the present embodiment, the display device 1 has a pixel PIX including a light-emitting element EL and a transistor MP14 (drive transistor) connected in series with the light-emitting element EL between a power supply line VCCP (first power supply line) and a power supply line Vcath (second power supply line) and supplying a current corresponding to a data signal to the light-emitting element EL. A first voltage is supplied to the power supply line VCCP, and a second voltage lower than the first voltage is supplied to the power supply line Vcath. A power supply line VSS (second conductor pattern) having a voltage lower than the first voltage at least when the light-emitting element EL emits light is formed adjacent to a conductor Anode (first conductor pattern) connected to the anode of the light-emitting element EL. Specifically, the power supply line VSS is formed adjacent to the conductor Anode between layers. Furthermore, the power supply line VCCP (third conductor pattern) is not formed adjacent to the conductor Anode between layers. As a result, even if the conductor Anode is short-circuited between the power supply line VSS and the other layer, this will not result in a dark spot defect, and the yield can be improved.

[0042] 5. Other Configuration Examples of Pixel Circuits Other configuration examples of the pixel PIX will be described below. Note that the following configuration examples are merely illustrative and do not exclude other configurations. Furthermore, when the present technology is applied to the following pixel PIX, as described above, a second conductor pattern is arranged adjacent to a first conductor pattern (including one that forms the anode electrode; the same applies hereinafter) connected to the anode of the light-emitting element EL in the same layer or an adjacent layer. This prevents a dark spot defect even if the first conductor pattern and the second conductor pattern are shorted, thereby improving yield. Furthermore, as described above, a third conductor pattern is not arranged adjacent to the first conductor pattern connected to the anode of the light-emitting element EL in the same layer or an adjacent layer. This prevents a short between the first conductor pattern and the third conductor pattern, reduces bright spot defects, and improves yield.

[0043] 9 shows an example of the configuration of a pixel PIX included in the pixel unit 2. The pixel PIX includes a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are N-type MOSFETs. The gate of the transistor MN02 is connected to a control line WSL, the other of the source and drain is connected to a signal line SGL, and one of the source and drain is connected to the gate of the transistor MN03 and one end of the capacitor C01. One end of the capacitor C01 is connected to one of the source and drain of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to one of the source and drain of the transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN03 and the other end of capacitor C01, and the cathode is connected to power supply line Vcath. The voltage of power supply line VCCP is switched appropriately between a first voltage equivalent to the first voltage described above and a second voltage lower than the first voltage.

[0044] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0045] In this pixel PIX, the second conductor pattern may be, for example, a conductor pattern connected to the gate electrode of transistor MN02. A low-voltage control signal is basically supplied to the gate of N-channel transistor MN02 during light emission. The third conductor pattern may be, for example, a power supply line VCCP (including a conductor connected to the power supply line VCCP; the same applies hereinafter).

[0046] (Configuration Example 2) Figure 10 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the other of its source and drain is connected to a power supply line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other of the source and drain is connected to one of the source and drain of transistor MN23, one of the source and drain is connected to the other end of capacitor C21, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the other of the source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and one of the source and drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the other of the source and drain of transistor MN25, and the cathode is connected to power supply line Vcath.

[0047] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0048] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0049] In this pixel PIX, the second conductor pattern can be, for example, the power supply line VSS (including a conductor connected to the power supply line VSS; the same applies below), a conductor pattern connected to the gate electrode of transistor MN22, or a conductor pattern connected to the gate electrode of transistor MN25. The third conductor pattern can be, for example, the power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MN23, or a conductor pattern connected to the other of the source and drain electrodes of transistor MN24.

[0050] (Configuration Example 3) Figure 11 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of the source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other of the source and drain of transistor MP34. The gate of transistor MP33 is connected to the other of the source and drain of transistor MP32, the other of the source and drain of transistor MP34, and the other end of capacitor C31, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP35 and one of the source and drain of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP35, and the other of its source and drain is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP34, and the other of its source and drain is connected to one of the source and drain of transistor MP36 and the anode of the light-emitting element EL.The gate of the transistor MP36 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP35 and the anode of the light-emitting element EL, the other of the source and drain is connected to the power supply line VSS, the anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP35 and one of the source and drain of the transistor MP36, and the cathode is connected to the power supply line Vcath.

[0051] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0052] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0053] In this pixel PIX, the second conductor pattern can be, for example, the power supply line VSS or a conductor pattern connected to the gate electrode of transistor MP35. The third conductor pattern can be, for example, the power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MP32, a conductor pattern connected to the gate electrode of transistor MP34, or a conductor pattern connected to the gate electrode of transistor MP36.

[0054] 12 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, one of its source and drain is connected to signal line SGL1, and the other of its source and drain is connected to signal line SGL2.

[0055] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. The transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, one of its source and drain is connected to a signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of the source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the sources and drains of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power supply line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP45 and one of the source and drain of transistor MP46, and the cathode is connected to power supply line Vcath.The anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP124 and one of the source and drain of the transistor MP125, and the cathode is connected to the power supply line Vcath.

[0056] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0057] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0058] In this pixel PIX, the second conductor pattern may be, for example, the power supply line VSS or a conductor pattern connected to the gate electrode of transistor MP45. The third conductor pattern may be, for example, the power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MP42, a conductor pattern connected to the gate electrode of transistor MP44, a conductor pattern connected to the gate electrode of transistor MP46, or a conductor pattern connected to the gate electrode of transistor MP49.

[0059] 13 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 91 and a second control unit 92.

[0060] The first control unit 91 includes transmission gates TG45 and TG46, transistors MP50 and MP51, and a capacitor C50. The transistors MP50 and MP51 are P-type MOSFETs. One end of the transmission gate TG45 receives a pixel signal, and the other end of the transmission gate TG45 is connected to a signal line 93a. One end of the transmission gate TG46 is connected to a signal line 93b, and the other end of the transmission gate TG46 is connected to a power supply line Vorst. One end of the capacitor C50 is connected to the signal line 93a, and the other end is connected to a power supply line VSS1. The gate of the transistor MP50 is connected to a control line INIL, one of its source and drain is connected to a power supply line Vini, and the other of its source and drain is connected to a signal line 93b. The gate of the transistor MP51 is connected to a control line ELL, one of its source and drain is connected to a power supply line Vel, and the other of its source and drain is connected to a signal line 93b.

[0061] The second control unit 92 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to a signal line 93a, and the other end is connected to the other of the source and drain of the transistor MP73 and one end of a capacitor C82. The gate of the transistor MP73 is connected to a control line REFL, one of the source and drain is connected to a power supply line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to a signal line 93b.

[0062] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, one of the source and drain is connected to the signal line 93b, and the other of the source and drain is connected to the gate of the transistor MP121 and the other end of the capacitor C132. One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the other of the source and drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the other of the source and drain of the transistor MP122 and the other end of the capacitor C132, one of the source and drain is connected to the power supply line Vel, and the other of the source and drain is connected to one of the sources and drains of the transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124, and the other of its source and drain is connected to signal line 93b. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power supply line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP124 and one of the source and drain of transistor MP125, and the cathode is connected to the power supply line Vcath.

[0063] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line 93b. While transistor MP125 is on, the voltage of the anode of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 93b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 93b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is set to the voltage of power supply line Vref, thereby being initialized.

[0064] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0065] In this pixel PIX, the second conductor pattern can be, for example, the power supply line Vorst (including a conductor connected to the power supply line Vorst) or a conductor pattern connected to the gate electrode of transistor MP124. The third conductor pattern can be, for example, the power supply line Vel (including a conductor connected to the power supply line Vel), a conductor pattern connected to the gate electrode of transistor MP122, a conductor pattern connected to the gate electrode of transistor MP123, or a conductor pattern connected to the gate electrode of transistor MP125.

[0066] (Configuration Example 6) Figure 14 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the other of the source and drain of transistor MP53 and one of the source and drain of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, one of its source and drain is connected to a power supply line VCCP, and the other of its source and drain is connected to the other of the source and drain of transistor MP52 and one of the source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51, with one of its source and drain connected to the other of the sources and drains of transistors MP52 and MP53, and the other connected to one of the sources and drains of transistors MP58 and MP59. Capacitor C51 has one end connected to the power supply line VCCP, and the other end connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. The gate of transistor MP55 is connected to control line AZSL1, with one of its source and drain connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other connected to one of the source and drain of transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, one of the source and drain is connected to the other of the source and drain of the transistor MP55, and the other of the source and drain is connected to the power supply line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of the source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, and one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP58, and the other of its source and drain is connected to one of the source and drain of transistor MP60 and the anode of the light-emitting element EL. The gate of the transistor MP60 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP59 and the anode of the light-emitting element EL, the other of the source and drain is connected to the power supply line VSS, the anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP59 and one of the source and drain of the transistor MP60, and the cathode is connected to the power supply line Vcath.

[0067] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0068] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0069] In this pixel PIX, the second conductor pattern can be, for example, the power supply line VSS, a conductor pattern connected to the gate electrode of transistor MP53, or a conductor pattern connected to the gate electrode of transistor MP59. The third conductor pattern can be, for example, the power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MP52, a conductor pattern connected to the gate electrode of transistor MP55, a conductor pattern connected to the gate electrode of transistor MP56, a conductor pattern connected to the gate electrode of transistor MP57, a conductor pattern connected to the gate electrode of transistor MP58, a conductor pattern connected to the gate electrode of transistor MP60, or a conductor pattern connected to one of the source and drain electrodes of transistor MP54.

[0070] 15 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0071] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, and the other of its source and drain is connected to a signal line SGL and one of the source and drain of the transistor MP64, and one of its source and drain is connected to the other of the source and drain of the transistor MP64, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, and one of its source and drain is connected to the signal line SGL and the other of the source and drain of the transistor MN63, and the other of the source and drain is connected to one of the source and drain of the transistor MN63, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may be connected to the power supply line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other of the sources and drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and one of the source and drain is connected to the power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of the source and drain is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN67, and the cathode is connected to the power supply line Vcath. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of the transistor MN65 may be connected to the other of the source and drain of the transistor MN66 and the anode of the light-emitting element EL.

[0072] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0073] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0074] In this pixel PIX, the second conductor pattern can be, for example, the power supply line VSS1 (including a conductor connected to the power supply line VSS1), the power supply line VSS2 (including a conductor connected to the power supply line VSS2), a conductor pattern connected to the gate electrode of transistor MN63, or a conductor pattern connected to the gate electrode of transistor MN66. The third conductor pattern can be, for example, the power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MP64, or a conductor pattern connected to the gate electrode of transistor MN67.

[0075] (Configuration Example 8) Figure 16 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DSL1, the other of its source and drain is connected to power supply line VCCP, and one of its source and drain is connected to the other of transistor MN74 and the other of transistor MN76. The gate of transistor MN74 is connected to one of the source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN76, and one of its source and drain is connected to one of the source and drain of transistor MN72 and the other of the source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77, and the anode of light-emitting element EL.The gate of transistor MN76 is connected to control line AZSL, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, and one of its source and drain is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75, and the anode of light-emitting element EL, and one of its source and drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN75, the other of the source and drain of transistor MN77, and the other end of capacitor C71, and the cathode is connected to power supply line Vcath.

[0076] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0077] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0078] In this pixel PIX, the second conductor pattern can be, for example, the power supply line VSS, a conductor pattern connected to the gate electrode of transistor MN72, a conductor pattern connected to the gate electrode of transistor MN76, or a conductor pattern connected to the gate electrode of transistor MN77. The third conductor pattern can be, for example, the power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MN73, a conductor pattern connected to the gate electrode of transistor MN75, or a conductor pattern connected to the other of the source and drain electrodes of transistor MN74.

[0079] <6. Modifications> Although the embodiments of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the above-described embodiments can be combined or substituted with each other as long as they do not deviate from the spirit of the present technology. Furthermore, one thing can be divided into two or more parts, and some parts can be omitted. Furthermore, as long as the present technology is applicable, the above-described configurations may be appropriately deleted, modified, or added with other configurations, or may be replaced with alternative configurations. Furthermore, the present technology may be an appropriate combination of the above-described embodiments.

[0080] For example, in the first embodiment described above, a configuration in which the second conductor pattern (power line VSS) runs parallel to the first conductor pattern (conductor Anode) and surrounds three of the four sides of the first conductor pattern has been illustrated, but the method of arranging the second conductor pattern adjacent to the first conductor pattern is not limited to this. For example, the second conductor pattern may surround all four sides of the first conductor pattern, may run partially parallel to the first conductor pattern, or may partially surround the first conductor pattern. The key is to reduce the possibility of the first conductor pattern shorting out with the third conductor pattern (power line VCCP, etc.).

[0081] Furthermore, for example, the first and second embodiments may be combined, so that the second conductor pattern is disposed adjacent to the first conductor pattern on the same layer and on adjacent layers, but the third conductor pattern is not disposed adjacent to the first conductor pattern, thereby further reducing bright spot defects and improving yield.

[0082] Furthermore, for example, in each of the above-described embodiments, a four-layer structure layout using the wiring layers 11 to 14 has been described, but the present invention is not limited to this, and may be, for example, a five-layer structure or a six-layer structure.

[0083] Furthermore, for example, in the above-described embodiments, the power supply line VSS or the like is exemplified as the second conductor pattern. However, the second conductor pattern need only have a voltage lower than the power supply line VCCP at least when emitting light, and is not limited to a pattern that will result in a dark dot if shorted. In other words, the voltage of the second conductor pattern when emitting light is not limited to a voltage lower than the threshold voltage of the light-emitting element EL. For example, a pattern that emits a slight amount of light when shorted may also be acceptable. If the second conductor pattern has a voltage lower than the power supply line VCCP at least when emitting light, the brightness will be reduced accordingly, making it less noticeable, which may contribute to improving yield. For example, the voltage lower than the voltage of the power supply line VCCP may be a voltage that will cause the light emitted by the light-emitting element EL to be at or below a predetermined brightness when the first conductor pattern and the second conductor pattern are connected (if shorted). This enables a wide range of layouts that take yield into consideration. Note that the emitting and non-emitting states, including bright and dark dots, are not limited to being strictly regulated. For example, even if there are periods of time when the state is different momentarily, it is acceptable as long as the state is maintained on average.

[0084] In each of the above-described embodiments, the second conductor pattern is used to connect to existing wiring, but this is not limited to this. The second conductor pattern may be intentionally routed using new wiring or the like and placed next to the first conductor pattern.

[0085] For example, the present technology can be applied to various displays. For example, the present technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, and phase modulation panels using SLM (Spatial Light Modulator) for displaying holograms. In addition, the present technology can be applied to panels such as LCOS (Liquid crystal on silicon, LCoS is a trademark) and HTPS (High Temperature Poly-Silicon).

[0086] For example, in the above-described embodiment, the second drive unit 5 outputs a pixel signal representing luminance by a voltage to the pixel unit 2, but the second drive unit 5 may output a pixel signal representing luminance by a current. In other words, the second drive unit 5 serves as a current source (a voltage source in the above-described embodiment) when generating the pixel signal.

[0087] 17 shows an example of the configuration of pixel PIX when this current-based adjustment is performed. This pixel PIX has a capacitor C81, transistors MP81 to MP84, and a light-emitting element EL. Transistors MP81 to MP84 are P-type MOSFETs. The gate of transistor MP81 is connected to a control line WSL and the gate of transistor MP84, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to one end of capacitor C81, the other of the source and drain of transistor MP82, and one of the source and drain of transistor MP83. One end of capacitor C81 is connected to the other of the sources and drains of transistors MP81 and MP82 and one of the source and drain of transistor MP83, and the other end is connected to the gate of transistor MP83 and one of the source and drain of transistor MP84. The gate of transistor MP82 is connected to the control line DSL, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one end of capacitor C81, the other of the source and drain of transistor MP81, and one of the source and drain of transistor MP83. The gate of transistor MP83 is connected to the other end of capacitor C81 and one of the source and drain of transistor MP84, one of its source and drain is connected to one end of capacitor C81 and the other of the sources and drains of transistors MP81 and MP82, and the other of its source and drain is connected to the other of the source and drain of transistor MP84 and the anode of the light-emitting element EL. The gate of transistor MP84 is connected to the control line WSL and the gate of transistor MP81, one of its source and drain is connected to the other end of capacitor C81 and the gate of transistor MP83, and the other of its source and drain is connected to the other of the source and drain of transistor MP83 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the sources and drains of the transistors MP83 and MP84, and the cathode is connected to the power supply line Vcath.The signal line SGL is supplied with a signal (IDATA) having a current value corresponding to the luminance from the second drive unit 5 .

[0088] With this configuration, in pixel PIX, transistor MP82 is turned off, followed by transistors MP81 and MP84 being turned on. Then, a pixel signal of pixel current IData corresponding to the pixel is supplied from signal line SGL, again turning transistors MP81 and MP84 off. This sets the voltage across capacitor C81 based on the pixel signal supplied from signal line SGL. While transistor MP82 is in the on state, transistor MP83 passes a current corresponding to the voltage across capacitor C81 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP83. In this way, pixel PIX emits light at a brightness corresponding to the pixel signal.

[0089] The transistors MP81 to MP84 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP81 and MP84 may be a transistor using an oxide semiconductor.

[0090] In this pixel PIX, the second conductor pattern may be, for example, a conductor pattern connected to the gate electrode of transistor MP82. The third conductor pattern may be, for example, a power supply line VCCP, a conductor pattern connected to the gate electrode of transistor MP81, a conductor pattern connected to the gate electrode of transistor MP84, or a conductor pattern connected to one of the source and drain electrodes of transistor MP83.

[0091] 7. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0092] 18 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0093] (Application Example 2) FIG. 19 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0094] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0095] (Application Example 3) Figures 20A and 20B show an example of the appearance of a digital still camera 130, with Figure 20A showing a front view and Figure 20B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0096] 21 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0097] 22 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0098] (Application Example 6) Figures 23A and 23B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 23A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 23B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0099] The vehicle in Figures 23A and 23B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0100] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 23A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0101] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0102] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0103] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0104] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0105] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0106] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0107] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0108] The present technology may also have the following configurations: (1) A display device having a pixel circuit including a light-emitting element and a drive transistor connected in series with the light-emitting element between a first power supply line and a second power supply line and supplying a current corresponding to a data signal to the light-emitting element, wherein a first voltage is supplied to the first power supply line and a second voltage lower than the first voltage is supplied to the second power supply line, and a second conductor pattern is formed adjacent to a first conductor pattern connected to an anode of the light-emitting element, the second conductor pattern having a voltage lower than the first voltage at least when the light-emitting element emits light. (2) The display device according to (1), in which the first conductor pattern and the second conductor pattern are formed adjacent to each other in the same layer. (3) The display device according to (2), in which the pixel circuit has a third conductor pattern to which a voltage equal to or higher than the first voltage is supplied at least when the light-emitting element emits light, and the third conductor pattern is not formed adjacent to the first conductor pattern. (4) The display device according to (3), in which the pixel circuit is formed using a wiring layer with a four-layer structure. (5) The display device according to any one of (1) to (4), which has a plurality of wiring layers stacked with an insulating layer interposed therebetween, and the first conductor pattern and the second conductor pattern are formed adjacent to each other between the wiring layers. (6) The display device according to (5), in which the pixel circuit is formed of a four-layer wiring layer structure. (7) The display device according to any one of (1) to (6), in which the second voltage is a voltage at which the light emission of the light-emitting element becomes equal to or lower than a predetermined luminance when the first conductor pattern and the second conductor pattern are connected. (8) The display device according to any one of (1) to (7), in which the second conductor pattern includes a conductor connected to another power supply line used in the pixel circuit. (9) The display device according to any one of (1) to (8), in which the pixel circuit has a transistor including a gate electrode to which a low-voltage control signal is supplied when the light-emitting element emits light, and the second conductor pattern includes a conductor connected to the gate electrode of the transistor. (10) The display device according to any one of (3) to (9), wherein the third conductor pattern includes a conductor connected to the first power supply line.(11) The display device according to any one of (3) to (10), wherein the pixel circuit has a transistor including a gate electrode to which a high-voltage control signal is supplied when the light-emitting element emits light, and the third conductor pattern includes a conductor connected to the gate electrode of the transistor. (12) The display device according to any one of (3) to (11), wherein the third conductor pattern includes a conductor connected to one of the source and drain electrodes of the drive transistor when the drive transistor is a P-type transistor, and includes a conductor connected to the other of the source and drain electrodes of the drive transistor when the drive transistor is an N-type transistor. (13) An electronic device having the display device according to any one of (1) to (12).

[0109] (Supplementary Notes on the Embodiments, etc.) The following supplementary notes are provided regarding the above-described embodiments, etc. In the following supplementary notes, a case where the pixel PIX shown in FIG. 2 is applied will be described, but the same can be applied to cases where other pixels PIX are used. FIG. 24 is a diagram showing an example of a layout for forming the pixel PIX used in the supplementary notes. FIG. 24 shows part of the conductor pattern of the fourth wiring layer (4MT). FIG. 24A shows an example of a layout in which the conductor patterns surround the four sides of the anode electrode 14A, and FIG. 24B shows an example of a layout in which the conductor patterns run parallel to the four sides of the anode electrode 14A.

[0110] In the example shown in FIGS. 24A and 24B , a conductor Anode, a power supply line VCCP, a power supply line VSS, and a signal line SGL are formed as conductor patterns around the anode electrode 14A in the fourth wiring layer 14. The conductor Anode in the fourth wiring layer 14 includes the anode electrode 14A. The same applies to FIGS. 25 and 26 . A power supply line VSS, which has a lower voltage than the power supply line VCCP at least during light emission, runs parallel to the conductor Anode in the fourth wiring layer 14. The parallel power supply line VSS may be another conductor pattern that can serve as the second conductor pattern. Specifically, the power supply line VSS may be another power supply line that can serve as the second conductor pattern (e.g., the power supply line Vcath, the power supply line VSS2 in the case of the other pixel PIX described above, etc.) or a control line that can serve as the second conductor pattern (e.g., the control line DSL, the control line in the case of the other pixel PIX described above, etc.).

[0111] In the layout example shown in FIG. 24A , the conductor Anode of the fourth wiring layer 14 is formed in a rectangular shape (more specifically, a rectangular shape; the same applies to other layout examples). The power supply lines VSS run parallel to the four sides of the rectangle, and the conductor Anode is completely and seamlessly surrounded on all four sides by the power supply lines VSS. In the layout example shown in FIG. 24B , the power supply lines VSS run parallel to the four sides of the rectangle, and the conductor Anode is completely and seamlessly surrounded on all four sides by the power supply lines VSS. The example shown in FIG. 24B differs from the example shown in FIG. 24A in that the enclosure is interrupted at the region P indicated by the dashed line. In this way, the conductor Anode does not have to be completely surrounded without any gaps. Note that the number, position, size, etc. of the region P are not limited to those shown in the figure. In this way, the power supply lines VSS surrounding the conductor Anode may or may not have their sides connected on the same layer. Furthermore, each conductor pattern surrounding the conductor Anode is not limited to the same type, such as only the power line VSS, but may be surrounded by multiple types of conductor patterns, such as the power line VSS and a pattern that can be another second conductor pattern.

[0112] In this way, the second conductor pattern that has a voltage lower than the voltage of the power supply line VCCP at least when the light-emitting element EL emits light is formed adjacent to the conductor Anode in the fourth wiring layer 14. Furthermore, the third conductor pattern that has a voltage higher than the voltage of the power supply line VCCP, such as the power supply line VCCP, supplied at least when the light-emitting element EL emits light, is not disposed adjacent to the conductor Anode in the same layer. Therefore, the yield can be improved as described above.

[0113] 25 is a diagram showing an example of a layout for forming pixels PIX used for supplementary explanation, and shows a part of the conductor pattern of the fourth wiring layer (4MT).

[0114] 25, a conductor Anode, a power supply line VCCP, and the control line DSL and signal line SGL of the pixel PIX shown in FIG. 2 are formed as conductor patterns around the anode electrode 14A in the above-described fourth wiring layer 14. A control line DSL having a voltage lower than that of the power supply line VCCP at least during light emission runs parallel to the conductor Anode in the fourth wiring layer 14. Note that this parallel running control line DSL may be another control line (specifically, a control line in the case of another pixel PIX) that can serve as the second conductor pattern.

[0115] In the layout example shown in Fig. 25, the conductor Anode of the fourth wiring layer 14 is formed in a rectangular shape with the control line DSL running parallel to one of the four sides, and the conductor Anode and the power supply line VCCP are formed with a sufficient distance between them. In other words, a sufficient distance is maintained between the conductor Anode and the power supply line VCCP so as not to cause a short circuit. Note that this parallel running may be along more than one side, or may be interrupted as described with reference to Fig. 24B.

[0116] In this way, the second conductor pattern that has a voltage lower than the voltage of the power supply line VCCP at least when the light-emitting element EL emits light is formed adjacent to the conductor Anode in the fourth wiring layer 14. Furthermore, the third conductor pattern that is supplied with a voltage equal to or higher than the voltage of the power supply line VCCP at least when the light-emitting element EL emits light, such as the power supply line VCCP, is not disposed adjacent to the conductor Anode in the same layer (close enough to cause a short circuit). This allows for improved yield as described above.

[0117] Fig. 26 is a diagram showing an example of a layout for forming a pixel PIX, which is used for supplementary explanation. Fig. 26 shows a portion of the conductor patterns of the third wiring layer 13 (3MT) and the fourth wiring layer 14 (4MT). Specifically, Fig. 26A shows the conductor patterns around the anode electrode 14A, and Fig. 26B shows a cross-sectional view taken along the cross-sectional line CC-CC in Fig. 26A (insulator layer 15 is not shown).

[0118] As shown in FIG. 26, the third wiring layer 13, which is the layer adjacent to (specifically, the lower layer of) the anode electrode 14A of the fourth wiring layer 14, has a power supply line VCCP, a power supply line VSS, a signal line SGL, a conductor DRs, a conductor Anode, and a control line DSL formed as conductor patterns.

[0119] As shown in FIG. 26B , the conductor DRs in the third wiring layer 13 includes a lower electrode 13A of a capacitor C11 (auxiliary capacitance Csub). An upper electrode 13B is stacked on the lower electrode 13A via a capacitance insulating film 13C, thereby forming a capacitor C11 (see FIG. 2 ) made of an MIM capacitor. The upper electrode 13B is connected to the power supply line VCCP via a conductive hole 16 and is a conductor with the same voltage as the power supply line VCCP. As shown in FIG. 26A , the conductor Anode in the third wiring layer 13 is rectangular, with the power supply line VSS running parallel to two of its short sides. Furthermore, the control line DSL runs parallel to one of its long sides. This makes the third wiring layer 13 less likely to cause bright spot defects even if a short occurs in the same layer.

[0120] Around the anode electrode 14A in the fourth wiring layer 14, a conductor Anode, a power supply line VCCP, and a signal line SGL are formed as conductor patterns.

[0121] Neither the conductor DRs nor the upper electrode 13B (a conductor connected to the power supply line VCCP), including the power supply line VCCP, is provided below the conductor Anode in the fourth wiring layer 14. Furthermore, the conductor patterns of the control line WSL and the control line AZSL are also not provided. A second conductor pattern is provided below the conductor Anode in the fourth wiring layer 14. Specifically, the control line DSL and the conductor Anode are formed adjacent to the conductor Anode in the fourth wiring layer 14 between layers. Furthermore, no third conductor pattern, such as the power supply line VCCP, is formed adjacent to the conductor Anode between layers. Therefore, the yield can be improved as described above.

[0122] As described above, if wiring efficiency is not a consideration, a control line such as the control line DSL may be provided in the fourth wiring layer 14 or routed between the fourth wiring layer 14 and the third wiring layer 13, and the second conductor pattern is not necessarily limited to a power supply line such as the power supply line VSS. Furthermore, the second conductor pattern may be a wiring other than a control line as long as it has a lower voltage than the voltage of the power supply line VCCP during light emission.

[0123] Here, we will provide additional information regarding the above-mentioned anode electrode 14. Conductor patterns (first conductor patterns) electrically connected to the anode of the light-emitting element EL are formed in various layers among the wiring layers, but the above-mentioned anode electrode 14A corresponds to the widest one. Specifically, this widest anode electrode 14A is either (1) or (2) below.

[0124] (1) The largest area among the above-mentioned conductor patterns, excluding the pattern arranged on the anode layer (the layer on which the anode of the light-emitting element EL is formed). (2) Among the above-mentioned conductor patterns, the conductor pattern arranged on the anode layer (including the anode of the light-emitting element EL).

[0125] This can efficiently reduce the probability of short-circuiting between the first conductor pattern and the third conductor pattern, thereby improving yield. The anode layer (not shown) described above is provided, for example, between the fourth wiring layer 14 and the organic layer 17, and the conductor pattern connected to the anode of the light-emitting element EL in the anode layer and the conductor Anode of the fourth wiring layer 14 are electrically connected, for example, via a conductive hole.

[0126] REFERENCE SIGNS LIST 1 display device, 2 pixel unit, 3 timing controller, 4 first driving unit, 5 second driving unit, PIX pixel (pixel circuit), EL light emitting element, VCCP power supply line (high voltage), VSS power supply line (low voltage), Anode, DRs conductor

Claims

1. A display device having a pixel circuit including a light-emitting element and a drive transistor connected in series with the light-emitting element between a first power supply line and a second power supply line, the drive transistor supplying a current to the light-emitting element according to a data signal, wherein a first voltage is supplied to the first power supply line, and a second voltage lower than the first voltage is supplied to the second power supply line, and a second conductor pattern is formed adjacent to a first conductor pattern connected to the anode of the light-emitting element, the second conductor pattern having a voltage lower than the first voltage at least when the light-emitting element emits light.

2. The display device according to claim 1, wherein the first conductor pattern and the second conductor pattern are formed adjacent to each other on the same layer.

3. The display device according to claim 2, wherein the pixel circuit has a third conductor pattern to which a voltage equal to or higher than the first voltage is supplied at least when the light-emitting element emits light, and the third conductor pattern is not formed adjacent to the first conductor pattern.

4. The display device according to claim 3, wherein the pixel circuit is formed of a wiring layer having a four-layer structure.

5. The display device according to claim 1, which has a plurality of wiring layers stacked with insulating layers interposed therebetween, and wherein the first conductor pattern and the second conductor pattern are formed adjacent to each other between the wiring layers.

6. The display device according to claim 5, wherein the pixel circuit is formed of a wiring layer having a four-layer structure.

7. The display device according to claim 1, wherein the second voltage is a voltage at which the light emitted by the light-emitting element becomes equal to or lower than a predetermined brightness when the first conductor pattern and the second conductor pattern are connected.

8. The display device according to claim 1, wherein the second conductor pattern includes a conductor connected to another power supply line used in the pixel circuit.

9. The display device according to claim 1, wherein the pixel circuit has a transistor including a gate electrode to which a low-voltage control signal is supplied when the light-emitting element emits light, and the second conductor pattern includes a conductor connected to the gate electrode of the transistor.

10. The display device according to claim 3, wherein the third conductor pattern includes a conductor connected to the first power supply line.

11. The display device according to claim 3, wherein the pixel circuit has a transistor including a gate electrode to which a high-voltage control signal is supplied when the light-emitting element emits light, and the third conductor pattern includes a conductor connected to the gate electrode of the transistor.

12. The display device according to claim 3, wherein the third conductor pattern includes a conductor connected to one of the source and drain electrodes of the drive transistor when the drive transistor is a P-type transistor, and includes a conductor connected to the other of the source and drain electrodes of the drive transistor when the drive transistor is an N-type transistor.

13. An electronic device having the display device according to claim 1.

Images