Method and apparatus for transmitting cochlear implant data using clock image method-based cochlear implant data transmission protocol

Abstract

An external speech processor of a cochlear implant based on a clock image method-based cochlear implant data transmission protocol according to an embodiment defines an NP2 interface and an NP2 protocol to stably capture NP2 data transmitted using an NP2 clock internally restored at a period inferred by a conversion chip from data transmitted by a speech processing chip even in a situation where a clock period of the speech processing chip and a clock period of the conversion chip are not related to each other at all. In addition, the external speech processor of a cochlear implant based on a clock image method-based cochlear implant data transmission protocol according to the embodiment stores the amount of data period variation during 12 bits in a buffer through a clock image, which is a snap-shot for a predetermined section, and repeatedly uses same. In the embodiment, all count values are stored as one data set and the stored data set is used. That is, in the embodiment, it is assumed that the sum of period changes of each bit during 12 bits and the sum of period changes of each bit during next 12 bits will have the same amount of variation, and each bit during the next 12 bits is captured at different time points according to the period of each bit stored in the buffer.

Description

Artificial cochlear implant data transmission method and device using an artificial cochlear implant data transmission protocol based on a clock image method

[0001] The present disclosure relates to a method and device for transmitting data for a cochlear implant using a clock image-based cochlear implant data transmission protocol, and more particularly, to a lossless, low-power data transmission protocol applicable to two components operating with different clocks. The device also relates to a method for transmitting data for a cochlear implant and an external audio processor for a cochlear implant.

[0002] Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application, and their inclusion in this section is not intended to be admitted as prior art.

[0003] A cochlear implant is a device that provides hearing to patients with profound sensorineural hearing loss or deafness due to damage to the inner ear by electrically stimulating the auditory nerve. Figure 1 is a diagram illustrating a cochlear implant. As shown in Figure 1, the cochlear implant converts audio signals from an external speech processor into neural stimulation information and transmits them to the internal implant via wireless communication. The internal implant then converts the neural signal information into neural stimulation signals and transmits them to a neural electrode unit that includes multiple stimulation electrodes.

[0004] The stimulation electrodes in the neural electrode unit directly stimulate the auditory nerve with neural stimulation signals, allowing the user to recognize sound. The external speech processor and the internal implant transmit data through wireless power transmission and two-way wireless communication. While a normal person perceives sound through a sound transmission pathway including the eardrum, ossicles, and cochlea, a cochlear implant recognizes sound through Path A, illustrated in Figure 1. The external speech processor converts speech signals into neural stimulation information and transmits the converted neural stimulation information through Path A. Path A is a pathway that includes the external unit, the neural stimulator, and the neural electrode unit.

[0005] Figure 2 is a diagram illustrating the configuration of an external voice processor for an artificial cochlea. Referring to Figure 2, the external voice processor for an artificial cochlea is configured to include a voice processing chip and a conversion chip (protocol conversion chip).

[0006] The clock frequency of the voice processing chip on the sending side (master) can be flexibly changed between 500 kHz and 2 MHz, and the clock frequency of the conversion chip on the receiving side (slave) is fixed at about 20 MHz and operates, so it is very important for the receiving side to correctly restore the clock of the sending side.

[0007] Typically, digital systems use a clock signal to generate data. Data toggling occurs when the value of this generated data changes. The clock signal, which periodically indicates the timing of data transmission, is essential for synchronizing data in electronic devices. Data toggling occurs when a data bit changes from "0" to "1" or vice versa. Meanwhile, in digital systems, data toggling caused by the clock signal ultimately results in power loss. For example, power loss due to switching loss occurs every time a data bit switches, or toggles. This dynamic power loss occurs when the power and ground of a digital element are momentarily shorted when a transistor in the digital element switches, changing its internal state. Furthermore, switching losses due to the rapid toggling of the clock signal, which causes clock tree drive loss during the process of distributing the clock signal across the entire chip, also contribute to significant dynamic power loss in the entire system. In addition, power loss due to load capacitance also occurs whenever the voltage of the data line changes due to the parasitic load capacitance of each data line inside and outside the chip. In principle, this loss is also dynamic power consumption that occurs when charge is accumulated or released in the parasitic capacitor as data toggles. As shown above, the switching loss due to the clock accounts for the largest proportion of the various factors of dynamic power consumption. This is because the clock signal continuously toggles at a high frequency of hundreds of kHz to tens of MHz, causing extremely large dynamic power consumption.

[0008] In order to reduce this dynamic power loss, a method is needed in which the receiver infers and generates the clock of the sender without exporting the clock signal, which accounts for a large portion of power consumption, to the outside of the chip. Our conventional external voice processor for cochlear implants communicates by restoring the clock of the sender through the average cycle clock method. The average cycle clock method is a method in which, when restoring the clock on the receiver, a clock that is much faster than the data generation clock on the sender is used to count the length of one bit of data, and the count value of each bit is averaged over a certain number of data bits to restore the clock cycle of the sender based on the received clock.

[0009] The averaging clock method uses the 12-bit repeating 0101... of the preamble packet to calculate the average value of the count values ​​from 0 to 1 and uses this as the cycle of the internal data capturing clock. However, since the averaging clock method restores the clock that generated the data using only the data, the data cannot be read correctly if the data is not read in an appropriate way. In other words, the averaging clock method inevitably loses synchronization.

[0010] The problem of lost sync arises from a fundamental error caused by the clock cycles of the sender and receiver differing. Furthermore, clock domain crossing (CDC) processing during data reception can cause a discrepancy between the actual clock cycle of the sender and the predicted cycle after capture.

[0011] Clock Domain Crossing (CDC) error is a problem related to data transmission between two different clock domains in a digital system. A clock domain is a region of a circuit that is synchronized by a specific clock signal. CDC error can occur when data is exchanged with another region that is synchronized by a different clock signal. For example, although the length of one bit is actually 20 cycles in the sent clock cycle, the clock cycle recovered at the receiving end can vary from 17 to 23 cycles due to period variation due to jitter of the sending clock and period error incurred during CDC processing. If the average value of the periods measured during the frequency detection section is 17 cycles, which is the minimum value of this variation, a 3-cycle error can cause the bit values ​​of the incoming data to be incorrectly recognized starting from the 7th bit (3 cycles * 7 = 21 cycles).

[0012] That is, in the conventional average cycle clock method, even in a situation where the clock cycle of the sender is ideally unchanged, the CDC error that occurred when receiving is included in the clock cycle itself restored by the receiver, so a bit recognition error can occur in a short period of time just due to the accumulated error caused by CDC processing.

[0013] A cochlear implant data transmission method using a cochlear implant data transmission protocol based on a clock image method according to an embodiment and an external voice processor of a cochlear implant using a cochlear implant data transmission protocol based on a clock image method stably capture NP2 data transmitted by using an NP2 (NP Square) clock that the converter chip internally restores to a cycle inferred from data sent by the voice processing chip even in a situation where the clock cycle of the voice processing chip and the clock cycle of the converter chip are completely unrelated to each other. (The NP2 interface will be described later.)

[0014] In addition, the artificial cochlear implant data transmission method using the artificial cochlear implant data transmission protocol based on the clock image method according to the embodiment and the external voice processor of the artificial cochlear implant using the artificial cochlear implant data transmission protocol based on the clock image method store the change in the data cycle for 12 bits in a buffer through a clock image, which is a snapshot for a certain section, and repeatedly use this to capture data for several multiples or several tens of times the storage section.

[0015] In addition, in the embodiment, the entire count value of each bit in a certain time interval is conceptually stored as a single data set, and the stored data set is used to create a capture clock for the corresponding bit to read each bit. That is, in the embodiment, it is assumed that the sum of the periodic changes of each bit for 12 bits and the sum of the periodic changes of each bit for the next 12 bits will have almost the same amount of change overall when viewed over a long period of time, and each bit for the next 12 bits is captured at different points in time according to the corresponding period of each bit stored in the buffer.

[0016] Additionally, in the embodiment, in order to stably capture data, the capture point of the data is shifted to match the middle of the data, avoiding the point at which the data received by the conversion chip of the external voice processor of the artificial cochlea changes.

[0017] In addition, the clock image method provided in the embodiment stores a certain period of cycles as a whole so that the jitter of the clock itself and the error due to CDC processing cancel each other out within a certain period, and when capturing data, a data capturing clock point is generated at the location stored for each bit.

[0018] However, the problems to be solved according to one embodiment are not limited to those mentioned above.

[0019] In a cochlear implant data transmission method according to an embodiment, the cochlear implant includes an external voice processor and an internal unit, and the external voice processor of the cochlear implant includes a voice processing chip that controls the internal unit and a conversion chip; and a conversion chip that performs decoding of data received from the voice processing chip for communication with the internal unit; and the voice processing chip and the conversion chip of the external voice processor of the cochlear implant use an NP2 (Normalized Parameter Packet) interface configured as a 2-wire unidirectional serial interface for communication, the NP2 interface includes a sync signal and a data signal, the sync signal is a signal that toggles at every boundary of a packet frame including a plurality of bits, and the data signal is an N-bit data packet transmitted from the voice processing chip to the conversion chip, and the cochlear implant data transmission method includes the steps of: the voice processing chip transmitting the sync signal and the data signal to the conversion chip; the conversion chip reading the period of the data signal per bit; the conversion chip storing in a buffer a period change of the data signal received for a specific number of bits; A step of capturing a data signal through a clock image method in which a conversion chip repeatedly captures a data signal for a specific number of bits by repeatedly using periodic changes stored in a buffer; wherein the clock image method assumes that the sum of periodic changes of each bit for a current specific number of bits and the sum of periodic changes of each bit for a next specific number of bits have the same value, and can capture data signals for each bit at different points in time for the next specific number of bits according to the period of each current bit stored in the buffer.

[0020] In addition, the artificial cochlear implant data transmission method further includes a step of shifting the data capture point in time to match the middle of the data signal cycle in order to stably capture data by avoiding the point in time when the data signal changes.

[0021] In addition, the voice processing chip can use a preamble packet, which is a one-time packet used in the process of starting data transmission to synchronize the voice processing chip and the conversion chip in the NP2 interface, a data packet including parameter data transmitted to the conversion chip and an internal device, a NOP packet to compensate for the difference in data rate that occurs during shortening of the length of the clock image and protocol conversion, and an Abort packet used by the voice processing chip to bring the FSM of the conversion chip out of the deadlock situation when a deadlock situation occurs in the NP2 protocol FSM (Finite State Machine) of the conversion chip.

[0022] Additionally, the preamble packet may have 12 bits of 010101010101 in the frequency detection section for determining the variable frequency after the data signal remains 1 for at least 1 frame of the sync signal.

[0023] In addition, an abort packet is a packet in which the header 3 bits of the data signal are 0, and the protocol FSM (Finite State Machine) of the abort packet can be configured so that the conversion chip recognizes it as an abort packet when the sync signal is toggled twice or more with a length greater than the length of the 3 bits of the data signal after the data signal remains 0.

[0024] In addition, the NOP packet does not perform any operation on the NP2 interface, and is used to maintain the connection between the voice processing chip and the converter chip or to adjust the timing. The NOP packet includes a frequency detection section for updating the data signal capture period, and when the converter chip receives a NOP packet, it updates the data signal capture period to minimize the length of the clock image storage period.

[0025] In addition, the method further includes: a step of obtaining the period of the first bit through an up-count method that increases from 0 by 1 when the conversion chip reads the period of the first bit of the frequency detection section in the preamble packet or the NOP packet, and setting the period of the first bit as a reference period for clock image capture; a step of storing the difference between the period of each subsequent bit and the reference period as an offset value through a down-count method that decreases by 1 from the reference period for subsequent bits; and when the conversion chip captures a data signal through the clock image method, the offset value can be used as a period change of each bit.

[0026] In addition, when the conversion chip down-counts, if the last counted value of the corresponding bit period is negative, it means that the corresponding bit period is larger than the reference period, so a step of storing the sign of the offset value, which is an error from the reference period, as (+); when the conversion chip down-counts, if the last counted value of the corresponding bit period is positive, it means that the corresponding bit period is smaller than the reference period, so a step of storing the sign of the offset value as (-); When the conversion chip restores each bit period for the next specific number of bits, each bit period can be restored by adding the offset value to the reference period.

[0027] Additionally, the number of bits included in one packet frame of the sync signal may be 20 bits.

[0028] Additionally, the specific number of bits used in the clock image method may be 12 bits.

[0029] Additionally, packets transmitted and received in artificial intelligence data transmission can be composed of a 3-bit header and a 17-bit payload.

[0030] The artificial cochlear implant data transmission method using the artificial cochlear implant data transmission protocol based on the clock image method as described above and the external voice processor of the artificial cochlear implant using the artificial cochlear implant data transmission protocol based on the clock image method provide a low-power interface that uses a minimum number of signals for connection between the internal signal processing chip and the conversion chip and minimizes dynamic power by not directly sending a clock signal and thus has little toggling.

[0031] In addition, in the embodiment, data is captured while avoiding the point at which data received by the protocol conversion chip changes, thereby improving the stability of data capture.

[0032] In addition, the clock image method provided in the embodiment generates a data capturing clock by storing a period of a certain period as a whole so that the jitter of the clock itself and the error due to CDC processing are offset within a certain period, thereby minimizing the problem of data recognition errors due to accumulated errors occurring in each bit.

[0033] The clock image method according to the embodiment can accurately predict the NP2 clock cycle for a longer period of time as the length of the interval for storing the clock image becomes longer.

[0034] In addition, the artificial cochlear implant data transmission method using the artificial cochlear implant data transmission protocol based on the clock image method according to the embodiment and the external voice processor of the artificial cochlear implant using the artificial cochlear implant data transmission protocol based on the clock image method provide a method of updating a snapshot image for a restored NP2 clock intermittently in the protocol even if the length is the same, thereby enabling more accurate prediction for a longer period of time.

[0035] In addition, in the embodiment, a NOP packet with a frequency detection section is additionally defined to provide the above method in the NP2 protocol, thereby enabling the snapshot image to be updated intermittently, thereby minimizing the length of the clock image storage section and reducing the buffer size within the device.

[0036] In addition, the cochlear implant data transmission method using the cochlear implant data transmission protocol based on the clock image method according to the embodiment and the external voice processor of the cochlear implant using the cochlear implant data transmission protocol based on the clock image method minimize synchronization problems that may occur during the data transmission process by having the conversion chip internally restore the cycle of data sent from the voice processing chip to generate an NP2 clock, even though the clock cycles between the voice processing chip and the conversion chip are not related. This can increase the reliability of data transmission and reduce errors.

[0037] In addition, in the embodiment, by using a protocol according to the clock image method, only the offset, which is a change in the data cycle over a certain period of time, is stored in a buffer and used repeatedly, thereby optimizing the amount of calculation and memory usage required while processing data.

[0038] In addition, the clock image method according to the embodiment is designed so that the jitter of the clock itself and the clock domain crossing error can be offset within a certain range, thereby ensuring accurate timing during data capture and reducing potential errors that may occur during data transmission.

[0039] Additionally, in this embodiment, the conversion chip can capture received data more accurately by shifting the capture point to the middle of the data, avoiding data changes. This ensures data integrity and improves real-time data processing efficiency.

[0040] Furthermore, the embodiment enhances the performance of medical devices, such as cochlear implants, where real-time performance is crucial. Accurate data capture and processing through the embodiment can provide users with a more natural hearing experience.

[0041] In addition, the artificial cochlear implant data transmission protocol based on the clock image method according to the embodiment and the external voice processor of the artificial cochlear implant using the artificial cochlear implant data transmission protocol based on the clock image method significantly reduce power consumption in the voice processor due to data transmission and reception between the internal implant of the artificial cochlear implant and the external voice processor by using the clock image method.

[0042] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the detailed description of the present invention or the composition of the invention described in the claims.

[0043] Figure 1 is a drawing showing an artificial cochlea.

[0044] Figure 2 is a diagram showing the configuration of an external voice processor for an artificial cochlea.

[0045] Figure 3 is a drawing showing an external voice processor (1000) of an artificial cochlea according to an embodiment.

[0046] Figure 4 is a block diagram showing a voice processing chip of an external voice processor according to an embodiment.

[0047] FIG. 5 is a drawing for explaining a sync signal and data signal of an NP2 interface according to an embodiment.

[0048] FIG. 6 is a diagram for explaining two types of control packets based on the NP2 protocol transmitted through the NP2 interface according to an embodiment and the frequency detection section of the preamble packet.

[0049] FIG. 7 is a diagram for explaining the types of data packets of the NP2 protocol according to an embodiment and the definition of a NOP packet, which is one of the control packets.

[0050] Figure 8 is a drawing for explaining a clock restoration method using a clock image method according to an embodiment.

[0051] FIG. 9 is a diagram for explaining a method for generating an NP2 data capturing clock (rcvClkEn) using a restored NP2 interface according to an embodiment.

[0052] In a cochlear implant data transmission method according to an embodiment, the cochlear implant includes an external voice processor and an internal unit, and the external voice processor of the cochlear implant includes a voice processing chip that controls the internal unit and a conversion chip; and a conversion chip that performs decoding of data received from the voice processing chip for communication with the internal unit; and the voice processing chip and the conversion chip of the external voice processor of the cochlear implant use an NP2 (Normalized Parameter Packet) interface configured as a 2-wire unidirectional serial interface for communication, the NP2 interface includes a sync signal and a data signal, the sync signal is a signal that toggles at every boundary of a packet frame including a plurality of bits, and the data signal is an N-bit data packet transmitted from the voice processing chip to the conversion chip, and the cochlear implant data transmission method includes the steps of: the voice processing chip transmitting the sync signal and the data signal to the conversion chip; the conversion chip reading the period of the data signal per bit; the conversion chip storing in a buffer a period change of the data signal received for a specific number of bits; A step of capturing a data signal through a clock image method in which a conversion chip repeatedly captures a data signal for a specific number of bits by repeatedly using periodic changes stored in a buffer; wherein the clock image method assumes that the sum of periodic changes of each bit for a current specific number of bits and the sum of periodic changes of each bit for a next specific number of bits have the same value, and can capture data signals for each bit at different points in time for the next specific number of bits according to the period of each current bit stored in the buffer.

[0053] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably only for the convenience of writing the specification, and do not in themselves have distinct meanings or roles. In addition, when describing the embodiments disclosed in this specification, if it is determined that a specific description of a related known technology may obscure the gist of the embodiments disclosed in this specification, a detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

[0054] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0055] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0056] In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0057] In this specification, the term "unit" includes a unit realized by hardware, a unit realized by software, and a unit realized using both. Furthermore, a single unit may be realized using two or more pieces of hardware, and two or more units may be realized by a single piece of hardware.

[0058] Some of the operations or functions described herein as being performed by a terminal, apparatus, or device may instead be performed by a server connected to the terminal, apparatus, or device. Similarly, some of the operations or functions described herein as being performed by a server may also be performed by a terminal, apparatus, or device connected to the server.

[0059] Hereinafter, the present invention will be described in detail with reference to the attached drawings.

[0060] Fig. 2 is a drawing showing an artificial cochlea according to an embodiment.

[0061] Referring to FIG. 2, an artificial cochlear implant according to an embodiment includes a voice processor externally attached by the user and an internal device, which is an internal implant. In an embodiment, the voice processor may be configured to include a voice processing chip and a conversion chip. In an embodiment, the voice processing chip controls the internal device and the conversion chip. In addition, the conversion chip converts data received from the voice processing chip for communication with the internal device.

[0062] FIG. 3 is a drawing showing an external voice processor (1000) of an artificial cochlea according to an embodiment.

[0063] Referring to FIG. 3, an external voice processor (1000) of an artificial cochlear implant according to an embodiment may be configured to include a voice processing chip (100) and a conversion chip (200). The voice processing chip (100) of the external voice processor (1000) converts an external sound received into a digital signal (digital data). The conversion chip (200) converts data received from the voice processing chip (100) into wireless protocol data and then communicates with an internal device according to the protocol. The conversion chip (200) controls an electromagnetic induction type wireless link and generates conversion chip status information according to the wireless link status. The internal device converts a digital signal (neural signal information) received from the conversion chip into neural stimulation information and transmits it to the wearer's neural electrode.

[0064] In the embodiment, the voice processing chip and the conversion chip of the external voice processor of the cochlear implant use an interface configured as a 2-wire unidirectional serial interface for communication. In the present invention, the 2-wire unidirectional serial interface is referred to as NP2 (Normalized Parameter Packet). The NP2 interface includes a sync signal and a data signal. The NP2 interface is a unidirectional interface transmitted from the voice processing chip to the conversion chip, and this is to reduce the overall amount of data communication, thereby reducing energy loss generated during data processing and communication.

[0065] In an embodiment of the present invention, the NP2 Sync signal is a signal that toggles at each boundary of a packet frame including a plurality of bits, and the NP2 Data signal is an N-bit data packet transmitted from a voice processing chip to a conversion chip. In an embodiment, the plurality of bits of each packet frame distinguished by the NP2 Sync signal may include 20 bits.

[0066] In an embodiment, a voice processing chip (100) performs communication with an external voice processor of a cochlear implant using a cochlear implant data transmission protocol based on a clock image method. In an embodiment, the cochlear implant data transmission protocol includes an NP2 (Normalized Parameter Packet) interface configured as a 2-wire unidirectional serial interface, which is a communication protocol between the voice processing chip (100) of the external voice processor of the cochlear implant and a converter chip (200). In an embodiment, the 2-wire interface may be configured with two lines that transmit an NP2 sync signal indicating a boundary of a data frame and an NP2 data signal which is a data bit transmitted to the converter chip (200). That is, in an embodiment, one line of the 2-wire interface is used for sync signal transmission, and the other line is used for data transmission. In this embodiment, the communication lines are configured to a minimum of two lines and a NP2 sync line with less toggling is defined and used instead of a clock, minimizing toggling for data acquisition. This significantly reduces power consumption due to switching.

[0067] In an embodiment, the conversion chip (200) receives data through a clock image method that stores the change in the data cycle for a certain number of bits in a buffer based on the NP2 interface and repeatedly uses the stored change. In an embodiment, the clock image method assumes that the sum of the change in the cycle of each bit for 12 bits and the sum of the change in the cycle of each bit for the next 12 bits have the same change, and captures data at different points in time according to the cycle of each bit stored in the buffer for each bit for the next 12 bits, and uses the captured data.

[0068] To elaborate further:

[0069] The NP2 interface includes a sync signal and a data signal, wherein the sync signal is a signal that toggles at each boundary of a packet frame containing multiple bits, and the data signal is an N-bit data packet transmitted from a voice processing chip to a conversion chip.

[0070] An external voice signal is input, the voice processing chip transmits a sync signal and a data signal to a conversion chip, and the conversion chip reads the period of the data signal per bit. At this time, the conversion chip stores the periodic variation of the data signal received for a specific number of bits in a buffer. The conversion chip captures the data signal through a clock image method, which repeatedly captures the data signal for a specific number of bits by repeatedly using the periodic variation stored in the buffer.

[0071] The above clock image method assumes that the sum of the periodic changes of each bit during the current specific number of bits (e.g., 12 bits) and the sum of the periodic changes of each bit during the next specific number of bits (e.g., 12 bits) have the same value. In this case, an efficient approach to data acquisition is possible because the conversion chip captures data during the next specific number of bits using the periodic changes that occurred during the current specific number of bits. Specifically, the conversion chip captures data signals for each bit at different points in time during the next specific number of bits according to the period of each current bit stored in the buffer. In the embodiment referring to FIG. 8, periodic changes for 12 bits, such as 42 count periods, 43 count periods, and 41 count periods per bit, are used.

[0072] Through this, the external voice processor of the cochlear implant based on the cochlear implant data transmission protocol according to the embodiment can stably capture data transmitted from the voice processing chip (100) to the conversion chip by using the clock (referred to as 'NP2 clock' in the present invention) internally restored by the conversion chip to a cycle inferred from the data sent by the voice processing chip even in a situation where the clock cycle of the voice processing chip (100) and the clock cycle of the conversion chip (200) are completely unrelated to each other. That is, according to the present invention, there is no need to separately transmit clock data between the voice processing chip and the conversion chip, thereby reducing the amount of data to be transmitted and enabling efficient use of power.

[0073] In the embodiment, the voice processing chip (100) uses a preamble packet, which is a one-time packet used in the process of starting data transmission for synchronizing the voice processing chip and the conversion chip in the NP2 interface, a data packet including parameter data transmitted to the conversion chip and an internal device, a NOP packet for compensating for the difference in data rate that occurs during shortening the length of the clock image and protocol conversion, and an Abort packet used by the voice processing chip (100) to bring the FSM of the conversion chip (200) out of the deadlock situation when a deadlock situation occurs in the NP2 protocol FSM (Finite State Machine) of the conversion chip (200).

[0074] In an embodiment, a preamble packet may have 12 bits of 010101010101 in a frequency detection section for determining a variable frequency after a data signal is maintained as 1 for at least 1 frame of a sync signal. In an embodiment, 1 frame may be composed of 20 bits. In addition, an abort packet is a packet in which 3 bits of a header of a data signal are 0, and a protocol FSM (Finite State Machine) of the abort packet is configured such that if the sync signal is toggled twice or more with a length of 3 bits or more of the data signal after the data signal is maintained as 0, a conversion chip recognizes it as an abort packet.

[0075] In addition, the external speech processor of the cochlear implant based on the cochlear implant data transmission protocol based on the clock image method according to the embodiment stores the change in the data period for 12 bits in a buffer through a clock image, which is a snapshot for a certain section, and repeatedly uses it. In the embodiment, for the count values ​​corresponding to the period of each bit for 12 bits, instead of using one average value for the entire 12-bit period as the period of all bits, each count value is stored as one data set and the stored data set is used. That is, in the embodiment, it is assumed that the sum of the period change of each bit for 12 bits and the sum of the period change of each bit for the next 12 bits will have the same amount of change, and each bit for the next 12 bits is captured at different points in time according to the period of each bit stored in the buffer, and then the captured data is used.

[0076] In addition, in the embodiment, the cochlear implant data transmission method using the cochlear implant data transmission protocol based on the clock image method and the external voice processor of the cochlear implant using the cochlear implant data transmission protocol based on the clock image method shift the capture point of the data to match the middle of the data in order to stably capture the data by avoiding the point at which the data received by the conversion chip (200) changes. For example, the conversion chip (200) may shift the data capture point to match the middle of the data signal cycle in order to stably capture the data by avoiding the point at which the data signal changes.

[0077] In addition, the clock image method provided in the embodiment generates a data capturing clock by storing a period of a certain period as a whole so that the jitter of the clock itself and the error due to CDC processing are offset within a certain period.

[0078] In communications, a clock signal is a signal used to synchronize data bits and is essential for controlling the timing of data transmission in a communications system. The clock signal is mainly composed of pulses at regular intervals, and these pulses indicate the appropriate time to transmit or receive data. However, these clock signals cause dynamic switching power losses, which consume the system's power supply. For example, when toggling and changing from 0 to 1, a current of V is instantaneously ddPower consumption inevitably occurs at the timing when the signal is shorted to ground. Since the clock signal has a fast frequency, this dynamic power loss is also relatively much larger than that of other data. Accordingly, if the clock signal is included in the interface for data communication, dynamic power loss may occur in the external speech processor of the cochlear implant. In the embodiment, in order to solve this power loss problem, data communication between the speech processing chip and the conversion chip is performed using a clock image method rather than using an actual clock in the external speech processor of the cochlear implant, so that power consumption due to the clock signal can be significantly reduced.

[0079] Fig. 4 is a block diagram of a voice processing chip of an external voice processor according to an embodiment. The configuration of the voice processing chip (100) illustrated in Fig. 4 is merely a simplified example.

[0080] The communication unit (110) performs communication based on the NP2 protocol using the NP2 interface. In an embodiment, the communication unit (110) can perform communication through a wired protocol used in SPI, I2C, and I2S protocols similar to the NP2 protocol according to the embodiment. The communication protocol used in the embodiment includes a wired protocol as a chip-to-chip interface.

[0081] The memory (120) may refer to any type of storage medium. For example, the memory (120) may include at least one type of storage medium among a flash memory type, a hard disk type, a multimedia card micro type, a card type memory (e.g., SD or XD memory, etc.), a RAM (Random Access Memory), a SRAM (Static Random Access Memory), a ROM (Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a PROM (Programmable Read-Only Memory), a magnetic memory, a magnetic disk, and an optical disk. Such a memory (120) may also constitute a database as illustrated in FIG. 1.

[0082] The memory (120) can store at least one instruction that can be executed by the processor (130). In addition, the memory (120) can store any type of information generated or determined by the processor (130) and any type of information received by the server (100). For example, the memory (120) stores RM (Resource Management) data and RM protocols according to the user, as will be described later. In addition, the memory (120) stores various types of modules, instruction sets, or models.

[0083] In the embodiment, the processor (130) performs operations according to commands and performs communication with an external device of the artificial cochlea through an artificial cochlea data transmission protocol.

[0084] In an embodiment, the cochlear implant data transmission protocol includes an NP2 interface configured as a 2-wire unidirectional serial interface, which is a communication interface between a voice processing chip (100) of an external voice processor of the cochlear implant and a converter chip (200). In an embodiment, the processor (130) generates and transmits an NP2 sync signal and an NP2 data signal in accordance with its own clock, and captures data by inferring the clock used by the processor (130) through a clock image method in a slave converter chip. In an embodiment, the processor (130) uses the clock it is using when transmitting data. In an embodiment, the clock being used includes a clock having a frequency between 500 kHz and 2 MHz.

[0085] The clock image method proposed in the embodiment assumes that the sum of the periodic changes of each bit during 12 bits and the sum of the periodic changes of each bit during the next 12 bits have the same amount of change, and then captures each bit during the next 12 bits at different points in time according to the period of each bit stored in the buffer.

[0086] FIG. 5 is a diagram for explaining a sync signal and a data signal of an NP2 interface according to an embodiment.

[0087] Referring to FIG. 5, the NP2 interface according to the embodiment is a 2-wire unidirectional serial interface. The NP2 sync illustrated in FIG. 5 is a signal that toggles at each packet frame boundary of a frame composed of N-bit packets. In the embodiment, it toggles every 20 bits.

[0088] NP2 data is an N-bit data packet transmitted from a voice processing chip (100) to a conversion chip (200). In the embodiment, data transmission is implemented with a minimum number of signals through the NP2 interface.

[0089] Typically, dynamic power loss is caused by a toggling signal. Toggling is a phenomenon in which each N bit changes from 1 to 0, or 0 to 1. In other words, dynamic power loss occurs momentarily at the moment of changing from one state to another. Accordingly, in the embodiment, instead of directly transmitting a clock, a 20-bit data signal is configured in one frame and toggled every 20 bits, thereby sending an NP2 Sync signal that can distinguish packet frame boundaries with minimal toggling so that the receiving end recognizes the start time of the frame, thereby synchronizing the data being sent and received. Since the voice processing chip does not directly send a clock signal to the conversion chip, toggling is reduced, thereby minimizing power loss.

[0090] FIG. 6 is a diagram for explaining a control packet of the NP2 protocol according to an embodiment, separately explaining the bit configuration for two control packets with different bit configurations from the data packet, and explaining the frequency detection section of the preamble packet.

[0091] Referring to FIGS. 6 and 7, packets transmitted as NP2 data signals in the NP2 interface may include preamble packets, data packets, NOP packets, and interrupt packets. In the embodiment, NOP packets are packets that do not perform any special tasks, and are packets for frequency correction, timing maintenance, bus maintenance, error detection, state maintenance, expansion, and flow control. Data packets include, but are not limited to, TCP (Transmission Control Protocol) packets, UDP (User Datagram Protocol) packets, and the like.

[0092] In an embodiment, a packet transmitted and received in artificial cochlear implant data transmission may be composed of a 3-bit header and a 17-bit payload. In an embodiment, the payload may be composed of a certain number of bits, such as 13 to 61 bits. The number of bits of the payload is not limited to the example described above. Packets defined in the NP2 protocol are largely divided into two types: data packets and control packets.

[0093] As shown in the embodiment of Fig. 7, the data packet provided in the NP2 protocol consists of a data packet for the stimulation chip and a data packet for the conversion chip. All data packets consist of 20 bits, and each 20 bits is specifically composed of a 3-bit header and a 17-bit payload. The data packet for the stimulation chip is a packet that sends parameter information required when generating an electrical stimulation signal, and consists of a 3-bit header, a 1-bit packet mode, and 16-bit data. In addition, the data packet for the stimulation chip is divided into two types: a parameter packet and a configuration packet. Each packet is divided into a parameter packet and a configuration packet according to the packet mode, and the bit area of ​​the 16-bit data is defined as a unique bit field for each packet.

[0094] Control packets, as defined in the NP2 protocol, unlike the aforementioned data packets, do not actually contain the data being transmitted. Instead, they serve the role of sending packet control information to the receiver to ensure proper transmission of the data packet. There are three types of control packets defined in the NP2 protocol: preamble packets, NOP packets, and abort packets.

[0095] The Preamble Packet is a one-time packet used in the data transmission start process to synchronize the voice processing chip (100) and the converter chip (200). The NOP packet is a packet used to simply maintain a connection or adjust timing without performing any work on the NP2 interface. In an embodiment, the NOP packet may include a packet for compensating for a shortened NP2 clock image length and a difference in data bit rate that occurs during protocol conversion. The Abort Packet is a packet used by the voice processing chip (100) to forcibly cause the converter chip FSM (200) to escape from a deadlock situation when a deadlock situation occurs in the NP2 protocol FSM of the converter chip.

[0096] In the embodiment, the NOP packet does not perform any task in the NP2 interface, and is used to maintain the connection between the voice processing chip and the converter chip or to adjust the timing, and the NOP packet includes a frequency detection section for updating the data signal capture period. In addition, since the converter chip can update the data signal capture period when receiving the NOP packet, if the voice processing chip (100) sends the NOP packet at a short period, the length of the clock image storage period can be reduced in proportion to the decrease in the period. As a result, the length of the clock image storage period can be minimized through this NOP packet.

[0097] In addition, as illustrated in FIG. 6, the preamble packet according to the embodiment has NP2 data maintained as 1 for a certain period of time (e.g., at least 1 frame) or more, and has 010101010101 (12 bits) as a frequency detection section for determining a variable frequency. In the embodiment, the NP2 clock frequency of the voice processing chip for generating NP2 data can be varied in the range of 500 kHz to 2 MHz.

[0098] In an embodiment, the initial period identification at the start of data transmission is performed by the receiving converter chip through a preamble packet in the NP2 protocol. The longer the total period stored in the clock image method, the less errors due to CDC errors there are. In addition, the clock image method according to the embodiment does not calculate the average of each period, but treats multiple periods as one to offset errors within the period, thereby ensuring the accuracy of data received between the entire periods treated as a whole. In addition, in the embodiment, when receiving data with a long period that is a multiple of the stored clock image, the stored image can be repeatedly used until there is no error.

[0099] The Abort Packet in Fig. 6 is a packet that has the same bit structure as a data packet by definition and a header bit of 0. In an embodiment, the NP2 protocol FSM must be able to recognize an abort packet even if it has not completely received one frame of data consisting of 20 bits indicated by the NP2 Sync signal, if the NP2 data remains 0 and the NP2 sync is toggled twice or more with a length greater than or equal to the length of 3 bits of the NP2 data, it must be able to recognize an abort packet. This is an optional function to shorten the aborting time by enabling the abort to be performed immediately without having to send a long control signal to notify the FSM of the transmission interruption because in fact all the data to be transmitted is 0. In an embodiment, the number of bits of the NP2 data included in one packet frame indicated by the NP2 Sync signal may be 20 bits, and the specific number of bits used in the clock image method may be 12 bits.

[0100] FIG. 7 is a diagram for explaining the types of data packets of the NP2 protocol according to an embodiment and the definition of a NOP packet, which is one of the control packets.

[0101] Referring to FIG. 7, the stimulus chip parameter packet is a parameter packet that is converted into a COLA packet, which is a wireless protocol not described in the present invention, and transmitted to the stimulus chip.

[0102] The Converter Chip Setting Packet is a packet used to configure the converter chip to create a COLA packet. The Converter Chip Setting Packet is a packet used to set settings that need to be aligned with the COLA packet in terms of timing. The Protocol Abort Packet is a protocol abort packet sent to initialize the NP2 interface FSM of the converter chip.

[0103] The conventional average period clock method uses the average value of the count values ​​from the moment when 0 to 1 is calculated from the 12 bits of the preamble packet where 0101… is repeated, and uses this as the period of the internal data capturing clock. However, when we experimentally checked by running a long-run test, we were able to confirm that the synchronization was frequently lost in the middle. In addition to the fundamental error caused by the clock cycles of the sender and receiver being different, it is caused by a large difference between the actual cycle of the clock sending the data and the cycle predicted after capturing due to the CDC processing when receiving NP2 data.

[0104] For example, although the length of one bit is actually 20 cycles in the sent clock cycle, the clock cycle recovered on the receiving end can vary from 17 cycles to 23 cycles due to the period change caused by the jitter of the sending clock and the period error caused by the CDC processing. Therefore, if the average value of the periods measured in the frequency detection section is 17 cycles, there are cases where the bit values ​​of the NP2 data coming in from the 7th bit (3 cycles * 7 = 21 cycles) are incorrectly recognized due to a 3-cycle error. In other words, in the conventional method, even in a situation where the clock cycle of the sending end is ideally unchanged, the CDC error that occurred during reception is included in the clock cycle itself, so a bit recognition error can occur in a short period of time just due to the accumulated error caused by this CDC processing.

[0105] To solve this problem, the embodiment provides a clock image method, which is a snapshot concept for a certain period. The clock image method stores the changes in the data period for 12 bits in a buffer and repeatedly uses the stored changes. That is, in the embodiment, rather than using a single average value for the entire 12-bit period for the count values ​​corresponding to the period of each bit for 12 bits as the period of all bits, each count value is stored as a single data set and the stored data set is used. That is, the embodiment assumes that the sum of the period changes of each bit for 12 bits and the sum of the period changes of each bit for the next 12 bits will have the same amount of change. Thereafter, each bit for the next 12 bits is captured at different points in time according to the periods of each bit stored in the buffer. In addition, in the embodiment, the capture point is shifted to align with the middle of the data in order to capture data stably while avoiding points where the incoming NP2 data changes, thereby improving the stability of data capture. The clock image method provided in the embodiment generates a data capturing clock by fully storing a certain period of the cycle so that the jitter of the clock itself and the error due to CDC processing are offset within the certain period. This minimizes data recognition errors caused by accumulated errors occurring in each bit. The clock image method according to the embodiment was confirmed to rarely experience sync loss situations through experimental long-run tests.

[0106] In the conversion chip (200), the continuous toggling edge of the NP2 data is detected in the frequency detection section of the preamble packet sent from the voice processing chip (100) to determine the period of the NP2 clock used when creating the data. At this time, since the NP2 clock period of the voice processing chip (100) that creates the NP2 data and the internal clock period of the conversion chip (200) that captures the NP2 data are different, the incoming data is subjected to CDC (Clock Domain Crossing) processing using the internal clock of the conversion chip. In this way, the NP2 data is created as a signal in the internal clock domain of the conversion chip, and the period of the NP2 clock of the voice processing chip is determined using the created data. At this time, since the error due to the period difference between the internal clocks of different chips changes randomly, it is fundamentally impossible to accurately infer the period of the NP2 clock used by the voice processing chip when sending data.

[0107] To solve this, in the embodiment, even in a situation where the clock cycle of the voice processing chip and the clock cycle of the conversion chip are completely unrelated to each other, the conversion chip must stably capture the NP2 data sent by the voice processing chip using the NP2 clock that is internally restored to a cycle inferred from the data sent by the voice processing chip.

[0108] To this end, in the embodiment, the clock cycle fluctuation itself for a certain period is stored as a snapshot image, and the stored clock image is repeatedly used when capturing incoming data for a period corresponding to several multiples of the stored length, thereby minimizing the accumulated clock cycle error occurring during the same period.

[0109] The clock image method according to the embodiment is a continuous image of a fluctuating clock cycle that reflects clock jitter and period error due to CDC processing for a certain section, so it is representative of the fluctuating clock cycle for the entire section, and can accurately predict the clock cycle for a much longer period than a clock generated simply by the average cycle. Through this, data capture errors can be eliminated for the predicted period. In addition, the clock image method according to the embodiment can capture the transmitted data without error for a longer period than the average cycle clock method.

[0110] The average cycle clock method cannot properly reflect the real-time changing clock pattern and random errors due to CDC processing, and instead captures incoming data assuming a clock pattern with a constant cycle. Therefore, in real-world situations, even after several dozen cycles, a significant amount of cycle error accumulates, resulting in data capture errors.

[0111] However, the clock image method according to the embodiment can accurately predict the NP2 clock cycle for a longer period of time as the interval for storing the clock image increases. Furthermore, even if the interval is the same length, if the snapshot image for the restored NP2 clock can be updated intermittently, accurate prediction for a longer period of time is possible. This means that the required clock image storage interval length can be reduced by adjusting the update interval.

[0112] In the embodiment, a method is provided to update a snapshot image intermittently by defining a NOP packet on the NP2 interface, thereby minimizing the length of the clock image storage interval.

[0113] Fig. 8 is a drawing for explaining a clock restoration method using a clock image method according to an embodiment.

[0114] Referring to FIG. 8, in an embodiment, when reading the period of the first bit of a frequency detection section in a preamble packet or a NOP packet, the conversion chip acquires the period of the first bit through an up-count method that increases from 0 by 1, and sets the period of the first bit as a reference period for clock image capture. In an embodiment, as illustrated in FIG. 8, the period of the first bit can be set to 41 clocks.

[0115] The conversion chip (200) stores the difference between the period of each subsequent bit and the reference period as an offset value through a down-count method that decreases the period by 1 from the reference period in the following bits. The offset values ​​shown in Fig. 8 are 0, -1, and 1.

[0116] Afterwards, the conversion chip (200) uses the offset value as the periodic change of each bit when capturing the data signal through the clock image method.

[0117] In an embodiment, NP2 clock frequency detection is performed using NP2 data, and a snapshot image is generated. In an embodiment, the NP2 clock frequency is determined through an up-count in the first bit of the frequency detection section in a preamble packet or a NOP packet. Thereafter, the determined frequency value is set as a reference value, and in the subsequent bits, a down-count is performed from the reference value, thereby storing an offset value generated compared to the reference value in memory, thereby generating a snapshot image for the clock. Here, the offset value can be a (+) or (-) value.

[0118] In the embodiment, as illustrated in FIG. 8, when the conversion chip (200) down-counts, if the last counted value of the corresponding bit period is negative, it means that the corresponding bit period is larger than the reference period, and therefore, the sign of the offset value, which is the error from the reference period, is stored as (+). In addition, when the conversion chip down-counts, if the last counted value of the corresponding bit period is positive, it means that the corresponding bit period is smaller than the reference period, and therefore, the sign of the offset value is stored as (-). Thereafter, when the conversion chip restores each bit period for the next specific number of bits, it restores each bit period by adding the offset value to the reference period.

[0119] Specifically, in the embodiment, when down-counting from the reference value, if the offset value is a (-) value, it means that it is larger than the reference value, so the offset value, which is the error with the reference period value, is stored in the buffer as a (+) value, and if the offset value is a (+) value, it means that it is smaller than the reference value, so the offset value is stored as a (-) value, and when restoring the clock later, this offset value is added to the reference value representing one period to restore the clock period. In the embodiment, the conversion chip stores the sign of the error (offset) based on the last counting value of each bit period, so that the difference between the actual bit period and the reference period can be concisely expressed. If the conversion chip processes and stores data in the same manner as in the embodiment, the data can be used faster and more efficiently in subsequent analysis or processing steps, which can contribute to improving the performance of the overall system.

[0120] FIG. 9 is a diagram for explaining a method for generating an NP2 data capturing clock (rcvClkEn) using a restored NP2 clock cycle according to an embodiment.

[0121] Referring to Fig. 9, a total of 21 clock signals (rcvClkEn) appear during a 20-bit regular frame. Specifically, the clock signal (rcvClkEn) may include one frame sync clock and 20 data capturing clocks.

[0122] In the embodiment, a frame sync clock is generated for each frame to align the count values, thereby preventing the problem of sync lost.

[0123] The first bit section of each frame generates a restored clock signal (rcvClkEn) by loading the aforementioned clock cycle reference value based on the Frame Sync Clock signal and counting down, and for the subsequent bit sections, the offsets in the clock image buffer are sequentially extracted and added to the clock cycle reference value to generate a count value. In the embodiment, the clock signals (rcvClkEn) of each bit section are generated by continuously counting down by loading a newly created value when the previous count value expires. The clock image buffer is a circular buffer, and clock images can be infinitely repeatedly generated by going back to the beginning from the end of the buffer and reusing values.

[0124] In the embodiment, if the number of counts for 1 bit is N based on the internal clock of the conversion chip, a clock signal (rcvClkEn) is generated so that data capturing is performed at a timing when half of it becomes N / 2.

[0125] In the last 20th bit, when the data capturing clock comes up, even if the count value is not finished, the down-count is stopped and the frame sync clock is kept waiting to prepare for the next regular frame. This is to prevent the problem that the frame sync clock may not be recognized and sync lost if the point in time when the down-count is finished is later than the point in time when the frame sync clock occurs when the next regular frame starts if the count value is performed to the end.

[0126] In an embodiment, in order to prevent a data rate error of the conversion chip due to a difference in data transmission speed that may occur when converting NP2 data to COLA packet data when the clock rate of the NP2 packet is fast, at least one NOP may be inserted in the middle. Here, 66 bits of the COLA packet is an example when the phase extender is the minimum duration. In an embodiment, the minimum duration may be 0.5 us per bit.

[0127] The external voice processor of the cochlear implant based on the artificial cochlear implant data transmission protocol based on the clock image method as described above provides a low-power interface with minimal dynamic power by using a minimum number of signals and not directly sending clock signals, thereby minimizing toggling.

[0128] In addition, in the embodiment, data is captured while avoiding the point at which data received by the protocol conversion chip changes, thereby improving the stability of data capture.

[0129] In addition, the clock image method provided in the embodiment generates a data capturing clock by storing a period of a certain period as a whole so that the jitter of the clock itself and the error due to CDC processing are offset within a certain period, thereby minimizing the problem of data recognition errors due to accumulated errors occurring in each bit.

[0130] The clock image method according to the embodiment can accurately predict the NP2 clock cycle for a longer period of time as the length of the interval for storing the clock image becomes longer.

[0131] In addition, the external speech processor of the cochlear implant based on the cochlear implant data transmission protocol based on the clock image method according to the embodiment enables accurate prediction for a longer period of time by updating the snapshot image for the restored NP2 clock at intervals even if the length is the same.

[0132] In addition, the embodiment defines a NOP packet in the NP2 interface so that the snapshot image can be updated intermittently, thereby minimizing the length of the clock image storage interval.

[0133] The disclosed content is merely an example, and various modifications and implementations can be made by a person skilled in the art without departing from the gist of the claims claimed in the patent, so the scope of protection of the disclosed content is not limited to the specific embodiments described above.

[0134] The artificial cochlear implant data transmission method using the artificial cochlear implant data transmission protocol based on the clock image method as described above and the external voice processor of the artificial cochlear implant using the artificial cochlear implant data transmission protocol based on the clock image method provide a low-power interface that uses a minimum number of signals for connection between the internal signal processing chip and the conversion chip and minimizes dynamic power by not directly sending a clock signal and thus has little toggling.

[0135] In addition, in the embodiment, data is captured while avoiding the point at which data received by the protocol conversion chip changes, thereby improving the stability of data capture.

[0136] 1000: External speech processor for cochlear implants

Claims

1. In the method of transmitting artificial cochlear data, The above artificial cochlea includes an external speech processor and an internal device, The external voice processor of the above artificial cochlea is, A voice processing chip that controls the internal device and conversion chip; and A conversion chip that performs decoding of data received from the voice processing chip for communication with the internal device; The voice processing chip and conversion chip of the external voice processor of the above artificial cochlea use the NP2 (Normalized Parameter Packet) interface consisting of a 2-wire unidirectional serial interface for communication, and the NP2 interface includes a sync signal and a data signal. The above sync signal is a signal that toggles at each boundary of a packet frame containing multiple bits, The above data signal is an N-bit data packet transmitted from the voice processing chip to the conversion chip, The above artificial cochlear data transmission method is, A step in which the above voice processing chip transmits a sync signal and a data signal to a conversion chip; A step in which the above conversion chip reads the cycle of the data signal per bit; A step of storing the periodic change of the data signal received by the above conversion chip for a specific number of bits in a buffer; The above conversion chip comprises a step of capturing a data signal through a clock image method in which the data signal is repeatedly captured for a specific number of bits by repeatedly using the periodic variation stored in the buffer; The above clock image method is characterized in that it assumes that the sum of the periodic changes of each bit during the current specific number of bits and the sum of the periodic changes of each bit during the next specific number of bits have the same value, and captures the data signal of each bit at a different time during the next specific number of bits according to the period of each current bit stored in the buffer. Artificial cochlear implant data transmission method.

2. In paragraph 1, The above conversion chip further includes a step of shifting the data capture point to match the middle of the data signal cycle in order to stably capture data while avoiding the point at which the data signal changes. Artificial cochlear implant data transmission method.

3. In the first paragraph, the voice processing chip A preamble packet is a one-time packet used at the beginning of data transmission to synchronize the voice processing chip and conversion chip in the NP2 interface. A data packet containing parameter data transmitted to the converter chip and internal device, NOP packets to compensate for the difference in data rate that occurs during shortening of the clock image length and protocol conversion, and When a deadlock situation occurs in the NP2 protocol FSM (Finite State Machine) of the conversion chip, the voice processing chip uses an Abort packet to bring the FSM of the conversion chip out of the deadlock situation. Artificial cochlear implant data transmission method.

4. In the third paragraph, the preamble packet After the data signal remains 1 for at least 1 frame of the sync signal, the frequency detection section for determining the variable frequency has N bits repeated in the form of 010101010101. Artificial cochlear implant data transmission method.

5. In the third paragraph, the interrupt packet A packet in which the header 3 bits of the data signal are 0. The protocol FSM (Finite State Machine) of the above abort packet is configured so that the converter chip recognizes it as an abort packet when the sync signal is toggled twice or more with a length greater than 3 bits of the data signal after the data signal remains 0. Artificial cochlear implant data transmission method.

6. In the third paragraph, the NOP packet It is used to maintain the connection between the voice processing chip and the conversion chip or to adjust the timing without performing any operation on the NP2 interface, and the NOP packet includes a frequency detection section for updating the data signal capture period. When the above conversion chip receives the NOP packet, the data signal capture cycle is updated to minimize the clock image storage section length. Artificial cochlear implant data transmission method.

7. In paragraph 6, A step of obtaining the period of the first bit through an up-count method that increases from 0 to 1 when the above conversion chip reads the period of the first bit of the frequency detection section in the preamble packet or the NOP packet, and setting the period of the first bit as a reference period for clock image capture; The above conversion chip further includes a step of storing the difference value between the period of each subsequent bit and the reference period as an offset value through a down-count method that decreases the period by 1 from the reference period in the following bits; The above conversion chip is characterized in that, when capturing a data signal through a clock image method, the offset value is used as a periodic change of each bit. Artificial cochlear implant data transmission method.

8. In paragraph 7, When the above conversion chip down-counts, if the last counting value of the corresponding bit cycle is negative, it means that the corresponding bit cycle is greater than the reference cycle, so a step of storing the sign of the offset value, which is the error from the reference cycle, as (+); A step of storing the sign of the offset value as (-) when the last counting value of the corresponding bit cycle is positive when the above conversion chip down-counts, as this means that the corresponding bit cycle is smaller than the reference cycle; When the above conversion chip restores each bit cycle for the next specific number of bits, each bit cycle is restored by adding the offset value to the reference cycle. Artificial cochlear implant data transmission method.

9. In paragraph 1, A plurality of bits included in one packet frame of the sync signal are characterized in that they are bits in the range of 16 bits to 64 bits. Artificial cochlear implant data transmission method.

10. In paragraph 9, The specific number of bits used in the above clock image method is characterized by being 12 bits. Artificial cochlear implant data transmission method.

11. In the third paragraph, the packets transmitted and received in the artificial cochlea data transmission are It is characterized by being composed of a 3-bit header and a payload of a certain number of bits. Artificial cochlear implant data transmission method.

12. In the external voice processor of the artificial cochlea, The above artificial cochlea includes an external speech processor and an internal device, The external voice processor of the above artificial cochlea is, A voice processing chip that controls the internal device and conversion chip; and A conversion chip that performs decoding of data received from the voice processing chip for communication with the internal device; The voice processing chip and conversion chip of the external voice processor of the above artificial cochlea use the NP2 (Normalized Parameter Packet) interface consisting of a 2-wire unidirectional serial interface for communication, and the NP2 interface includes a sync signal and a data signal. The above sync signal is a signal that toggles at each boundary of a packet frame containing multiple bits, The above data signal is an N-bit data packet transmitted from the voice processing chip to the conversion chip, The above artificial cochlea is for data transmission, The above voice processing chip transmits the sync signal and data signal to the conversion chip, The above conversion chip reads the cycle of the data signal per bit, The above conversion chip stores the periodic change of the data signal received for a specific number of bits in a buffer; The above conversion chip is configured to capture a data signal through a clock image method that repeatedly captures a data signal for a specific number of bits by repeatedly using the periodic variation stored in the buffer, The above clock image method is characterized in that it assumes that the sum of the periodic changes of each bit during the current specific number of bits and the sum of the periodic changes of each bit during the next specific number of bits have the same value, and captures the data signal of each bit at a different time during the next specific number of bits according to the period of each current bit stored in the buffer. External speech processor of cochlear implant.

13. In paragraph 12, The above conversion chip is configured to shift the data capture point to match the middle of the data signal cycle in order to stably capture data while avoiding the point at which the data signal changes. External speech processor of cochlear implant.

14. In the 12th paragraph, the voice processing chip A preamble packet is a one-time packet used at the beginning of data transmission to synchronize the voice processing chip and conversion chip in the NP2 interface. A data packet containing parameter data transmitted to the converter chip and internal device, NOP packets to compensate for the difference in data rate that occurs during shortening of the clock image length and protocol conversion, and When a deadlock situation occurs in the NP2 protocol FSM (Finite State Machine) of the conversion chip, the voice processing chip uses an Abort packet to bring the FSM of the conversion chip out of the deadlock situation. External speech processor of cochlear implant.

15. In paragraph 14, the preamble packet After the data signal remains 1 for at least 1 frame of the sync signal, the frequency detection section for determining the variable frequency has N bits repeated in the form of 010101010101. External speech processor of cochlear implant.

16. In paragraph 14, the interrupt packet is A packet in which the header 3 bits of the data signal are 0. The protocol FSM (Finite State Machine) of the above abort packet is configured so that the converter chip recognizes it as an abort packet when the sync signal is toggled twice or more with a length greater than 3 bits of the data signal after the data signal remains 0. External speech processor of cochlear implant.

17. In paragraph 14, the NOP packet It is used to maintain the connection between the voice processing chip and the conversion chip or to adjust the timing without performing any operation on the NP2 interface, and the NOP packet includes a frequency detection section for updating the data signal capture period. When the above conversion chip receives the NOP packet, the data signal capture cycle is updated to minimize the clock image storage section length. External speech processor of cochlear implant.

18. In paragraph 17, The above conversion chip, when reading the period of the first bit of the frequency detection section in the preamble packet or the NOP packet, acquires the period of the first bit through an up-count method that increases from 0 to 1, and sets the period of the first bit as a reference period for clock image capture. The above conversion chip stores the difference between the period of each subsequent bit and the reference period as an offset value through a down-count method that decreases the period by 1 from the reference period in the following bits. The above conversion chip is characterized in that, when capturing a data signal through a clock image method, the offset value is used as a periodic change of each bit. External speech processor of cochlear implant.

19. In paragraph 18, When the above conversion chip down-counts, if the last counting value of the corresponding bit cycle is negative, it means that the corresponding bit cycle is greater than the reference cycle, so the sign of the offset value, which is the error from the reference cycle, is stored as (+). When the above conversion chip down-counts, if the last counting value of the corresponding bit cycle is positive, it means that the corresponding bit cycle is smaller than the reference cycle, so the sign of the offset value is stored as (-). When the above conversion chip restores each bit cycle for the next specific number of bits, each bit cycle is restored by adding the offset value to the reference cycle. External speech processor of cochlear implant.

20. In paragraph 12, A plurality of bits included in one packet frame of the sync signal are characterized in that they are bits in the range of 16 bits to 64 bits. External speech processor of cochlear implant.

21. In paragraph 20, The specific number of bits used in the above clock image method is characterized by being 12 bits. External speech processor of cochlear implant 22. In paragraph 14, the packets transmitted and received in the artificial cochlea data transmission are It is characterized by being composed of a 3-bit header and a payload ranging from 13 to 61 bits. External speech processor of cochlear implant

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