Solar cell and preparation method therefor

Abstract

The present application relates to the technical field of solar cell manufacturing. Disclosed are a solar cell and a preparation method therefor. The solar cell comprises: a silicon substrate; an emitter and a first passivation and anti-reflection structure that are arranged from inside to outside on one side of the silicon substrate in the direction of thickness, wherein the first passivation and anti-reflection structure comprises a first passivation and anti-reflection layer and a second passivation and anti-reflection layer; and a tunneling oxide layer, a doped polysilicon layer and a second passivation and anti-reflection structure that are arranged from inside to outside on the other side of the silicon substrate in the direction of thickness, wherein the second passivation and anti-reflection structure comprises a third passivation and anti-reflection layer and a fourth passivation and anti-reflection layer, and the second passivation and anti-reflection layer and the fourth passivation and anti-reflection layer are arranged in an edge region of the silicon substrate. The embodiment effectively increases the thickness of the passivation and anti-reflection layers at the edge of the silicon substrate, thereby improving the passivation performance and photoelectric conversion efficiency at the edge of the solar cell.

Description

Solar cell and preparation method thereof

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to Chinese Patent Application No. 202410806816.7, filed on June 20, 2024, entitled "Solar cell and preparation method thereof", the disclosure of which is hereby incorporated by reference in its entirety as part of, or all of, the present application. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cell manufacturing, and particularly relates to a preparation method of a solar cell and a back contact solar cell. BACKGROUND

[0004] The existing tunnel oxide passivated contact solar cell prepares an ultrathin silicon oxide layer (i.e., a tunnel oxide layer) and a highly doped polysilicon layer on the surface of silicon to effectively inhibit the recombination of minority carriers on the surface of silicon and improve the open-circuit voltage of the cell by using the selective permeability of the ultrathin silicon oxide layer to carriers and the good field passivation effect of the highly doped polysilicon layer on the substrate. However, as the area of the solar cell wafer continues to increase, uneven heating occurs due to the influence of edge airflow during mass production of the solar cell, resulting in a thinner silicon oxide layer at the edge, which affects the passivation uniformity of the entire cell and thus affects the conversion efficiency of the cell.

[0005] SUMMARY

[0006] In view of this, the embodiments of the present disclosure provide a solar cell and a preparation method thereof.

[0007] To solve the above technical problems, the present disclosure provides the following technical solutions:

[0008] In a first aspect, the present disclosure provides a solar cell, comprising: a silicon substrate; an emitter and a first passivation and anti-reflection structure arranged from inside to outside on one side of the silicon substrate in the thickness direction, wherein the first passivation and anti-reflection structure comprises a first passivation and anti-reflection layer and a second passivation and anti-reflection layer, and the second passivation and anti-reflection layer is arranged on an edge region of the silicon substrate; a tunnel oxide layer, a doped polysilicon layer, and a second passivation and anti-reflection structure arranged from inside to outside on the other side of the silicon substrate in the thickness direction, wherein the second passivation and anti-reflection structure comprises a third passivation and anti-reflection layer and a fourth passivation and anti-reflection layer, and the fourth passivation and anti-reflection layer is arranged on the edge region of the silicon substrate.

[0009] According to one or more embodiments of the present disclosure, the first passivation and anti-reflection layer and the fourth passivation and anti-reflection layer are formed synchronously, and the second passivation and anti-reflection layer and the third passivation and anti-reflection layer are formed synchronously.

[0010] According to one or more embodiments of the present disclosure, the fourth passivation anti-reflection layer is formed by controlling the fitting distance between the silicon substrate and the carrier when the first passivation anti-reflection layer is prepared; and the second passivation anti-reflection layer is formed by controlling the fitting distance between the silicon substrate and the carrier when the third passivation anti-reflection layer is prepared.

[0011] According to one or more embodiments of the present disclosure, the second passivation anti-reflection layer is arranged outside the first passivation anti-reflection layer; and the fourth passivation anti-reflection layer is arranged between the doped polysilicon layer and the third passivation anti-reflection layer.

[0012] According to one or more embodiments of the present disclosure, the second passivation anti-reflection layer is arranged between the first passivation anti-reflection layer and the emitter; and the fourth passivation anti-reflection layer is arranged outside the third passivation anti-reflection layer.

[0013] According to one or more embodiments of the present disclosure, the width of the second passivation anti-reflection layer is 0.5mm-10mm; and / or, the width of the fourth passivation anti-reflection layer is 0.5mm-10mm.

[0014] According to one or more embodiments of the present disclosure, the first passivation anti-reflection layer and / or the fourth passivation anti-reflection layer comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride; and / or, the second passivation anti-reflection layer and / or the third passivation anti-reflection layer comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride.

[0015] According to one or more embodiments of the present disclosure, the thickness of the first passivation anti-reflection layer and / or the fourth passivation anti-reflection layer is 20nm-180nm; and / or, the thickness of the second passivation anti-reflection layer and / or the third passivation anti-reflection layer is 25nm-200nm.

[0016] According to one or more embodiments of the present disclosure, the thickness of the tunneling oxide layer is 0.5nm-5nm; and / or, the thickness of the doped polysilicon layer is 30nm-200nm.

[0017] In a second aspect, the present disclosure provides a preparation method of the above-mentioned solar cell, comprising:

[0018] Step 1, preparing an emitter on one side of the silicon substrate in the thickness direction of the silicon substrate;

[0019] Step 2, sequentially preparing a tunneling oxide layer and a doped polysilicon layer from inside to outside on the other side of the silicon substrate in the thickness direction of the silicon substrate;

[0020] Step 3, a first passivation anti-reflection structure and a second passivation anti-reflection structure are respectively prepared outside the emitter and outside the doped polysilicon layer; wherein the first passivation anti-reflection structure comprises a first passivation anti-reflection layer and a second passivation anti-reflection layer, and the second passivation anti-reflection layer is arranged at the edge region of the silicon substrate; the second passivation anti-reflection structure comprises a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, and the fourth passivation anti-reflection layer is arranged at the edge region of the silicon substrate. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are used to better understand the present disclosure, and do not constitute improper limitations on the present disclosure. Among them:

[0022] Fig. 1 is a schematic diagram of the overall structure of a graphite boat carrier according to an embodiment of the present disclosure;

[0023] Fig. 2 is a front view of a graphite boat carrier into which a silicon substrate is inserted according to an embodiment of the present disclosure;

[0024] Fig. 3 is a schematic diagram of the cross-sectional structure of a solar cell structure according to an embodiment of the present disclosure;

[0025] Fig. 4 is a schematic diagram of the cross-sectional structure of another solar cell structure according to an embodiment of the present disclosure;

[0026] Fig. 5 is a flowchart of a preparation method of a solar cell according to an embodiment of the present disclosure;

[0027] Fig. 6 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared through step S501 according to an embodiment of the present disclosure;

[0028] Fig. 7 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared through step S502 according to an embodiment of the present disclosure;

[0029] Fig. 8 is a specific flowchart of a preparation method of a first passivation anti-reflection structure and a second passivation anti-reflection structure according to an embodiment of the present disclosure;

[0030] Fig. 9 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared through step S801 according to an embodiment of the present disclosure;

[0031] Fig. 10 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared through step S802 according to an embodiment of the present disclosure;

[0032] Fig. 11 is a specific flowchart of another preparation method of a first passivation anti-reflection structure and a second passivation anti-reflection structure according to an embodiment of the present disclosure;

[0033] Fig. 12 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared through step S1101 according to an embodiment of the present disclosure;

[0034] FIG. 13 is a schematic diagram of a cross-sectional structure of a silicon substrate prepared through step S1102 according to an embodiment of the present disclosure;

[0035] FIG. 14 is a PL result of a solar cell obtained according to Example 1 according to an embodiment of the present disclosure;

[0036] FIG. 15 is a PL result of a solar cell obtained according to Comparative Example 1 according to an embodiment of the present disclosure.

[0037] Reference signs are as follows:

[0038] 1-silicon substrate; 2-emitter; 3-first passivation and anti-reflection structure; 31-first passivation and anti-reflection layer; 32-second passivation and anti-reflection layer; 4-first metal electrode; 5-tunneling oxide layer; 6-doped polysilicon layer; 7-second passivation and anti-reflection structure; 71-third passivation and anti-reflection layer; 72-fourth passivation and anti-reflection layer; 8-second metal electrode. DETAILED DESCRIPTION

[0039] A solar cell is a kind of photovoltaic semiconductor wafer that directly generates electricity from sunlight, also known as a "solar chip" or "photovoltaic cell". It can output voltage and generate current in a loop as long as it is illuminated by light with a certain illuminance. In physics, it is called solar photovoltaic (Photovoltaic, abbreviated as PV) and photovoltaic. In order to facilitate and clearly describe the preparation method of the solar cell and the solar cell of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the drawings, which include various details of the embodiments of the present disclosure to help understanding, which should be considered only as exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, in order to be clear and concise, the description in the following description omits the description of well-known functions and structures.

[0040] In recent years, with the development of single-crystal solar cells, especially the successful industrialization of passivated emitter and back surface field (PERC) technology, the efficiency of mass-produced cells on P-type silicon wafers has reached a bottleneck. More attention is paid to N-type cells with higher bulk minority carrier lifetime and smaller attenuation. Three kinds of cell structures, such as N-type PERT, heterojunction (HJT) and tunnel oxide passivated contact (TOPCon), have gradually attracted attention in the industry. Among them, the TOPCon cell, also known as the passivated contact cell, has a structure of preparing an ultra-thin silicon oxide layer and a highly doped polysilicon layer on the surface of silicon. The selective permeability of the ultra-thin silicon oxide to carriers and the good field passivation effect of the highly doped polysilicon and the substrate effectively suppresses the recombination of silicon surface minority carriers and improves the open voltage of the cell.

[0041] However, the existing passivated contact cells usually sequentially deposit the oxide layer and the doped polysilicon layer by whole layer deposition. In the process of mass production of solar cells, due to the influence of edge airflow, the phenomenon of uneven heating occurs, which causes the thickness of the oxide layer and the doped polysilicon layer at the edge to be thinner, affecting the passivation uniformity of the whole cell, and thus affecting the conversion efficiency of the cell. For this, the current solutions are to improve the structure of the production equipment or adjust the process parameters of the deposition method to obtain more uniform film layers. This not only has high optimization cost, but also has complex process and poor effect. Therefore, the embodiments of the present disclosure solve this problem by improving the structure of the solar cell.

[0042] In one embodiment of the present disclosure, the embodiment provides a solar cell, comprising: a silicon substrate 1; an emitter 2 and a first passivation and anti-reflection structure 3 arranged from inside to outside on one side of the silicon substrate 1 in the thickness direction, wherein the first passivation and anti-reflection structure 3 comprises a first passivation and anti-reflection layer 31 and a second passivation and anti-reflection layer 32, and the second passivation and anti-reflection layer 32 is arranged in the edge region of the silicon substrate 1; a tunnel oxide layer 5, a doped polysilicon layer 6 and a second passivation and anti-reflection structure 7 arranged from inside to outside on the other side of the silicon substrate 1 in the thickness direction, wherein the second passivation and anti-reflection structure 7 comprises a third passivation and anti-reflection layer 71 and a fourth passivation and anti-reflection layer 72, and the fourth passivation and anti-reflection layer 72 is arranged in the edge region of the silicon substrate 1.

[0043] The solar cell and the preparation method thereof provided by the embodiments of the present disclosure can effectively increase the thickness of the passivation and anti-reflection layer at the edge of the silicon substrate 1, improve the passivation performance at the edge of the solar cell, and thus increase the overall photoelectric conversion efficiency of the solar cell, by arranging the first passivation and anti-reflection structure 3 comprising the first passivation and anti-reflection layer 31 and the second passivation and anti-reflection layer 32, and the second passivation and anti-reflection structure 7 comprising the third passivation and anti-reflection layer 71 and the fourth passivation and anti-reflection layer 72.

[0044] The first passivation anti-reflection layer 31 and the third passivation anti-reflection layer 71 can be understood as front passivation anti-reflection layers and back passivation anti-reflection layers of a conventional structure in the prior art, which are deposited on the outer side of the emitter 2 on the front side of the silicon substrate 1 and the outer side of the doped polysilicon layer 6 on the back side, respectively, and cover the outer side of the emitter 2 and the outer side of the doped polysilicon layer 6. The second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are only arranged on the edge region of the silicon substrate 1. It can be understood that if the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are also arranged to be deposited in a whole layer, although the thickness of the edge region of the silicon substrate 1 can be increased, the light absorption of the middle part of the silicon substrate 1 will be affected. Therefore, in order to solve the uneven thickness of the edge oxidation layer, the passivation anti-reflection layer is additionally arranged on the edge region to increase the thickness of the passivation anti-reflection layer on the edge region. In an optional embodiment, the first passivation anti-reflection layer 31 is formed synchronously with the fourth passivation anti-reflection layer 72, and the second passivation anti-reflection layer 32 is formed synchronously with the third passivation anti-reflection layer 71. It should be noted that the present embodiment does not increase an additional preparation process, but forms the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 synchronously on the basis of the preparation of the first passivation anti-reflection layer 31 and the third passivation anti-reflection layer 71, without increasing an additional process, and increases an additional technical effect on the basis of the existing process.

[0045] Specifically, the present embodiment realizes the synchronous preparation process of the passivation anti-reflection layers on different sides by controlling the fitting distance between the silicon substrate 1 and the carrier. The carrier can be understood as a carrier or container that loads the silicon substrate 1 and deposits the passivation anti-reflection layer, and is usually a graphite boat carrier. In an optional embodiment, the fourth passivation anti-reflection layer 72 is formed by controlling the fitting distance between the silicon substrate 1 and the carrier when the first passivation anti-reflection layer 31 is prepared; and the second passivation anti-reflection layer 32 is formed by controlling the fitting distance between the silicon substrate 1 and the carrier when the third passivation anti-reflection layer 71 is prepared. It can be understood that since the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are formed by around plating, they can be formed by around plating on multiple edge regions around the silicon substrate 1. For example, for a rectangular silicon wafer, the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 can be formed by around plating on the four edges of the rectangular silicon wafer, or only on two edges parallel to the metal electrode or two edges perpendicular to the metal electrode according to actual needs, and the present disclosure does not make specific limitations thereon, and the actual situation can be set according to the actual situation.

[0046] Exemplarily, the positional relationship between the silicon substrate 1 and the graphite boat carrier is described with reference to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram of the overall structure of the graphite boat carrier, and FIG. 2 is a front view of the graphite boat carrier with the silicon substrate 1 inserted. As shown in FIG. 1, the graphite boat carrier 100 includes multiple partitions, and a loading space for accommodating the silicon substrate 1 is formed between every two partitions longitudinally (as indicated by the arrow in FIG. 1), that is, the silicon substrate 1 is inserted longitudinally into the graphite boat carrier 100 for deposition during preparation. As shown in FIG. 1 and FIG. 2, multiple graphite boat clamping points a are arranged on the graphite boat carrier 100, which are used to clamp the fulcrum of the silicon substrate 1. By controlling the left and right and up and down positions of the multiple graphite boat clamping points, on the one hand, the silicon substrate 1 can be clamped firmly inside the graphite boat carrier 100 and cannot be displaced, and on the other hand, the specific placement position of the silicon substrate 1 in the graphite boat carrier 100 and the fitting distance of the silicon substrate 1 and the graphite boat carrier 100 can be controlled, and the fitting distance of the silicon substrate 1 and the graphite boat carrier 100 can determine whether the passivation and anti-reflection layer is formed during deposition. It can be understood that within a certain range, the greater the fitting distance of the silicon substrate 1 and the graphite boat carrier 100 (that is, the greater the gap interval), the greater the width of the passivation and anti-reflection layer formed by passivation, and the smaller the fitting distance of the silicon substrate 1 and the graphite boat carrier 100 (that is, the smaller the gap interval), the smaller the width of the passivation and anti-reflection layer formed by passivation. However, the width of the passivation and anti-reflection layer formed by passivation itself has certain limitations, and it is impossible for the second passivation and anti-reflection layer 32 and the fourth passivation and anti-reflection layer 72 to cover the entire first passivation and anti-reflection layer 31 and the third passivation and anti-reflection layer outside, so the embodiment of the present disclosure can effectively control the width of the second passivation and anti-reflection layer 32 and the fourth passivation and anti-reflection layer 72 formed by passivation by controlling the fitting distance of the silicon substrate 1 and the graphite boat carrier 100, thereby controlling the quality of the final solar cell.

[0047] In an alternative embodiment, the width of the second passivation anti-reflective layer 32 and the fourth passivation anti-reflective layer 72 should not be too large or too small. Specifically, the width of the second passivation anti-reflective layer 32 is 0.5mm-10mm, for example, 0.5mm, 1mm, 2.5mm, 3.5mm, 5mm, 6.5mm, 8mm, 9mm, 10mm, etc.; without changing the positional relationship between the silicon substrate 1 and the graphite boat carrier 100, the width of the fourth passivation anti-reflective layer 72 can also be set to 0.5mm-10mm, for example, 0.5mm, 1mm, 2.5mm, 3.5mm, 5mm, 6.5mm, 8mm, 9mm, 10mm, etc. It can be understood that if the width of the second passivation anti-reflective layer 32 and the fourth passivation anti-reflective layer 72 is set too large, the light absorption of the middle part of the silicon substrate 1 will be lost, affecting the light conversion efficiency of the solar cell, and if the width of the second passivation anti-reflective layer 32 and the fourth passivation anti-reflective layer 72 is set too small, the problem of thin oxide layer thickness cannot be effectively improved, therefore, the second passivation anti-reflective layer 32 and the fourth passivation anti-reflective layer 72 are set to 0.5mm-10mm in the embodiment of the present disclosure, which can achieve the technical effects to be achieved by the present disclosure, and will not affect the performance of the solar cell.

[0048] In the embodiment of the present disclosure, when the passivation anti-reflective layer is prepared in different sequences, different solar cell structures will be formed, therefore, the solar cell structures obtained by preferentially preparing the front passivation anti-reflective layer and the solar cell structures obtained by preferentially preparing the back passivation anti-reflective layer are described separately, which can be shown in FIG. 3 and FIG. 4. Specifically, FIG. 3 shows the solar cell structure obtained by preferentially preparing the front passivation anti-reflective layer, and FIG. 4 shows the solar cell structure obtained by preferentially preparing the back passivation anti-reflective layer.

[0049] As shown in FIG. 3, the second passivation anti-reflective layer 32 is arranged outside the first passivation anti-reflective layer 31, and the fourth passivation anti-reflective layer 72 is arranged between the doped polysilicon layer 6 and the third passivation anti-reflective layer 71. It can be understood that since the first passivation anti-reflective layer 31 and the fourth passivation anti-reflective layer 72 are formed synchronously, when the first passivation anti-reflective layer 31 on the front side of the silicon substrate 1 is preferentially prepared, the fourth passivation anti-reflective layer 72 will be formed synchronously at both ends of the edge on the back side of the silicon substrate 1, so that when the third passivation anti-reflective layer 71 is prepared outside the fourth passivation anti-reflective layer on the back side of the silicon substrate 1, the second passivation anti-reflective layer 32 formed synchronously will be outside the first passivation anti-reflective layer 31.

[0050] As shown in FIG. 4, the second passivation anti-reflection layer 32 is disposed between the first passivation anti-reflection layer 31 and the emitter 2, and the fourth passivation anti-reflection layer 72 is disposed outside the third passivation anti-reflection layer 71. As in the above process, when the passivation anti-reflection layer on the back side of the silicon substrate 1 is prepared first, the third passivation anti-reflection layer 71 is located between the fourth passivation anti-reflection layer 72 and the doped polysilicon layer 6, and when the fourth passivation anti-reflection layer 72 is prepared first, the front side is also formed with the second passivation anti-reflection layer 32 first, and then the first passivation anti-reflection layer 31 is formed outside the second passivation anti-reflection layer 32.

[0051] As can be seen from the above FIG. 3 and FIG. 4, the solar cell with different structures can be obtained by the two different preparation sequences provided in the embodiments of the present disclosure, and the purpose of increasing the thickness of the passivation anti-reflection layer on the edge of the silicon substrate can be achieved, the passivation performance of the edge of the solar cell is improved, and thus the overall photoelectric conversion efficiency of the solar cell is increased.

[0052] For the material of the passivation anti-reflection layer, since the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 are formed at the same time, and the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 are formed at the same time, the material of the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 is the same, and the material of the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 is the same. In an optional embodiment, the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride; and the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride. It should be noted that the passivation anti-reflection layer actually includes a passivation layer and an anti-reflection layer, and is usually a multi-layer structure arranged in layers, so the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 in the embodiments of the present disclosure are actually formed by combination of at least two of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0053] It can be understood that when the materials of the first passivation anti-reflection layer 31, the second passivation anti-reflection layer 32, the third passivation anti-reflection layer 71, and the fourth passivation anti-reflection layer 72 are the same, the structures of FIG. 3 and FIG. 4 provided in the embodiments of the present disclosure are substantially the same, and when the materials of the first passivation anti-reflection layer 31 and the second passivation anti-reflection layer 32 are different, the structures of FIG. 3 and FIG. 4 provided in the embodiments of the present disclosure are different as described above.

[0054] For the thickness of the deposited layers, in general, the thickness of the first and fourth passivation anti-reflection layers 31 and 72 deposited synchronously is the same, and the thickness of the second and third passivation anti-reflection layers 32 and 71 deposited synchronously is the same. In an alternative embodiment, the thickness of the first and / or fourth passivation anti-reflection layers 31 and 72 is 20-180 nm, for example, 20 nm, 30 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 160 nm, 180 nm, etc. Meanwhile, the thickness of the second and / or third passivation anti-reflection layers 32 and 71 is 25-200 nm, for example, 25 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0055] For the thickness of the tunneling oxide layer 5, in an alternative embodiment, it can be 0.5-5 nm, for example, 0.5 nm, 0.8 nm, 1.2 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc. For the thickness of the doped polysilicon layer 6, in an alternative embodiment, it can be 30-200 nm, for example, 30 nm, 80 nm, 150 nm, 200 nm, etc. In order to ensure the photoelectric conversion performance of the solar cell, the concentration of the doping elements in the doped polysilicon layer 6 needs to be 1E20-1E21 atom / cm 3 , where E can be understood as the value 10, 1E20 = 1*10 20 , and the concentration of the doping elements in the emitter 2 needs to be 1E18-1E19 atom / cm 3 .

[0056] In addition, in an alternative embodiment, a first metal electrode 4 is arranged on one side of the thickness direction of the silicon substrate 1, and a second metal electrode 8 is arranged on the other side of the thickness direction of the silicon substrate 1, wherein the first metal electrode 4 is electrically connected to the emitter 2 through the first passivation anti-reflection layer 31, and the second metal electrode 8 is electrically connected to the doped polysilicon layer 6 through the third passivation anti-reflection layer 71.

[0057] As can be seen from the above, the solar cell provided by the embodiments of the present disclosure can effectively increase the thickness of the passivation anti-reflection layer at the edge of the silicon substrate, improve the passivation performance at the edge of the solar cell, and thus increase the overall photoelectric conversion efficiency of the solar cell, by arranging the first passivation anti-reflection structure including the first and second passivation anti-reflection layers, and the second passivation anti-reflection structure including the third and fourth passivation anti-reflection layers.

[0058] FIG. 5 shows a flowchart of a method for preparing a solar cell according to an embodiment of the present disclosure. As shown in FIG. 5, the method for preparing a solar cell according to the present disclosure comprises the following steps:

[0059] In step S501, an emitter 2 is prepared on one side of the silicon substrate 1 in the thickness direction of the silicon substrate 1.

[0060] In step S502, a tunneling oxide layer 5 and a doped polysilicon layer 6 are prepared successively from inside to outside on the other side of the silicon substrate 1 in the thickness direction of the silicon substrate 1.

[0061] In step S503, a first passivation anti-reflection structure 3 and a second passivation anti-reflection structure 7 are prepared on the outside of the emitter 2 and the outside of the doped polysilicon layer 6, respectively. The first passivation anti-reflection structure 3 comprises a first passivation anti-reflection layer 31 and a second passivation anti-reflection layer 32, and the second passivation anti-reflection layer 32 is arranged at the edge region of the silicon substrate 1. The second passivation anti-reflection structure 5 comprises a third passivation anti-reflection layer 71 and a fourth passivation anti-reflection layer 72, and the fourth passivation anti-reflection layer 72 is arranged at the edge region of the silicon substrate 1.

[0062] The silicon substrate structure prepared in step S501 is shown in FIG. 6, and the silicon substrate structure prepared in step S502 is shown in FIG. 7. As can be seen from FIGS. 6 and 7, after steps S501 and S502, P+ emitters and passivation contact structures (tunneling oxide layer and doped polysilicon layer) are formed on both sides of the silicon substrate 1 in the thickness direction. Whether the passivation anti-reflection layer on the front side is prepared first or the passivation anti-reflection layer on the back side is prepared first, steps S501 and S502 are the same before the passivation anti-reflection layer is prepared.

[0063] In an alternative embodiment, when the passivation anti-reflection layer on the front side of the silicon substrate 1 is prepared first, step S503 can be as shown in FIG. 8, comprising:

[0064] In step S801, the first passivation anti-reflection layer 31 is prepared on the outside of the emitter 2, and at the same time, the fourth passivation anti-reflection layer 72 is formed on the outside of the doped polysilicon layer 6.

[0065] In step S802, the third passivation anti-reflection layer 71 is prepared on the outside of the fourth passivation anti-reflection layer 72 and the outside of the doped polysilicon layer 6, and at the same time, the second passivation anti-reflection layer 32 is formed on the outside of the first passivation anti-reflection layer 31.

[0066] The above process shown in Fig. 8 is specifically explained below by means of Fig. 9 and Fig. 10, wherein Fig. 9 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S801; and Fig. 10 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S802. As can be seen from Fig. 9 and Fig. 10, after step S801, a whole layer of the first passivation anti-reflection layer 31 is deposited on the front side of the silicon substrate 1, and meanwhile, the fourth passivation anti-reflection layer 72 is formed on the back side of the silicon substrate 1 by wrap plating, which is arranged at both ends in the width direction of the silicon substrate 1. Then, after step S802, the third passivation anti-reflection layer 71 is prepared on the back side of the silicon substrate 1 on the basis of the fourth passivation anti-reflection layer 72, and the second passivation anti-reflection layer 32 is formed on the outside of the first passivation anti-reflection layer 31 by wrap plating. Herein, W1 represents the width of the second passivation anti-reflection layer 32, and W2 represents the width of the fourth passivation anti-reflection layer 72.

[0067] In another alternative embodiment, when the passivation anti-reflection layer on the back side of the silicon substrate 1 is prepared first, step S503 can be as shown in Fig. 11, which comprises:

[0068] Step S1101, the third passivation anti-reflection layer 71 is prepared on the outside of the doped polysilicon layer 6, and meanwhile, the second passivation anti-reflection layer 32 is formed on the outside of the emitter 2;

[0069] Step S1102, the first passivation anti-reflection layer 31 is prepared on the outside of the second passivation anti-reflection layer 32 and the outside of the emitter 2, and meanwhile, the fourth passivation anti-reflection layer 72 is formed on the outside of the third passivation anti-reflection layer 71.

[0070] The above process shown in Fig. 11 is specifically explained below by means of Fig. 12 and Fig. 13, wherein Fig. 12 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S1101; and Fig. 13 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S1102. As can be seen from Fig. 12 and Fig. 13, after step S1101, a whole layer of the third passivation anti-reflection layer 71 is deposited on the back side of the silicon substrate 1, and meanwhile, the second passivation anti-reflection layer 32 is formed on the front side of the silicon substrate 1 by wrap plating, which is arranged at both ends in the width direction of the silicon substrate 1. Then, after step S1102, the first passivation anti-reflection layer 31 is prepared on the front side of the silicon substrate 1 on the basis of the second passivation anti-reflection layer 32, and the fourth passivation anti-reflection layer 72 is formed on the outside of the third passivation anti-reflection layer 71 by wrap plating. Herein, W1 represents the width of the second passivation anti-reflection layer 32, and W2 represents the width of the fourth passivation anti-reflection layer 72.

[0071] In an alternative embodiment, in order to precisely control the width of the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 formed by plating, the present embodiment sets the fitting distance between the silicon substrate 1 and the carrier to 80-400 μm, for example, 80 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, etc., so as to prepare the first passivation anti-reflection structure 3 and the second passivation anti-reflection structure 7, so that the width of the second passivation anti-reflection layer 32 and / or the fourth passivation anti-reflection layer 72 prepared is 0.5-10 mm.

[0072] In an alternative embodiment, after step S503, further comprising: preparing the first metal electrode 4 and the second metal electrode 8 on the two sides of the silicon substrate 1 in the thickness direction, respectively. The silicon substrate structure obtained after preparing the metal electrode is the solar cell structure shown in FIGS. 3 and 4.

[0073] In summary, the preparation method of the solar cell provided by the present embodiment can effectively increase the thickness of the passivation anti-reflection layer at the edge of the silicon substrate, improve the passivation performance of the edge of the solar cell, and thus increase the overall photoelectric conversion efficiency of the solar cell.

[0074] Embodiment One

[0075] S1. Alkaline texturing is performed on the n-type silicon substrate (the alkaline solution is a sodium hydroxide solution with a volume concentration of 1%, and the texturing temperature is 80°C, and the soaking time is 400 s), so as to form a textured structure on the two sides of the silicon substrate in the thickness direction;

[0076] S2. The n-type silicon substrate with the textured structure is placed in a high-temperature diffusion furnace (the reaction of a boron-containing compound such as boron trichloride and boron tribromide and oxygen, temperature 1000°C, reaction time 3 h) to perform a diffusion / oxidation process of boron-doped elements, so as to form a p+ emitter on the front surface of the n-type silicon substrate; wherein the doping concentration of boron elements in the p+ emitter is 5E18 atoms / cm3;

[0077] S3. A hydrofluoric acid solution with a volume concentration of 30% is used to remove the silicon glass layer formed by plating on the back surface and the side surface of the n-type silicon substrate;

[0078] S4. Alkaline polishing treatment is performed on the front surface of the n-type silicon substrate (the alkaline solution is a sodium hydroxide solution with a volume concentration of 2%, the reaction temperature is 60°C, and the soaking time is 200 s);

[0079] S5. A tunneling oxide layer and an n+ doped polysilicon layer are prepared on the back surface of the n-type silicon substrate in sequence; the tunneling oxide layer is a silicon oxide layer deposited by LPCVD, the reaction temperature is 600°C, the deposition time is 15 min, and the thickness is 2 nm; the doping concentration of the n+ doped polysilicon layer is 4.5E20 atoms / cm3;

[0080] S6. The boron+ phosphor silicon glass layer, the front surface non-padded area, and the side surface padded phosphor silicon glass layer of the n-type silicon substrate are removed by using 10% hydrogen fluoride acid;

[0081] S7. The n-type silicon substrate is subjected to cleaning treatment (RCA cleaning technology is adopted);

[0082] S8. A first passivation anti-reflection layer is deposited on one side of the front surface of the silicon substrate by ALD (atomic layer deposition) method at 320°C and by PECVD at 550°C, 255 Pa pressure, and 10000 W radio frequency power, and a fourth passivation anti-reflection layer is simultaneously formed by padding on one side of the back surface of the silicon substrate, wherein the first passivation anti-reflection layer and the fourth passivation anti-reflection layer are both composite film layers of aluminum oxide (passivation layer) and silicon oxynitride (anti-reflection layer), the overall thickness is 95 nm, and the width of the fourth passivation anti-reflection layer is 8 mm;

[0083] S9. A third passivation anti-reflection layer is deposited on one side of the back surface of the silicon substrate by PECVD at 550°C, 255 Pa pressure, and 10000 W radio frequency power, and a second passivation anti-reflection layer is simultaneously formed by padding on one side of the front surface of the silicon substrate, wherein the second passivation anti-reflection layer and the third passivation anti-reflection layer are both silicon oxynitride layers, the overall thickness is 100 nm, and the width of the second passivation anti-reflection layer is 8 mm;

[0084] S10. A first metal electrode and a second metal electrode are respectively prepared on the front surface and the back surface of the silicon substrate by screen printing, wherein the first metal electrode is electrically connected with the p+ emitter through the first passivation anti-reflection layer, and the second metal electrode is electrically connected with the n+ doped polysilicon layer through the third passivation anti-reflection layer.

[0085] Example Two

[0086] S1. The n-type silicon substrate is subjected to alkali texturing (the alkali solution is 1% sodium hydroxide solution by volume concentration, the texturing temperature is 80°C, and the soaking time is 400 s), and a textured structure is formed on the surfaces of both sides of the silicon substrate in the thickness direction;

[0087] S2. The n-type silicon wafer forming a suede structure is placed in a high-temperature diffusion furnace (reactants: boron-containing compounds such as boron trichloride, boron tribromide, and oxygen mixed reaction, temperature 1000℃, reaction time 3h) to perform a diffusion / oxidation process of boron-doped elements to form a p+ emitter on the front surface of the n-type silicon substrate; wherein the doping concentration of boron elements in the p+ emitter is 5E18 atoms / cm3;

[0088] S3. The silicon glass layer formed on the back surface and the side surface of the n-type silicon substrate is removed by using a hydrofluoric acid solution with a volume concentration of 30%;

[0089] S4. The front surface of the n-type silicon substrate is subjected to alkali polishing treatment (alkali solution: sodium hydroxide solution with a volume concentration of 2%, reaction temperature: 60℃, soaking time: 200s);

[0090] S5. A tunneling oxide layer and an n+ doped polysilicon layer are sequentially prepared on the back surface of the n-type silicon substrate; wherein the tunneling oxide layer is a silicon oxide layer obtained by LPCVD deposition, the reaction temperature is 600℃, the deposition time is 15min, and the thickness is 2nm; the doping concentration of the n+ doped polysilicon layer is 4.5E20 atoms / cm3;

[0091] S6. The boron+phosphorus silicon glass layer formed on the front surface of the n-type silicon substrate, the front surface area not formed by wrapping, and the phosphorus silicon glass layer formed on the side surface of the n-type silicon substrate are removed by using a hydrofluoric acid solution with a volume concentration of 10%;

[0092] S7. The n-type silicon substrate is subjected to cleaning treatment (RCA cleaning technology is adopted);

[0093] S8. A third passivation and anti-reflection layer is deposited on one side of the back surface of the silicon substrate by ALD (atomic layer deposition) method at 320℃, and a second passivation and anti-reflection layer is simultaneously formed on one side of the front surface of the silicon substrate by wrapping, under the conditions of 550℃, pressure 255Pa, and radio frequency power 10000W; wherein the third passivation and anti-reflection layer and the second passivation and anti-reflection layer are both composite film layers of aluminum oxide (passivation layer) and silicon oxynitride (anti-reflection layer), the overall thickness is 95nm, and the width of the second passivation and anti-reflection layer is 8mm;

[0094] S9. A first passivation and anti-reflection layer is deposited on one side of the front surface of the silicon substrate by PECVD under the conditions of 550℃, pressure 255Pa, and radio frequency power 10000W, and a fourth passivation and anti-reflection layer is simultaneously formed on one side of the back surface of the silicon substrate by wrapping; wherein the first passivation and anti-reflection layer and the fourth passivation and anti-reflection layer are both silicon oxynitride layers, the overall thickness is 100nm, and the width of the fourth passivation and anti-reflection layer is 8mm;

[0095] S10. First and second metal electrodes are prepared on the front and back surfaces of the silicon substrate by screen printing, wherein the first metal electrode is electrically connected to the p+ emitter through the first passivation anti-reflection layer, and the second metal electrode is electrically connected to the n+ doped polysilicon layer through the third passivation anti-reflection layer.

[0096] Comparative Example 1

[0097] S1. The n-type silicon substrate is alkali-textured (the alkali solution is a 1% by volume sodium hydroxide solution, the texturing temperature is 80°C, and the immersion time is 400s), and a textured structure is formed on both sides of the silicon substrate in the thickness direction;

[0098] S2. The n-type silicon wafer with the textured structure is placed in a high-temperature diffusion furnace (a mixture of a boron-containing compound such as boron trichloride and boron tribromide and oxygen is reacted, the temperature is 1000°C, and the reaction time is 3h) to perform a diffusion / oxidation process of boron-doped elements, so as to form a p+ emitter on the front surface of the n-type silicon substrate; wherein the doping concentration of boron elements in the p+ emitter is 5E18 atoms / cm3;

[0099] S3. The silicon glass layer formed by the back surface and side surface of the n-type silicon substrate is removed by using a 30% by volume hydrofluoric acid solution;

[0100] S4. The front surface of the n-type silicon substrate is subjected to alkali polishing treatment (the alkali solution is a 2% by volume sodium hydroxide solution, the reaction temperature is 60°C, and the immersion time is 200s);

[0101] S5. A tunneling oxide layer and an n+ doped polysilicon layer are prepared on the back surface of the n-type silicon substrate in sequence; wherein the tunneling oxide layer is a silicon oxide layer obtained by LPCVD deposition, the reaction temperature is 600°C, the deposition time is 15min, and the thickness is 2nm; the doping concentration of the n+ doped polysilicon layer is 4.5E20 atoms / cm3;

[0102] S6. The boron+ phosphorus silicon glass layer on the front surface of the n-type silicon substrate, the front surface area not plated, and the phosphorus silicon glass layer plated on the side surface are removed by using a 10% by volume hydrofluoric acid;

[0103] S7. The n-type silicon substrate is subjected to cleaning treatment (RCA cleaning technology is used);

[0104] S8. A first passivation anti-reflection layer is deposited on one side of the front surface of the silicon substrate by ALD (atomic layer deposition) method at 320°C, and a third passivation anti-reflection layer is deposited on one side of the back surface of the silicon substrate by PECVD at 550°C, 255Pa pressure, and 10000W radio frequency power, and the overall thickness is 100nm;

[0105] S9. First and second metal electrodes are prepared on the front and back surfaces of the silicon substrate by screen printing, wherein the first metal electrode is electrically connected with the p+ emitter through the first passivation anti-reflection layer, and the second metal electrode is electrically connected with the n+ doped polysilicon layer through the third passivation anti-reflection layer.

[0106] The solar cells prepared in the above examples and comparative examples are tested for performance, and the performance comparison results are shown in the following table:

[0107] Table 1

[0108] As shown in Table 1, the open-circuit voltage (Voc) of the solar cells prepared in Example 1 and Example 2 is about 1 mV greater than that of Comparative Example 1, the fill factor (FF) of the solar cells prepared in Example 1 and Example 2 is about 0.1% greater than that of Comparative Example 1, the cell conversion efficiency (Eta) of the solar cells prepared in Example 1 and Example 2 is about 0.06% greater than that of Comparative Example 1, and the proportion of solar cell sheet black edge defects of the solar cells prepared in Example 1 and Example 2 is about 1% less than that of Comparative Example 1.

[0109] Meanwhile, the solar cells prepared in Example 1 and Comparative Example 1 are respectively subjected to PL (photoluminescence) detection, and the PL results are shown in FIG. 14 and FIG. 15. FIG. 14 is the PL result of the solar cell prepared in Example 1, and FIG. 15 is the PL result of the solar cell prepared in Comparative Example 1. As shown in FIG. 14 and FIG. 15, the area of black edge defects of the solar cell prepared in Example 1 is obviously reduced.

[0110] As shown in the above performance comparison results, by setting the first passivation anti-reflection structure including the first and second passivation anti-reflection layers, and the second passivation anti-reflection structure including the third and fourth passivation anti-reflection layers, the thickness of the passivation anti-reflection layer at the edge of the silicon substrate can be effectively increased, the passivation performance of the edge of the solar cell can be improved, and thus the overall photoelectric conversion efficiency of the solar cell can be increased.

[0111] The above steps are provided only to help understand the structure, method and core idea of the present disclosure. For ordinary skilled in the technical field, some improvements and modifications can be made to the present disclosure without departing from the principles of the present disclosure, and these improvements and modifications also belong to the scope of protection of the present disclosure.

Claims

1. A solar cell, comprising: a silicon substrate (1) ; an emitter (2) and a first passivation anti-reflection structure (3) disposed from inside to outside on one side of the silicon substrate (1) in a thickness direction of the silicon substrate (1), wherein the first passivation anti-reflection structure (3) comprises a first passivation anti-reflection layer (31) and a second passivation anti-reflection layer (32), and the second passivation anti-reflection layer (32) is disposed in an edge region of the silicon substrate (1) ; a tunnel oxide layer (5), a doped polysilicon layer (6) and a second passivation anti-reflection structure (7) disposed from inside to outside on the other side of the silicon substrate (1) in the thickness direction of the silicon substrate (1), wherein the second passivation anti-reflection structure (7) comprises a third passivation anti-reflection layer (71) and a fourth passivation anti-reflection layer (72), and the fourth passivation anti-reflection layer (72) is disposed in the edge region of the silicon substrate (1). 2.The solar cell of claim 1, wherein: the first passivation anti-reflection layer (31) and the fourth passivation anti-reflection layer (72) are formed synchronously, and the second passivation anti-reflection layer (32) and the third passivation anti-reflection layer (71) are formed synchronously. 3.The solar cell of claim 2, wherein: the fourth passivation anti-reflection layer (72) is formed by around-plating when the first passivation anti-reflection layer (31) is prepared by controlling a fitting distance between the silicon substrate (1) and a carrier; and the second passivation anti-reflection layer (32) is formed by around-plating when the third passivation anti-reflection layer (71) is prepared by controlling the fitting distance between the silicon substrate (1) and the carrier. 4.The solar cell of any one of claims 1 to 3, wherein: the second passivation anti-reflection layer (32) is disposed outside the first passivation anti-reflection layer (31) ; and the fourth passivation anti-reflection layer (72) is disposed between the doped polysilicon layer (6) and the third passivation anti-reflection layer (71). 5.The solar cell of any one of claims 1 to 3, wherein: the second passivation anti-reflection layer (32) is disposed between the first passivation anti-reflection layer (31) and the emitter (2) ; and the fourth passivation anti-reflection layer (72) is disposed outside the third passivation anti-reflection layer (71). 6.The solar cell of claim 1, wherein: a width of the second passivation anti-reflection layer (32) is 0.5mm to 10mm; and / or a width of the fourth passivation anti-reflection layer (72) is 0.5mm to 10mm. 7.The solar cell of claim 1, wherein: the first passivation anti-reflection layer (31) and / or the fourth passivation anti-reflection layer (72) comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride; and / or the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride. 8.The solar cell of claim 1, wherein: a thickness of the first passivation anti-reflection layer (31) and / or the fourth passivation anti-reflection layer (72) is 20nm to 180nm; and / or a thickness of the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) is 20nm to 180nm. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The thickness of the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) is 25nm-200nm; and / or, The thickness of the tunneling oxide layer (5) is 0.5nm-5nm; and / or, The thickness of the doped polysilicon layer (6) is 30nm-200nm.

9. A method for preparing the solar cell of any one of claims 1-8, comprising: Step 1: preparing an emitter (2) on one side of the silicon substrate (1) in the thickness direction; Step 2: preparing a tunneling oxide layer (5) and a doped polysilicon layer (6) from inside to outside on the other side of the silicon substrate (1) in the thickness direction; Step 3: preparing a first passivation anti-reflection structure (3) and a second passivation anti-reflection structure (7) on the outside of the emitter (2) and the doped polysilicon layer (6), respectively; wherein the first passivation anti-reflection structure (3) comprises a first passivation anti-reflection layer (31) and a second passivation anti-reflection layer (32), and the second passivation anti-reflection layer (32) is arranged at the edge region of the silicon substrate (1); the second passivation anti-reflection structure (5) comprises a third passivation anti-reflection layer (71) and a fourth passivation anti-reflection layer (72), and the fourth passivation anti-reflection layer (72) is arranged at the edge region of the silicon substrate (1).

10. The production method according to claim 9, wherein The step 3 comprises: forming the fourth passivation anti-reflection layer (72) on the outside of the doped polysilicon layer (6) while preparing the first passivation anti-reflection layer (31) on the outside of the emitter (2); forming the second passivation anti-reflection layer (32) on the outside of the first passivation anti-reflection layer (31) while preparing the third passivation anti-reflection layer (71) on the outside of the fourth passivation anti-reflection layer (72) and the doped polysilicon layer (6); Alternatively, the step 3 comprises: forming the second passivation anti-reflection layer (32) on the outside of the emitter (2) while preparing the third passivation anti-reflection layer (71) on the outside of the doped polysilicon layer (6); forming the fourth passivation anti-reflection layer (72) on the outside of the third passivation anti-reflection layer (71) while preparing the first passivation anti-reflection layer (31) on the outside of the second passivation anti-reflection layer (32) and the emitter (2); and / or, the step 3 further comprises: setting the fitting distance of the silicon substrate (1) and the carrier to 80μm-400μm to prepare the first passivation anti-reflection structure (3) and the second passivation anti-reflection structure (7).

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