Chip, memory, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a chip, a memory, and an electronic device. Making ΔG1 be greater than or equal to ΔG2 can prevent a gate from further capturing oxygen from at least part of the material of a channel layer, thereby ameliorating the problem of drift in the characteristics of a transistor and improving the stability of the transistor. The chip comprises a substrate and a transistor disposed on the substrate, wherein the transistor comprises a channel layer, a gate insulating layer and a gate, which are stacked in sequence. The material of the gate comprises a metal element, and the Gibbs free energy of the oxidization of the metal element is ΔG1; the material of the channel layer comprises an oxide semiconductor, an element capable of undergoing an oxidation reaction in the oxide semiconductor is a first element, and the minimum value of the oxidization Gibbs free energy of the first element is ΔG2; and ΔG1 and ΔG2 are both less than 0, and ΔG1≥ΔG2.

Description

Chips, memory, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202410813923.2, filed on June 21, 2024, entitled "Chip, Memory, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a chip, memory, and electronic device. Background Technology

[0003] Oxide semiconductor thin film transistors (OS TFTs) are widely used due to their low fabrication temperature, low leakage current, and low manufacturing cost.

[0004] However, the impact of the gate on the thermal stability of OS TFTs has been overlooked. An OS TFT consists of a gate, gate insulating layer, channel layer, source, and drain. During chip fabrication, the gate readily abstracts oxygen from the channel layer, causing drift in OS TFT characteristics. Furthermore, oxygen abstraction is more likely to occur at high temperatures, potentially leading to insufficient thermal budget during transistor fabrication and affecting the stability of the OS TFT. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a chip, memory, and electronic device that, by ensuring that ΔG1 ≥ ΔG2, prevents the gate from stripping oxygen from at least a portion of the channel layer material, thereby improving the transistor characteristic drift problem and enhancing transistor stability.

[0006] In a first aspect, this application provides a chip including a substrate and a transistor disposed on the substrate. The transistor includes a channel layer, a gate insulating layer, and a gate layer sequentially stacked. The gate layer is made of a metal element, and the metal element has an oxidation Gibbs free energy of ΔG1. The channel layer is made of an oxide semiconductor, and the element in the oxide semiconductor capable of undergoing an oxidation reaction is designated as a first element, and the minimum oxidation Gibbs free energy of the first element is ΔG2. Both ΔG1 and ΔG2 are less than 0, and ΔG1 ≥ ΔG2.

[0007] Those skilled in the art should know that stable elements can undergo oxidation reactions with oxygen. When a stable element is oxidized to a compound with a specified oxidation number, a Gibbs free energy change occurs. Furthermore, the smaller the Gibbs free energy caused by the oxidation reaction, the easier it is to be oxidized. In the embodiments of this application, when ΔG1 = ΔG2, the oxidation ability of the gate material is comparable to that of at least a portion of the channel layer material, and the gate no longer abstracts oxygen from at least a portion of the channel layer material. When ΔG1 > ΔG2, at least a portion of the channel layer material is more easily oxidized than the gate, increasing the oxygen abstraction ability of at least a portion of the channel layer material, making the oxygen abstraction ability of at least a portion of the channel layer material greater than that of the gate material, and the gate no longer abstracts oxygen from at least a portion of the channel layer material. Thus, by making ΔG1 ≥ ΔG2, the problem of the gate abstracting oxygen from the channel layer through the gate insulating layer can be improved, thereby improving the transistor characteristic drift problem. Furthermore, since the gate material is more difficult to oxidize than at least some of the material in the channel layer, or the gate material has an oxidation capacity comparable to at least some of the material in the channel layer, even at high temperatures, the gate no longer removes oxygen from at least some of the material in the channel layer. This improves the problem of insufficient thermal budget during transistor fabrication caused by oxygen removal from the channel layer, thereby enhancing the stability of the transistor.

[0008] Furthermore, when the gate material includes a metal oxide, and the gate material also contains oxygen, if ΔG1 and ΔG2 are in any relative order, since the gate material itself is a metal oxide, it no longer abstracts oxygen from the channel layer. However, if ΔG1 > ΔG2, by making at least a portion of the channel layer material more capable of abstracting oxygen than the gate material, the channel layer can still abstract oxygen from the gate; in other words, the gate can also reverse-transport oxygen into the channel layer. Since the semiconductor oxide in the existing channel layer is often in an oxygen-deficient state, reverse-transporting oxygen from the gate into the channel layer can also increase the oxygen content in the channel layer, thereby improving the overall performance of the transistor.

[0009] In some possible implementations, the oxide semiconductor is a multi-element oxide semiconductor, where the oxidation Gibbs free energy of the first element is in the range [ΔG2, ΔG3], and ΔG3 is less than 0. Alternatively, the oxide semiconductor is a mono-element oxide semiconductor, where the oxidation Gibbs free energy of the first element is ΔG2.

[0010] If the oxide semiconductor in the channel layer comprises an oxide of a single material, then the oxide semiconductor is a monooxide. For example, the oxide semiconductor is gallium oxide (Ga₂O₃), in which the first element capable of oxidation is gallium (Ga), and the oxidation Gibbs free energy of gallium (Ga) is ΔG₂.

[0011] When ΔG1 = ΔG2, the oxidation capabilities of the gate material and the channel layer material are comparable, and the gate no longer abstracts oxygen from the channel layer. When ΔG1 > ΔG2, the channel layer is more easily oxidized than the gate, increasing the channel layer's ability to abstract oxygen. This makes the channel layer material's oxygen-abstraction capability greater than that of the gate material, and the gate no longer abstracts oxygen from the channel layer. Therefore, by ensuring ΔG1 ≥ ΔG2, the problem of the gate abstracting oxygen from the channel layer through the gate insulating layer can be mitigated, thereby improving the transistor characteristic drift problem.

[0012] If the oxide semiconductor in the channel layer comprises oxides of multiple materials, then the oxide semiconductor is a multi-element oxide. For example, the oxide semiconductor can be a ternary indium gallium zinc oxide (IGaZn), composed of indium oxide (In₂O₃), gallium oxide (Ga₂O₃), and zinc oxide (ZnO). The first element capable of oxidation in IGaZn includes indium (In), gallium (Ga), and zinc (Zn). The Gibbs free energy of oxidation for indium is the first Gibbs free energy, for gallium (Ga) it is the second Gibbs free energy, and for zinc (Zn) it is the third Gibbs free energy. The minimum value among the first, second, and third Gibbs free energies is ΔG₂, and the maximum value is ΔG₃. Alternatively, when the oxide semiconductor is a multi-element oxide semiconductor, the range of the Gibbs free energy of oxidation for the first element is [ΔG₂, ΔG₃], where ΔG₃ is less than 0.

[0013] In this case, if ΔG3 > ΔG1 ≥ ΔG2, and ΔG3 > ΔG1 = ΔG2, the oxidation ability of the gate material is comparable to that of a portion of the channel layer material, and the gate no longer abstracts oxygen from the channel layer material. For example, ΔG1 is equal to the first Gibbs free energy and less than the second and third Gibbs free energies. In the case of ΔG3 > ΔG1 > ΔG2, a portion of the channel layer material is more easily oxidized than the gate material to increase the channel layer's oxygen abstraction ability, making the oxygen abstraction ability of the channel layer material greater than that of the gate material, and the gate no longer abstracts oxygen from the channel layer material. For example, ΔG1 is greater than the first Gibbs free energy and less than the second and third Gibbs free energies.

[0014] If ΔG1 > ΔG3 > ΔG2, all materials in the channel layer are more easily oxidized than the gate material to enhance the channel layer's ability to abstract oxygen. This results in the channel layer material having a greater ability to abstract oxygen than the gate material, and the gate no longer abstracts oxygen from the channel layer. For example, the first Gibbs free energy, the second Gibbs free energy, and the third Gibbs free energy are all less than ΔG1.

[0015] In some possible implementations, when the oxide semiconductor is a multi-element oxide semiconductor, ΔG1 > ΔG3 > ΔG2. Compared to ΔG3 > ΔG1 > ΔG2 and ΔG3 > ΔG1 = ΔG2, for the ΔG1 > ΔG3 > ΔG2 scheme, all materials in the channel layer are more easily oxidized than the gate material, further improving the oxygen abstraction capability of the channel layer. This makes the oxygen abstraction capability of all materials in the channel layer greater than that of the gate material, thereby further improving the problem of the gate abstracting oxygen from the channel layer through the gate insulating layer.

[0016] In some possible implementations, the gate is a single-layer structure, and the gate material includes at least one of elemental metal, conductive metal oxide, and conductive metal nitride. In this way, by applying different voltages to the gate, the transistor can be controlled to turn on or off.

[0017] In some possible implementations, the gate is a stacked structure, comprising a first gate and a second gate. The first gate is disposed between the gate insulating layer and the second gate, and the material of the first gate includes a conductive metal oxide. The material of the second gate includes at least one of an elemental metal and a conductive metal nitride. Alternatively, along the direction from the first gate to the second gate, the second gate includes a first sub-gate and a second sub-gate stacked together, wherein the material of the first sub-gate is an elemental metal and the material of the second sub-gate is a metal nitride; or, the material of the first sub-gate is a metal nitride and the material of the second sub-gate is an elemental metal.

[0018] The first gate is disposed between the gate insulating layer and the second gate. In other words, the first gate is disposed closer to the channel layer and the second gate is disposed further away from the channel layer. Furthermore, the material of the first gate includes a conductive metal oxide, so that in the case of ΔG3>ΔG1>ΔG2, or even ΔG1>ΔG3>ΔG2, the first gate can reverse oxygen supply to the channel layer.

[0019] Considering that the resistivity of metal oxide layers is usually high and can easily affect the conductivity of the gate, the material of the second gate may optionally include materials such as metal elements with low resistivity and conductive metal nitrides to improve the overall conductivity of the gate.

[0020] In some possible implementations, the element capable of oxidation in the first gate is the second element, and the element capable of oxidation in the second gate is the third element. The oxidation Gibbs free energy of the second element is greater than or equal to that of the third element. That is, the oxygen abstraction capability of the first gate is greater than or equal to that of the second gate, thereby preventing the second gate from abstracting oxygen from the first gate. This would prevent the formation of an oxide interface layer related to the material of the second gate at the interface between the first and second gates during oxygen diffusion from the first gate to the second gate, which would affect the transistor's performance.

[0021] In some possible implementations, regardless of whether the gate is a single-layer or multi-layer structure, as long as the gate material includes an oxide, a metal oxide with low resistivity can be selected as the gate material. This avoids the metal oxide having excessively high resistivity, which could affect the gate's conductivity and thus the transistor's performance. Optionally, when the gate material includes a conductive metal oxide, the resistivity of the conductive metal oxide is in the range of 10. -6 ~10 -2 Ω*cm.

[0022] In some possible implementations, the element capable of oxidation in the gate insulating layer is a fourth element, with an oxidation Gibbs free energy of ΔG4. The gate insulating layer material includes oxide insulating materials, where ΔG4 < 0 and ΔG4 < ΔG2. Compared to the gate and channel layers, the gate insulating layer material is more easily oxidized; therefore, the gate insulating layer is already in a stable state and no longer abstracts oxygen from the gate and channel layers. Simultaneously, the gate insulating layer does not act as a barrier layer to prevent oxygen diffusion from the channel and gate layers.

[0023] In some possible implementations, to avoid the negative impact of transistor miniaturization, when the chip includes multiple transistors, such as the chip provided in this application used in memory, multiple transistors can be stacked along the direction from the substrate to the transistors.

[0024] Secondly, this application provides a chip including a substrate and a transistor disposed on the substrate. The transistor includes a channel layer, a gate insulating layer, and a gate disposed sequentially. The channel layer is made of oxide semiconductor. The transistor also includes a barrier layer disposed between the gate and the channel layer, the barrier layer being used to prevent oxygen in the channel layer from diffusing to the gate.

[0025] Although both the barrier layer and the gate insulating layer are disposed between the channel layer and the gate, unlike the gate insulating layer, oxygen has a lower diffusion coefficient D in the barrier layer. The barrier layer can be used to prevent oxygen in the channel layer from diffusing to the gate, thereby solving the problem of transistor characteristic drift. Furthermore, even in high-temperature environments, the barrier layer can be used to prevent oxygen in the channel layer from diffusing to the gate, thereby improving the stability of the transistor.

[0026] In some possible implementations, the barrier layer is disposed between the gate and the gate insulating layer; or, along the direction from the channel layer to the gate, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked together, and the barrier layer is disposed between the first gate insulating layer and the second gate insulating layer; or, the barrier layer is disposed between the channel layer and the gate insulating layer.

[0027] Compared to placing the barrier layer between the channel layer and the gate insulating layer, placing the barrier layer between the gate and the gate insulating layer, or between the first gate insulating layer and the second gate insulating layer, can prevent the barrier layer from affecting the interface state between the channel layer and the gate insulating layer.

[0028] In some possible implementations, the materials suitable for the barrier layer include at least one of aluminum nitride, titanium aluminum nitride, aluminum tantalum nitride, titanium silicon nitride, titanium silicon nitride, aluminum silicon nitride, and silicon nitride. When at least one of the above materials is used as the barrier layer material, the barrier layer can prevent oxygen in the channel layer from diffusing to the gate.

[0029] In some possible implementations, the thickness of the barrier layer ranges from 1 nm to 5 nm. Within this thickness range, the barrier layer is not only sufficient to prevent oxygen in the channel layer from diffusing to the gate, but also avoids the thickness being too large and affecting the thickness of the transistor.

[0030] In some possible implementations, to avoid the negative impact of transistor miniaturization, when the chip includes multiple transistors, such as the chip provided in this application used in memory, multiple transistors can be stacked along the direction from the substrate to the transistors.

[0031] Thirdly, this application provides a memory that includes a chip provided in the first or second aspect, and the chip further includes a capacitor, which, along with a transistor, serves as a storage unit in the memory.

[0032] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0033] Fourthly, this application provides an electronic device, which includes a circuit board and a chip as described in the first aspect, the second aspect, or the third aspect, wherein the chip or memory is disposed on the circuit board. Attached Figure Description

[0034] Figure 1 is an interaction diagram of the modules in the memory provided in an embodiment of this application;

[0035] Figure 2 is a schematic diagram of the chip structure provided in an embodiment of this application;

[0036] Figure 3a is a diagram showing the size relationship between ΔG1, ΔG2, ΔG3, and ΔG4 provided in the embodiments of this application;

[0037] Figure 3b is a diagram showing the size relationship between ΔG1, ΔG2, ΔG3, and ΔG4 provided in the embodiments of this application;

[0038] Figure 3c is a diagram showing the size relationship between ΔG1, ΔG2, ΔG3, and ΔG4 provided in the embodiments of this application;

[0039] Figure 4a is a schematic diagram of the chip structure provided in an embodiment of this application;

[0040] Figure 4b is a schematic diagram of the chip structure provided in an embodiment of this application;

[0041] Figure 5a is a schematic diagram of the chip structure provided in an embodiment of this application;

[0042] Figure 5b is a schematic diagram of the chip structure provided in an embodiment of this application;

[0043] Figure 5c is a schematic diagram of the chip structure provided in the embodiment of this application.

[0044] Reference numerals: 10-substrate; 11-channel layer; 12-source; 13-drain; 14-gate insulating layer; 141-first gate insulating layer; 142-second gate insulating layer; 15-gate; 151-first gate; 152-second gate; 1521-first sub-gate; 1522-second sub-gate; 20-barrier layer. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0047] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0048] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0049] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0050] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device that includes an OS TFT.

[0051] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory devices, radar, base stations, and other communication equipment containing memory chips.

[0052] For ease of explanation, the following description uses a mobile phone as an example. A mobile phone may include a circuit board, a processor, and a memory, which can be mounted on the circuit board. As shown in Figure 1, the memory includes a storage array, a controller, a row decoder, and a column decoder. The processor can send the address of the selected storage cell to the row and column decoders through the controller. After decoding the received address, the row and column decoders determine the storage cell in the storage array, thereby enabling read and write operations on the selected storage cell. The storage cell includes a transistor and a capacitor. The transistor includes a channel layer, a source, a drain, a gate insulating layer, and a gate.

[0053] As mentioned in the background section, OS TFTs are widely used due to their advantages such as low fabrication temperature, low leakage current, and low manufacturing cost. In OS TFTs, the channel layer material includes oxide semiconductors. However, the stability of OS TFTs during chip fabrication remains a critical issue.

[0054] Currently, to improve the thermal stability and reliability of OS TFTs, crystalline oxide semiconductors are used as the channel layer material, or hydrogen and oxygen barrier layers are added to the OS TFT. However, the influence of the gate on the thermal stability of the OS TFT is often overlooked.

[0055] In the field of silicon-based semiconductors, the oxygen scavenging effect, or remote oxygen scavenging, becomes very significant after the gate insulating layer is thinned. As mentioned earlier, the channel layer material of OS TFTs includes oxide semiconductors, which means that if the gate can scavenge oxygen in the channel layer through the gate insulating layer, it will cause a drift in OS TFT characteristics. Furthermore, oxygen scavenging is more likely to occur at high temperatures, potentially leading to insufficient thermal budget during transistor fabrication and affecting the stability of OS TFTs.

[0056] Based on this, embodiments of this application provide a chip in which the material of the gate is selected such that the material of the gate is more difficult to be oxidized than at least a portion of the material of the channel layer, or the material of the gate has an oxidation capacity comparable to at least a portion of the material of the channel layer, so that the gate no longer absorbs oxygen from at least a portion of the material of the channel layer, thereby solving the problem of transistor characteristic drift and improving the stability of the transistor.

[0057] Specifically, as shown in Figure 2, the chip includes a substrate 10 and a transistor disposed on the substrate 10. The transistor includes a channel layer 11, a source 12, a drain 13, a gate insulating layer 14, and a gate 15. In some structures, the transistor also includes an interlayer insulating layer 16. The channel layer 11, the gate insulating layer 14, and the gate 15 are stacked sequentially in the transistor. The transistor can be an OS TFT, where the channel layer of the OS TFT includes an oxide semiconductor. This application does not limit the specific structure of the transistor, as long as the channel layer 11, the gate insulating layer 14, and the gate 15 are stacked sequentially. For example, the transistor can be a gate-around transistor, a fin field-effect transistor (FinFET), etc.

[0058] The material of gate 15 includes a metallic element. For example, the material of gate 15 includes at least one of conductive metal nitrides, conductive metal oxides, and elemental metals. Optionally, the metal nitride includes nitrides of materials such as cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), ruthenium (Ru), and iridium (Ir); the metal oxide includes indium oxide doped with tin (Sn) (e.g., In₂O₃), indium oxide doped with tungsten (W) (e.g., In₂O₃), zinc oxide doped with aluminum (Al) (e.g., ZnO), zinc oxide doped with gallium (Ga) (e.g., ZnO), doped with titanium dioxide (e.g., TiO₂), ruthenium dioxide (e.g., RuO₂), etc.; the elemental metal may include cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), ruthenium (Ru), and iridium (Ir). The material of gate 15 includes at least one metal nitride, and / or at least one metal oxide, and / or at least one elemental metal.

[0059] In this context, the oxidation Gibbs free energy of the metal element in gate 15 is ΔG1. In channel layer 11, the element in the oxide semiconductor capable of undergoing oxidation is the first element, and the minimum oxidation Gibbs free energy of the first element is ΔG2. Furthermore, both ΔG1 and ΔG2 are less than 0, and ΔG1 ≥ ΔG2.

[0060] Those skilled in the art should know that stable elements can undergo oxidation reactions with oxygen. When a stable element is oxidized to a compound with a specified oxidation number, a change in Gibbs free energy occurs. In this application, the Gibbs free energy of an element undergoing an oxidation reaction is referred to as the oxidation Gibbs free energy. For example, the oxidation Gibbs free energy of a metallic element refers to the Gibbs free energy of an element undergoing an oxidation reaction. The oxidation Gibbs free energy of a first element refers to the Gibbs free energy of a first element undergoing an oxidation reaction. Depending on the material properties of each element, the Gibbs free energy value of any element undergoing an oxidation reaction is unique to that element, and will not be elaborated further below.

[0061] The expression for the Gibbs free energy ΔG is ΔG = ΔH - TΔS * 10 -3 ΔH represents enthalpy, T represents temperature, and ΔS represents entropy. That is, the Gibbs free energy ΔG is defined as the difference between the products of enthalpy and entropy. In the Ellingham diagram, it is believed that at the interface between the oxide of an element with a higher Gibbs free energy and the oxide layer of an element with a lower Gibbs free energy, oxygen movement is inhibited from the layer containing the oxide of the element with the lower Gibbs free energy to the oxide of the element with the higher Gibbs free energy. In other words, the smaller the Gibbs free energy caused by the oxidation reaction, the easier it is for oxygen to be captured and oxidized.

[0062] In this embodiment, when ΔG1 = ΔG2, the oxidation capability of the gate 15 material is comparable to that of at least a portion of the material in the channel layer 11, and the gate 15 no longer abstracts oxygen from at least a portion of the material in the channel layer 11. When ΔG1 > ΔG2, at least a portion of the material in the channel layer 11 is more easily oxidized than the gate 15, increasing the oxygen abstraction capability of the at least a portion of the material in the channel layer 11, making the oxygen abstraction capability of the at least a portion of the material in the channel layer 11 greater than that of the material in the gate 15, and the gate 15 no longer abstracts oxygen from at least a portion of the material in the channel layer 11. Thus, by making ΔG1 ≥ ΔG2, the problem of the gate 15 abstracting oxygen from the channel layer 11 through the gate insulating layer 14 can be improved, thereby improving the transistor characteristic drift problem. Furthermore, since the material of the gate 15 is more difficult to oxidize than at least some of the material in the channel layer 11, or the material of the gate 15 has an oxidation capacity comparable to that of at least some of the material in the channel layer 11, even at high temperatures, the gate 15 no longer removes oxygen from at least some of the material in the channel layer 11. This improves the problem of insufficient thermal budget during transistor fabrication caused by oxygen removal from the channel layer 11, and enhances the stability of the transistor.

[0063] Furthermore, when the material of gate 15 includes metal oxide, and the material of gate 15 also contains oxygen, if ΔG1 and ΔG2 are in any relative order, since the material of gate 15 itself is metal oxide, it no longer abstracts oxygen from channel layer 11. However, if ΔG1 > ΔG2, by making the oxygen abstraction capability of at least a portion of the material in channel layer 11 greater than that of the material of gate 15, channel layer 11 can also abstract oxygen from gate 15. In other words, gate 15 can also reverse-transport oxygen to channel layer 11. Since the semiconductor oxide in existing channel layer 11 is often in an oxygen-deficient state, reverse-transporting oxygen from gate 15 to channel layer 11 can also increase the oxygen content in channel layer 11, thereby improving the overall performance of the transistor.

[0064] In some possible implementations, the oxide semiconductor in the channel layer 11 may include at least one oxide of materials such as indium (In), gallium (Ga), zinc (Zn), tin (Sn), magnesium (Mg), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0065] The material of the channel layer 11 is an oxide semiconductor, which can be a mono-oxide semiconductor or a multi-oxide semiconductor.

[0066] If the oxide semiconductor in the channel layer 11 includes an oxide of one of the aforementioned materials, then the oxide semiconductor is a monooxide. For example, the oxide semiconductor is gallium oxide (Ga₂O₃), where the first element capable of undergoing the oxidation reaction in gallium oxide (Ga₂O₃) is gallium (Ga), and the oxidation Gibbs free energy of gallium (Ga) is ΔG₂.

[0067] When ΔG1 = ΔG2, the oxidation capabilities of the gate 15 material and the channel layer 11 material are comparable, and the gate 15 no longer abstracts oxygen from the channel layer 11. When ΔG1 > ΔG2, the channel layer 11 is more easily oxidized than the gate 15, increasing the oxygen abstraction capability of the channel layer 11. This makes the oxygen abstraction capability of the channel layer 11 material greater than that of the gate 15 material, and the gate 15 no longer abstracts oxygen from the channel layer 11. Thus, by making ΔG1 ≥ ΔG2, the problem of the gate 15 abstracting oxygen from the channel layer 11 through the gate insulating layer 14 can be improved, thereby mitigating the transistor characteristic drift problem.

[0068] If the oxide semiconductor in the channel layer 11 includes oxides of the aforementioned materials, then the oxide semiconductor is a multi-element oxide. For example, the oxide semiconductor is a ternary indium gallium zinc oxide (IGZO). IGZO is composed of indium oxide (In₂O₃), gallium oxide (Ga₂O₃), and zinc oxide (ZnO). The first element capable of oxidation in IGZO includes indium (In), gallium (Ga), and zinc (Zn). The Gibbs free energy of indium (In) is the first Gibbs free energy, the Gibbs free energy of gallium (Ga) is the second Gibbs free energy, and the Gibbs free energy of zinc (Zn) is the third Gibbs free energy. The minimum value among the first, second, and third Gibbs free energies is ΔG₂, and the maximum value is ΔG₃. Alternatively, when the oxide semiconductor is a multi-element oxide semiconductor, the range of the Gibbs free energy of the first element is [ΔG₂, ΔG₃], where ΔG₃ is less than 0. In addition, the channel layer 11 may also include an oxide of aluminum (Al), which can form a multi-element oxide semiconductor with the oxide of the above-mentioned materials.

[0069] In this case, if ΔG3 > ΔG1 ≥ ΔG2, as shown in Figure 3a, when ΔG3 > ΔG1 = ΔG2, the oxidation ability of the gate 15 material is comparable to that of a portion of the channel layer 11 material, and the gate 15 no longer abstracts oxygen from the portion of the channel layer 11 material. For example, ΔG1 is equal to the first Gibbs free energy and less than the second and third Gibbs free energies. As shown in Figure 3b, when ΔG3 > ΔG1 > ΔG2, a portion of the channel layer 11 material is more easily oxidized than the gate 15 material to enhance the oxygen abstraction ability of the channel layer 11, making the oxygen abstraction ability of the portion of the channel layer 11 greater than that of the gate 15 material, and the gate 15 no longer abstracts oxygen from the portion of the channel layer 11 material. For example, ΔG1 is greater than the first Gibbs free energy and less than the second and third Gibbs free energies.

[0070] As shown in Figure 3c, if ΔG1 > ΔG3 > ΔG2, all materials in the channel layer 11 are more easily oxidized than the material in the gate 15. The oxygen-stripping ability of all materials in the channel layer 11 is greater than that of the material in the gate 15, and the gate 15 no longer strips oxygen from the channel layer 11. For example, the first Gibbs free energy, the second Gibbs free energy, and the third Gibbs free energy are all less than ΔG1.

[0071] Compared to ΔG3>ΔG1>ΔG2 and ΔG3>ΔG1=ΔG2, for the scheme of ΔG1>ΔG3>ΔG2, all materials in the channel layer 11 are more easily oxidized than the material of the gate 15, which further improves the oxygen abstraction capability of the channel layer 11. This makes the oxygen abstraction capability of all materials in the channel layer 11 greater than that of the material of the gate 15, thereby further improving the problem of the gate 15 abstracting oxygen from the channel layer 11 through the gate insulating layer 14.

[0072] In some possible implementations, the gate 15 in the embodiments of this application can be a single-layer structure or a stacked structure.

[0073] As shown in Figure 2, the gate 15 has a single-layer structure, and the material of the gate 15 may include at least one of the aforementioned elemental metals, conductive metal oxides, and conductive metal nitrides.

[0074] As shown in Figure 4a, the gate 15 has a stacked structure, including a first gate 151 and a second gate 152. The first gate 151 is disposed between the gate insulating layer 151 and the second gate 152. In other words, the first gate 151 is disposed closer to the channel layer 11, and the second gate 152 is disposed further away from the channel layer 11. Furthermore, the material of the first gate 151 includes a conductive metal oxide, so that when ΔG3 > ΔG1 > ΔG2, or even ΔG1 > ΔG3 > ΔG2, the first gate 151 can reversely transport oxygen to the channel layer 11.

[0075] Furthermore, considering that the resistivity of the metal oxide layer is generally high and can easily affect the conductivity of the gate, the material of the second gate 152 may optionally include a material with low resistivity to improve the overall conductivity of the gate 15. For example, the material of the second gate 152 includes at least one of a metallic element and a conductive metal nitride.

[0076] Alternatively, as shown in Figure 4b, the gate 15 has a stacked structure, including a first gate 151 and a second gate 152. The first gate 151 is disposed between the gate insulating layer 151 and the second gate 152. In other words, the first gate 151 is disposed closer to the channel layer 11, and the second gate 152 is disposed further away from the channel layer 11. Furthermore, the material of the first gate 151 includes a conductive metal oxide, so that in the case of ΔG3 > ΔG1 > ΔG2, or even ΔG1 > ΔG3 > ΔG2, the first gate 151 can reversely supply oxygen to the channel layer 11.

[0077] Furthermore, along the direction from the first gate 151 to the second gate 152, the second gate 152 includes a first sub-gate 1521 and a second sub-gate 1522 stacked together. Considering that the resistivity of the metal oxide layer is generally high and can easily affect the conductivity of the gate, optionally, the materials of the first sub-gate 1521 and the second sub-gate 1522 may include materials with low resistivity to improve the overall conductivity of the gate 15. For example, the material of the first sub-gate 1521 is a metal element, and the material of the second sub-gate 1522 is a metal nitride; or, the material of the first sub-gate 1521 is a metal nitride, and the material of the second sub-gate 1522 is a metal element.

[0078] Of course, the second gate 151 can be a multi-layer structure in addition to the single-layer and double-layer structures described above, and this application does not limit this.

[0079] Furthermore, when the gate 15 has a stacked structure, the element capable of oxidation in the first gate 151 is the second element, and the element capable of oxidation in the second gate 152 is the third element. Moreover, the oxidation Gibbs free energy of the second element is greater than or equal to that of the third element. That is, the oxygen abstraction capability of the first gate 151 is greater than or equal to that of the second gate 152. This prevents the second gate 152 from abstracting oxygen from the first gate 151, thus avoiding the formation of an oxide interface layer related to the material of the second gate 152 at the interface between the first gate 151 and the second gate 152 during the diffusion of oxygen from the first gate 151 to the second gate 152, which would otherwise affect the transistor's performance.

[0080] As before, the oxidation Gibbs free energy of the second element refers to the Gibbs free energy of the second element undergoing an oxidation reaction. The oxidation Gibbs free energy of the third element refers to the Gibbs free energy of the third element undergoing an oxidation reaction.

[0081] In other possible implementations, regardless of whether the gate 15 is a single-layer or multi-layer structure, as long as the material of the gate 15 includes an oxide, a metal oxide with low resistivity can be selected as the material for the gate 15. This is to avoid the metal oxide having excessively high resistivity, which could affect the conductivity of the gate 15 and thus the performance of the transistor. Optionally, the resistivity of the metal oxide can be in the range of 10 Ω·cm. -6 ~10 -2 Ω*cm, for example, the resistivity of a metal oxide is 10 Ω*cm. -6 Ω*cm, 10 -4 Ω*cm, 10 -2 Ω*cm, etc.

[0082] In some possible implementations, as shown in Figures 3a-3c, the element capable of oxidation in the gate insulating layer 14 is a fourth element, with an oxidation Gibbs free energy of ΔG4. The material of the gate insulating layer 14 includes an oxide insulating material, where ΔG4 < 0 and ΔG4 < ΔG2. Compared to the gate 15 and channel layer 11, the material of the gate insulating layer 14 is more easily oxidized. Therefore, the gate insulating layer 14 is already in a stable state and no longer absorbs oxygen from the gate 15 and channel layer 11. Simultaneously, the gate insulating layer 14 does not act as a barrier layer to prevent oxygen diffusion from the channel layer 11 and gate 15.

[0083] As before, the oxidation Gibbs free energy of the fourth element refers to the Gibbs free energy of the fourth element undergoing an oxidation reaction.

[0084] In some embodiments, where the chip includes multiple transistors, the multiple transistors may be arranged on the same plane.

[0085] As integrated circuit technology continues to evolve, the number of transistors per unit area on chips in electronic products such as computers and mobile phones is constantly increasing, thereby optimizing the performance of electronic products. On the one hand, the amount of data that processors can process per unit time is constantly increasing; on the other hand, the storage density of memory is also constantly increasing, thus meeting people's data processing needs in the information age. However, due to the differences in structure and manufacturing process between the logic units of processors and the storage units of memory, a gap has emerged in the performance improvement of processors and memory in recent years. The storage density and read / write speed of memory cannot keep up with the processing speed of processors, resulting in the "memory wall" phenomenon, which ultimately limits the overall performance of the system.

[0086] Taking traditional dynamic random access memory (DRAM) as an example, a DRAM cell typically consists of one transistor and one capacitor (1T1C). With the continuous development of integrated circuits, the size of transistors has shrunk dramatically, leading to unavoidable short-channel effects such as increased leakage current and reduced mobility. This presents a significant challenge to the traditional 1T1C memory architecture: even when the transistor is off, leakage current still exists between the source and drain. Therefore, implementing a planar 1T1C memory architecture at advanced technology nodes (e.g., 10nm, 7nm, 5nm and higher) presents considerable challenges. Simultaneously, the projected area of ​​the capacitor is also decreasing with transistor miniaturization. To ensure stable DRAM operation, transistor leakage current must be minimized. The continuous shrinking of the capacitor's projected area also poses significant challenges to the etching process.

[0087] To avoid the negative impact of transistor miniaturization, when a chip includes multiple transistors, such as the chip provided in the embodiments of this application used in a memory, the multiple transistors can also be stacked in a direction perpendicular to the aforementioned plane.

[0088] In another embodiment, this application also provides a chip that improves transistor stability by adding a barrier layer between the channel layer 11 and the gate 15 to prevent oxygen in the channel layer 11 from diffusing to the gate 15.

[0089] As shown in Figures 5a-5c, the chip includes a substrate 10 and a transistor disposed on the substrate 10. The transistor includes a channel layer 11, a source 12, a drain 13, a gate insulating layer 14, and a gate 15. In some structures, the transistor also includes an interlayer insulating layer 16. The channel layer 11, gate insulating layer 14, and gate 15 are stacked sequentially in the transistor. This transistor can be an OS TFT, where the channel layer 11 is made of oxide semiconductor. The transistor also includes a barrier layer 20 disposed between the gate 15 and the channel layer 11. Although both the barrier layer 20 and the gate insulating layer 14 are disposed between the channel layer 11 and the gate 15, unlike the gate insulating layer 14, the oxygen diffusion coefficient D in the barrier layer 20 is lower. The barrier layer 20 can be used to prevent oxygen in the channel layer 11 from diffusing to the gate 15, thereby solving the problem of transistor characteristic drift. Furthermore, even at high temperatures, the barrier layer 20 can be used to prevent oxygen in the channel layer 11 from diffusing to the gate 15, thus improving the stability of the transistor.

[0090] In some possible implementations, the material of the barrier layer 20 is not limited, as long as the oxygen diffusion coefficient D in the barrier layer 20 is low enough to prevent oxygen in the channel layer 11 from diffusing to the gate 15. For example, at a temperature of 600°C, the oxygen diffusion coefficient D in the barrier layer 20 is less than 1.0 × 10⁻⁶. -11 cm 2 / s.

[0091] Optionally, the material suitable for the barrier layer 20 may include at least one of aluminum nitride (AlN), titanium aluminum nitride (TiAlN), aluminum tantalum nitride (TaAlN), titanium silicon nitride (TaSiN), titanium silicon nitride (TiSiN), aluminum silicon nitride (AlSiN), and silicon nitride (SiN).

[0092] In some possible implementations, the thickness of the barrier layer 20 is not limited in this application embodiment, as long as the thickness of the barrier layer 20 is sufficient to prevent oxygen in the channel layer 11 from diffusing to the gate 15. Optionally, the thickness of the barrier layer 20 can be in the range of 1nm to 5nm. Within this thickness range, the barrier layer 20 is not only sufficient to prevent oxygen in the channel layer 11 from diffusing to the gate 15, but also avoids the thickness being too large and affecting the thickness of the transistor.

[0093] In some possible implementations, as shown in FIG5a, the barrier layer 20 is disposed between the gate 15 and the gate insulating layer 14. Alternatively, as shown in FIG5b, along the direction from the channel layer 11 to the gate 15, the gate insulating layer 14 includes a first gate insulating layer 141 and a second gate insulating layer 142 stacked together, and the barrier layer 20 is disposed between the first gate insulating layer 141 and the second gate insulating layer 142. Alternatively, the barrier layer 20 is disposed between the channel layer 11 and the gate insulating layer 14.

[0094] Compared to placing the barrier layer 20 between the channel layer 11 and the gate insulating layer 14, placing the barrier layer 20 between the gate 15 and the gate insulating layer 14, or between the first gate insulating layer 141 and the second gate insulating layer 142, can prevent the barrier layer 20 from affecting the interface state between the channel layer 11 and the gate insulating layer 14.

[0095] Furthermore, this application does not limit the materials of the first gate insulating layer 141 and the second gate insulating layer 142. Optionally, the materials of the first gate insulating layer 141 and the second gate insulating layer 142 may be the same or different. For example, the materials of the first gate insulating layer 141 and the second gate insulating layer 142 include at least one of the following insulating materials: silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), and silicon nitride (Si3N4).

[0096] In some possible implementations, similar to the previous embodiment, when the chip includes multiple transistors, the multiple transistors can be arranged on the same plane. Alternatively, to avoid the negative impact of transistor miniaturization, when the chip includes multiple transistors, such as when the chip provided in the embodiments of this application is used in a memory, the multiple transistors can also be stacked in a direction perpendicular to the aforementioned plane.

[0097] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized in that, The device includes a substrate and a transistor disposed on the substrate, wherein the transistor includes a channel layer, a gate insulating layer, and a gate layer that are sequentially stacked. The gate material includes a metal element, and the oxidation Gibbs free energy of the metal element is ΔG1; the channel layer material includes an oxide semiconductor, and the element in the oxide semiconductor that can undergo oxidation reaction is a first element, and the minimum oxidation Gibbs free energy of the first element is ΔG2. In this case, both ΔG1 and ΔG2 are less than 0, and ΔG1 ≥ ΔG2.

2. The chip according to claim 1, characterized in that, The oxide semiconductor is a multi-element oxide semiconductor, and the oxidation Gibbs free energy range of the first element is [ΔG2, ΔG3], where ΔG3 is less than 0; or... The oxide semiconductor is a unary oxide semiconductor, and the oxidation Gibbs free energy of the first element is ΔG2.

3. The chip according to claim 2, characterized in that, When the oxide semiconductor is a multi-element oxide semiconductor, ΔG1 > ΔG3.

4. The chip according to any one of claims 1-3, characterized in that, The gate is a single-layer structure, and the material of the gate includes at least one of elemental metal, conductive metal oxide, and conductive metal nitride.

5. The chip according to any one of claims 1-3, characterized in that, The gate has a stacked structure, and the gate includes a first gate and a second gate. The first gate is disposed between the gate insulating layer and the second gate, and the material of the first gate includes a conductive metal oxide. The material of the second gate includes at least one of an elemental metal and a conductive metal nitride; or, along the direction from the first gate to the second gate, the second gate includes a first sub-gate and a second sub-gate stacked together, wherein the material of the first sub-gate is an elemental metal and the material of the second sub-gate is a metal nitride; or, the material of the first sub-gate is a metal nitride and the material of the second sub-gate is an elemental metal.

6. The chip according to claim 4 or 5, characterized in that, The element that can undergo oxidation in the first gate is the second element, and the element that can undergo oxidation in the second gate is the third element; The oxidation Gibbs free energy of the second element is greater than or equal to the oxidation Gibbs free energy of the third element.

7. The chip according to any one of claims 3-6, characterized in that, When the material of the gate includes the conductive metal oxide, the resistivity of the conductive metal oxide is in the range of 10. -6 ~10 -2 Ω*cm.

8. The chip according to claim 1, characterized in that, The element in the gate insulating layer that can undergo oxidation is the fourth element, and the oxidation Gibbs free energy of the fourth element is ΔG4. The material of the gate insulating layer includes oxide insulating material, where ΔG4 < 0 and ΔG4 < ΔG2.

9. The chip according to any one of claims 1-8, characterized in that, A plurality of transistors are stacked along the direction from the substrate toward the transistor.

10. A chip, characterized in that, The device includes a substrate and a transistor disposed on the substrate. The transistor includes a channel layer, a gate insulating layer, and a gate disposed in sequence. The material of the channel layer includes an oxide semiconductor. The transistor further includes a barrier layer disposed between the gate and the channel layer, the barrier layer being used to prevent oxygen in the channel layer from diffusing to the gate.

11. The chip according to claim 10, characterized in that, The barrier layer is disposed between the gate and the gate insulating layer; or... Along the direction from the channel layer to the gate, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked together, and the barrier layer is disposed between the first gate insulating layer and the second gate insulating layer; or... The barrier layer is disposed between the channel layer and the gate insulation layer.

12. The chip according to claim 10 or 11, characterized in that, The material of the barrier layer includes at least one of aluminum nitride, titanium aluminum nitride, aluminum tantalum nitride, titanium silicon nitride, titanium silicon nitride, aluminum silicon nitride, and silicon nitride.

13. The chip according to any one of claims 9-11, characterized in that, The thickness of the barrier layer ranges from 1 nm to 5 nm.

14. The chip according to any one of claims 10-13, characterized in that, A plurality of transistors are stacked along the direction from the substrate toward the transistor.

15. A memory, characterized in that, It includes a controller and a chip as described in any one of claims 1-9 or any one of claims 10-14, wherein the controller is used to control the chip to read and write data.

16. An electronic device, characterized in that, The device includes a circuit board, and a chip as described in any one of claims 1-9, or a chip as described in any one of claims 10-14, or a memory as described in claim 15, wherein the chip or the memory is disposed on the circuit board.

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